ite-cir.c 41 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for ITE Tech Inc. IT8712F/IT8512 CIR
  4. *
  5. * Copyright (C) 2010 Juan Jesús García de Soria <[email protected]>
  6. *
  7. * Inspired by the original lirc_it87 and lirc_ite8709 drivers, on top of the
  8. * skeleton provided by the nuvoton-cir driver.
  9. *
  10. * The lirc_it87 driver was originally written by Hans-Gunter Lutke Uphues
  11. * <[email protected]> in 2001, with enhancements by Christoph Bartelmus
  12. * <[email protected]>, Andrew Calkin <[email protected]> and James Edwards
  13. * <[email protected]>.
  14. *
  15. * The lirc_ite8709 driver was written by Grégory Lardière
  16. * <[email protected]> in 2008.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/pnp.h>
  21. #include <linux/io.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/input.h>
  27. #include <linux/bitops.h>
  28. #include <media/rc-core.h>
  29. #include <linux/pci_ids.h>
  30. #include "ite-cir.h"
  31. /* module parameters */
  32. /* default sample period */
  33. static long sample_period = NSEC_PER_SEC / 115200;
  34. module_param(sample_period, long, S_IRUGO | S_IWUSR);
  35. MODULE_PARM_DESC(sample_period, "sample period");
  36. /* override detected model id */
  37. static int model_number = -1;
  38. module_param(model_number, int, S_IRUGO | S_IWUSR);
  39. MODULE_PARM_DESC(model_number, "Use this model number, don't autodetect");
  40. /* HW-independent code functions */
  41. /* check whether carrier frequency is high frequency */
  42. static inline bool ite_is_high_carrier_freq(unsigned int freq)
  43. {
  44. return freq >= ITE_HCF_MIN_CARRIER_FREQ;
  45. }
  46. /* get the bits required to program the carrier frequency in CFQ bits,
  47. * unshifted */
  48. static u8 ite_get_carrier_freq_bits(unsigned int freq)
  49. {
  50. if (ite_is_high_carrier_freq(freq)) {
  51. if (freq < 425000)
  52. return ITE_CFQ_400;
  53. else if (freq < 465000)
  54. return ITE_CFQ_450;
  55. else if (freq < 490000)
  56. return ITE_CFQ_480;
  57. else
  58. return ITE_CFQ_500;
  59. } else {
  60. /* trim to limits */
  61. if (freq < ITE_LCF_MIN_CARRIER_FREQ)
  62. freq = ITE_LCF_MIN_CARRIER_FREQ;
  63. if (freq > ITE_LCF_MAX_CARRIER_FREQ)
  64. freq = ITE_LCF_MAX_CARRIER_FREQ;
  65. /* convert to kHz and subtract the base freq */
  66. freq = DIV_ROUND_CLOSEST(freq - ITE_LCF_MIN_CARRIER_FREQ, 1000);
  67. return (u8) freq;
  68. }
  69. }
  70. /* get the bits required to program the pulse with in TXMPW */
  71. static u8 ite_get_pulse_width_bits(unsigned int freq, int duty_cycle)
  72. {
  73. unsigned long period_ns, on_ns;
  74. /* sanitize freq into range */
  75. if (freq < ITE_LCF_MIN_CARRIER_FREQ)
  76. freq = ITE_LCF_MIN_CARRIER_FREQ;
  77. if (freq > ITE_HCF_MAX_CARRIER_FREQ)
  78. freq = ITE_HCF_MAX_CARRIER_FREQ;
  79. period_ns = 1000000000UL / freq;
  80. on_ns = period_ns * duty_cycle / 100;
  81. if (ite_is_high_carrier_freq(freq)) {
  82. if (on_ns < 750)
  83. return ITE_TXMPW_A;
  84. else if (on_ns < 850)
  85. return ITE_TXMPW_B;
  86. else if (on_ns < 950)
  87. return ITE_TXMPW_C;
  88. else if (on_ns < 1080)
  89. return ITE_TXMPW_D;
  90. else
  91. return ITE_TXMPW_E;
  92. } else {
  93. if (on_ns < 6500)
  94. return ITE_TXMPW_A;
  95. else if (on_ns < 7850)
  96. return ITE_TXMPW_B;
  97. else if (on_ns < 9650)
  98. return ITE_TXMPW_C;
  99. else if (on_ns < 11950)
  100. return ITE_TXMPW_D;
  101. else
  102. return ITE_TXMPW_E;
  103. }
  104. }
  105. /* decode raw bytes as received by the hardware, and push them to the ir-core
  106. * layer */
  107. static void ite_decode_bytes(struct ite_dev *dev, const u8 * data, int
  108. length)
  109. {
  110. unsigned long *ldata;
  111. unsigned int next_one, next_zero, size;
  112. struct ir_raw_event ev = {};
  113. if (length == 0)
  114. return;
  115. ldata = (unsigned long *)data;
  116. size = length << 3;
  117. next_one = find_next_bit_le(ldata, size, 0);
  118. if (next_one > 0) {
  119. ev.pulse = true;
  120. ev.duration = ITE_BITS_TO_US(next_one, sample_period);
  121. ir_raw_event_store_with_filter(dev->rdev, &ev);
  122. }
  123. while (next_one < size) {
  124. next_zero = find_next_zero_bit_le(ldata, size, next_one + 1);
  125. ev.pulse = false;
  126. ev.duration = ITE_BITS_TO_US(next_zero - next_one, sample_period);
  127. ir_raw_event_store_with_filter(dev->rdev, &ev);
  128. if (next_zero < size) {
  129. next_one = find_next_bit_le(ldata, size, next_zero + 1);
  130. ev.pulse = true;
  131. ev.duration = ITE_BITS_TO_US(next_one - next_zero,
  132. sample_period);
  133. ir_raw_event_store_with_filter(dev->rdev, &ev);
  134. } else
  135. next_one = size;
  136. }
  137. ir_raw_event_handle(dev->rdev);
  138. dev_dbg(&dev->rdev->dev, "decoded %d bytes\n", length);
  139. }
  140. /* set all the rx/tx carrier parameters; this must be called with the device
  141. * spinlock held */
  142. static void ite_set_carrier_params(struct ite_dev *dev)
  143. {
  144. unsigned int freq, low_freq, high_freq;
  145. int allowance;
  146. bool use_demodulator;
  147. bool for_tx = dev->transmitting;
  148. if (for_tx) {
  149. /* we don't need no stinking calculations */
  150. freq = dev->tx_carrier_freq;
  151. allowance = ITE_RXDCR_DEFAULT;
  152. use_demodulator = false;
  153. } else {
  154. low_freq = dev->rx_low_carrier_freq;
  155. high_freq = dev->rx_high_carrier_freq;
  156. if (low_freq == 0) {
  157. /* don't demodulate */
  158. freq = ITE_DEFAULT_CARRIER_FREQ;
  159. allowance = ITE_RXDCR_DEFAULT;
  160. use_demodulator = false;
  161. } else {
  162. /* calculate the middle freq */
  163. freq = (low_freq + high_freq) / 2;
  164. /* calculate the allowance */
  165. allowance =
  166. DIV_ROUND_CLOSEST(10000 * (high_freq - low_freq),
  167. ITE_RXDCR_PER_10000_STEP
  168. * (high_freq + low_freq));
  169. if (allowance < 1)
  170. allowance = 1;
  171. if (allowance > ITE_RXDCR_MAX)
  172. allowance = ITE_RXDCR_MAX;
  173. use_demodulator = true;
  174. }
  175. }
  176. /* set the carrier parameters in a device-dependent way */
  177. dev->params->set_carrier_params(dev, ite_is_high_carrier_freq(freq),
  178. use_demodulator, ite_get_carrier_freq_bits(freq), allowance,
  179. ite_get_pulse_width_bits(freq, dev->tx_duty_cycle));
  180. }
  181. /* interrupt service routine for incoming and outgoing CIR data */
  182. static irqreturn_t ite_cir_isr(int irq, void *data)
  183. {
  184. struct ite_dev *dev = data;
  185. irqreturn_t ret = IRQ_RETVAL(IRQ_NONE);
  186. u8 rx_buf[ITE_RX_FIFO_LEN];
  187. int rx_bytes;
  188. int iflags;
  189. /* grab the spinlock */
  190. spin_lock(&dev->lock);
  191. /* read the interrupt flags */
  192. iflags = dev->params->get_irq_causes(dev);
  193. /* Check for RX overflow */
  194. if (iflags & ITE_IRQ_RX_FIFO_OVERRUN) {
  195. dev_warn(&dev->rdev->dev, "receive overflow\n");
  196. ir_raw_event_overflow(dev->rdev);
  197. }
  198. /* check for the receive interrupt */
  199. if (iflags & (ITE_IRQ_RX_FIFO | ITE_IRQ_RX_FIFO_OVERRUN)) {
  200. /* read the FIFO bytes */
  201. rx_bytes = dev->params->get_rx_bytes(dev, rx_buf,
  202. ITE_RX_FIFO_LEN);
  203. dev_dbg(&dev->rdev->dev, "interrupt %d RX bytes\n", rx_bytes);
  204. if (rx_bytes > 0) {
  205. /* drop the spinlock, since the ir-core layer
  206. * may call us back again through
  207. * ite_s_idle() */
  208. spin_unlock(&dev->lock);
  209. /* decode the data we've just received */
  210. ite_decode_bytes(dev, rx_buf, rx_bytes);
  211. /* reacquire the spinlock */
  212. spin_lock(&dev->lock);
  213. /* mark the interrupt as serviced */
  214. ret = IRQ_RETVAL(IRQ_HANDLED);
  215. }
  216. } else if (iflags & ITE_IRQ_TX_FIFO) {
  217. /* FIFO space available interrupt */
  218. dev_dbg(&dev->rdev->dev, "interrupt TX FIFO\n");
  219. /* wake any sleeping transmitter */
  220. wake_up_interruptible(&dev->tx_queue);
  221. /* mark the interrupt as serviced */
  222. ret = IRQ_RETVAL(IRQ_HANDLED);
  223. }
  224. /* drop the spinlock */
  225. spin_unlock(&dev->lock);
  226. return ret;
  227. }
  228. /* set the rx carrier freq range, guess it's in Hz... */
  229. static int ite_set_rx_carrier_range(struct rc_dev *rcdev, u32 carrier_low, u32
  230. carrier_high)
  231. {
  232. unsigned long flags;
  233. struct ite_dev *dev = rcdev->priv;
  234. spin_lock_irqsave(&dev->lock, flags);
  235. dev->rx_low_carrier_freq = carrier_low;
  236. dev->rx_high_carrier_freq = carrier_high;
  237. ite_set_carrier_params(dev);
  238. spin_unlock_irqrestore(&dev->lock, flags);
  239. return 0;
  240. }
  241. /* set the tx carrier freq, guess it's in Hz... */
  242. static int ite_set_tx_carrier(struct rc_dev *rcdev, u32 carrier)
  243. {
  244. unsigned long flags;
  245. struct ite_dev *dev = rcdev->priv;
  246. spin_lock_irqsave(&dev->lock, flags);
  247. dev->tx_carrier_freq = carrier;
  248. ite_set_carrier_params(dev);
  249. spin_unlock_irqrestore(&dev->lock, flags);
  250. return 0;
  251. }
  252. /* set the tx duty cycle by controlling the pulse width */
  253. static int ite_set_tx_duty_cycle(struct rc_dev *rcdev, u32 duty_cycle)
  254. {
  255. unsigned long flags;
  256. struct ite_dev *dev = rcdev->priv;
  257. spin_lock_irqsave(&dev->lock, flags);
  258. dev->tx_duty_cycle = duty_cycle;
  259. ite_set_carrier_params(dev);
  260. spin_unlock_irqrestore(&dev->lock, flags);
  261. return 0;
  262. }
  263. /* transmit out IR pulses; what you get here is a batch of alternating
  264. * pulse/space/pulse/space lengths that we should write out completely through
  265. * the FIFO, blocking on a full FIFO */
  266. static int ite_tx_ir(struct rc_dev *rcdev, unsigned *txbuf, unsigned n)
  267. {
  268. unsigned long flags;
  269. struct ite_dev *dev = rcdev->priv;
  270. bool is_pulse = false;
  271. int remaining_us, fifo_avail, fifo_remaining, last_idx = 0;
  272. int max_rle_us, next_rle_us;
  273. int ret = n;
  274. u8 last_sent[ITE_TX_FIFO_LEN];
  275. u8 val;
  276. /* clear the array just in case */
  277. memset(last_sent, 0, sizeof(last_sent));
  278. spin_lock_irqsave(&dev->lock, flags);
  279. /* let everybody know we're now transmitting */
  280. dev->transmitting = true;
  281. /* and set the carrier values for transmission */
  282. ite_set_carrier_params(dev);
  283. /* calculate how much time we can send in one byte */
  284. max_rle_us =
  285. (ITE_BAUDRATE_DIVISOR * sample_period *
  286. ITE_TX_MAX_RLE) / 1000;
  287. /* disable the receiver */
  288. dev->params->disable_rx(dev);
  289. /* this is where we'll begin filling in the FIFO, until it's full.
  290. * then we'll just activate the interrupt, wait for it to wake us up
  291. * again, disable it, continue filling the FIFO... until everything
  292. * has been pushed out */
  293. fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev);
  294. while (n > 0) {
  295. /* transmit the next sample */
  296. is_pulse = !is_pulse;
  297. remaining_us = *(txbuf++);
  298. n--;
  299. dev_dbg(&dev->rdev->dev, "%s: %d\n",
  300. is_pulse ? "pulse" : "space", remaining_us);
  301. /* repeat while the pulse is non-zero length */
  302. while (remaining_us > 0) {
  303. if (remaining_us > max_rle_us)
  304. next_rle_us = max_rle_us;
  305. else
  306. next_rle_us = remaining_us;
  307. remaining_us -= next_rle_us;
  308. /* check what's the length we have to pump out */
  309. val = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us;
  310. /* put it into the sent buffer */
  311. last_sent[last_idx++] = val;
  312. last_idx &= (ITE_TX_FIFO_LEN);
  313. /* encode it for 7 bits */
  314. val = (val - 1) & ITE_TX_RLE_MASK;
  315. /* take into account pulse/space prefix */
  316. if (is_pulse)
  317. val |= ITE_TX_PULSE;
  318. else
  319. val |= ITE_TX_SPACE;
  320. /*
  321. * if we get to 0 available, read again, just in case
  322. * some other slot got freed
  323. */
  324. if (fifo_avail <= 0)
  325. fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev);
  326. /* if it's still full */
  327. if (fifo_avail <= 0) {
  328. /* enable the tx interrupt */
  329. dev->params->enable_tx_interrupt(dev);
  330. /* drop the spinlock */
  331. spin_unlock_irqrestore(&dev->lock, flags);
  332. /* wait for the FIFO to empty enough */
  333. wait_event_interruptible(dev->tx_queue,
  334. (fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev)) >= 8);
  335. /* get the spinlock again */
  336. spin_lock_irqsave(&dev->lock, flags);
  337. /* disable the tx interrupt again. */
  338. dev->params->disable_tx_interrupt(dev);
  339. }
  340. /* now send the byte through the FIFO */
  341. dev->params->put_tx_byte(dev, val);
  342. fifo_avail--;
  343. }
  344. }
  345. /* wait and don't return until the whole FIFO has been sent out;
  346. * otherwise we could configure the RX carrier params instead of the
  347. * TX ones while the transmission is still being performed! */
  348. fifo_remaining = dev->params->get_tx_used_slots(dev);
  349. remaining_us = 0;
  350. while (fifo_remaining > 0) {
  351. fifo_remaining--;
  352. last_idx--;
  353. last_idx &= (ITE_TX_FIFO_LEN - 1);
  354. remaining_us += last_sent[last_idx];
  355. }
  356. remaining_us = (remaining_us * max_rle_us) / (ITE_TX_MAX_RLE);
  357. /* drop the spinlock while we sleep */
  358. spin_unlock_irqrestore(&dev->lock, flags);
  359. /* sleep remaining_us microseconds */
  360. mdelay(DIV_ROUND_UP(remaining_us, 1000));
  361. /* reacquire the spinlock */
  362. spin_lock_irqsave(&dev->lock, flags);
  363. /* now we're not transmitting anymore */
  364. dev->transmitting = false;
  365. /* and set the carrier values for reception */
  366. ite_set_carrier_params(dev);
  367. /* re-enable the receiver */
  368. dev->params->enable_rx(dev);
  369. /* notify transmission end */
  370. wake_up_interruptible(&dev->tx_ended);
  371. spin_unlock_irqrestore(&dev->lock, flags);
  372. return ret;
  373. }
  374. /* idle the receiver if needed */
  375. static void ite_s_idle(struct rc_dev *rcdev, bool enable)
  376. {
  377. unsigned long flags;
  378. struct ite_dev *dev = rcdev->priv;
  379. if (enable) {
  380. spin_lock_irqsave(&dev->lock, flags);
  381. dev->params->idle_rx(dev);
  382. spin_unlock_irqrestore(&dev->lock, flags);
  383. }
  384. }
  385. /* IT8712F HW-specific functions */
  386. /* retrieve a bitmask of the current causes for a pending interrupt; this may
  387. * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
  388. * */
  389. static int it87_get_irq_causes(struct ite_dev *dev)
  390. {
  391. u8 iflags;
  392. int ret = 0;
  393. /* read the interrupt flags */
  394. iflags = inb(dev->cir_addr + IT87_IIR) & IT87_II;
  395. switch (iflags) {
  396. case IT87_II_RXDS:
  397. ret = ITE_IRQ_RX_FIFO;
  398. break;
  399. case IT87_II_RXFO:
  400. ret = ITE_IRQ_RX_FIFO_OVERRUN;
  401. break;
  402. case IT87_II_TXLDL:
  403. ret = ITE_IRQ_TX_FIFO;
  404. break;
  405. }
  406. return ret;
  407. }
  408. /* set the carrier parameters; to be called with the spinlock held */
  409. static void it87_set_carrier_params(struct ite_dev *dev, bool high_freq,
  410. bool use_demodulator,
  411. u8 carrier_freq_bits, u8 allowance_bits,
  412. u8 pulse_width_bits)
  413. {
  414. u8 val;
  415. /* program the RCR register */
  416. val = inb(dev->cir_addr + IT87_RCR)
  417. & ~(IT87_HCFS | IT87_RXEND | IT87_RXDCR);
  418. if (high_freq)
  419. val |= IT87_HCFS;
  420. if (use_demodulator)
  421. val |= IT87_RXEND;
  422. val |= allowance_bits;
  423. outb(val, dev->cir_addr + IT87_RCR);
  424. /* program the TCR2 register */
  425. outb((carrier_freq_bits << IT87_CFQ_SHIFT) | pulse_width_bits,
  426. dev->cir_addr + IT87_TCR2);
  427. }
  428. /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
  429. * held */
  430. static int it87_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
  431. {
  432. int fifo, read = 0;
  433. /* read how many bytes are still in the FIFO */
  434. fifo = inb(dev->cir_addr + IT87_RSR) & IT87_RXFBC;
  435. while (fifo > 0 && buf_size > 0) {
  436. *(buf++) = inb(dev->cir_addr + IT87_DR);
  437. fifo--;
  438. read++;
  439. buf_size--;
  440. }
  441. return read;
  442. }
  443. /* return how many bytes are still in the FIFO; this will be called
  444. * with the device spinlock NOT HELD while waiting for the TX FIFO to get
  445. * empty; let's expect this won't be a problem */
  446. static int it87_get_tx_used_slots(struct ite_dev *dev)
  447. {
  448. return inb(dev->cir_addr + IT87_TSR) & IT87_TXFBC;
  449. }
  450. /* put a byte to the TX fifo; this should be called with the spinlock held */
  451. static void it87_put_tx_byte(struct ite_dev *dev, u8 value)
  452. {
  453. outb(value, dev->cir_addr + IT87_DR);
  454. }
  455. /* idle the receiver so that we won't receive samples until another
  456. pulse is detected; this must be called with the device spinlock held */
  457. static void it87_idle_rx(struct ite_dev *dev)
  458. {
  459. /* disable streaming by clearing RXACT writing it as 1 */
  460. outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXACT,
  461. dev->cir_addr + IT87_RCR);
  462. /* clear the FIFO */
  463. outb(inb(dev->cir_addr + IT87_TCR1) | IT87_FIFOCLR,
  464. dev->cir_addr + IT87_TCR1);
  465. }
  466. /* disable the receiver; this must be called with the device spinlock held */
  467. static void it87_disable_rx(struct ite_dev *dev)
  468. {
  469. /* disable the receiver interrupts */
  470. outb(inb(dev->cir_addr + IT87_IER) & ~(IT87_RDAIE | IT87_RFOIE),
  471. dev->cir_addr + IT87_IER);
  472. /* disable the receiver */
  473. outb(inb(dev->cir_addr + IT87_RCR) & ~IT87_RXEN,
  474. dev->cir_addr + IT87_RCR);
  475. /* clear the FIFO and RXACT (actually RXACT should have been cleared
  476. * in the previous outb() call) */
  477. it87_idle_rx(dev);
  478. }
  479. /* enable the receiver; this must be called with the device spinlock held */
  480. static void it87_enable_rx(struct ite_dev *dev)
  481. {
  482. /* enable the receiver by setting RXEN */
  483. outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXEN,
  484. dev->cir_addr + IT87_RCR);
  485. /* just prepare it to idle for the next reception */
  486. it87_idle_rx(dev);
  487. /* enable the receiver interrupts and master enable flag */
  488. outb(inb(dev->cir_addr + IT87_IER) | IT87_RDAIE | IT87_RFOIE | IT87_IEC,
  489. dev->cir_addr + IT87_IER);
  490. }
  491. /* disable the transmitter interrupt; this must be called with the device
  492. * spinlock held */
  493. static void it87_disable_tx_interrupt(struct ite_dev *dev)
  494. {
  495. /* disable the transmitter interrupts */
  496. outb(inb(dev->cir_addr + IT87_IER) & ~IT87_TLDLIE,
  497. dev->cir_addr + IT87_IER);
  498. }
  499. /* enable the transmitter interrupt; this must be called with the device
  500. * spinlock held */
  501. static void it87_enable_tx_interrupt(struct ite_dev *dev)
  502. {
  503. /* enable the transmitter interrupts and master enable flag */
  504. outb(inb(dev->cir_addr + IT87_IER) | IT87_TLDLIE | IT87_IEC,
  505. dev->cir_addr + IT87_IER);
  506. }
  507. /* disable the device; this must be called with the device spinlock held */
  508. static void it87_disable(struct ite_dev *dev)
  509. {
  510. /* clear out all interrupt enable flags */
  511. outb(inb(dev->cir_addr + IT87_IER) &
  512. ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE),
  513. dev->cir_addr + IT87_IER);
  514. /* disable the receiver */
  515. it87_disable_rx(dev);
  516. /* erase the FIFO */
  517. outb(IT87_FIFOCLR | inb(dev->cir_addr + IT87_TCR1),
  518. dev->cir_addr + IT87_TCR1);
  519. }
  520. /* initialize the hardware */
  521. static void it87_init_hardware(struct ite_dev *dev)
  522. {
  523. /* enable just the baud rate divisor register,
  524. disabling all the interrupts at the same time */
  525. outb((inb(dev->cir_addr + IT87_IER) &
  526. ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE)) | IT87_BR,
  527. dev->cir_addr + IT87_IER);
  528. /* write out the baud rate divisor */
  529. outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT87_BDLR);
  530. outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff, dev->cir_addr + IT87_BDHR);
  531. /* disable the baud rate divisor register again */
  532. outb(inb(dev->cir_addr + IT87_IER) & ~IT87_BR,
  533. dev->cir_addr + IT87_IER);
  534. /* program the RCR register defaults */
  535. outb(ITE_RXDCR_DEFAULT, dev->cir_addr + IT87_RCR);
  536. /* program the TCR1 register */
  537. outb(IT87_TXMPM_DEFAULT | IT87_TXENDF | IT87_TXRLE
  538. | IT87_FIFOTL_DEFAULT | IT87_FIFOCLR,
  539. dev->cir_addr + IT87_TCR1);
  540. /* program the carrier parameters */
  541. ite_set_carrier_params(dev);
  542. }
  543. /* IT8512F on ITE8708 HW-specific functions */
  544. /* retrieve a bitmask of the current causes for a pending interrupt; this may
  545. * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
  546. * */
  547. static int it8708_get_irq_causes(struct ite_dev *dev)
  548. {
  549. u8 iflags;
  550. int ret = 0;
  551. /* read the interrupt flags */
  552. iflags = inb(dev->cir_addr + IT8708_C0IIR);
  553. if (iflags & IT85_TLDLI)
  554. ret |= ITE_IRQ_TX_FIFO;
  555. if (iflags & IT85_RDAI)
  556. ret |= ITE_IRQ_RX_FIFO;
  557. if (iflags & IT85_RFOI)
  558. ret |= ITE_IRQ_RX_FIFO_OVERRUN;
  559. return ret;
  560. }
  561. /* set the carrier parameters; to be called with the spinlock held */
  562. static void it8708_set_carrier_params(struct ite_dev *dev, bool high_freq,
  563. bool use_demodulator,
  564. u8 carrier_freq_bits, u8 allowance_bits,
  565. u8 pulse_width_bits)
  566. {
  567. u8 val;
  568. /* program the C0CFR register, with HRAE=1 */
  569. outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
  570. dev->cir_addr + IT8708_BANKSEL);
  571. val = (inb(dev->cir_addr + IT8708_C0CFR)
  572. & ~(IT85_HCFS | IT85_CFQ)) | carrier_freq_bits;
  573. if (high_freq)
  574. val |= IT85_HCFS;
  575. outb(val, dev->cir_addr + IT8708_C0CFR);
  576. outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
  577. dev->cir_addr + IT8708_BANKSEL);
  578. /* program the C0RCR register */
  579. val = inb(dev->cir_addr + IT8708_C0RCR)
  580. & ~(IT85_RXEND | IT85_RXDCR);
  581. if (use_demodulator)
  582. val |= IT85_RXEND;
  583. val |= allowance_bits;
  584. outb(val, dev->cir_addr + IT8708_C0RCR);
  585. /* program the C0TCR register */
  586. val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW;
  587. val |= pulse_width_bits;
  588. outb(val, dev->cir_addr + IT8708_C0TCR);
  589. }
  590. /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
  591. * held */
  592. static int it8708_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
  593. {
  594. int fifo, read = 0;
  595. /* read how many bytes are still in the FIFO */
  596. fifo = inb(dev->cir_addr + IT8708_C0RFSR) & IT85_RXFBC;
  597. while (fifo > 0 && buf_size > 0) {
  598. *(buf++) = inb(dev->cir_addr + IT8708_C0DR);
  599. fifo--;
  600. read++;
  601. buf_size--;
  602. }
  603. return read;
  604. }
  605. /* return how many bytes are still in the FIFO; this will be called
  606. * with the device spinlock NOT HELD while waiting for the TX FIFO to get
  607. * empty; let's expect this won't be a problem */
  608. static int it8708_get_tx_used_slots(struct ite_dev *dev)
  609. {
  610. return inb(dev->cir_addr + IT8708_C0TFSR) & IT85_TXFBC;
  611. }
  612. /* put a byte to the TX fifo; this should be called with the spinlock held */
  613. static void it8708_put_tx_byte(struct ite_dev *dev, u8 value)
  614. {
  615. outb(value, dev->cir_addr + IT8708_C0DR);
  616. }
  617. /* idle the receiver so that we won't receive samples until another
  618. pulse is detected; this must be called with the device spinlock held */
  619. static void it8708_idle_rx(struct ite_dev *dev)
  620. {
  621. /* disable streaming by clearing RXACT writing it as 1 */
  622. outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXACT,
  623. dev->cir_addr + IT8708_C0RCR);
  624. /* clear the FIFO */
  625. outb(inb(dev->cir_addr + IT8708_C0MSTCR) | IT85_FIFOCLR,
  626. dev->cir_addr + IT8708_C0MSTCR);
  627. }
  628. /* disable the receiver; this must be called with the device spinlock held */
  629. static void it8708_disable_rx(struct ite_dev *dev)
  630. {
  631. /* disable the receiver interrupts */
  632. outb(inb(dev->cir_addr + IT8708_C0IER) &
  633. ~(IT85_RDAIE | IT85_RFOIE),
  634. dev->cir_addr + IT8708_C0IER);
  635. /* disable the receiver */
  636. outb(inb(dev->cir_addr + IT8708_C0RCR) & ~IT85_RXEN,
  637. dev->cir_addr + IT8708_C0RCR);
  638. /* clear the FIFO and RXACT (actually RXACT should have been cleared
  639. * in the previous outb() call) */
  640. it8708_idle_rx(dev);
  641. }
  642. /* enable the receiver; this must be called with the device spinlock held */
  643. static void it8708_enable_rx(struct ite_dev *dev)
  644. {
  645. /* enable the receiver by setting RXEN */
  646. outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXEN,
  647. dev->cir_addr + IT8708_C0RCR);
  648. /* just prepare it to idle for the next reception */
  649. it8708_idle_rx(dev);
  650. /* enable the receiver interrupts and master enable flag */
  651. outb(inb(dev->cir_addr + IT8708_C0IER)
  652. |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
  653. dev->cir_addr + IT8708_C0IER);
  654. }
  655. /* disable the transmitter interrupt; this must be called with the device
  656. * spinlock held */
  657. static void it8708_disable_tx_interrupt(struct ite_dev *dev)
  658. {
  659. /* disable the transmitter interrupts */
  660. outb(inb(dev->cir_addr + IT8708_C0IER) & ~IT85_TLDLIE,
  661. dev->cir_addr + IT8708_C0IER);
  662. }
  663. /* enable the transmitter interrupt; this must be called with the device
  664. * spinlock held */
  665. static void it8708_enable_tx_interrupt(struct ite_dev *dev)
  666. {
  667. /* enable the transmitter interrupts and master enable flag */
  668. outb(inb(dev->cir_addr + IT8708_C0IER)
  669. |IT85_TLDLIE | IT85_IEC,
  670. dev->cir_addr + IT8708_C0IER);
  671. }
  672. /* disable the device; this must be called with the device spinlock held */
  673. static void it8708_disable(struct ite_dev *dev)
  674. {
  675. /* clear out all interrupt enable flags */
  676. outb(inb(dev->cir_addr + IT8708_C0IER) &
  677. ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
  678. dev->cir_addr + IT8708_C0IER);
  679. /* disable the receiver */
  680. it8708_disable_rx(dev);
  681. /* erase the FIFO */
  682. outb(IT85_FIFOCLR | inb(dev->cir_addr + IT8708_C0MSTCR),
  683. dev->cir_addr + IT8708_C0MSTCR);
  684. }
  685. /* initialize the hardware */
  686. static void it8708_init_hardware(struct ite_dev *dev)
  687. {
  688. /* disable all the interrupts */
  689. outb(inb(dev->cir_addr + IT8708_C0IER) &
  690. ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
  691. dev->cir_addr + IT8708_C0IER);
  692. /* program the baud rate divisor */
  693. outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
  694. dev->cir_addr + IT8708_BANKSEL);
  695. outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT8708_C0BDLR);
  696. outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
  697. dev->cir_addr + IT8708_C0BDHR);
  698. outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
  699. dev->cir_addr + IT8708_BANKSEL);
  700. /* program the C0MSTCR register defaults */
  701. outb((inb(dev->cir_addr + IT8708_C0MSTCR) &
  702. ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL |
  703. IT85_FIFOCLR | IT85_RESET)) |
  704. IT85_FIFOTL_DEFAULT,
  705. dev->cir_addr + IT8708_C0MSTCR);
  706. /* program the C0RCR register defaults */
  707. outb((inb(dev->cir_addr + IT8708_C0RCR) &
  708. ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND |
  709. IT85_RXACT | IT85_RXDCR)) |
  710. ITE_RXDCR_DEFAULT,
  711. dev->cir_addr + IT8708_C0RCR);
  712. /* program the C0TCR register defaults */
  713. outb((inb(dev->cir_addr + IT8708_C0TCR) &
  714. ~(IT85_TXMPM | IT85_TXMPW))
  715. |IT85_TXRLE | IT85_TXENDF |
  716. IT85_TXMPM_DEFAULT | IT85_TXMPW_DEFAULT,
  717. dev->cir_addr + IT8708_C0TCR);
  718. /* program the carrier parameters */
  719. ite_set_carrier_params(dev);
  720. }
  721. /* IT8512F on ITE8709 HW-specific functions */
  722. /* read a byte from the SRAM module */
  723. static inline u8 it8709_rm(struct ite_dev *dev, int index)
  724. {
  725. outb(index, dev->cir_addr + IT8709_RAM_IDX);
  726. return inb(dev->cir_addr + IT8709_RAM_VAL);
  727. }
  728. /* write a byte to the SRAM module */
  729. static inline void it8709_wm(struct ite_dev *dev, u8 val, int index)
  730. {
  731. outb(index, dev->cir_addr + IT8709_RAM_IDX);
  732. outb(val, dev->cir_addr + IT8709_RAM_VAL);
  733. }
  734. static void it8709_wait(struct ite_dev *dev)
  735. {
  736. int i = 0;
  737. /*
  738. * loop until device tells it's ready to continue
  739. * iterations count is usually ~750 but can sometimes achieve 13000
  740. */
  741. for (i = 0; i < 15000; i++) {
  742. udelay(2);
  743. if (it8709_rm(dev, IT8709_MODE) == IT8709_IDLE)
  744. break;
  745. }
  746. }
  747. /* read the value of a CIR register */
  748. static u8 it8709_rr(struct ite_dev *dev, int index)
  749. {
  750. /* just wait in case the previous access was a write */
  751. it8709_wait(dev);
  752. it8709_wm(dev, index, IT8709_REG_IDX);
  753. it8709_wm(dev, IT8709_READ, IT8709_MODE);
  754. /* wait for the read data to be available */
  755. it8709_wait(dev);
  756. /* return the read value */
  757. return it8709_rm(dev, IT8709_REG_VAL);
  758. }
  759. /* write the value of a CIR register */
  760. static void it8709_wr(struct ite_dev *dev, u8 val, int index)
  761. {
  762. /* we wait before writing, and not afterwards, since this allows us to
  763. * pipeline the host CPU with the microcontroller */
  764. it8709_wait(dev);
  765. it8709_wm(dev, val, IT8709_REG_VAL);
  766. it8709_wm(dev, index, IT8709_REG_IDX);
  767. it8709_wm(dev, IT8709_WRITE, IT8709_MODE);
  768. }
  769. /* retrieve a bitmask of the current causes for a pending interrupt; this may
  770. * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
  771. * */
  772. static int it8709_get_irq_causes(struct ite_dev *dev)
  773. {
  774. u8 iflags;
  775. int ret = 0;
  776. /* read the interrupt flags */
  777. iflags = it8709_rm(dev, IT8709_IIR);
  778. if (iflags & IT85_TLDLI)
  779. ret |= ITE_IRQ_TX_FIFO;
  780. if (iflags & IT85_RDAI)
  781. ret |= ITE_IRQ_RX_FIFO;
  782. if (iflags & IT85_RFOI)
  783. ret |= ITE_IRQ_RX_FIFO_OVERRUN;
  784. return ret;
  785. }
  786. /* set the carrier parameters; to be called with the spinlock held */
  787. static void it8709_set_carrier_params(struct ite_dev *dev, bool high_freq,
  788. bool use_demodulator,
  789. u8 carrier_freq_bits, u8 allowance_bits,
  790. u8 pulse_width_bits)
  791. {
  792. u8 val;
  793. val = (it8709_rr(dev, IT85_C0CFR)
  794. &~(IT85_HCFS | IT85_CFQ)) |
  795. carrier_freq_bits;
  796. if (high_freq)
  797. val |= IT85_HCFS;
  798. it8709_wr(dev, val, IT85_C0CFR);
  799. /* program the C0RCR register */
  800. val = it8709_rr(dev, IT85_C0RCR)
  801. & ~(IT85_RXEND | IT85_RXDCR);
  802. if (use_demodulator)
  803. val |= IT85_RXEND;
  804. val |= allowance_bits;
  805. it8709_wr(dev, val, IT85_C0RCR);
  806. /* program the C0TCR register */
  807. val = it8709_rr(dev, IT85_C0TCR) & ~IT85_TXMPW;
  808. val |= pulse_width_bits;
  809. it8709_wr(dev, val, IT85_C0TCR);
  810. }
  811. /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
  812. * held */
  813. static int it8709_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
  814. {
  815. int fifo, read = 0;
  816. /* read how many bytes are still in the FIFO */
  817. fifo = it8709_rm(dev, IT8709_RFSR) & IT85_RXFBC;
  818. while (fifo > 0 && buf_size > 0) {
  819. *(buf++) = it8709_rm(dev, IT8709_FIFO + read);
  820. fifo--;
  821. read++;
  822. buf_size--;
  823. }
  824. /* 'clear' the FIFO by setting the writing index to 0; this is
  825. * completely bound to be racy, but we can't help it, since it's a
  826. * limitation of the protocol */
  827. it8709_wm(dev, 0, IT8709_RFSR);
  828. return read;
  829. }
  830. /* return how many bytes are still in the FIFO; this will be called
  831. * with the device spinlock NOT HELD while waiting for the TX FIFO to get
  832. * empty; let's expect this won't be a problem */
  833. static int it8709_get_tx_used_slots(struct ite_dev *dev)
  834. {
  835. return it8709_rr(dev, IT85_C0TFSR) & IT85_TXFBC;
  836. }
  837. /* put a byte to the TX fifo; this should be called with the spinlock held */
  838. static void it8709_put_tx_byte(struct ite_dev *dev, u8 value)
  839. {
  840. it8709_wr(dev, value, IT85_C0DR);
  841. }
  842. /* idle the receiver so that we won't receive samples until another
  843. pulse is detected; this must be called with the device spinlock held */
  844. static void it8709_idle_rx(struct ite_dev *dev)
  845. {
  846. /* disable streaming by clearing RXACT writing it as 1 */
  847. it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXACT,
  848. IT85_C0RCR);
  849. /* clear the FIFO */
  850. it8709_wr(dev, it8709_rr(dev, IT85_C0MSTCR) | IT85_FIFOCLR,
  851. IT85_C0MSTCR);
  852. }
  853. /* disable the receiver; this must be called with the device spinlock held */
  854. static void it8709_disable_rx(struct ite_dev *dev)
  855. {
  856. /* disable the receiver interrupts */
  857. it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
  858. ~(IT85_RDAIE | IT85_RFOIE),
  859. IT85_C0IER);
  860. /* disable the receiver */
  861. it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) & ~IT85_RXEN,
  862. IT85_C0RCR);
  863. /* clear the FIFO and RXACT (actually RXACT should have been cleared
  864. * in the previous it8709_wr(dev, ) call) */
  865. it8709_idle_rx(dev);
  866. }
  867. /* enable the receiver; this must be called with the device spinlock held */
  868. static void it8709_enable_rx(struct ite_dev *dev)
  869. {
  870. /* enable the receiver by setting RXEN */
  871. it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXEN,
  872. IT85_C0RCR);
  873. /* just prepare it to idle for the next reception */
  874. it8709_idle_rx(dev);
  875. /* enable the receiver interrupts and master enable flag */
  876. it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
  877. |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
  878. IT85_C0IER);
  879. }
  880. /* disable the transmitter interrupt; this must be called with the device
  881. * spinlock held */
  882. static void it8709_disable_tx_interrupt(struct ite_dev *dev)
  883. {
  884. /* disable the transmitter interrupts */
  885. it8709_wr(dev, it8709_rr(dev, IT85_C0IER) & ~IT85_TLDLIE,
  886. IT85_C0IER);
  887. }
  888. /* enable the transmitter interrupt; this must be called with the device
  889. * spinlock held */
  890. static void it8709_enable_tx_interrupt(struct ite_dev *dev)
  891. {
  892. /* enable the transmitter interrupts and master enable flag */
  893. it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
  894. |IT85_TLDLIE | IT85_IEC,
  895. IT85_C0IER);
  896. }
  897. /* disable the device; this must be called with the device spinlock held */
  898. static void it8709_disable(struct ite_dev *dev)
  899. {
  900. /* clear out all interrupt enable flags */
  901. it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
  902. ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
  903. IT85_C0IER);
  904. /* disable the receiver */
  905. it8709_disable_rx(dev);
  906. /* erase the FIFO */
  907. it8709_wr(dev, IT85_FIFOCLR | it8709_rr(dev, IT85_C0MSTCR),
  908. IT85_C0MSTCR);
  909. }
  910. /* initialize the hardware */
  911. static void it8709_init_hardware(struct ite_dev *dev)
  912. {
  913. /* disable all the interrupts */
  914. it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
  915. ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
  916. IT85_C0IER);
  917. /* program the baud rate divisor */
  918. it8709_wr(dev, ITE_BAUDRATE_DIVISOR & 0xff, IT85_C0BDLR);
  919. it8709_wr(dev, (ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
  920. IT85_C0BDHR);
  921. /* program the C0MSTCR register defaults */
  922. it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) &
  923. ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL
  924. | IT85_FIFOCLR | IT85_RESET)) | IT85_FIFOTL_DEFAULT,
  925. IT85_C0MSTCR);
  926. /* program the C0RCR register defaults */
  927. it8709_wr(dev, (it8709_rr(dev, IT85_C0RCR) &
  928. ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND | IT85_RXACT
  929. | IT85_RXDCR)) | ITE_RXDCR_DEFAULT,
  930. IT85_C0RCR);
  931. /* program the C0TCR register defaults */
  932. it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR) & ~(IT85_TXMPM | IT85_TXMPW))
  933. | IT85_TXRLE | IT85_TXENDF | IT85_TXMPM_DEFAULT
  934. | IT85_TXMPW_DEFAULT,
  935. IT85_C0TCR);
  936. /* program the carrier parameters */
  937. ite_set_carrier_params(dev);
  938. }
  939. /* generic hardware setup/teardown code */
  940. /* activate the device for use */
  941. static int ite_open(struct rc_dev *rcdev)
  942. {
  943. struct ite_dev *dev = rcdev->priv;
  944. unsigned long flags;
  945. spin_lock_irqsave(&dev->lock, flags);
  946. /* enable the receiver */
  947. dev->params->enable_rx(dev);
  948. spin_unlock_irqrestore(&dev->lock, flags);
  949. return 0;
  950. }
  951. /* deactivate the device for use */
  952. static void ite_close(struct rc_dev *rcdev)
  953. {
  954. struct ite_dev *dev = rcdev->priv;
  955. unsigned long flags;
  956. spin_lock_irqsave(&dev->lock, flags);
  957. /* wait for any transmission to end */
  958. spin_unlock_irqrestore(&dev->lock, flags);
  959. wait_event_interruptible(dev->tx_ended, !dev->transmitting);
  960. spin_lock_irqsave(&dev->lock, flags);
  961. dev->params->disable(dev);
  962. spin_unlock_irqrestore(&dev->lock, flags);
  963. }
  964. /* supported models and their parameters */
  965. static const struct ite_dev_params ite_dev_descs[] = {
  966. { /* 0: ITE8704 */
  967. .model = "ITE8704 CIR transceiver",
  968. .io_region_size = IT87_IOREG_LENGTH,
  969. .io_rsrc_no = 0,
  970. /* operations */
  971. .get_irq_causes = it87_get_irq_causes,
  972. .enable_rx = it87_enable_rx,
  973. .idle_rx = it87_idle_rx,
  974. .disable_rx = it87_idle_rx,
  975. .get_rx_bytes = it87_get_rx_bytes,
  976. .enable_tx_interrupt = it87_enable_tx_interrupt,
  977. .disable_tx_interrupt = it87_disable_tx_interrupt,
  978. .get_tx_used_slots = it87_get_tx_used_slots,
  979. .put_tx_byte = it87_put_tx_byte,
  980. .disable = it87_disable,
  981. .init_hardware = it87_init_hardware,
  982. .set_carrier_params = it87_set_carrier_params,
  983. },
  984. { /* 1: ITE8713 */
  985. .model = "ITE8713 CIR transceiver",
  986. .io_region_size = IT87_IOREG_LENGTH,
  987. .io_rsrc_no = 0,
  988. /* operations */
  989. .get_irq_causes = it87_get_irq_causes,
  990. .enable_rx = it87_enable_rx,
  991. .idle_rx = it87_idle_rx,
  992. .disable_rx = it87_idle_rx,
  993. .get_rx_bytes = it87_get_rx_bytes,
  994. .enable_tx_interrupt = it87_enable_tx_interrupt,
  995. .disable_tx_interrupt = it87_disable_tx_interrupt,
  996. .get_tx_used_slots = it87_get_tx_used_slots,
  997. .put_tx_byte = it87_put_tx_byte,
  998. .disable = it87_disable,
  999. .init_hardware = it87_init_hardware,
  1000. .set_carrier_params = it87_set_carrier_params,
  1001. },
  1002. { /* 2: ITE8708 */
  1003. .model = "ITE8708 CIR transceiver",
  1004. .io_region_size = IT8708_IOREG_LENGTH,
  1005. .io_rsrc_no = 0,
  1006. /* operations */
  1007. .get_irq_causes = it8708_get_irq_causes,
  1008. .enable_rx = it8708_enable_rx,
  1009. .idle_rx = it8708_idle_rx,
  1010. .disable_rx = it8708_idle_rx,
  1011. .get_rx_bytes = it8708_get_rx_bytes,
  1012. .enable_tx_interrupt = it8708_enable_tx_interrupt,
  1013. .disable_tx_interrupt =
  1014. it8708_disable_tx_interrupt,
  1015. .get_tx_used_slots = it8708_get_tx_used_slots,
  1016. .put_tx_byte = it8708_put_tx_byte,
  1017. .disable = it8708_disable,
  1018. .init_hardware = it8708_init_hardware,
  1019. .set_carrier_params = it8708_set_carrier_params,
  1020. },
  1021. { /* 3: ITE8709 */
  1022. .model = "ITE8709 CIR transceiver",
  1023. .io_region_size = IT8709_IOREG_LENGTH,
  1024. .io_rsrc_no = 2,
  1025. /* operations */
  1026. .get_irq_causes = it8709_get_irq_causes,
  1027. .enable_rx = it8709_enable_rx,
  1028. .idle_rx = it8709_idle_rx,
  1029. .disable_rx = it8709_idle_rx,
  1030. .get_rx_bytes = it8709_get_rx_bytes,
  1031. .enable_tx_interrupt = it8709_enable_tx_interrupt,
  1032. .disable_tx_interrupt =
  1033. it8709_disable_tx_interrupt,
  1034. .get_tx_used_slots = it8709_get_tx_used_slots,
  1035. .put_tx_byte = it8709_put_tx_byte,
  1036. .disable = it8709_disable,
  1037. .init_hardware = it8709_init_hardware,
  1038. .set_carrier_params = it8709_set_carrier_params,
  1039. },
  1040. };
  1041. static const struct pnp_device_id ite_ids[] = {
  1042. {"ITE8704", 0}, /* Default model */
  1043. {"ITE8713", 1}, /* CIR found in EEEBox 1501U */
  1044. {"ITE8708", 2}, /* Bridged IT8512 */
  1045. {"ITE8709", 3}, /* SRAM-Bridged IT8512 */
  1046. {"", 0},
  1047. };
  1048. /* allocate memory, probe hardware, and initialize everything */
  1049. static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id
  1050. *dev_id)
  1051. {
  1052. const struct ite_dev_params *dev_desc = NULL;
  1053. struct ite_dev *itdev = NULL;
  1054. struct rc_dev *rdev = NULL;
  1055. int ret = -ENOMEM;
  1056. int model_no;
  1057. int io_rsrc_no;
  1058. itdev = kzalloc(sizeof(struct ite_dev), GFP_KERNEL);
  1059. if (!itdev)
  1060. return ret;
  1061. /* input device for IR remote (and tx) */
  1062. rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
  1063. if (!rdev)
  1064. goto exit_free_dev_rdev;
  1065. itdev->rdev = rdev;
  1066. ret = -ENODEV;
  1067. /* get the model number */
  1068. model_no = (int)dev_id->driver_data;
  1069. dev_dbg(&pdev->dev, "Auto-detected model: %s\n",
  1070. ite_dev_descs[model_no].model);
  1071. if (model_number >= 0 && model_number < ARRAY_SIZE(ite_dev_descs)) {
  1072. model_no = model_number;
  1073. dev_info(&pdev->dev, "model has been forced to: %s",
  1074. ite_dev_descs[model_no].model);
  1075. }
  1076. /* get the description for the device */
  1077. dev_desc = &ite_dev_descs[model_no];
  1078. io_rsrc_no = dev_desc->io_rsrc_no;
  1079. /* validate pnp resources */
  1080. if (!pnp_port_valid(pdev, io_rsrc_no) ||
  1081. pnp_port_len(pdev, io_rsrc_no) < dev_desc->io_region_size) {
  1082. dev_err(&pdev->dev, "IR PNP Port not valid!\n");
  1083. goto exit_free_dev_rdev;
  1084. }
  1085. if (!pnp_irq_valid(pdev, 0)) {
  1086. dev_err(&pdev->dev, "PNP IRQ not valid!\n");
  1087. goto exit_free_dev_rdev;
  1088. }
  1089. /* store resource values */
  1090. itdev->cir_addr = pnp_port_start(pdev, io_rsrc_no);
  1091. itdev->cir_irq = pnp_irq(pdev, 0);
  1092. /* initialize spinlocks */
  1093. spin_lock_init(&itdev->lock);
  1094. /* set driver data into the pnp device */
  1095. pnp_set_drvdata(pdev, itdev);
  1096. itdev->pdev = pdev;
  1097. /* initialize waitqueues for transmission */
  1098. init_waitqueue_head(&itdev->tx_queue);
  1099. init_waitqueue_head(&itdev->tx_ended);
  1100. /* Set model-specific parameters */
  1101. itdev->params = dev_desc;
  1102. /* set up hardware initial state */
  1103. itdev->tx_duty_cycle = 33;
  1104. itdev->tx_carrier_freq = ITE_DEFAULT_CARRIER_FREQ;
  1105. itdev->params->init_hardware(itdev);
  1106. /* set up ir-core props */
  1107. rdev->priv = itdev;
  1108. rdev->dev.parent = &pdev->dev;
  1109. rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
  1110. rdev->open = ite_open;
  1111. rdev->close = ite_close;
  1112. rdev->s_idle = ite_s_idle;
  1113. rdev->s_rx_carrier_range = ite_set_rx_carrier_range;
  1114. /* FIFO threshold is 17 bytes, so 17 * 8 samples minimum */
  1115. rdev->min_timeout = 17 * 8 * ITE_BAUDRATE_DIVISOR *
  1116. sample_period / 1000;
  1117. rdev->timeout = IR_DEFAULT_TIMEOUT;
  1118. rdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
  1119. rdev->rx_resolution = ITE_BAUDRATE_DIVISOR * sample_period / 1000;
  1120. rdev->tx_resolution = ITE_BAUDRATE_DIVISOR * sample_period / 1000;
  1121. /* set up transmitter related values */
  1122. rdev->tx_ir = ite_tx_ir;
  1123. rdev->s_tx_carrier = ite_set_tx_carrier;
  1124. rdev->s_tx_duty_cycle = ite_set_tx_duty_cycle;
  1125. rdev->device_name = dev_desc->model;
  1126. rdev->input_id.bustype = BUS_HOST;
  1127. rdev->input_id.vendor = PCI_VENDOR_ID_ITE;
  1128. rdev->input_id.product = 0;
  1129. rdev->input_id.version = 0;
  1130. rdev->driver_name = ITE_DRIVER_NAME;
  1131. rdev->map_name = RC_MAP_RC6_MCE;
  1132. ret = rc_register_device(rdev);
  1133. if (ret)
  1134. goto exit_free_dev_rdev;
  1135. ret = -EBUSY;
  1136. /* now claim resources */
  1137. if (!request_region(itdev->cir_addr,
  1138. dev_desc->io_region_size, ITE_DRIVER_NAME))
  1139. goto exit_unregister_device;
  1140. if (request_irq(itdev->cir_irq, ite_cir_isr, IRQF_SHARED,
  1141. ITE_DRIVER_NAME, (void *)itdev))
  1142. goto exit_release_cir_addr;
  1143. return 0;
  1144. exit_release_cir_addr:
  1145. release_region(itdev->cir_addr, itdev->params->io_region_size);
  1146. exit_unregister_device:
  1147. rc_unregister_device(rdev);
  1148. rdev = NULL;
  1149. exit_free_dev_rdev:
  1150. rc_free_device(rdev);
  1151. kfree(itdev);
  1152. return ret;
  1153. }
  1154. static void ite_remove(struct pnp_dev *pdev)
  1155. {
  1156. struct ite_dev *dev = pnp_get_drvdata(pdev);
  1157. unsigned long flags;
  1158. spin_lock_irqsave(&dev->lock, flags);
  1159. /* disable hardware */
  1160. dev->params->disable(dev);
  1161. spin_unlock_irqrestore(&dev->lock, flags);
  1162. /* free resources */
  1163. free_irq(dev->cir_irq, dev);
  1164. release_region(dev->cir_addr, dev->params->io_region_size);
  1165. rc_unregister_device(dev->rdev);
  1166. kfree(dev);
  1167. }
  1168. static int ite_suspend(struct pnp_dev *pdev, pm_message_t state)
  1169. {
  1170. struct ite_dev *dev = pnp_get_drvdata(pdev);
  1171. unsigned long flags;
  1172. /* wait for any transmission to end */
  1173. wait_event_interruptible(dev->tx_ended, !dev->transmitting);
  1174. spin_lock_irqsave(&dev->lock, flags);
  1175. /* disable all interrupts */
  1176. dev->params->disable(dev);
  1177. spin_unlock_irqrestore(&dev->lock, flags);
  1178. return 0;
  1179. }
  1180. static int ite_resume(struct pnp_dev *pdev)
  1181. {
  1182. struct ite_dev *dev = pnp_get_drvdata(pdev);
  1183. unsigned long flags;
  1184. spin_lock_irqsave(&dev->lock, flags);
  1185. /* reinitialize hardware config registers */
  1186. dev->params->init_hardware(dev);
  1187. /* enable the receiver */
  1188. dev->params->enable_rx(dev);
  1189. spin_unlock_irqrestore(&dev->lock, flags);
  1190. return 0;
  1191. }
  1192. static void ite_shutdown(struct pnp_dev *pdev)
  1193. {
  1194. struct ite_dev *dev = pnp_get_drvdata(pdev);
  1195. unsigned long flags;
  1196. spin_lock_irqsave(&dev->lock, flags);
  1197. /* disable all interrupts */
  1198. dev->params->disable(dev);
  1199. spin_unlock_irqrestore(&dev->lock, flags);
  1200. }
  1201. static struct pnp_driver ite_driver = {
  1202. .name = ITE_DRIVER_NAME,
  1203. .id_table = ite_ids,
  1204. .probe = ite_probe,
  1205. .remove = ite_remove,
  1206. .suspend = ite_suspend,
  1207. .resume = ite_resume,
  1208. .shutdown = ite_shutdown,
  1209. };
  1210. MODULE_DEVICE_TABLE(pnp, ite_ids);
  1211. MODULE_DESCRIPTION("ITE Tech Inc. IT8712F/ITE8512F CIR driver");
  1212. MODULE_AUTHOR("Juan J. Garcia de Soria <[email protected]>");
  1213. MODULE_LICENSE("GPL");
  1214. module_pnp_driver(ite_driver);