coda-bit.c 76 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Coda multi-standard codec IP - BIT processor functions
  4. *
  5. * Copyright (C) 2012 Vista Silicon S.L.
  6. * Javier Martin, <[email protected]>
  7. * Xavier Duret
  8. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/irqreturn.h>
  12. #include <linux/kernel.h>
  13. #include <linux/log2.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/ratelimit.h>
  16. #include <linux/reset.h>
  17. #include <linux/slab.h>
  18. #include <linux/videodev2.h>
  19. #include <media/v4l2-common.h>
  20. #include <media/v4l2-ctrls.h>
  21. #include <media/v4l2-fh.h>
  22. #include <media/v4l2-mem2mem.h>
  23. #include <media/videobuf2-v4l2.h>
  24. #include <media/videobuf2-dma-contig.h>
  25. #include <media/videobuf2-vmalloc.h>
  26. #include "coda.h"
  27. #include "imx-vdoa.h"
  28. #define CREATE_TRACE_POINTS
  29. #include "trace.h"
  30. #define CODA_PARA_BUF_SIZE (10 * 1024)
  31. #define CODA7_PS_BUF_SIZE 0x28000
  32. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  33. #define CODA_DEFAULT_GAMMA 4096
  34. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  35. static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  36. static inline int coda_is_initialized(struct coda_dev *dev)
  37. {
  38. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  39. }
  40. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  41. {
  42. return coda_read(dev, CODA_REG_BIT_BUSY);
  43. }
  44. static int coda_wait_timeout(struct coda_dev *dev)
  45. {
  46. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  47. while (coda_isbusy(dev)) {
  48. if (time_after(jiffies, timeout))
  49. return -ETIMEDOUT;
  50. }
  51. return 0;
  52. }
  53. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  54. {
  55. struct coda_dev *dev = ctx->dev;
  56. if (dev->devtype->product == CODA_HX4 ||
  57. dev->devtype->product == CODA_7541 ||
  58. dev->devtype->product == CODA_960) {
  59. /* Restore context related registers to CODA */
  60. coda_write(dev, ctx->bit_stream_param,
  61. CODA_REG_BIT_BIT_STREAM_PARAM);
  62. coda_write(dev, ctx->frm_dis_flg,
  63. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  64. coda_write(dev, ctx->frame_mem_ctrl,
  65. CODA_REG_BIT_FRAME_MEM_CTRL);
  66. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  67. }
  68. if (dev->devtype->product == CODA_960) {
  69. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  70. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  71. }
  72. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  73. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  74. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  75. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  76. trace_coda_bit_run(ctx, cmd);
  77. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  78. }
  79. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  80. {
  81. struct coda_dev *dev = ctx->dev;
  82. int ret;
  83. lockdep_assert_held(&dev->coda_mutex);
  84. coda_command_async(ctx, cmd);
  85. ret = coda_wait_timeout(dev);
  86. trace_coda_bit_done(ctx);
  87. return ret;
  88. }
  89. int coda_hw_reset(struct coda_ctx *ctx)
  90. {
  91. struct coda_dev *dev = ctx->dev;
  92. unsigned long timeout;
  93. unsigned int idx;
  94. int ret;
  95. lockdep_assert_held(&dev->coda_mutex);
  96. if (!dev->rstc)
  97. return -ENOENT;
  98. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  99. if (dev->devtype->product == CODA_960) {
  100. timeout = jiffies + msecs_to_jiffies(100);
  101. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  102. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  103. if (time_after(jiffies, timeout))
  104. return -ETIME;
  105. cpu_relax();
  106. }
  107. }
  108. ret = reset_control_reset(dev->rstc);
  109. if (ret < 0)
  110. return ret;
  111. if (dev->devtype->product == CODA_960)
  112. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  113. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  114. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  115. ret = coda_wait_timeout(dev);
  116. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  117. return ret;
  118. }
  119. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  120. {
  121. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  122. struct coda_dev *dev = ctx->dev;
  123. u32 rd_ptr;
  124. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  125. kfifo->out = (kfifo->in & ~kfifo->mask) |
  126. (rd_ptr - ctx->bitstream.paddr);
  127. if (kfifo->out > kfifo->in)
  128. kfifo->out -= kfifo->mask + 1;
  129. }
  130. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  131. {
  132. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  133. struct coda_dev *dev = ctx->dev;
  134. u32 rd_ptr, wr_ptr;
  135. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  136. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  137. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  138. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  139. }
  140. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  141. {
  142. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  143. struct coda_dev *dev = ctx->dev;
  144. u32 wr_ptr;
  145. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  146. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  147. }
  148. static int coda_h264_bitstream_pad(struct coda_ctx *ctx, u32 size)
  149. {
  150. unsigned char *buf;
  151. u32 n;
  152. if (size < 6)
  153. size = 6;
  154. buf = kmalloc(size, GFP_KERNEL);
  155. if (!buf)
  156. return -ENOMEM;
  157. coda_h264_filler_nal(size, buf);
  158. n = kfifo_in(&ctx->bitstream_fifo, buf, size);
  159. kfree(buf);
  160. return (n < size) ? -ENOSPC : 0;
  161. }
  162. int coda_bitstream_flush(struct coda_ctx *ctx)
  163. {
  164. int ret;
  165. if (ctx->inst_type != CODA_INST_DECODER || !ctx->use_bit)
  166. return 0;
  167. ret = coda_command_sync(ctx, CODA_COMMAND_DEC_BUF_FLUSH);
  168. if (ret < 0) {
  169. v4l2_err(&ctx->dev->v4l2_dev, "failed to flush bitstream\n");
  170. return ret;
  171. }
  172. kfifo_init(&ctx->bitstream_fifo, ctx->bitstream.vaddr,
  173. ctx->bitstream.size);
  174. coda_kfifo_sync_to_device_full(ctx);
  175. return 0;
  176. }
  177. static int coda_bitstream_queue(struct coda_ctx *ctx, const u8 *buf, u32 size)
  178. {
  179. u32 n = kfifo_in(&ctx->bitstream_fifo, buf, size);
  180. return (n < size) ? -ENOSPC : 0;
  181. }
  182. static u32 coda_buffer_parse_headers(struct coda_ctx *ctx,
  183. struct vb2_v4l2_buffer *src_buf,
  184. u32 payload)
  185. {
  186. u8 *vaddr = vb2_plane_vaddr(&src_buf->vb2_buf, 0);
  187. u32 size = 0;
  188. switch (ctx->codec->src_fourcc) {
  189. case V4L2_PIX_FMT_MPEG2:
  190. size = coda_mpeg2_parse_headers(ctx, vaddr, payload);
  191. break;
  192. case V4L2_PIX_FMT_MPEG4:
  193. size = coda_mpeg4_parse_headers(ctx, vaddr, payload);
  194. break;
  195. default:
  196. break;
  197. }
  198. return size;
  199. }
  200. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  201. struct vb2_v4l2_buffer *src_buf)
  202. {
  203. unsigned long payload = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
  204. u8 *vaddr = vb2_plane_vaddr(&src_buf->vb2_buf, 0);
  205. int ret;
  206. int i;
  207. if (coda_get_bitstream_payload(ctx) + payload + 512 >=
  208. ctx->bitstream.size)
  209. return false;
  210. if (!vaddr) {
  211. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  212. return true;
  213. }
  214. if (ctx->qsequence == 0 && payload < 512) {
  215. /*
  216. * Add padding after the first buffer, if it is too small to be
  217. * fetched by the CODA, by repeating the headers. Without
  218. * repeated headers, or the first frame already queued, decoder
  219. * sequence initialization fails with error code 0x2000 on i.MX6
  220. * or error code 0x1 on i.MX51.
  221. */
  222. u32 header_size = coda_buffer_parse_headers(ctx, src_buf,
  223. payload);
  224. if (header_size) {
  225. coda_dbg(1, ctx, "pad with %u-byte header\n",
  226. header_size);
  227. for (i = payload; i < 512; i += header_size) {
  228. ret = coda_bitstream_queue(ctx, vaddr,
  229. header_size);
  230. if (ret < 0) {
  231. v4l2_err(&ctx->dev->v4l2_dev,
  232. "bitstream buffer overflow\n");
  233. return false;
  234. }
  235. if (ctx->dev->devtype->product == CODA_960)
  236. break;
  237. }
  238. } else {
  239. coda_dbg(1, ctx,
  240. "could not parse header, sequence initialization might fail\n");
  241. }
  242. /* Add padding before the first buffer, if it is too small */
  243. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
  244. coda_h264_bitstream_pad(ctx, 512 - payload);
  245. }
  246. ret = coda_bitstream_queue(ctx, vaddr, payload);
  247. if (ret < 0) {
  248. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  249. return false;
  250. }
  251. src_buf->sequence = ctx->qsequence++;
  252. /* Sync read pointer to device */
  253. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  254. coda_kfifo_sync_to_device_write(ctx);
  255. /* Set the stream-end flag after the last buffer is queued */
  256. if (src_buf->flags & V4L2_BUF_FLAG_LAST)
  257. coda_bit_stream_end_flag(ctx);
  258. ctx->hold = false;
  259. return true;
  260. }
  261. void coda_fill_bitstream(struct coda_ctx *ctx, struct list_head *buffer_list)
  262. {
  263. struct vb2_v4l2_buffer *src_buf;
  264. struct coda_buffer_meta *meta;
  265. u32 start;
  266. lockdep_assert_held(&ctx->bitstream_mutex);
  267. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
  268. return;
  269. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  270. /*
  271. * Only queue two JPEGs into the bitstream buffer to keep
  272. * latency low. We need at least one complete buffer and the
  273. * header of another buffer (for prescan) in the bitstream.
  274. */
  275. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  276. ctx->num_metas > 1)
  277. break;
  278. if (ctx->num_internal_frames &&
  279. ctx->num_metas >= ctx->num_internal_frames) {
  280. meta = list_first_entry(&ctx->buffer_meta_list,
  281. struct coda_buffer_meta, list);
  282. /*
  283. * If we managed to fill in at least a full reorder
  284. * window of buffers (num_internal_frames is a
  285. * conservative estimate for this) and the bitstream
  286. * prefetcher has at least 2 256 bytes periods beyond
  287. * the first buffer to fetch, we can safely stop queuing
  288. * in order to limit the decoder drain latency.
  289. */
  290. if (coda_bitstream_can_fetch_past(ctx, meta->end))
  291. break;
  292. }
  293. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  294. /* Drop frames that do not start/end with a SOI/EOI markers */
  295. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  296. !coda_jpeg_check_buffer(ctx, &src_buf->vb2_buf)) {
  297. v4l2_err(&ctx->dev->v4l2_dev,
  298. "dropping invalid JPEG frame %d\n",
  299. ctx->qsequence);
  300. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  301. if (buffer_list) {
  302. struct v4l2_m2m_buffer *m2m_buf;
  303. m2m_buf = container_of(src_buf,
  304. struct v4l2_m2m_buffer,
  305. vb);
  306. list_add_tail(&m2m_buf->list, buffer_list);
  307. } else {
  308. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
  309. }
  310. continue;
  311. }
  312. /* Dump empty buffers */
  313. if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
  314. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  315. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  316. continue;
  317. }
  318. /* Buffer start position */
  319. start = ctx->bitstream_fifo.kfifo.in;
  320. if (coda_bitstream_try_queue(ctx, src_buf)) {
  321. /*
  322. * Source buffer is queued in the bitstream ringbuffer;
  323. * queue the timestamp and mark source buffer as done
  324. */
  325. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  326. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  327. if (meta) {
  328. meta->sequence = src_buf->sequence;
  329. meta->timecode = src_buf->timecode;
  330. meta->timestamp = src_buf->vb2_buf.timestamp;
  331. meta->start = start;
  332. meta->end = ctx->bitstream_fifo.kfifo.in;
  333. meta->last = src_buf->flags & V4L2_BUF_FLAG_LAST;
  334. if (meta->last)
  335. coda_dbg(1, ctx, "marking last meta");
  336. spin_lock(&ctx->buffer_meta_lock);
  337. list_add_tail(&meta->list,
  338. &ctx->buffer_meta_list);
  339. ctx->num_metas++;
  340. spin_unlock(&ctx->buffer_meta_lock);
  341. trace_coda_bit_queue(ctx, src_buf, meta);
  342. }
  343. if (buffer_list) {
  344. struct v4l2_m2m_buffer *m2m_buf;
  345. m2m_buf = container_of(src_buf,
  346. struct v4l2_m2m_buffer,
  347. vb);
  348. list_add_tail(&m2m_buf->list, buffer_list);
  349. } else {
  350. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  351. }
  352. } else {
  353. break;
  354. }
  355. }
  356. }
  357. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  358. {
  359. struct coda_dev *dev = ctx->dev;
  360. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  361. /* If this context is currently running, update the hardware flag */
  362. if ((dev->devtype->product == CODA_960) &&
  363. coda_isbusy(dev) &&
  364. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  365. coda_write(dev, ctx->bit_stream_param,
  366. CODA_REG_BIT_BIT_STREAM_PARAM);
  367. }
  368. }
  369. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  370. {
  371. struct coda_dev *dev = ctx->dev;
  372. u32 *p = ctx->parabuf.vaddr;
  373. if (dev->devtype->product == CODA_DX6)
  374. p[index] = value;
  375. else
  376. p[index ^ 1] = value;
  377. }
  378. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  379. struct coda_aux_buf *buf, size_t size,
  380. const char *name)
  381. {
  382. return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
  383. }
  384. static void coda_free_framebuffers(struct coda_ctx *ctx)
  385. {
  386. int i;
  387. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  388. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i].buf);
  389. }
  390. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  391. struct coda_q_data *q_data, u32 fourcc)
  392. {
  393. struct coda_dev *dev = ctx->dev;
  394. unsigned int ysize, ycbcr_size;
  395. int ret;
  396. int i;
  397. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  398. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 ||
  399. ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 ||
  400. ctx->codec->dst_fourcc == V4L2_PIX_FMT_MPEG4)
  401. ysize = round_up(q_data->rect.width, 16) *
  402. round_up(q_data->rect.height, 16);
  403. else
  404. ysize = round_up(q_data->rect.width, 8) * q_data->rect.height;
  405. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  406. ycbcr_size = round_up(ysize, 4096) + ysize / 2;
  407. else
  408. ycbcr_size = ysize + ysize / 2;
  409. /* Allocate frame buffers */
  410. for (i = 0; i < ctx->num_internal_frames; i++) {
  411. size_t size = ycbcr_size;
  412. char *name;
  413. /* Add space for mvcol buffers */
  414. if (dev->devtype->product != CODA_DX6 &&
  415. (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  416. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)))
  417. size += ysize / 4;
  418. name = kasprintf(GFP_KERNEL, "fb%d", i);
  419. if (!name) {
  420. coda_free_framebuffers(ctx);
  421. return -ENOMEM;
  422. }
  423. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i].buf,
  424. size, name);
  425. kfree(name);
  426. if (ret < 0) {
  427. coda_free_framebuffers(ctx);
  428. return ret;
  429. }
  430. }
  431. /* Register frame buffers in the parameter buffer */
  432. for (i = 0; i < ctx->num_internal_frames; i++) {
  433. u32 y, cb, cr, mvcol;
  434. /* Start addresses of Y, Cb, Cr planes */
  435. y = ctx->internal_frames[i].buf.paddr;
  436. cb = y + ysize;
  437. cr = y + ysize + ysize/4;
  438. mvcol = y + ysize + ysize/4 + ysize/4;
  439. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
  440. cb = round_up(cb, 4096);
  441. mvcol = cb + ysize/2;
  442. cr = 0;
  443. /* Packed 20-bit MSB of base addresses */
  444. /* YYYYYCCC, CCyyyyyc, cccc.... */
  445. y = (y & 0xfffff000) | cb >> 20;
  446. cb = (cb & 0x000ff000) << 12;
  447. }
  448. coda_parabuf_write(ctx, i * 3 + 0, y);
  449. coda_parabuf_write(ctx, i * 3 + 1, cb);
  450. coda_parabuf_write(ctx, i * 3 + 2, cr);
  451. if (dev->devtype->product == CODA_DX6)
  452. continue;
  453. /* mvcol buffer for h.264 and mpeg4 */
  454. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264)
  455. coda_parabuf_write(ctx, 96 + i, mvcol);
  456. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4 && i == 0)
  457. coda_parabuf_write(ctx, 97, mvcol);
  458. }
  459. return 0;
  460. }
  461. static void coda_free_context_buffers(struct coda_ctx *ctx)
  462. {
  463. struct coda_dev *dev = ctx->dev;
  464. coda_free_aux_buf(dev, &ctx->slicebuf);
  465. coda_free_aux_buf(dev, &ctx->psbuf);
  466. if (dev->devtype->product != CODA_DX6)
  467. coda_free_aux_buf(dev, &ctx->workbuf);
  468. coda_free_aux_buf(dev, &ctx->parabuf);
  469. }
  470. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  471. struct coda_q_data *q_data)
  472. {
  473. struct coda_dev *dev = ctx->dev;
  474. size_t size;
  475. int ret;
  476. if (!ctx->parabuf.vaddr) {
  477. ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
  478. CODA_PARA_BUF_SIZE, "parabuf");
  479. if (ret < 0)
  480. return ret;
  481. }
  482. if (dev->devtype->product == CODA_DX6)
  483. return 0;
  484. if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
  485. /* worst case slice size */
  486. size = (DIV_ROUND_UP(q_data->rect.width, 16) *
  487. DIV_ROUND_UP(q_data->rect.height, 16)) * 3200 / 8 + 512;
  488. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  489. "slicebuf");
  490. if (ret < 0)
  491. goto err;
  492. }
  493. if (!ctx->psbuf.vaddr && (dev->devtype->product == CODA_HX4 ||
  494. dev->devtype->product == CODA_7541)) {
  495. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  496. CODA7_PS_BUF_SIZE, "psbuf");
  497. if (ret < 0)
  498. goto err;
  499. }
  500. if (!ctx->workbuf.vaddr) {
  501. size = dev->devtype->workbuf_size;
  502. if (dev->devtype->product == CODA_960 &&
  503. q_data->fourcc == V4L2_PIX_FMT_H264)
  504. size += CODA9_PS_SAVE_SIZE;
  505. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
  506. "workbuf");
  507. if (ret < 0)
  508. goto err;
  509. }
  510. return 0;
  511. err:
  512. coda_free_context_buffers(ctx);
  513. return ret;
  514. }
  515. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
  516. int header_code, u8 *header, int *size)
  517. {
  518. struct vb2_buffer *vb = &buf->vb2_buf;
  519. struct coda_dev *dev = ctx->dev;
  520. struct coda_q_data *q_data_src;
  521. struct v4l2_rect *r;
  522. size_t bufsize;
  523. int ret;
  524. int i;
  525. if (dev->devtype->product == CODA_960)
  526. memset(vb2_plane_vaddr(vb, 0), 0, 64);
  527. coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
  528. CODA_CMD_ENC_HEADER_BB_START);
  529. bufsize = vb2_plane_size(vb, 0);
  530. if (dev->devtype->product == CODA_960)
  531. bufsize /= 1024;
  532. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  533. if (dev->devtype->product == CODA_960 &&
  534. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264 &&
  535. header_code == CODA_HEADER_H264_SPS) {
  536. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  537. r = &q_data_src->rect;
  538. if (r->width % 16 || r->height % 16) {
  539. u32 crop_right = round_up(r->width, 16) - r->width;
  540. u32 crop_bottom = round_up(r->height, 16) - r->height;
  541. coda_write(dev, crop_right,
  542. CODA9_CMD_ENC_HEADER_FRAME_CROP_H);
  543. coda_write(dev, crop_bottom,
  544. CODA9_CMD_ENC_HEADER_FRAME_CROP_V);
  545. header_code |= CODA9_HEADER_FRAME_CROP;
  546. }
  547. }
  548. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  549. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  550. if (ret < 0) {
  551. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  552. return ret;
  553. }
  554. if (dev->devtype->product == CODA_960) {
  555. for (i = 63; i > 0; i--)
  556. if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
  557. break;
  558. *size = i + 1;
  559. } else {
  560. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  561. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  562. }
  563. memcpy(header, vb2_plane_vaddr(vb, 0), *size);
  564. return 0;
  565. }
  566. static u32 coda_slice_mode(struct coda_ctx *ctx)
  567. {
  568. int size, unit;
  569. switch (ctx->params.slice_mode) {
  570. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  571. default:
  572. return 0;
  573. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB:
  574. size = ctx->params.slice_max_mb;
  575. unit = 1;
  576. break;
  577. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES:
  578. size = ctx->params.slice_max_bits;
  579. unit = 0;
  580. break;
  581. }
  582. return ((size & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET) |
  583. ((unit & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET) |
  584. ((1 & CODA_SLICING_MODE_MASK) << CODA_SLICING_MODE_OFFSET);
  585. }
  586. static int coda_enc_param_change(struct coda_ctx *ctx)
  587. {
  588. struct coda_dev *dev = ctx->dev;
  589. u32 change_enable = 0;
  590. u32 success;
  591. int ret;
  592. if (ctx->params.gop_size_changed) {
  593. change_enable |= CODA_PARAM_CHANGE_RC_GOP;
  594. coda_write(dev, ctx->params.gop_size,
  595. CODA_CMD_ENC_PARAM_RC_GOP);
  596. ctx->gopcounter = ctx->params.gop_size - 1;
  597. ctx->params.gop_size_changed = false;
  598. }
  599. if (ctx->params.h264_intra_qp_changed) {
  600. coda_dbg(1, ctx, "parameter change: intra Qp %u\n",
  601. ctx->params.h264_intra_qp);
  602. if (ctx->params.bitrate) {
  603. change_enable |= CODA_PARAM_CHANGE_RC_INTRA_QP;
  604. coda_write(dev, ctx->params.h264_intra_qp,
  605. CODA_CMD_ENC_PARAM_RC_INTRA_QP);
  606. }
  607. ctx->params.h264_intra_qp_changed = false;
  608. }
  609. if (ctx->params.bitrate_changed) {
  610. coda_dbg(1, ctx, "parameter change: bitrate %u kbit/s\n",
  611. ctx->params.bitrate);
  612. change_enable |= CODA_PARAM_CHANGE_RC_BITRATE;
  613. coda_write(dev, ctx->params.bitrate,
  614. CODA_CMD_ENC_PARAM_RC_BITRATE);
  615. ctx->params.bitrate_changed = false;
  616. }
  617. if (ctx->params.framerate_changed) {
  618. coda_dbg(1, ctx, "parameter change: frame rate %u/%u Hz\n",
  619. ctx->params.framerate & 0xffff,
  620. (ctx->params.framerate >> 16) + 1);
  621. change_enable |= CODA_PARAM_CHANGE_RC_FRAME_RATE;
  622. coda_write(dev, ctx->params.framerate,
  623. CODA_CMD_ENC_PARAM_RC_FRAME_RATE);
  624. ctx->params.framerate_changed = false;
  625. }
  626. if (ctx->params.intra_refresh_changed) {
  627. coda_dbg(1, ctx, "parameter change: intra refresh MBs %u\n",
  628. ctx->params.intra_refresh);
  629. change_enable |= CODA_PARAM_CHANGE_INTRA_MB_NUM;
  630. coda_write(dev, ctx->params.intra_refresh,
  631. CODA_CMD_ENC_PARAM_INTRA_MB_NUM);
  632. ctx->params.intra_refresh_changed = false;
  633. }
  634. if (ctx->params.slice_mode_changed) {
  635. change_enable |= CODA_PARAM_CHANGE_SLICE_MODE;
  636. coda_write(dev, coda_slice_mode(ctx),
  637. CODA_CMD_ENC_PARAM_SLICE_MODE);
  638. ctx->params.slice_mode_changed = false;
  639. }
  640. if (!change_enable)
  641. return 0;
  642. coda_write(dev, change_enable, CODA_CMD_ENC_PARAM_CHANGE_ENABLE);
  643. ret = coda_command_sync(ctx, CODA_COMMAND_RC_CHANGE_PARAMETER);
  644. if (ret < 0)
  645. return ret;
  646. success = coda_read(dev, CODA_RET_ENC_PARAM_CHANGE_SUCCESS);
  647. if (success != 1)
  648. coda_dbg(1, ctx, "parameter change failed: %u\n", success);
  649. return 0;
  650. }
  651. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  652. {
  653. phys_addr_t ret;
  654. size = round_up(size, 1024);
  655. if (size > iram->remaining)
  656. return 0;
  657. iram->remaining -= size;
  658. ret = iram->next_paddr;
  659. iram->next_paddr += size;
  660. return ret;
  661. }
  662. static void coda_setup_iram(struct coda_ctx *ctx)
  663. {
  664. struct coda_iram_info *iram_info = &ctx->iram_info;
  665. struct coda_dev *dev = ctx->dev;
  666. int w64, w128;
  667. int mb_width;
  668. int dbk_bits;
  669. int bit_bits;
  670. int ip_bits;
  671. int me_bits;
  672. memset(iram_info, 0, sizeof(*iram_info));
  673. iram_info->next_paddr = dev->iram.paddr;
  674. iram_info->remaining = dev->iram.size;
  675. if (!dev->iram.vaddr)
  676. return;
  677. switch (dev->devtype->product) {
  678. case CODA_HX4:
  679. dbk_bits = CODA7_USE_HOST_DBK_ENABLE;
  680. bit_bits = CODA7_USE_HOST_BIT_ENABLE;
  681. ip_bits = CODA7_USE_HOST_IP_ENABLE;
  682. me_bits = CODA7_USE_HOST_ME_ENABLE;
  683. break;
  684. case CODA_7541:
  685. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  686. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  687. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  688. me_bits = CODA7_USE_HOST_ME_ENABLE | CODA7_USE_ME_ENABLE;
  689. break;
  690. case CODA_960:
  691. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  692. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  693. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  694. me_bits = 0;
  695. break;
  696. default: /* CODA_DX6 */
  697. return;
  698. }
  699. if (ctx->inst_type == CODA_INST_ENCODER) {
  700. struct coda_q_data *q_data_src;
  701. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  702. mb_width = DIV_ROUND_UP(q_data_src->rect.width, 16);
  703. w128 = mb_width * 128;
  704. w64 = mb_width * 64;
  705. /* Prioritize in case IRAM is too small for everything */
  706. if (dev->devtype->product == CODA_HX4 ||
  707. dev->devtype->product == CODA_7541) {
  708. iram_info->search_ram_size = round_up(mb_width * 16 *
  709. 36 + 2048, 1024);
  710. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  711. iram_info->search_ram_size);
  712. if (!iram_info->search_ram_paddr) {
  713. pr_err("IRAM is smaller than the search ram size\n");
  714. goto out;
  715. }
  716. iram_info->axi_sram_use |= me_bits;
  717. }
  718. /* Only H.264BP and H.263P3 are considered */
  719. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  720. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  721. if (!iram_info->buf_dbk_y_use || !iram_info->buf_dbk_c_use)
  722. goto out;
  723. iram_info->axi_sram_use |= dbk_bits;
  724. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  725. if (!iram_info->buf_bit_use)
  726. goto out;
  727. iram_info->axi_sram_use |= bit_bits;
  728. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  729. if (!iram_info->buf_ip_ac_dc_use)
  730. goto out;
  731. iram_info->axi_sram_use |= ip_bits;
  732. /* OVL and BTP disabled for encoder */
  733. } else if (ctx->inst_type == CODA_INST_DECODER) {
  734. struct coda_q_data *q_data_dst;
  735. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  736. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  737. w128 = mb_width * 128;
  738. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  739. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  740. if (!iram_info->buf_dbk_y_use || !iram_info->buf_dbk_c_use)
  741. goto out;
  742. iram_info->axi_sram_use |= dbk_bits;
  743. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  744. if (!iram_info->buf_bit_use)
  745. goto out;
  746. iram_info->axi_sram_use |= bit_bits;
  747. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  748. if (!iram_info->buf_ip_ac_dc_use)
  749. goto out;
  750. iram_info->axi_sram_use |= ip_bits;
  751. /* OVL and BTP unused as there is no VC1 support yet */
  752. }
  753. out:
  754. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  755. coda_dbg(1, ctx, "IRAM smaller than needed\n");
  756. if (dev->devtype->product == CODA_HX4 ||
  757. dev->devtype->product == CODA_7541) {
  758. /* TODO - Enabling these causes picture errors on CODA7541 */
  759. if (ctx->inst_type == CODA_INST_DECODER) {
  760. /* fw 1.4.50 */
  761. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  762. CODA7_USE_IP_ENABLE);
  763. } else {
  764. /* fw 13.4.29 */
  765. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  766. CODA7_USE_HOST_DBK_ENABLE |
  767. CODA7_USE_IP_ENABLE |
  768. CODA7_USE_DBK_ENABLE);
  769. }
  770. }
  771. }
  772. static u32 coda_supported_firmwares[] = {
  773. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  774. CODA_FIRMWARE_VERNUM(CODA_HX4, 1, 4, 50),
  775. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  776. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  777. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 9),
  778. CODA_FIRMWARE_VERNUM(CODA_960, 2, 3, 10),
  779. CODA_FIRMWARE_VERNUM(CODA_960, 3, 1, 1),
  780. };
  781. static bool coda_firmware_supported(u32 vernum)
  782. {
  783. int i;
  784. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  785. if (vernum == coda_supported_firmwares[i])
  786. return true;
  787. return false;
  788. }
  789. int coda_check_firmware(struct coda_dev *dev)
  790. {
  791. u16 product, major, minor, release;
  792. u32 data;
  793. int ret;
  794. ret = clk_prepare_enable(dev->clk_per);
  795. if (ret)
  796. goto err_clk_per;
  797. ret = clk_prepare_enable(dev->clk_ahb);
  798. if (ret)
  799. goto err_clk_ahb;
  800. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  801. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  802. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  803. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  804. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  805. if (coda_wait_timeout(dev)) {
  806. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  807. ret = -EIO;
  808. goto err_run_cmd;
  809. }
  810. if (dev->devtype->product == CODA_960) {
  811. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  812. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  813. data);
  814. }
  815. /* Check we are compatible with the loaded firmware */
  816. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  817. product = CODA_FIRMWARE_PRODUCT(data);
  818. major = CODA_FIRMWARE_MAJOR(data);
  819. minor = CODA_FIRMWARE_MINOR(data);
  820. release = CODA_FIRMWARE_RELEASE(data);
  821. clk_disable_unprepare(dev->clk_per);
  822. clk_disable_unprepare(dev->clk_ahb);
  823. if (product != dev->devtype->product) {
  824. v4l2_err(&dev->v4l2_dev,
  825. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  826. coda_product_name(dev->devtype->product),
  827. coda_product_name(product), major, minor, release);
  828. return -EINVAL;
  829. }
  830. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  831. coda_product_name(product));
  832. if (coda_firmware_supported(data)) {
  833. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  834. major, minor, release);
  835. } else {
  836. v4l2_warn(&dev->v4l2_dev,
  837. "Unsupported firmware version: %u.%u.%u\n",
  838. major, minor, release);
  839. }
  840. return 0;
  841. err_run_cmd:
  842. clk_disable_unprepare(dev->clk_ahb);
  843. err_clk_ahb:
  844. clk_disable_unprepare(dev->clk_per);
  845. err_clk_per:
  846. return ret;
  847. }
  848. static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
  849. {
  850. u32 cache_size, cache_config;
  851. if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
  852. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  853. cache_size = 0x20262024;
  854. cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
  855. } else {
  856. /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
  857. cache_size = 0x02440243;
  858. cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
  859. }
  860. coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  861. if (fourcc == V4L2_PIX_FMT_NV12 || fourcc == V4L2_PIX_FMT_YUYV) {
  862. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  863. 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  864. 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  865. } else {
  866. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  867. 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  868. 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  869. }
  870. coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  871. }
  872. /*
  873. * Encoder context operations
  874. */
  875. static int coda_encoder_reqbufs(struct coda_ctx *ctx,
  876. struct v4l2_requestbuffers *rb)
  877. {
  878. struct coda_q_data *q_data_src;
  879. int ret;
  880. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  881. return 0;
  882. if (rb->count) {
  883. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  884. ret = coda_alloc_context_buffers(ctx, q_data_src);
  885. if (ret < 0)
  886. return ret;
  887. } else {
  888. coda_free_context_buffers(ctx);
  889. }
  890. return 0;
  891. }
  892. static int coda_start_encoding(struct coda_ctx *ctx)
  893. {
  894. struct coda_dev *dev = ctx->dev;
  895. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  896. struct coda_q_data *q_data_src, *q_data_dst;
  897. u32 bitstream_buf, bitstream_size;
  898. struct vb2_v4l2_buffer *buf;
  899. int gamma, ret, value;
  900. u32 dst_fourcc;
  901. int num_fb;
  902. u32 stride;
  903. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  904. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  905. dst_fourcc = q_data_dst->fourcc;
  906. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  907. bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
  908. bitstream_size = q_data_dst->sizeimage;
  909. if (!coda_is_initialized(dev)) {
  910. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  911. return -EFAULT;
  912. }
  913. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  914. if (!ctx->params.jpeg_qmat_tab[0]) {
  915. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  916. if (!ctx->params.jpeg_qmat_tab[0])
  917. return -ENOMEM;
  918. }
  919. if (!ctx->params.jpeg_qmat_tab[1]) {
  920. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  921. if (!ctx->params.jpeg_qmat_tab[1])
  922. return -ENOMEM;
  923. }
  924. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  925. }
  926. mutex_lock(&dev->coda_mutex);
  927. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  928. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  929. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  930. switch (dev->devtype->product) {
  931. case CODA_DX6:
  932. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  933. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  934. break;
  935. case CODA_960:
  936. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  937. fallthrough;
  938. case CODA_HX4:
  939. case CODA_7541:
  940. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  941. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  942. break;
  943. }
  944. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  945. CODA9_FRAME_TILED2LINEAR);
  946. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  947. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  948. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  949. ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
  950. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  951. if (dev->devtype->product == CODA_DX6) {
  952. /* Configure the coda */
  953. coda_write(dev, dev->iram.paddr,
  954. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  955. }
  956. /* Could set rotation here if needed */
  957. value = 0;
  958. switch (dev->devtype->product) {
  959. case CODA_DX6:
  960. value = (q_data_src->rect.width & CODADX6_PICWIDTH_MASK)
  961. << CODADX6_PICWIDTH_OFFSET;
  962. value |= (q_data_src->rect.height & CODADX6_PICHEIGHT_MASK)
  963. << CODA_PICHEIGHT_OFFSET;
  964. break;
  965. case CODA_HX4:
  966. case CODA_7541:
  967. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  968. value = (round_up(q_data_src->rect.width, 16) &
  969. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  970. value |= (round_up(q_data_src->rect.height, 16) &
  971. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  972. break;
  973. }
  974. fallthrough;
  975. case CODA_960:
  976. value = (q_data_src->rect.width & CODA7_PICWIDTH_MASK)
  977. << CODA7_PICWIDTH_OFFSET;
  978. value |= (q_data_src->rect.height & CODA7_PICHEIGHT_MASK)
  979. << CODA_PICHEIGHT_OFFSET;
  980. }
  981. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  982. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  983. ctx->params.framerate = 0;
  984. coda_write(dev, ctx->params.framerate,
  985. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  986. ctx->params.codec_mode = ctx->codec->mode;
  987. switch (dst_fourcc) {
  988. case V4L2_PIX_FMT_MPEG4:
  989. if (dev->devtype->product == CODA_960)
  990. coda_write(dev, CODA9_STD_MPEG4,
  991. CODA_CMD_ENC_SEQ_COD_STD);
  992. else
  993. coda_write(dev, CODA_STD_MPEG4,
  994. CODA_CMD_ENC_SEQ_COD_STD);
  995. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  996. break;
  997. case V4L2_PIX_FMT_H264:
  998. if (dev->devtype->product == CODA_960)
  999. coda_write(dev, CODA9_STD_H264,
  1000. CODA_CMD_ENC_SEQ_COD_STD);
  1001. else
  1002. coda_write(dev, CODA_STD_H264,
  1003. CODA_CMD_ENC_SEQ_COD_STD);
  1004. value = ((ctx->params.h264_disable_deblocking_filter_idc &
  1005. CODA_264PARAM_DISABLEDEBLK_MASK) <<
  1006. CODA_264PARAM_DISABLEDEBLK_OFFSET) |
  1007. ((ctx->params.h264_slice_alpha_c0_offset_div2 &
  1008. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  1009. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  1010. ((ctx->params.h264_slice_beta_offset_div2 &
  1011. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  1012. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET) |
  1013. (ctx->params.h264_constrained_intra_pred_flag <<
  1014. CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_OFFSET) |
  1015. (ctx->params.h264_chroma_qp_index_offset &
  1016. CODA_264PARAM_CHROMAQPOFFSET_MASK);
  1017. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  1018. break;
  1019. case V4L2_PIX_FMT_JPEG:
  1020. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  1021. coda_write(dev, ctx->params.jpeg_restart_interval,
  1022. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  1023. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  1024. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  1025. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  1026. coda_jpeg_write_tables(ctx);
  1027. break;
  1028. default:
  1029. v4l2_err(v4l2_dev,
  1030. "dst format (0x%08x) invalid.\n", dst_fourcc);
  1031. ret = -EINVAL;
  1032. goto out;
  1033. }
  1034. /*
  1035. * slice mode and GOP size registers are used for thumb size/offset
  1036. * in JPEG mode
  1037. */
  1038. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  1039. value = coda_slice_mode(ctx);
  1040. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  1041. value = ctx->params.gop_size;
  1042. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  1043. }
  1044. if (ctx->params.bitrate && (ctx->params.frame_rc_enable ||
  1045. ctx->params.mb_rc_enable)) {
  1046. ctx->params.bitrate_changed = false;
  1047. ctx->params.h264_intra_qp_changed = false;
  1048. /* Rate control enabled */
  1049. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  1050. << CODA_RATECONTROL_BITRATE_OFFSET;
  1051. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  1052. value |= (ctx->params.vbv_delay &
  1053. CODA_RATECONTROL_INITIALDELAY_MASK)
  1054. << CODA_RATECONTROL_INITIALDELAY_OFFSET;
  1055. if (dev->devtype->product == CODA_960)
  1056. value |= BIT(31); /* disable autoskip */
  1057. } else {
  1058. value = 0;
  1059. }
  1060. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  1061. coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  1062. coda_write(dev, ctx->params.intra_refresh,
  1063. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  1064. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  1065. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  1066. value = 0;
  1067. if (dev->devtype->product == CODA_960)
  1068. gamma = CODA9_DEFAULT_GAMMA;
  1069. else
  1070. gamma = CODA_DEFAULT_GAMMA;
  1071. if (gamma > 0) {
  1072. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  1073. CODA_CMD_ENC_SEQ_RC_GAMMA);
  1074. }
  1075. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  1076. coda_write(dev,
  1077. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  1078. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  1079. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  1080. }
  1081. if (dev->devtype->product == CODA_960) {
  1082. if (ctx->params.h264_max_qp)
  1083. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  1084. if (CODA_DEFAULT_GAMMA > 0)
  1085. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  1086. } else {
  1087. if (CODA_DEFAULT_GAMMA > 0) {
  1088. if (dev->devtype->product == CODA_DX6)
  1089. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  1090. else
  1091. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  1092. }
  1093. if (ctx->params.h264_min_qp)
  1094. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  1095. if (ctx->params.h264_max_qp)
  1096. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  1097. }
  1098. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  1099. if (ctx->params.frame_rc_enable && !ctx->params.mb_rc_enable)
  1100. value = 1;
  1101. else
  1102. value = 0;
  1103. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  1104. coda_setup_iram(ctx);
  1105. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  1106. switch (dev->devtype->product) {
  1107. case CODA_DX6:
  1108. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  1109. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  1110. break;
  1111. case CODA_HX4:
  1112. case CODA_7541:
  1113. coda_write(dev, ctx->iram_info.search_ram_paddr,
  1114. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  1115. coda_write(dev, ctx->iram_info.search_ram_size,
  1116. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  1117. break;
  1118. case CODA_960:
  1119. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  1120. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  1121. }
  1122. }
  1123. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  1124. if (ret < 0) {
  1125. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1126. goto out;
  1127. }
  1128. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  1129. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  1130. ret = -EFAULT;
  1131. goto out;
  1132. }
  1133. ctx->initialized = 1;
  1134. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  1135. if (dev->devtype->product == CODA_960)
  1136. ctx->num_internal_frames = 4;
  1137. else
  1138. ctx->num_internal_frames = 2;
  1139. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  1140. if (ret < 0) {
  1141. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  1142. goto out;
  1143. }
  1144. num_fb = 2;
  1145. stride = q_data_src->bytesperline;
  1146. } else {
  1147. ctx->num_internal_frames = 0;
  1148. num_fb = 0;
  1149. stride = 0;
  1150. }
  1151. coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
  1152. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1153. if (dev->devtype->product == CODA_HX4 ||
  1154. dev->devtype->product == CODA_7541) {
  1155. coda_write(dev, q_data_src->bytesperline,
  1156. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  1157. }
  1158. if (dev->devtype->product != CODA_DX6) {
  1159. coda_write(dev, ctx->iram_info.buf_bit_use,
  1160. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1161. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1162. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1163. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1164. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1165. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1166. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1167. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1168. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1169. if (dev->devtype->product == CODA_960) {
  1170. coda_write(dev, ctx->iram_info.buf_btp_use,
  1171. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1172. coda9_set_frame_cache(ctx, q_data_src->fourcc);
  1173. /* FIXME */
  1174. coda_write(dev, ctx->internal_frames[2].buf.paddr,
  1175. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  1176. coda_write(dev, ctx->internal_frames[3].buf.paddr,
  1177. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  1178. }
  1179. }
  1180. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  1181. if (ret < 0) {
  1182. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1183. goto out;
  1184. }
  1185. coda_dbg(1, ctx, "start encoding %dx%d %4.4s->%4.4s @ %d/%d Hz\n",
  1186. q_data_src->rect.width, q_data_src->rect.height,
  1187. (char *)&ctx->codec->src_fourcc, (char *)&dst_fourcc,
  1188. ctx->params.framerate & 0xffff,
  1189. (ctx->params.framerate >> 16) + 1);
  1190. /* Save stream headers */
  1191. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1192. switch (dst_fourcc) {
  1193. case V4L2_PIX_FMT_H264:
  1194. /*
  1195. * Get SPS in the first frame and copy it to an
  1196. * intermediate buffer.
  1197. */
  1198. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  1199. &ctx->vpu_header[0][0],
  1200. &ctx->vpu_header_size[0]);
  1201. if (ret < 0)
  1202. goto out;
  1203. /*
  1204. * If visible width or height are not aligned to macroblock
  1205. * size, the crop_right and crop_bottom SPS fields must be set
  1206. * to the difference between visible and coded size. This is
  1207. * only supported by CODA960 firmware. All others do not allow
  1208. * writing frame cropping parameters, so we have to manually
  1209. * fix up the SPS RBSP (Sequence Parameter Set Raw Byte
  1210. * Sequence Payload) ourselves.
  1211. */
  1212. if (ctx->dev->devtype->product != CODA_960 &&
  1213. ((q_data_src->rect.width % 16) ||
  1214. (q_data_src->rect.height % 16))) {
  1215. ret = coda_h264_sps_fixup(ctx, q_data_src->rect.width,
  1216. q_data_src->rect.height,
  1217. &ctx->vpu_header[0][0],
  1218. &ctx->vpu_header_size[0],
  1219. sizeof(ctx->vpu_header[0]));
  1220. if (ret < 0)
  1221. goto out;
  1222. }
  1223. /*
  1224. * Get PPS in the first frame and copy it to an
  1225. * intermediate buffer.
  1226. */
  1227. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  1228. &ctx->vpu_header[1][0],
  1229. &ctx->vpu_header_size[1]);
  1230. if (ret < 0)
  1231. goto out;
  1232. /*
  1233. * Length of H.264 headers is variable and thus it might not be
  1234. * aligned for the coda to append the encoded frame. In that is
  1235. * the case a filler NAL must be added to header 2.
  1236. */
  1237. ctx->vpu_header_size[2] = coda_h264_padding(
  1238. (ctx->vpu_header_size[0] +
  1239. ctx->vpu_header_size[1]),
  1240. ctx->vpu_header[2]);
  1241. break;
  1242. case V4L2_PIX_FMT_MPEG4:
  1243. /*
  1244. * Get VOS in the first frame and copy it to an
  1245. * intermediate buffer
  1246. */
  1247. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  1248. &ctx->vpu_header[0][0],
  1249. &ctx->vpu_header_size[0]);
  1250. if (ret < 0)
  1251. goto out;
  1252. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  1253. &ctx->vpu_header[1][0],
  1254. &ctx->vpu_header_size[1]);
  1255. if (ret < 0)
  1256. goto out;
  1257. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  1258. &ctx->vpu_header[2][0],
  1259. &ctx->vpu_header_size[2]);
  1260. if (ret < 0)
  1261. goto out;
  1262. break;
  1263. default:
  1264. /* No more formats need to save headers at the moment */
  1265. break;
  1266. }
  1267. out:
  1268. mutex_unlock(&dev->coda_mutex);
  1269. return ret;
  1270. }
  1271. static int coda_prepare_encode(struct coda_ctx *ctx)
  1272. {
  1273. struct coda_q_data *q_data_src, *q_data_dst;
  1274. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  1275. struct coda_dev *dev = ctx->dev;
  1276. int force_ipicture;
  1277. int quant_param = 0;
  1278. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  1279. u32 rot_mode = 0;
  1280. u32 dst_fourcc;
  1281. u32 reg;
  1282. int ret;
  1283. ret = coda_enc_param_change(ctx);
  1284. if (ret < 0) {
  1285. v4l2_warn(&ctx->dev->v4l2_dev, "parameter change failed: %d\n",
  1286. ret);
  1287. }
  1288. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  1289. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1290. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1291. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1292. dst_fourcc = q_data_dst->fourcc;
  1293. src_buf->sequence = ctx->osequence;
  1294. dst_buf->sequence = ctx->osequence;
  1295. ctx->osequence++;
  1296. force_ipicture = ctx->params.force_ipicture;
  1297. if (force_ipicture)
  1298. ctx->params.force_ipicture = false;
  1299. else if (ctx->params.gop_size != 0 &&
  1300. (src_buf->sequence % ctx->params.gop_size) == 0)
  1301. force_ipicture = 1;
  1302. /*
  1303. * Workaround coda firmware BUG that only marks the first
  1304. * frame as IDR. This is a problem for some decoders that can't
  1305. * recover when a frame is lost.
  1306. */
  1307. if (!force_ipicture) {
  1308. src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
  1309. src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1310. } else {
  1311. src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
  1312. src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
  1313. }
  1314. if (dev->devtype->product == CODA_960)
  1315. coda_set_gdi_regs(ctx);
  1316. /*
  1317. * Copy headers in front of the first frame and forced I frames for
  1318. * H.264 only. In MPEG4 they are already copied by the CODA.
  1319. */
  1320. if (src_buf->sequence == 0 || force_ipicture) {
  1321. pic_stream_buffer_addr =
  1322. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
  1323. ctx->vpu_header_size[0] +
  1324. ctx->vpu_header_size[1] +
  1325. ctx->vpu_header_size[2];
  1326. pic_stream_buffer_size = q_data_dst->sizeimage -
  1327. ctx->vpu_header_size[0] -
  1328. ctx->vpu_header_size[1] -
  1329. ctx->vpu_header_size[2];
  1330. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
  1331. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  1332. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
  1333. + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
  1334. ctx->vpu_header_size[1]);
  1335. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
  1336. + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
  1337. &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
  1338. } else {
  1339. pic_stream_buffer_addr =
  1340. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
  1341. pic_stream_buffer_size = q_data_dst->sizeimage;
  1342. }
  1343. if (force_ipicture) {
  1344. switch (dst_fourcc) {
  1345. case V4L2_PIX_FMT_H264:
  1346. quant_param = ctx->params.h264_intra_qp;
  1347. break;
  1348. case V4L2_PIX_FMT_MPEG4:
  1349. quant_param = ctx->params.mpeg4_intra_qp;
  1350. break;
  1351. case V4L2_PIX_FMT_JPEG:
  1352. quant_param = 30;
  1353. break;
  1354. default:
  1355. v4l2_warn(&ctx->dev->v4l2_dev,
  1356. "cannot set intra qp, fmt not supported\n");
  1357. break;
  1358. }
  1359. } else {
  1360. switch (dst_fourcc) {
  1361. case V4L2_PIX_FMT_H264:
  1362. quant_param = ctx->params.h264_inter_qp;
  1363. break;
  1364. case V4L2_PIX_FMT_MPEG4:
  1365. quant_param = ctx->params.mpeg4_inter_qp;
  1366. break;
  1367. default:
  1368. v4l2_warn(&ctx->dev->v4l2_dev,
  1369. "cannot set inter qp, fmt not supported\n");
  1370. break;
  1371. }
  1372. }
  1373. /* submit */
  1374. if (ctx->params.rot_mode)
  1375. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1376. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1377. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1378. if (dev->devtype->product == CODA_960) {
  1379. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1380. coda_write(dev, q_data_src->bytesperline,
  1381. CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1382. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1383. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1384. } else {
  1385. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1386. }
  1387. coda_write_base(ctx, q_data_src, src_buf, reg);
  1388. coda_write(dev, force_ipicture << 1 & 0x2,
  1389. CODA_CMD_ENC_PIC_OPTION);
  1390. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1391. coda_write(dev, pic_stream_buffer_size / 1024,
  1392. CODA_CMD_ENC_PIC_BB_SIZE);
  1393. if (!ctx->streamon_out) {
  1394. /* After streamoff on the output side, set stream end flag */
  1395. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1396. coda_write(dev, ctx->bit_stream_param,
  1397. CODA_REG_BIT_BIT_STREAM_PARAM);
  1398. }
  1399. if (dev->devtype->product != CODA_DX6)
  1400. coda_write(dev, ctx->iram_info.axi_sram_use,
  1401. CODA7_REG_BIT_AXI_SRAM_USE);
  1402. trace_coda_enc_pic_run(ctx, src_buf);
  1403. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1404. return 0;
  1405. }
  1406. static char coda_frame_type_char(u32 flags)
  1407. {
  1408. return (flags & V4L2_BUF_FLAG_KEYFRAME) ? 'I' :
  1409. (flags & V4L2_BUF_FLAG_PFRAME) ? 'P' :
  1410. (flags & V4L2_BUF_FLAG_BFRAME) ? 'B' : '?';
  1411. }
  1412. static void coda_finish_encode(struct coda_ctx *ctx)
  1413. {
  1414. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  1415. struct coda_dev *dev = ctx->dev;
  1416. u32 wr_ptr, start_ptr;
  1417. if (ctx->aborting)
  1418. return;
  1419. /*
  1420. * Lock to make sure that an encoder stop command running in parallel
  1421. * will either already have marked src_buf as last, or it will wake up
  1422. * the capture queue after the buffers are returned.
  1423. */
  1424. mutex_lock(&ctx->wakeup_mutex);
  1425. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1426. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1427. trace_coda_enc_pic_done(ctx, dst_buf);
  1428. /* Get results from the coda */
  1429. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1430. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1431. /* Calculate bytesused field */
  1432. if (dst_buf->sequence == 0 ||
  1433. src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
  1434. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
  1435. ctx->vpu_header_size[0] +
  1436. ctx->vpu_header_size[1] +
  1437. ctx->vpu_header_size[2]);
  1438. } else {
  1439. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
  1440. }
  1441. coda_dbg(1, ctx, "frame size = %u\n", wr_ptr - start_ptr);
  1442. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1443. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1444. dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1445. V4L2_BUF_FLAG_PFRAME |
  1446. V4L2_BUF_FLAG_LAST);
  1447. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0)
  1448. dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
  1449. else
  1450. dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
  1451. dst_buf->flags |= src_buf->flags & V4L2_BUF_FLAG_LAST;
  1452. v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, false);
  1453. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1454. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1455. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
  1456. mutex_unlock(&ctx->wakeup_mutex);
  1457. ctx->gopcounter--;
  1458. if (ctx->gopcounter < 0)
  1459. ctx->gopcounter = ctx->params.gop_size - 1;
  1460. coda_dbg(1, ctx, "job finished: encoded %c frame (%d)%s\n",
  1461. coda_frame_type_char(dst_buf->flags), dst_buf->sequence,
  1462. (dst_buf->flags & V4L2_BUF_FLAG_LAST) ? " (last)" : "");
  1463. }
  1464. static void coda_seq_end_work(struct work_struct *work)
  1465. {
  1466. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1467. struct coda_dev *dev = ctx->dev;
  1468. mutex_lock(&ctx->buffer_mutex);
  1469. mutex_lock(&dev->coda_mutex);
  1470. if (ctx->initialized == 0)
  1471. goto out;
  1472. coda_dbg(1, ctx, "%s: sent command 'SEQ_END' to coda\n", __func__);
  1473. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1474. v4l2_err(&dev->v4l2_dev,
  1475. "CODA_COMMAND_SEQ_END failed\n");
  1476. }
  1477. /*
  1478. * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
  1479. * from the output stream after the h.264 decoder has run. Resetting the
  1480. * hardware after the decoder has finished seems to help.
  1481. */
  1482. if (dev->devtype->product == CODA_960)
  1483. coda_hw_reset(ctx);
  1484. kfifo_init(&ctx->bitstream_fifo,
  1485. ctx->bitstream.vaddr, ctx->bitstream.size);
  1486. coda_free_framebuffers(ctx);
  1487. ctx->initialized = 0;
  1488. out:
  1489. mutex_unlock(&dev->coda_mutex);
  1490. mutex_unlock(&ctx->buffer_mutex);
  1491. }
  1492. static void coda_bit_release(struct coda_ctx *ctx)
  1493. {
  1494. mutex_lock(&ctx->buffer_mutex);
  1495. coda_free_framebuffers(ctx);
  1496. coda_free_context_buffers(ctx);
  1497. coda_free_bitstream_buffer(ctx);
  1498. mutex_unlock(&ctx->buffer_mutex);
  1499. }
  1500. const struct coda_context_ops coda_bit_encode_ops = {
  1501. .queue_init = coda_encoder_queue_init,
  1502. .reqbufs = coda_encoder_reqbufs,
  1503. .start_streaming = coda_start_encoding,
  1504. .prepare_run = coda_prepare_encode,
  1505. .finish_run = coda_finish_encode,
  1506. .seq_end_work = coda_seq_end_work,
  1507. .release = coda_bit_release,
  1508. };
  1509. /*
  1510. * Decoder context operations
  1511. */
  1512. static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
  1513. struct coda_q_data *q_data)
  1514. {
  1515. if (ctx->bitstream.vaddr)
  1516. return 0;
  1517. ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
  1518. ctx->bitstream.vaddr = dma_alloc_wc(ctx->dev->dev, ctx->bitstream.size,
  1519. &ctx->bitstream.paddr, GFP_KERNEL);
  1520. if (!ctx->bitstream.vaddr) {
  1521. v4l2_err(&ctx->dev->v4l2_dev,
  1522. "failed to allocate bitstream ringbuffer");
  1523. return -ENOMEM;
  1524. }
  1525. kfifo_init(&ctx->bitstream_fifo,
  1526. ctx->bitstream.vaddr, ctx->bitstream.size);
  1527. return 0;
  1528. }
  1529. static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
  1530. {
  1531. if (ctx->bitstream.vaddr == NULL)
  1532. return;
  1533. dma_free_wc(ctx->dev->dev, ctx->bitstream.size, ctx->bitstream.vaddr,
  1534. ctx->bitstream.paddr);
  1535. ctx->bitstream.vaddr = NULL;
  1536. kfifo_init(&ctx->bitstream_fifo, NULL, 0);
  1537. }
  1538. static int coda_decoder_reqbufs(struct coda_ctx *ctx,
  1539. struct v4l2_requestbuffers *rb)
  1540. {
  1541. struct coda_q_data *q_data_src;
  1542. int ret;
  1543. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1544. return 0;
  1545. if (rb->count) {
  1546. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1547. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1548. if (ret < 0)
  1549. return ret;
  1550. ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
  1551. if (ret < 0) {
  1552. coda_free_context_buffers(ctx);
  1553. return ret;
  1554. }
  1555. } else {
  1556. coda_free_bitstream_buffer(ctx);
  1557. coda_free_context_buffers(ctx);
  1558. }
  1559. return 0;
  1560. }
  1561. static bool coda_reorder_enable(struct coda_ctx *ctx)
  1562. {
  1563. struct coda_dev *dev = ctx->dev;
  1564. int profile;
  1565. if (dev->devtype->product != CODA_HX4 &&
  1566. dev->devtype->product != CODA_7541 &&
  1567. dev->devtype->product != CODA_960)
  1568. return false;
  1569. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1570. return false;
  1571. if (ctx->codec->src_fourcc != V4L2_PIX_FMT_H264)
  1572. return true;
  1573. profile = coda_h264_profile(ctx->params.h264_profile_idc);
  1574. if (profile < 0)
  1575. v4l2_warn(&dev->v4l2_dev, "Unknown H264 Profile: %u\n",
  1576. ctx->params.h264_profile_idc);
  1577. /* Baseline profile does not support reordering */
  1578. return profile > V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE;
  1579. }
  1580. static void coda_decoder_drop_used_metas(struct coda_ctx *ctx)
  1581. {
  1582. struct coda_buffer_meta *meta, *tmp;
  1583. /*
  1584. * All metas that end at or before the RD pointer (fifo out),
  1585. * are now consumed by the VPU and should be released.
  1586. */
  1587. spin_lock(&ctx->buffer_meta_lock);
  1588. list_for_each_entry_safe(meta, tmp, &ctx->buffer_meta_list, list) {
  1589. if (ctx->bitstream_fifo.kfifo.out >= meta->end) {
  1590. coda_dbg(2, ctx, "releasing meta: seq=%d start=%d end=%d\n",
  1591. meta->sequence, meta->start, meta->end);
  1592. list_del(&meta->list);
  1593. ctx->num_metas--;
  1594. ctx->first_frame_sequence++;
  1595. kfree(meta);
  1596. }
  1597. }
  1598. spin_unlock(&ctx->buffer_meta_lock);
  1599. }
  1600. static int __coda_decoder_seq_init(struct coda_ctx *ctx)
  1601. {
  1602. struct coda_q_data *q_data_src, *q_data_dst;
  1603. u32 bitstream_buf, bitstream_size;
  1604. struct coda_dev *dev = ctx->dev;
  1605. int width, height;
  1606. u32 src_fourcc, dst_fourcc;
  1607. u32 val;
  1608. int ret;
  1609. lockdep_assert_held(&dev->coda_mutex);
  1610. coda_dbg(1, ctx, "Video Data Order Adapter: %s\n",
  1611. ctx->use_vdoa ? "Enabled" : "Disabled");
  1612. /* Start decoding */
  1613. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1614. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1615. bitstream_buf = ctx->bitstream.paddr;
  1616. bitstream_size = ctx->bitstream.size;
  1617. src_fourcc = q_data_src->fourcc;
  1618. dst_fourcc = q_data_dst->fourcc;
  1619. /* Update coda bitstream read and write pointers from kfifo */
  1620. coda_kfifo_sync_to_device_full(ctx);
  1621. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  1622. CODA9_FRAME_TILED2LINEAR);
  1623. if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
  1624. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1625. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  1626. ctx->frame_mem_ctrl |= (0x3 << 9) |
  1627. ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
  1628. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1629. ctx->display_idx = -1;
  1630. ctx->frm_dis_flg = 0;
  1631. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1632. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1633. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1634. val = 0;
  1635. if (coda_reorder_enable(ctx))
  1636. val |= CODA_REORDER_ENABLE;
  1637. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1638. val |= CODA_NO_INT_ENABLE;
  1639. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1640. ctx->params.codec_mode = ctx->codec->mode;
  1641. if (dev->devtype->product == CODA_960 &&
  1642. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1643. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1644. else
  1645. ctx->params.codec_mode_aux = 0;
  1646. if (src_fourcc == V4L2_PIX_FMT_MPEG4) {
  1647. coda_write(dev, CODA_MP4_CLASS_MPEG4,
  1648. CODA_CMD_DEC_SEQ_MP4_ASP_CLASS);
  1649. }
  1650. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1651. if (dev->devtype->product == CODA_HX4 ||
  1652. dev->devtype->product == CODA_7541) {
  1653. coda_write(dev, ctx->psbuf.paddr,
  1654. CODA_CMD_DEC_SEQ_PS_BB_START);
  1655. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1656. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1657. }
  1658. if (dev->devtype->product == CODA_960) {
  1659. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1660. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1661. }
  1662. }
  1663. if (src_fourcc == V4L2_PIX_FMT_JPEG)
  1664. coda_write(dev, 0, CODA_CMD_DEC_SEQ_JPG_THUMB_EN);
  1665. if (dev->devtype->product != CODA_960)
  1666. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1667. ctx->bit_stream_param = CODA_BIT_DEC_SEQ_INIT_ESCAPE;
  1668. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  1669. ctx->bit_stream_param = 0;
  1670. if (ret) {
  1671. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1672. return ret;
  1673. }
  1674. ctx->sequence_offset = ~0U;
  1675. ctx->initialized = 1;
  1676. ctx->first_frame_sequence = 0;
  1677. /* Update kfifo out pointer from coda bitstream read pointer */
  1678. coda_kfifo_sync_from_device(ctx);
  1679. /*
  1680. * After updating the read pointer, we need to check if
  1681. * any metas are consumed and should be released.
  1682. */
  1683. coda_decoder_drop_used_metas(ctx);
  1684. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1685. v4l2_err(&dev->v4l2_dev,
  1686. "CODA_COMMAND_SEQ_INIT failed, error code = 0x%x\n",
  1687. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1688. return -EAGAIN;
  1689. }
  1690. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1691. if (dev->devtype->product == CODA_DX6) {
  1692. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1693. height = val & CODADX6_PICHEIGHT_MASK;
  1694. } else {
  1695. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1696. height = val & CODA7_PICHEIGHT_MASK;
  1697. }
  1698. if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
  1699. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1700. width, height, q_data_dst->bytesperline,
  1701. q_data_dst->height);
  1702. return -EINVAL;
  1703. }
  1704. width = round_up(width, 16);
  1705. height = round_up(height, 16);
  1706. coda_dbg(1, ctx, "start decoding: %dx%d\n", width, height);
  1707. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1708. /*
  1709. * If the VDOA is used, the decoder needs one additional frame,
  1710. * because the frames are freed when the next frame is decoded.
  1711. * Otherwise there are visible errors in the decoded frames (green
  1712. * regions in displayed frames) and a broken order of frames (earlier
  1713. * frames are sporadically displayed after later frames).
  1714. */
  1715. if (ctx->use_vdoa)
  1716. ctx->num_internal_frames += 1;
  1717. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1718. v4l2_err(&dev->v4l2_dev,
  1719. "not enough framebuffers to decode (%d < %d)\n",
  1720. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1721. return -EINVAL;
  1722. }
  1723. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1724. u32 left_right;
  1725. u32 top_bottom;
  1726. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1727. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1728. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1729. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1730. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1731. (left_right & 0x3ff);
  1732. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1733. (top_bottom & 0x3ff);
  1734. }
  1735. if (dev->devtype->product != CODA_DX6) {
  1736. u8 profile, level;
  1737. val = coda_read(dev, CODA7_RET_DEC_SEQ_HEADER_REPORT);
  1738. profile = val & 0xff;
  1739. level = (val >> 8) & 0x7f;
  1740. if (profile || level)
  1741. coda_update_profile_level_ctrls(ctx, profile, level);
  1742. }
  1743. return 0;
  1744. }
  1745. static void coda_dec_seq_init_work(struct work_struct *work)
  1746. {
  1747. struct coda_ctx *ctx = container_of(work,
  1748. struct coda_ctx, seq_init_work);
  1749. struct coda_dev *dev = ctx->dev;
  1750. mutex_lock(&ctx->buffer_mutex);
  1751. mutex_lock(&dev->coda_mutex);
  1752. if (!ctx->initialized)
  1753. __coda_decoder_seq_init(ctx);
  1754. mutex_unlock(&dev->coda_mutex);
  1755. mutex_unlock(&ctx->buffer_mutex);
  1756. }
  1757. static int __coda_start_decoding(struct coda_ctx *ctx)
  1758. {
  1759. struct coda_q_data *q_data_src, *q_data_dst;
  1760. struct coda_dev *dev = ctx->dev;
  1761. u32 src_fourcc, dst_fourcc;
  1762. int ret;
  1763. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1764. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1765. src_fourcc = q_data_src->fourcc;
  1766. dst_fourcc = q_data_dst->fourcc;
  1767. if (!ctx->initialized) {
  1768. ret = __coda_decoder_seq_init(ctx);
  1769. if (ret < 0)
  1770. return ret;
  1771. } else {
  1772. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  1773. CODA9_FRAME_TILED2LINEAR);
  1774. if (dst_fourcc == V4L2_PIX_FMT_NV12 || dst_fourcc == V4L2_PIX_FMT_YUYV)
  1775. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1776. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  1777. ctx->frame_mem_ctrl |= (0x3 << 9) |
  1778. ((ctx->use_vdoa) ? 0 : CODA9_FRAME_TILED2LINEAR);
  1779. }
  1780. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1781. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1782. if (ret < 0) {
  1783. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1784. return ret;
  1785. }
  1786. /* Tell the decoder how many frame buffers we allocated. */
  1787. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1788. coda_write(dev, round_up(q_data_dst->rect.width, 16),
  1789. CODA_CMD_SET_FRAME_BUF_STRIDE);
  1790. if (dev->devtype->product != CODA_DX6) {
  1791. /* Set secondary AXI IRAM */
  1792. coda_setup_iram(ctx);
  1793. coda_write(dev, ctx->iram_info.buf_bit_use,
  1794. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1795. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1796. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1797. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1798. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1799. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1800. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1801. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1802. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1803. if (dev->devtype->product == CODA_960) {
  1804. coda_write(dev, ctx->iram_info.buf_btp_use,
  1805. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1806. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1807. coda9_set_frame_cache(ctx, dst_fourcc);
  1808. }
  1809. }
  1810. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1811. coda_write(dev, ctx->slicebuf.paddr,
  1812. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1813. coda_write(dev, ctx->slicebuf.size / 1024,
  1814. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1815. }
  1816. if (dev->devtype->product == CODA_HX4 ||
  1817. dev->devtype->product == CODA_7541) {
  1818. int max_mb_x = 1920 / 16;
  1819. int max_mb_y = 1088 / 16;
  1820. int max_mb_num = max_mb_x * max_mb_y;
  1821. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1822. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1823. } else if (dev->devtype->product == CODA_960) {
  1824. int max_mb_x = 1920 / 16;
  1825. int max_mb_y = 1088 / 16;
  1826. int max_mb_num = max_mb_x * max_mb_y;
  1827. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1828. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1829. }
  1830. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1831. v4l2_err(&ctx->dev->v4l2_dev,
  1832. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1833. return -ETIMEDOUT;
  1834. }
  1835. return 0;
  1836. }
  1837. static int coda_start_decoding(struct coda_ctx *ctx)
  1838. {
  1839. struct coda_dev *dev = ctx->dev;
  1840. int ret;
  1841. mutex_lock(&dev->coda_mutex);
  1842. ret = __coda_start_decoding(ctx);
  1843. mutex_unlock(&dev->coda_mutex);
  1844. return ret;
  1845. }
  1846. static int coda_prepare_decode(struct coda_ctx *ctx)
  1847. {
  1848. struct vb2_v4l2_buffer *dst_buf;
  1849. struct coda_dev *dev = ctx->dev;
  1850. struct coda_q_data *q_data_dst;
  1851. struct coda_buffer_meta *meta;
  1852. u32 rot_mode = 0;
  1853. u32 reg_addr, reg_stride;
  1854. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1855. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1856. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1857. mutex_lock(&ctx->bitstream_mutex);
  1858. coda_fill_bitstream(ctx, NULL);
  1859. mutex_unlock(&ctx->bitstream_mutex);
  1860. if (coda_get_bitstream_payload(ctx) < 512 &&
  1861. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1862. coda_dbg(1, ctx, "bitstream payload: %d, skipping\n",
  1863. coda_get_bitstream_payload(ctx));
  1864. return -EAGAIN;
  1865. }
  1866. /* Run coda_start_decoding (again) if not yet initialized */
  1867. if (!ctx->initialized) {
  1868. int ret = __coda_start_decoding(ctx);
  1869. if (ret < 0) {
  1870. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1871. return -EAGAIN;
  1872. } else {
  1873. ctx->initialized = 1;
  1874. }
  1875. }
  1876. if (dev->devtype->product == CODA_960)
  1877. coda_set_gdi_regs(ctx);
  1878. if (ctx->use_vdoa &&
  1879. ctx->display_idx >= 0 &&
  1880. ctx->display_idx < ctx->num_internal_frames) {
  1881. vdoa_device_run(ctx->vdoa,
  1882. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0),
  1883. ctx->internal_frames[ctx->display_idx].buf.paddr);
  1884. } else {
  1885. if (dev->devtype->product == CODA_960) {
  1886. /*
  1887. * It was previously assumed that the CODA960 has an
  1888. * internal list of 64 buffer entries that contains
  1889. * both the registered internal frame buffers as well
  1890. * as the rotator buffer output, and that the ROT_INDEX
  1891. * register must be set to a value between the last
  1892. * internal frame buffers' index and 64.
  1893. * At least on firmware version 3.1.1 it turns out that
  1894. * setting ROT_INDEX to any value >= 32 causes CODA
  1895. * hangups that it can not recover from with the SRC VPU
  1896. * reset.
  1897. * It does appear to work however, to just set it to a
  1898. * fixed value in the [ctx->num_internal_frames, 31]
  1899. * range, for example CODA_MAX_FRAMEBUFFERS.
  1900. */
  1901. coda_write(dev, CODA_MAX_FRAMEBUFFERS,
  1902. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1903. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1904. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1905. } else {
  1906. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1907. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1908. }
  1909. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1910. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1911. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1912. }
  1913. coda_write(dev, rot_mode, CODA_CMD_DEC_PIC_ROT_MODE);
  1914. switch (dev->devtype->product) {
  1915. case CODA_DX6:
  1916. /* TBD */
  1917. case CODA_HX4:
  1918. case CODA_7541:
  1919. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1920. break;
  1921. case CODA_960:
  1922. /* 'hardcode to use interrupt disable mode'? */
  1923. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1924. break;
  1925. }
  1926. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1927. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1928. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1929. if (dev->devtype->product != CODA_DX6)
  1930. coda_write(dev, ctx->iram_info.axi_sram_use,
  1931. CODA7_REG_BIT_AXI_SRAM_USE);
  1932. spin_lock(&ctx->buffer_meta_lock);
  1933. meta = list_first_entry_or_null(&ctx->buffer_meta_list,
  1934. struct coda_buffer_meta, list);
  1935. if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1936. /* If this is the last buffer in the bitstream, add padding */
  1937. if (meta->end == ctx->bitstream_fifo.kfifo.in) {
  1938. static unsigned char buf[512];
  1939. unsigned int pad;
  1940. /* Pad to multiple of 256 and then add 256 more */
  1941. pad = ((0 - meta->end) & 0xff) + 256;
  1942. memset(buf, 0xff, sizeof(buf));
  1943. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1944. }
  1945. }
  1946. spin_unlock(&ctx->buffer_meta_lock);
  1947. coda_kfifo_sync_to_device_full(ctx);
  1948. /* Clear decode success flag */
  1949. coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
  1950. /* Clear error return value */
  1951. coda_write(dev, 0, CODA_RET_DEC_PIC_ERR_MB);
  1952. trace_coda_dec_pic_run(ctx, meta);
  1953. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1954. return 0;
  1955. }
  1956. static void coda_finish_decode(struct coda_ctx *ctx)
  1957. {
  1958. struct coda_dev *dev = ctx->dev;
  1959. struct coda_q_data *q_data_src;
  1960. struct coda_q_data *q_data_dst;
  1961. struct vb2_v4l2_buffer *dst_buf;
  1962. struct coda_buffer_meta *meta;
  1963. int width, height;
  1964. int decoded_idx;
  1965. int display_idx;
  1966. struct coda_internal_frame *decoded_frame = NULL;
  1967. u32 src_fourcc;
  1968. int success;
  1969. u32 err_mb;
  1970. int err_vdoa = 0;
  1971. u32 val;
  1972. if (ctx->aborting)
  1973. return;
  1974. /* Update kfifo out pointer from coda bitstream read pointer */
  1975. coda_kfifo_sync_from_device(ctx);
  1976. /*
  1977. * in stream-end mode, the read pointer can overshoot the write pointer
  1978. * by up to 512 bytes
  1979. */
  1980. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1981. if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
  1982. kfifo_init(&ctx->bitstream_fifo,
  1983. ctx->bitstream.vaddr, ctx->bitstream.size);
  1984. }
  1985. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1986. src_fourcc = q_data_src->fourcc;
  1987. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1988. if (val != 1)
  1989. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1990. success = val & 0x1;
  1991. if (!success)
  1992. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1993. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1994. if (val & (1 << 3))
  1995. v4l2_err(&dev->v4l2_dev,
  1996. "insufficient PS buffer space (%d bytes)\n",
  1997. ctx->psbuf.size);
  1998. if (val & (1 << 2))
  1999. v4l2_err(&dev->v4l2_dev,
  2000. "insufficient slice buffer space (%d bytes)\n",
  2001. ctx->slicebuf.size);
  2002. }
  2003. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  2004. width = (val >> 16) & 0xffff;
  2005. height = val & 0xffff;
  2006. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  2007. /* frame crop information */
  2008. if (src_fourcc == V4L2_PIX_FMT_H264) {
  2009. u32 left_right;
  2010. u32 top_bottom;
  2011. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  2012. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  2013. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  2014. /* Keep current crop information */
  2015. } else {
  2016. struct v4l2_rect *rect = &q_data_dst->rect;
  2017. rect->left = left_right >> 16 & 0xffff;
  2018. rect->top = top_bottom >> 16 & 0xffff;
  2019. rect->width = width - rect->left -
  2020. (left_right & 0xffff);
  2021. rect->height = height - rect->top -
  2022. (top_bottom & 0xffff);
  2023. }
  2024. } else {
  2025. /* no cropping */
  2026. }
  2027. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  2028. if (err_mb > 0) {
  2029. if (__ratelimit(&dev->mb_err_rs))
  2030. coda_dbg(1, ctx, "errors in %d macroblocks\n", err_mb);
  2031. v4l2_ctrl_s_ctrl(ctx->mb_err_cnt_ctrl,
  2032. v4l2_ctrl_g_ctrl(ctx->mb_err_cnt_ctrl) + err_mb);
  2033. }
  2034. if (dev->devtype->product == CODA_HX4 ||
  2035. dev->devtype->product == CODA_7541) {
  2036. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  2037. if (val == 0) {
  2038. /* not enough bitstream data */
  2039. coda_dbg(1, ctx, "prescan failed: %d\n", val);
  2040. ctx->hold = true;
  2041. return;
  2042. }
  2043. }
  2044. /* Wait until the VDOA finished writing the previous display frame */
  2045. if (ctx->use_vdoa &&
  2046. ctx->display_idx >= 0 &&
  2047. ctx->display_idx < ctx->num_internal_frames) {
  2048. err_vdoa = vdoa_wait_for_completion(ctx->vdoa);
  2049. }
  2050. ctx->frm_dis_flg = coda_read(dev,
  2051. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  2052. /* The previous display frame was copied out and can be overwritten */
  2053. if (ctx->display_idx >= 0 &&
  2054. ctx->display_idx < ctx->num_internal_frames) {
  2055. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  2056. coda_write(dev, ctx->frm_dis_flg,
  2057. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  2058. }
  2059. /*
  2060. * The index of the last decoded frame, not necessarily in
  2061. * display order, and the index of the next display frame.
  2062. * The latter could have been decoded in a previous run.
  2063. */
  2064. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  2065. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  2066. if (decoded_idx == -1) {
  2067. /* no frame was decoded, but we might have a display frame */
  2068. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  2069. ctx->sequence_offset++;
  2070. else if (ctx->display_idx < 0)
  2071. ctx->hold = true;
  2072. } else if (decoded_idx == -2) {
  2073. if (ctx->display_idx >= 0 &&
  2074. ctx->display_idx < ctx->num_internal_frames)
  2075. ctx->sequence_offset++;
  2076. /* no frame was decoded, we still return remaining buffers */
  2077. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  2078. v4l2_err(&dev->v4l2_dev,
  2079. "decoded frame index out of range: %d\n", decoded_idx);
  2080. } else {
  2081. int sequence;
  2082. decoded_frame = &ctx->internal_frames[decoded_idx];
  2083. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM);
  2084. if (ctx->sequence_offset == -1)
  2085. ctx->sequence_offset = val;
  2086. sequence = val + ctx->first_frame_sequence
  2087. - ctx->sequence_offset;
  2088. spin_lock(&ctx->buffer_meta_lock);
  2089. if (!list_empty(&ctx->buffer_meta_list)) {
  2090. meta = list_first_entry(&ctx->buffer_meta_list,
  2091. struct coda_buffer_meta, list);
  2092. list_del(&meta->list);
  2093. ctx->num_metas--;
  2094. spin_unlock(&ctx->buffer_meta_lock);
  2095. /*
  2096. * Clamp counters to 16 bits for comparison, as the HW
  2097. * counter rolls over at this point for h.264. This
  2098. * may be different for other formats, but using 16 bits
  2099. * should be enough to detect most errors and saves us
  2100. * from doing different things based on the format.
  2101. */
  2102. if ((sequence & 0xffff) != (meta->sequence & 0xffff)) {
  2103. v4l2_err(&dev->v4l2_dev,
  2104. "sequence number mismatch (%d(%d) != %d)\n",
  2105. sequence, ctx->sequence_offset,
  2106. meta->sequence);
  2107. }
  2108. decoded_frame->meta = *meta;
  2109. kfree(meta);
  2110. } else {
  2111. spin_unlock(&ctx->buffer_meta_lock);
  2112. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  2113. memset(&decoded_frame->meta, 0,
  2114. sizeof(struct coda_buffer_meta));
  2115. decoded_frame->meta.sequence = sequence;
  2116. decoded_frame->meta.last = false;
  2117. ctx->sequence_offset++;
  2118. }
  2119. trace_coda_dec_pic_done(ctx, &decoded_frame->meta);
  2120. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  2121. decoded_frame->type = (val == 0) ? V4L2_BUF_FLAG_KEYFRAME :
  2122. (val == 1) ? V4L2_BUF_FLAG_PFRAME :
  2123. V4L2_BUF_FLAG_BFRAME;
  2124. decoded_frame->error = err_mb;
  2125. }
  2126. if (display_idx == -1) {
  2127. /*
  2128. * no more frames to be decoded, but there could still
  2129. * be rotator output to dequeue
  2130. */
  2131. ctx->hold = true;
  2132. } else if (display_idx == -3) {
  2133. /* possibly prescan failure */
  2134. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  2135. v4l2_err(&dev->v4l2_dev,
  2136. "presentation frame index out of range: %d\n",
  2137. display_idx);
  2138. }
  2139. /* If a frame was copied out, return it */
  2140. if (ctx->display_idx >= 0 &&
  2141. ctx->display_idx < ctx->num_internal_frames) {
  2142. struct coda_internal_frame *ready_frame;
  2143. ready_frame = &ctx->internal_frames[ctx->display_idx];
  2144. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  2145. dst_buf->sequence = ctx->osequence++;
  2146. dst_buf->field = V4L2_FIELD_NONE;
  2147. dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  2148. V4L2_BUF_FLAG_PFRAME |
  2149. V4L2_BUF_FLAG_BFRAME);
  2150. dst_buf->flags |= ready_frame->type;
  2151. meta = &ready_frame->meta;
  2152. if (meta->last && !coda_reorder_enable(ctx)) {
  2153. /*
  2154. * If this was the last decoded frame, and reordering
  2155. * is disabled, this will be the last display frame.
  2156. */
  2157. coda_dbg(1, ctx, "last meta, marking as last frame\n");
  2158. dst_buf->flags |= V4L2_BUF_FLAG_LAST;
  2159. } else if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG &&
  2160. display_idx == -1) {
  2161. /*
  2162. * If there is no designated presentation frame anymore,
  2163. * this frame has to be the last one.
  2164. */
  2165. coda_dbg(1, ctx,
  2166. "no more frames to return, marking as last frame\n");
  2167. dst_buf->flags |= V4L2_BUF_FLAG_LAST;
  2168. }
  2169. dst_buf->timecode = meta->timecode;
  2170. dst_buf->vb2_buf.timestamp = meta->timestamp;
  2171. trace_coda_dec_rot_done(ctx, dst_buf, meta);
  2172. vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
  2173. q_data_dst->sizeimage);
  2174. if (ready_frame->error || err_vdoa)
  2175. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
  2176. else
  2177. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
  2178. if (decoded_frame) {
  2179. coda_dbg(1, ctx, "job finished: decoded %c frame %u, returned %c frame %u (%u/%u)%s\n",
  2180. coda_frame_type_char(decoded_frame->type),
  2181. decoded_frame->meta.sequence,
  2182. coda_frame_type_char(dst_buf->flags),
  2183. ready_frame->meta.sequence,
  2184. dst_buf->sequence, ctx->qsequence,
  2185. (dst_buf->flags & V4L2_BUF_FLAG_LAST) ?
  2186. " (last)" : "");
  2187. } else {
  2188. coda_dbg(1, ctx, "job finished: no frame decoded (%d), returned %c frame %u (%u/%u)%s\n",
  2189. decoded_idx,
  2190. coda_frame_type_char(dst_buf->flags),
  2191. ready_frame->meta.sequence,
  2192. dst_buf->sequence, ctx->qsequence,
  2193. (dst_buf->flags & V4L2_BUF_FLAG_LAST) ?
  2194. " (last)" : "");
  2195. }
  2196. } else {
  2197. if (decoded_frame) {
  2198. coda_dbg(1, ctx, "job finished: decoded %c frame %u, no frame returned (%d)\n",
  2199. coda_frame_type_char(decoded_frame->type),
  2200. decoded_frame->meta.sequence,
  2201. ctx->display_idx);
  2202. } else {
  2203. coda_dbg(1, ctx, "job finished: no frame decoded (%d) or returned (%d)\n",
  2204. decoded_idx, ctx->display_idx);
  2205. }
  2206. }
  2207. /* The rotator will copy the current display frame next time */
  2208. ctx->display_idx = display_idx;
  2209. /*
  2210. * The current decode run might have brought the bitstream fill level
  2211. * below the size where we can start the next decode run. As userspace
  2212. * might have filled the output queue completely and might thus be
  2213. * blocked, we can't rely on the next qbuf to trigger the bitstream
  2214. * refill. Check if we have data to refill the bitstream now.
  2215. */
  2216. mutex_lock(&ctx->bitstream_mutex);
  2217. coda_fill_bitstream(ctx, NULL);
  2218. mutex_unlock(&ctx->bitstream_mutex);
  2219. }
  2220. static void coda_decode_timeout(struct coda_ctx *ctx)
  2221. {
  2222. struct vb2_v4l2_buffer *dst_buf;
  2223. /*
  2224. * For now this only handles the case where we would deadlock with
  2225. * userspace, i.e. userspace issued DEC_CMD_STOP and waits for EOS,
  2226. * but after a failed decode run we would hold the context and wait for
  2227. * userspace to queue more buffers.
  2228. */
  2229. if (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))
  2230. return;
  2231. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  2232. dst_buf->sequence = ctx->qsequence - 1;
  2233. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_ERROR);
  2234. }
  2235. const struct coda_context_ops coda_bit_decode_ops = {
  2236. .queue_init = coda_decoder_queue_init,
  2237. .reqbufs = coda_decoder_reqbufs,
  2238. .start_streaming = coda_start_decoding,
  2239. .prepare_run = coda_prepare_decode,
  2240. .finish_run = coda_finish_decode,
  2241. .run_timeout = coda_decode_timeout,
  2242. .seq_init_work = coda_dec_seq_init_work,
  2243. .seq_end_work = coda_seq_end_work,
  2244. .release = coda_bit_release,
  2245. };
  2246. irqreturn_t coda_irq_handler(int irq, void *data)
  2247. {
  2248. struct coda_dev *dev = data;
  2249. struct coda_ctx *ctx;
  2250. /* read status register to attend the IRQ */
  2251. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  2252. coda_write(dev, 0, CODA_REG_BIT_INT_REASON);
  2253. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  2254. CODA_REG_BIT_INT_CLEAR);
  2255. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  2256. if (ctx == NULL) {
  2257. v4l2_err(&dev->v4l2_dev,
  2258. "Instance released before the end of transaction\n");
  2259. return IRQ_HANDLED;
  2260. }
  2261. trace_coda_bit_done(ctx);
  2262. if (ctx->aborting) {
  2263. coda_dbg(1, ctx, "task has been aborted\n");
  2264. }
  2265. if (coda_isbusy(ctx->dev)) {
  2266. coda_dbg(1, ctx, "coda is still busy!!!!\n");
  2267. return IRQ_NONE;
  2268. }
  2269. complete(&ctx->completion);
  2270. return IRQ_HANDLED;
  2271. }