tw5864-video.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * TW5864 driver - video encoding functions
  4. *
  5. * Copyright (C) 2016 Bluecherry, LLC <[email protected]>
  6. */
  7. #include <linux/module.h>
  8. #include <media/v4l2-common.h>
  9. #include <media/v4l2-event.h>
  10. #include <media/videobuf2-dma-contig.h>
  11. #include "tw5864.h"
  12. #include "tw5864-reg.h"
  13. #define QUANTIZATION_TABLE_LEN 96
  14. #define VLC_LOOKUP_TABLE_LEN 1024
  15. static const u16 forward_quantization_table[QUANTIZATION_TABLE_LEN] = {
  16. 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
  17. 0x3333, 0x1f82, 0x3333, 0x1f82, 0x1f82, 0x147b, 0x1f82, 0x147b,
  18. 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
  19. 0x2e8c, 0x1d42, 0x2e8c, 0x1d42, 0x1d42, 0x1234, 0x1d42, 0x1234,
  20. 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
  21. 0x2762, 0x199a, 0x2762, 0x199a, 0x199a, 0x1062, 0x199a, 0x1062,
  22. 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
  23. 0x2492, 0x16c1, 0x2492, 0x16c1, 0x16c1, 0x0e3f, 0x16c1, 0x0e3f,
  24. 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
  25. 0x2000, 0x147b, 0x2000, 0x147b, 0x147b, 0x0d1b, 0x147b, 0x0d1b,
  26. 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d,
  27. 0x1c72, 0x11cf, 0x1c72, 0x11cf, 0x11cf, 0x0b4d, 0x11cf, 0x0b4d
  28. };
  29. static const u16 inverse_quantization_table[QUANTIZATION_TABLE_LEN] = {
  30. 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
  31. 0x800a, 0x800d, 0x800a, 0x800d, 0x800d, 0x8010, 0x800d, 0x8010,
  32. 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
  33. 0x800b, 0x800e, 0x800b, 0x800e, 0x800e, 0x8012, 0x800e, 0x8012,
  34. 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
  35. 0x800d, 0x8010, 0x800d, 0x8010, 0x8010, 0x8014, 0x8010, 0x8014,
  36. 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
  37. 0x800e, 0x8012, 0x800e, 0x8012, 0x8012, 0x8017, 0x8012, 0x8017,
  38. 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
  39. 0x8010, 0x8014, 0x8010, 0x8014, 0x8014, 0x8019, 0x8014, 0x8019,
  40. 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d,
  41. 0x8012, 0x8017, 0x8012, 0x8017, 0x8017, 0x801d, 0x8017, 0x801d
  42. };
  43. static const u16 encoder_vlc_lookup_table[VLC_LOOKUP_TABLE_LEN] = {
  44. 0x011, 0x000, 0x000, 0x000, 0x065, 0x021, 0x000, 0x000, 0x087, 0x064,
  45. 0x031, 0x000, 0x097, 0x086, 0x075, 0x053, 0x0a7, 0x096, 0x085, 0x063,
  46. 0x0b7, 0x0a6, 0x095, 0x074, 0x0df, 0x0b6, 0x0a5, 0x084, 0x0db, 0x0de,
  47. 0x0b5, 0x094, 0x0d8, 0x0da, 0x0dd, 0x0a4, 0x0ef, 0x0ee, 0x0d9, 0x0b4,
  48. 0x0eb, 0x0ea, 0x0ed, 0x0dc, 0x0ff, 0x0fe, 0x0e9, 0x0ec, 0x0fb, 0x0fa,
  49. 0x0fd, 0x0e8, 0x10f, 0x0f1, 0x0f9, 0x0fc, 0x10b, 0x10e, 0x10d, 0x0f8,
  50. 0x107, 0x10a, 0x109, 0x10c, 0x104, 0x106, 0x105, 0x108, 0x023, 0x000,
  51. 0x000, 0x000, 0x06b, 0x022, 0x000, 0x000, 0x067, 0x057, 0x033, 0x000,
  52. 0x077, 0x06a, 0x069, 0x045, 0x087, 0x066, 0x065, 0x044, 0x084, 0x076,
  53. 0x075, 0x056, 0x097, 0x086, 0x085, 0x068, 0x0bf, 0x096, 0x095, 0x064,
  54. 0x0bb, 0x0be, 0x0bd, 0x074, 0x0cf, 0x0ba, 0x0b9, 0x094, 0x0cb, 0x0ce,
  55. 0x0cd, 0x0bc, 0x0c8, 0x0ca, 0x0c9, 0x0b8, 0x0df, 0x0de, 0x0dd, 0x0cc,
  56. 0x0db, 0x0da, 0x0d9, 0x0dc, 0x0d7, 0x0eb, 0x0d6, 0x0d8, 0x0e9, 0x0e8,
  57. 0x0ea, 0x0d1, 0x0e7, 0x0e6, 0x0e5, 0x0e4, 0x04f, 0x000, 0x000, 0x000,
  58. 0x06f, 0x04e, 0x000, 0x000, 0x06b, 0x05f, 0x04d, 0x000, 0x068, 0x05c,
  59. 0x05e, 0x04c, 0x07f, 0x05a, 0x05b, 0x04b, 0x07b, 0x058, 0x059, 0x04a,
  60. 0x079, 0x06e, 0x06d, 0x049, 0x078, 0x06a, 0x069, 0x048, 0x08f, 0x07e,
  61. 0x07d, 0x05d, 0x08b, 0x08e, 0x07a, 0x06c, 0x09f, 0x08a, 0x08d, 0x07c,
  62. 0x09b, 0x09e, 0x089, 0x08c, 0x098, 0x09a, 0x09d, 0x088, 0x0ad, 0x097,
  63. 0x099, 0x09c, 0x0a9, 0x0ac, 0x0ab, 0x0aa, 0x0a5, 0x0a8, 0x0a7, 0x0a6,
  64. 0x0a1, 0x0a4, 0x0a3, 0x0a2, 0x021, 0x000, 0x000, 0x000, 0x067, 0x011,
  65. 0x000, 0x000, 0x064, 0x066, 0x031, 0x000, 0x063, 0x073, 0x072, 0x065,
  66. 0x062, 0x083, 0x082, 0x070, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  67. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  68. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  69. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  70. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  71. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  72. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  73. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  74. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  75. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  76. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  77. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  78. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  79. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  80. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  81. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  82. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  83. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  84. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  85. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  86. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  87. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  88. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  89. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  90. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  91. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  92. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  93. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  94. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  95. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  96. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x011, 0x010,
  97. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  98. 0x000, 0x000, 0x000, 0x000, 0x011, 0x021, 0x020, 0x000, 0x000, 0x000,
  99. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  100. 0x023, 0x022, 0x021, 0x020, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  101. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x022, 0x021, 0x031,
  102. 0x030, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  103. 0x000, 0x000, 0x023, 0x022, 0x033, 0x032, 0x031, 0x030, 0x000, 0x000,
  104. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x023, 0x030,
  105. 0x031, 0x033, 0x032, 0x035, 0x034, 0x000, 0x000, 0x000, 0x000, 0x000,
  106. 0x000, 0x000, 0x000, 0x000, 0x037, 0x036, 0x035, 0x034, 0x033, 0x032,
  107. 0x031, 0x041, 0x051, 0x061, 0x071, 0x081, 0x091, 0x0a1, 0x0b1, 0x000,
  108. 0x002, 0x000, 0x0e4, 0x011, 0x0f4, 0x002, 0x024, 0x003, 0x005, 0x012,
  109. 0x034, 0x013, 0x065, 0x024, 0x013, 0x063, 0x015, 0x022, 0x075, 0x034,
  110. 0x044, 0x023, 0x023, 0x073, 0x054, 0x033, 0x033, 0x004, 0x043, 0x014,
  111. 0x011, 0x043, 0x014, 0x001, 0x025, 0x015, 0x035, 0x025, 0x064, 0x055,
  112. 0x045, 0x035, 0x074, 0x065, 0x085, 0x0d5, 0x012, 0x095, 0x055, 0x045,
  113. 0x095, 0x0e5, 0x084, 0x075, 0x022, 0x0a5, 0x094, 0x085, 0x032, 0x0b5,
  114. 0x003, 0x0c5, 0x001, 0x044, 0x0a5, 0x032, 0x0b5, 0x094, 0x0c5, 0x0a4,
  115. 0x0a4, 0x054, 0x0d5, 0x0b4, 0x0b4, 0x064, 0x0f5, 0x0f5, 0x053, 0x0d4,
  116. 0x0e5, 0x0c4, 0x105, 0x105, 0x0c4, 0x074, 0x063, 0x0e4, 0x0d4, 0x084,
  117. 0x073, 0x0f4, 0x004, 0x005, 0x000, 0x053, 0x000, 0x000, 0x000, 0x000,
  118. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  119. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  120. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  121. 0x000, 0x000, 0x011, 0x021, 0x031, 0x030, 0x011, 0x021, 0x020, 0x000,
  122. 0x011, 0x010, 0x000, 0x000, 0x011, 0x033, 0x032, 0x043, 0x042, 0x053,
  123. 0x052, 0x063, 0x062, 0x073, 0x072, 0x083, 0x082, 0x093, 0x092, 0x091,
  124. 0x037, 0x036, 0x035, 0x034, 0x033, 0x045, 0x044, 0x043, 0x042, 0x053,
  125. 0x052, 0x063, 0x062, 0x061, 0x060, 0x000, 0x045, 0x037, 0x036, 0x035,
  126. 0x044, 0x043, 0x034, 0x033, 0x042, 0x053, 0x052, 0x061, 0x051, 0x060,
  127. 0x000, 0x000, 0x053, 0x037, 0x045, 0x044, 0x036, 0x035, 0x034, 0x043,
  128. 0x033, 0x042, 0x052, 0x051, 0x050, 0x000, 0x000, 0x000, 0x045, 0x044,
  129. 0x043, 0x037, 0x036, 0x035, 0x034, 0x033, 0x042, 0x051, 0x041, 0x050,
  130. 0x000, 0x000, 0x000, 0x000, 0x061, 0x051, 0x037, 0x036, 0x035, 0x034,
  131. 0x033, 0x032, 0x041, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
  132. 0x061, 0x051, 0x035, 0x034, 0x033, 0x023, 0x032, 0x041, 0x031, 0x060,
  133. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x061, 0x041, 0x051, 0x033,
  134. 0x023, 0x022, 0x032, 0x031, 0x060, 0x000, 0x000, 0x000, 0x000, 0x000,
  135. 0x000, 0x000, 0x061, 0x060, 0x041, 0x023, 0x022, 0x031, 0x021, 0x051,
  136. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x051, 0x050,
  137. 0x031, 0x023, 0x022, 0x021, 0x041, 0x000, 0x000, 0x000, 0x000, 0x000,
  138. 0x000, 0x000, 0x000, 0x000, 0x040, 0x041, 0x031, 0x032, 0x011, 0x033,
  139. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  140. 0x040, 0x041, 0x021, 0x011, 0x031, 0x000, 0x000, 0x000, 0x000, 0x000,
  141. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x030, 0x031, 0x011, 0x021,
  142. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  143. 0x000, 0x000, 0x020, 0x021, 0x011, 0x000, 0x000, 0x000, 0x000, 0x000,
  144. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x010, 0x011,
  145. 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000,
  146. 0x000, 0x000, 0x000, 0x000
  147. };
  148. static const unsigned int lambda_lookup_table[] = {
  149. 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
  150. 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020,
  151. 0x0040, 0x0040, 0x0040, 0x0040, 0x0060, 0x0060, 0x0060, 0x0080,
  152. 0x0080, 0x0080, 0x00a0, 0x00c0, 0x00c0, 0x00e0, 0x0100, 0x0120,
  153. 0x0140, 0x0160, 0x01a0, 0x01c0, 0x0200, 0x0240, 0x0280, 0x02e0,
  154. 0x0320, 0x03a0, 0x0400, 0x0480, 0x0500, 0x05a0, 0x0660, 0x0720,
  155. 0x0800, 0x0900, 0x0a20, 0x0b60
  156. };
  157. static const unsigned int intra4x4_lambda3[] = {
  158. 1, 1, 1, 1, 1, 1, 1, 1,
  159. 1, 1, 1, 1, 1, 1, 1, 1,
  160. 2, 2, 2, 2, 3, 3, 3, 4,
  161. 4, 4, 5, 6, 6, 7, 8, 9,
  162. 10, 11, 13, 14, 16, 18, 20, 23,
  163. 25, 29, 32, 36, 40, 45, 51, 57,
  164. 64, 72, 81, 91
  165. };
  166. static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std);
  167. static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std);
  168. static void tw5864_handle_frame_task(struct tasklet_struct *t);
  169. static void tw5864_handle_frame(struct tw5864_h264_frame *frame);
  170. static void tw5864_frame_interval_set(struct tw5864_input *input);
  171. static int tw5864_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
  172. unsigned int *num_planes, unsigned int sizes[],
  173. struct device *alloc_ctxs[])
  174. {
  175. if (*num_planes)
  176. return sizes[0] < H264_VLC_BUF_SIZE ? -EINVAL : 0;
  177. sizes[0] = H264_VLC_BUF_SIZE;
  178. *num_planes = 1;
  179. return 0;
  180. }
  181. static void tw5864_buf_queue(struct vb2_buffer *vb)
  182. {
  183. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  184. struct vb2_queue *vq = vb->vb2_queue;
  185. struct tw5864_input *dev = vb2_get_drv_priv(vq);
  186. struct tw5864_buf *buf = container_of(vbuf, struct tw5864_buf, vb);
  187. unsigned long flags;
  188. spin_lock_irqsave(&dev->slock, flags);
  189. list_add_tail(&buf->list, &dev->active);
  190. spin_unlock_irqrestore(&dev->slock, flags);
  191. }
  192. static int tw5864_input_std_get(struct tw5864_input *input,
  193. enum tw5864_vid_std *std)
  194. {
  195. struct tw5864_dev *dev = input->root;
  196. u8 std_reg = tw_indir_readb(TW5864_INDIR_VIN_E(input->nr));
  197. *std = (std_reg & 0x70) >> 4;
  198. if (std_reg & 0x80) {
  199. dev_dbg(&dev->pci->dev,
  200. "Video format detection is in progress, please wait\n");
  201. return -EAGAIN;
  202. }
  203. return 0;
  204. }
  205. static int tw5864_enable_input(struct tw5864_input *input)
  206. {
  207. struct tw5864_dev *dev = input->root;
  208. int nr = input->nr;
  209. unsigned long flags;
  210. int d1_width = 720;
  211. int d1_height;
  212. int frame_width_bus_value = 0;
  213. int frame_height_bus_value = 0;
  214. int reg_frame_bus = 0x1c;
  215. int fmt_reg_value = 0;
  216. int downscale_enabled = 0;
  217. dev_dbg(&dev->pci->dev, "Enabling channel %d\n", nr);
  218. input->frame_seqno = 0;
  219. input->frame_gop_seqno = 0;
  220. input->h264_idr_pic_id = 0;
  221. input->reg_dsp_qp = input->qp;
  222. input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
  223. input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
  224. input->reg_emu = TW5864_EMU_EN_LPF | TW5864_EMU_EN_BHOST
  225. | TW5864_EMU_EN_SEN | TW5864_EMU_EN_ME | TW5864_EMU_EN_DDR;
  226. input->reg_dsp = nr /* channel id */
  227. | TW5864_DSP_CHROM_SW
  228. | ((0xa << 8) & TW5864_DSP_MB_DELAY)
  229. ;
  230. input->resolution = D1;
  231. d1_height = (input->std == STD_NTSC) ? 480 : 576;
  232. input->width = d1_width;
  233. input->height = d1_height;
  234. input->reg_interlacing = 0x4;
  235. switch (input->resolution) {
  236. case D1:
  237. frame_width_bus_value = 0x2cf;
  238. frame_height_bus_value = input->height - 1;
  239. reg_frame_bus = 0x1c;
  240. fmt_reg_value = 0;
  241. downscale_enabled = 0;
  242. input->reg_dsp_codec |= TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD;
  243. input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
  244. input->reg_interlacing = TW5864_DI_EN | TW5864_DSP_INTER_ST;
  245. tw_setl(TW5864_FULL_HALF_FLAG, 1 << nr);
  246. break;
  247. case HD1:
  248. input->height /= 2;
  249. input->width /= 2;
  250. frame_width_bus_value = 0x2cf;
  251. frame_height_bus_value = input->height * 2 - 1;
  252. reg_frame_bus = 0x1c;
  253. fmt_reg_value = 0;
  254. downscale_enabled = 0;
  255. input->reg_dsp_codec |= TW5864_HD1_MAP_MD;
  256. input->reg_emu |= TW5864_DSP_FRAME_TYPE_D1;
  257. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  258. break;
  259. case CIF:
  260. input->height /= 4;
  261. input->width /= 2;
  262. frame_width_bus_value = 0x15f;
  263. frame_height_bus_value = input->height * 2 - 1;
  264. reg_frame_bus = 0x07;
  265. fmt_reg_value = 1;
  266. downscale_enabled = 1;
  267. input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
  268. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  269. break;
  270. case QCIF:
  271. input->height /= 4;
  272. input->width /= 4;
  273. frame_width_bus_value = 0x15f;
  274. frame_height_bus_value = input->height * 2 - 1;
  275. reg_frame_bus = 0x07;
  276. fmt_reg_value = 1;
  277. downscale_enabled = 1;
  278. input->reg_dsp_codec |= TW5864_CIF_MAP_MD;
  279. tw_clearl(TW5864_FULL_HALF_FLAG, 1 << nr);
  280. break;
  281. }
  282. /* analog input width / 4 */
  283. tw_indir_writeb(TW5864_INDIR_IN_PIC_WIDTH(nr), d1_width / 4);
  284. tw_indir_writeb(TW5864_INDIR_IN_PIC_HEIGHT(nr), d1_height / 4);
  285. /* output width / 4 */
  286. tw_indir_writeb(TW5864_INDIR_OUT_PIC_WIDTH(nr), input->width / 4);
  287. tw_indir_writeb(TW5864_INDIR_OUT_PIC_HEIGHT(nr), input->height / 4);
  288. /*
  289. * Crop width from 720 to 704.
  290. * Above register settings need value 720 involved.
  291. */
  292. input->width = 704;
  293. tw_indir_writeb(TW5864_INDIR_CROP_ETC,
  294. tw_indir_readb(TW5864_INDIR_CROP_ETC) |
  295. TW5864_INDIR_CROP_ETC_CROP_EN);
  296. tw_writel(TW5864_DSP_PIC_MAX_MB,
  297. ((input->width / 16) << 8) | (input->height / 16));
  298. tw_writel(TW5864_FRAME_WIDTH_BUS_A(nr),
  299. frame_width_bus_value);
  300. tw_writel(TW5864_FRAME_WIDTH_BUS_B(nr),
  301. frame_width_bus_value);
  302. tw_writel(TW5864_FRAME_HEIGHT_BUS_A(nr),
  303. frame_height_bus_value);
  304. tw_writel(TW5864_FRAME_HEIGHT_BUS_B(nr),
  305. (frame_height_bus_value + 1) / 2 - 1);
  306. tw5864_frame_interval_set(input);
  307. if (downscale_enabled)
  308. tw_setl(TW5864_H264EN_CH_DNS, 1 << nr);
  309. tw_mask_shift_writel(TW5864_H264EN_CH_FMT_REG1, 0x3, 2 * nr,
  310. fmt_reg_value);
  311. tw_mask_shift_writel((nr < 2
  312. ? TW5864_H264EN_RATE_MAX_LINE_REG1
  313. : TW5864_H264EN_RATE_MAX_LINE_REG2),
  314. 0x1f, 5 * (nr % 2),
  315. input->std == STD_NTSC ? 29 : 24);
  316. tw_mask_shift_writel((nr < 2) ? TW5864_FRAME_BUS1 :
  317. TW5864_FRAME_BUS2, 0xff, (nr % 2) * 8,
  318. reg_frame_bus);
  319. spin_lock_irqsave(&dev->slock, flags);
  320. input->enabled = 1;
  321. spin_unlock_irqrestore(&dev->slock, flags);
  322. return 0;
  323. }
  324. void tw5864_request_encoded_frame(struct tw5864_input *input)
  325. {
  326. struct tw5864_dev *dev = input->root;
  327. u32 enc_buf_id_new;
  328. tw_setl(TW5864_DSP_CODEC, TW5864_CIF_MAP_MD | TW5864_HD1_MAP_MD);
  329. tw_writel(TW5864_EMU, input->reg_emu);
  330. tw_writel(TW5864_INTERLACING, input->reg_interlacing);
  331. tw_writel(TW5864_DSP, input->reg_dsp);
  332. tw_writel(TW5864_DSP_QP, input->reg_dsp_qp);
  333. tw_writel(TW5864_DSP_REF_MVP_LAMBDA, input->reg_dsp_ref_mvp_lambda);
  334. tw_writel(TW5864_DSP_I4x4_WEIGHT, input->reg_dsp_i4x4_weight);
  335. tw_mask_shift_writel(TW5864_DSP_INTRA_MODE, TW5864_DSP_INTRA_MODE_MASK,
  336. TW5864_DSP_INTRA_MODE_SHIFT,
  337. TW5864_DSP_INTRA_MODE_16x16);
  338. if (input->frame_gop_seqno == 0) {
  339. /* Produce I-frame */
  340. tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN);
  341. input->h264_idr_pic_id++;
  342. input->h264_idr_pic_id &= TW5864_DSP_REF_FRM;
  343. } else {
  344. /* Produce P-frame */
  345. tw_writel(TW5864_MOTION_SEARCH_ETC, TW5864_INTRA_EN |
  346. TW5864_ME_EN | BIT(5) /* SRCH_OPT default */);
  347. }
  348. tw5864_prepare_frame_headers(input);
  349. tw_writel(TW5864_VLC,
  350. TW5864_VLC_PCI_SEL |
  351. ((input->tail_nb_bits + 24) << TW5864_VLC_BIT_ALIGN_SHIFT) |
  352. input->reg_dsp_qp);
  353. enc_buf_id_new = tw_mask_shift_readl(TW5864_ENC_BUF_PTR_REC1, 0x3,
  354. 2 * input->nr);
  355. tw_writel(TW5864_DSP_ENC_ORG_PTR_REG,
  356. enc_buf_id_new << TW5864_DSP_ENC_ORG_PTR_SHIFT);
  357. tw_writel(TW5864_DSP_ENC_REC,
  358. enc_buf_id_new << 12 | ((enc_buf_id_new + 3) & 3));
  359. tw_writel(TW5864_SLICE, TW5864_START_NSLICE);
  360. tw_writel(TW5864_SLICE, 0);
  361. }
  362. static int tw5864_disable_input(struct tw5864_input *input)
  363. {
  364. struct tw5864_dev *dev = input->root;
  365. unsigned long flags;
  366. dev_dbg(&dev->pci->dev, "Disabling channel %d\n", input->nr);
  367. spin_lock_irqsave(&dev->slock, flags);
  368. input->enabled = 0;
  369. spin_unlock_irqrestore(&dev->slock, flags);
  370. return 0;
  371. }
  372. static int tw5864_start_streaming(struct vb2_queue *q, unsigned int count)
  373. {
  374. struct tw5864_input *input = vb2_get_drv_priv(q);
  375. int ret;
  376. ret = tw5864_enable_input(input);
  377. if (!ret)
  378. return 0;
  379. while (!list_empty(&input->active)) {
  380. struct tw5864_buf *buf = list_entry(input->active.next,
  381. struct tw5864_buf, list);
  382. list_del(&buf->list);
  383. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
  384. }
  385. return ret;
  386. }
  387. static void tw5864_stop_streaming(struct vb2_queue *q)
  388. {
  389. unsigned long flags;
  390. struct tw5864_input *input = vb2_get_drv_priv(q);
  391. tw5864_disable_input(input);
  392. spin_lock_irqsave(&input->slock, flags);
  393. if (input->vb) {
  394. vb2_buffer_done(&input->vb->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  395. input->vb = NULL;
  396. }
  397. while (!list_empty(&input->active)) {
  398. struct tw5864_buf *buf = list_entry(input->active.next,
  399. struct tw5864_buf, list);
  400. list_del(&buf->list);
  401. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  402. }
  403. spin_unlock_irqrestore(&input->slock, flags);
  404. }
  405. static const struct vb2_ops tw5864_video_qops = {
  406. .queue_setup = tw5864_queue_setup,
  407. .buf_queue = tw5864_buf_queue,
  408. .start_streaming = tw5864_start_streaming,
  409. .stop_streaming = tw5864_stop_streaming,
  410. .wait_prepare = vb2_ops_wait_prepare,
  411. .wait_finish = vb2_ops_wait_finish,
  412. };
  413. static int tw5864_s_ctrl(struct v4l2_ctrl *ctrl)
  414. {
  415. struct tw5864_input *input =
  416. container_of(ctrl->handler, struct tw5864_input, hdl);
  417. struct tw5864_dev *dev = input->root;
  418. unsigned long flags;
  419. switch (ctrl->id) {
  420. case V4L2_CID_BRIGHTNESS:
  421. tw_indir_writeb(TW5864_INDIR_VIN_A_BRIGHT(input->nr),
  422. (u8)ctrl->val);
  423. break;
  424. case V4L2_CID_HUE:
  425. tw_indir_writeb(TW5864_INDIR_VIN_7_HUE(input->nr),
  426. (u8)ctrl->val);
  427. break;
  428. case V4L2_CID_CONTRAST:
  429. tw_indir_writeb(TW5864_INDIR_VIN_9_CNTRST(input->nr),
  430. (u8)ctrl->val);
  431. break;
  432. case V4L2_CID_SATURATION:
  433. tw_indir_writeb(TW5864_INDIR_VIN_B_SAT_U(input->nr),
  434. (u8)ctrl->val);
  435. tw_indir_writeb(TW5864_INDIR_VIN_C_SAT_V(input->nr),
  436. (u8)ctrl->val);
  437. break;
  438. case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
  439. input->gop = ctrl->val;
  440. return 0;
  441. case V4L2_CID_MPEG_VIDEO_H264_MIN_QP:
  442. spin_lock_irqsave(&input->slock, flags);
  443. input->qp = ctrl->val;
  444. input->reg_dsp_qp = input->qp;
  445. input->reg_dsp_ref_mvp_lambda = lambda_lookup_table[input->qp];
  446. input->reg_dsp_i4x4_weight = intra4x4_lambda3[input->qp];
  447. spin_unlock_irqrestore(&input->slock, flags);
  448. return 0;
  449. case V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD:
  450. memset(input->md_threshold_grid_values, ctrl->val,
  451. sizeof(input->md_threshold_grid_values));
  452. return 0;
  453. case V4L2_CID_DETECT_MD_MODE:
  454. return 0;
  455. case V4L2_CID_DETECT_MD_THRESHOLD_GRID:
  456. /* input->md_threshold_grid_ctrl->p_new.p_u16 contains data */
  457. memcpy(input->md_threshold_grid_values,
  458. input->md_threshold_grid_ctrl->p_new.p_u16,
  459. sizeof(input->md_threshold_grid_values));
  460. return 0;
  461. }
  462. return 0;
  463. }
  464. static int tw5864_fmt_vid_cap(struct file *file, void *priv,
  465. struct v4l2_format *f)
  466. {
  467. struct tw5864_input *input = video_drvdata(file);
  468. f->fmt.pix.width = 704;
  469. switch (input->std) {
  470. default:
  471. WARN_ON_ONCE(1);
  472. return -EINVAL;
  473. case STD_NTSC:
  474. f->fmt.pix.height = 480;
  475. break;
  476. case STD_PAL:
  477. case STD_SECAM:
  478. f->fmt.pix.height = 576;
  479. break;
  480. }
  481. f->fmt.pix.field = V4L2_FIELD_INTERLACED;
  482. f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
  483. f->fmt.pix.sizeimage = H264_VLC_BUF_SIZE;
  484. f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
  485. return 0;
  486. }
  487. static int tw5864_enum_input(struct file *file, void *priv,
  488. struct v4l2_input *i)
  489. {
  490. struct tw5864_input *input = video_drvdata(file);
  491. struct tw5864_dev *dev = input->root;
  492. u8 indir_0x000 = tw_indir_readb(TW5864_INDIR_VIN_0(input->nr));
  493. u8 indir_0x00d = tw_indir_readb(TW5864_INDIR_VIN_D(input->nr));
  494. u8 v1 = indir_0x000;
  495. u8 v2 = indir_0x00d;
  496. if (i->index)
  497. return -EINVAL;
  498. i->type = V4L2_INPUT_TYPE_CAMERA;
  499. snprintf(i->name, sizeof(i->name), "Encoder %d", input->nr);
  500. i->std = TW5864_NORMS;
  501. if (v1 & (1 << 7))
  502. i->status |= V4L2_IN_ST_NO_SYNC;
  503. if (!(v1 & (1 << 6)))
  504. i->status |= V4L2_IN_ST_NO_H_LOCK;
  505. if (v1 & (1 << 2))
  506. i->status |= V4L2_IN_ST_NO_SIGNAL;
  507. if (v1 & (1 << 1))
  508. i->status |= V4L2_IN_ST_NO_COLOR;
  509. if (v2 & (1 << 2))
  510. i->status |= V4L2_IN_ST_MACROVISION;
  511. return 0;
  512. }
  513. static int tw5864_g_input(struct file *file, void *priv, unsigned int *i)
  514. {
  515. *i = 0;
  516. return 0;
  517. }
  518. static int tw5864_s_input(struct file *file, void *priv, unsigned int i)
  519. {
  520. if (i)
  521. return -EINVAL;
  522. return 0;
  523. }
  524. static int tw5864_querycap(struct file *file, void *priv,
  525. struct v4l2_capability *cap)
  526. {
  527. struct tw5864_input *input = video_drvdata(file);
  528. strscpy(cap->driver, "tw5864", sizeof(cap->driver));
  529. snprintf(cap->card, sizeof(cap->card), "TW5864 Encoder %d",
  530. input->nr);
  531. return 0;
  532. }
  533. static int tw5864_querystd(struct file *file, void *priv, v4l2_std_id *std)
  534. {
  535. struct tw5864_input *input = video_drvdata(file);
  536. enum tw5864_vid_std tw_std;
  537. int ret;
  538. ret = tw5864_input_std_get(input, &tw_std);
  539. if (ret)
  540. return ret;
  541. *std = tw5864_get_v4l2_std(tw_std);
  542. return 0;
  543. }
  544. static int tw5864_g_std(struct file *file, void *priv, v4l2_std_id *std)
  545. {
  546. struct tw5864_input *input = video_drvdata(file);
  547. *std = input->v4l2_std;
  548. return 0;
  549. }
  550. static int tw5864_s_std(struct file *file, void *priv, v4l2_std_id std)
  551. {
  552. struct tw5864_input *input = video_drvdata(file);
  553. struct tw5864_dev *dev = input->root;
  554. input->v4l2_std = std;
  555. input->std = tw5864_from_v4l2_std(std);
  556. tw_indir_writeb(TW5864_INDIR_VIN_E(input->nr), input->std);
  557. return 0;
  558. }
  559. static int tw5864_enum_fmt_vid_cap(struct file *file, void *priv,
  560. struct v4l2_fmtdesc *f)
  561. {
  562. if (f->index)
  563. return -EINVAL;
  564. f->pixelformat = V4L2_PIX_FMT_H264;
  565. return 0;
  566. }
  567. static int tw5864_subscribe_event(struct v4l2_fh *fh,
  568. const struct v4l2_event_subscription *sub)
  569. {
  570. switch (sub->type) {
  571. case V4L2_EVENT_MOTION_DET:
  572. /*
  573. * Allow for up to 30 events (1 second for NTSC) to be stored.
  574. */
  575. return v4l2_event_subscribe(fh, sub, 30, NULL);
  576. default:
  577. return v4l2_ctrl_subscribe_event(fh, sub);
  578. }
  579. }
  580. static void tw5864_frame_interval_set(struct tw5864_input *input)
  581. {
  582. /*
  583. * This register value seems to follow such approach: In each second
  584. * interval, when processing Nth frame, it checks Nth bit of register
  585. * value and, if the bit is 1, it processes the frame, otherwise the
  586. * frame is discarded.
  587. * So unary representation would work, but more or less equal gaps
  588. * between the frames should be preserved.
  589. *
  590. * For 1 FPS - 0x00000001
  591. * 00000000 00000000 00000000 00000001
  592. *
  593. * For max FPS - set all 25/30 lower bits:
  594. * 00111111 11111111 11111111 11111111 (NTSC)
  595. * 00000001 11111111 11111111 11111111 (PAL)
  596. *
  597. * For half of max FPS - use such pattern:
  598. * 00010101 01010101 01010101 01010101 (NTSC)
  599. * 00000001 01010101 01010101 01010101 (PAL)
  600. *
  601. * Et cetera.
  602. *
  603. * The value supplied to hardware is capped by mask of 25/30 lower bits.
  604. */
  605. struct tw5864_dev *dev = input->root;
  606. u32 unary_framerate = 0;
  607. int shift = 0;
  608. int std_max_fps = input->std == STD_NTSC ? 30 : 25;
  609. for (shift = 0; shift < std_max_fps; shift += input->frame_interval)
  610. unary_framerate |= 0x00000001 << shift;
  611. tw_writel(TW5864_H264EN_RATE_CNTL_LO_WORD(input->nr, 0),
  612. unary_framerate >> 16);
  613. tw_writel(TW5864_H264EN_RATE_CNTL_HI_WORD(input->nr, 0),
  614. unary_framerate & 0xffff);
  615. }
  616. static int tw5864_frameinterval_get(struct tw5864_input *input,
  617. struct v4l2_fract *frameinterval)
  618. {
  619. struct tw5864_dev *dev = input->root;
  620. switch (input->std) {
  621. case STD_NTSC:
  622. frameinterval->numerator = 1001;
  623. frameinterval->denominator = 30000;
  624. break;
  625. case STD_PAL:
  626. case STD_SECAM:
  627. frameinterval->numerator = 1;
  628. frameinterval->denominator = 25;
  629. break;
  630. default:
  631. dev_warn(&dev->pci->dev, "tw5864_frameinterval_get requested for unknown std %d\n",
  632. input->std);
  633. return -EINVAL;
  634. }
  635. return 0;
  636. }
  637. static int tw5864_enum_framesizes(struct file *file, void *priv,
  638. struct v4l2_frmsizeenum *fsize)
  639. {
  640. struct tw5864_input *input = video_drvdata(file);
  641. if (fsize->index > 0)
  642. return -EINVAL;
  643. if (fsize->pixel_format != V4L2_PIX_FMT_H264)
  644. return -EINVAL;
  645. fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
  646. fsize->discrete.width = 704;
  647. fsize->discrete.height = input->std == STD_NTSC ? 480 : 576;
  648. return 0;
  649. }
  650. static int tw5864_enum_frameintervals(struct file *file, void *priv,
  651. struct v4l2_frmivalenum *fintv)
  652. {
  653. struct tw5864_input *input = video_drvdata(file);
  654. struct v4l2_fract frameinterval;
  655. int std_max_fps = input->std == STD_NTSC ? 30 : 25;
  656. struct v4l2_frmsizeenum fsize = { .index = fintv->index,
  657. .pixel_format = fintv->pixel_format };
  658. int ret;
  659. ret = tw5864_enum_framesizes(file, priv, &fsize);
  660. if (ret)
  661. return ret;
  662. if (fintv->width != fsize.discrete.width ||
  663. fintv->height != fsize.discrete.height)
  664. return -EINVAL;
  665. fintv->type = V4L2_FRMIVAL_TYPE_STEPWISE;
  666. ret = tw5864_frameinterval_get(input, &frameinterval);
  667. if (ret)
  668. return ret;
  669. fintv->stepwise.step = frameinterval;
  670. fintv->stepwise.min = frameinterval;
  671. fintv->stepwise.max = frameinterval;
  672. fintv->stepwise.max.numerator *= std_max_fps;
  673. return ret;
  674. }
  675. static int tw5864_g_parm(struct file *file, void *priv,
  676. struct v4l2_streamparm *sp)
  677. {
  678. struct tw5864_input *input = video_drvdata(file);
  679. struct v4l2_captureparm *cp = &sp->parm.capture;
  680. int ret;
  681. cp->capability = V4L2_CAP_TIMEPERFRAME;
  682. ret = tw5864_frameinterval_get(input, &cp->timeperframe);
  683. if (ret)
  684. return ret;
  685. cp->timeperframe.numerator *= input->frame_interval;
  686. cp->capturemode = 0;
  687. cp->readbuffers = 2;
  688. return ret;
  689. }
  690. static int tw5864_s_parm(struct file *file, void *priv,
  691. struct v4l2_streamparm *sp)
  692. {
  693. struct tw5864_input *input = video_drvdata(file);
  694. struct v4l2_fract *t = &sp->parm.capture.timeperframe;
  695. struct v4l2_fract time_base;
  696. int ret;
  697. ret = tw5864_frameinterval_get(input, &time_base);
  698. if (ret)
  699. return ret;
  700. if (!t->numerator || !t->denominator) {
  701. t->numerator = time_base.numerator * input->frame_interval;
  702. t->denominator = time_base.denominator;
  703. } else if (t->denominator != time_base.denominator) {
  704. t->numerator = t->numerator * time_base.denominator /
  705. t->denominator;
  706. t->denominator = time_base.denominator;
  707. }
  708. input->frame_interval = t->numerator / time_base.numerator;
  709. if (input->frame_interval < 1)
  710. input->frame_interval = 1;
  711. tw5864_frame_interval_set(input);
  712. return tw5864_g_parm(file, priv, sp);
  713. }
  714. static const struct v4l2_ctrl_ops tw5864_ctrl_ops = {
  715. .s_ctrl = tw5864_s_ctrl,
  716. };
  717. static const struct v4l2_file_operations video_fops = {
  718. .owner = THIS_MODULE,
  719. .open = v4l2_fh_open,
  720. .release = vb2_fop_release,
  721. .read = vb2_fop_read,
  722. .poll = vb2_fop_poll,
  723. .mmap = vb2_fop_mmap,
  724. .unlocked_ioctl = video_ioctl2,
  725. };
  726. #ifdef CONFIG_VIDEO_ADV_DEBUG
  727. #define INDIR_SPACE_MAP_SHIFT 0x100000
  728. static int tw5864_g_reg(struct file *file, void *fh,
  729. struct v4l2_dbg_register *reg)
  730. {
  731. struct tw5864_input *input = video_drvdata(file);
  732. struct tw5864_dev *dev = input->root;
  733. if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
  734. if (reg->reg > 0x87fff)
  735. return -EINVAL;
  736. reg->size = 4;
  737. reg->val = tw_readl(reg->reg);
  738. } else {
  739. __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
  740. if (indir_addr > 0xefe)
  741. return -EINVAL;
  742. reg->size = 1;
  743. reg->val = tw_indir_readb(reg->reg);
  744. }
  745. return 0;
  746. }
  747. static int tw5864_s_reg(struct file *file, void *fh,
  748. const struct v4l2_dbg_register *reg)
  749. {
  750. struct tw5864_input *input = video_drvdata(file);
  751. struct tw5864_dev *dev = input->root;
  752. if (reg->reg < INDIR_SPACE_MAP_SHIFT) {
  753. if (reg->reg > 0x87fff)
  754. return -EINVAL;
  755. tw_writel(reg->reg, reg->val);
  756. } else {
  757. __u64 indir_addr = reg->reg - INDIR_SPACE_MAP_SHIFT;
  758. if (indir_addr > 0xefe)
  759. return -EINVAL;
  760. tw_indir_writeb(reg->reg, reg->val);
  761. }
  762. return 0;
  763. }
  764. #endif
  765. static const struct v4l2_ioctl_ops video_ioctl_ops = {
  766. .vidioc_querycap = tw5864_querycap,
  767. .vidioc_enum_fmt_vid_cap = tw5864_enum_fmt_vid_cap,
  768. .vidioc_reqbufs = vb2_ioctl_reqbufs,
  769. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  770. .vidioc_querybuf = vb2_ioctl_querybuf,
  771. .vidioc_qbuf = vb2_ioctl_qbuf,
  772. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  773. .vidioc_expbuf = vb2_ioctl_expbuf,
  774. .vidioc_querystd = tw5864_querystd,
  775. .vidioc_s_std = tw5864_s_std,
  776. .vidioc_g_std = tw5864_g_std,
  777. .vidioc_enum_input = tw5864_enum_input,
  778. .vidioc_g_input = tw5864_g_input,
  779. .vidioc_s_input = tw5864_s_input,
  780. .vidioc_streamon = vb2_ioctl_streamon,
  781. .vidioc_streamoff = vb2_ioctl_streamoff,
  782. .vidioc_try_fmt_vid_cap = tw5864_fmt_vid_cap,
  783. .vidioc_s_fmt_vid_cap = tw5864_fmt_vid_cap,
  784. .vidioc_g_fmt_vid_cap = tw5864_fmt_vid_cap,
  785. .vidioc_log_status = v4l2_ctrl_log_status,
  786. .vidioc_subscribe_event = tw5864_subscribe_event,
  787. .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
  788. .vidioc_enum_framesizes = tw5864_enum_framesizes,
  789. .vidioc_enum_frameintervals = tw5864_enum_frameintervals,
  790. .vidioc_s_parm = tw5864_s_parm,
  791. .vidioc_g_parm = tw5864_g_parm,
  792. #ifdef CONFIG_VIDEO_ADV_DEBUG
  793. .vidioc_g_register = tw5864_g_reg,
  794. .vidioc_s_register = tw5864_s_reg,
  795. #endif
  796. };
  797. static const struct video_device tw5864_video_template = {
  798. .name = "tw5864_video",
  799. .fops = &video_fops,
  800. .ioctl_ops = &video_ioctl_ops,
  801. .release = video_device_release_empty,
  802. .tvnorms = TW5864_NORMS,
  803. .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE |
  804. V4L2_CAP_STREAMING,
  805. };
  806. /* Motion Detection Threshold matrix */
  807. static const struct v4l2_ctrl_config tw5864_md_thresholds = {
  808. .ops = &tw5864_ctrl_ops,
  809. .id = V4L2_CID_DETECT_MD_THRESHOLD_GRID,
  810. .dims = {MD_CELLS_HOR, MD_CELLS_VERT},
  811. .def = 14,
  812. /* See tw5864_md_metric_from_mvd() */
  813. .max = 2 * 0x0f,
  814. .step = 1,
  815. };
  816. static int tw5864_video_input_init(struct tw5864_input *dev, int video_nr);
  817. static void tw5864_video_input_fini(struct tw5864_input *dev);
  818. static void tw5864_encoder_tables_upload(struct tw5864_dev *dev);
  819. int tw5864_video_init(struct tw5864_dev *dev, int *video_nr)
  820. {
  821. int i;
  822. int ret;
  823. unsigned long flags;
  824. int last_dma_allocated = -1;
  825. int last_input_nr_registered = -1;
  826. for (i = 0; i < H264_BUF_CNT; i++) {
  827. struct tw5864_h264_frame *frame = &dev->h264_buf[i];
  828. frame->vlc.addr = dma_alloc_coherent(&dev->pci->dev,
  829. H264_VLC_BUF_SIZE,
  830. &frame->vlc.dma_addr,
  831. GFP_KERNEL | GFP_DMA32);
  832. if (!frame->vlc.addr) {
  833. dev_err(&dev->pci->dev, "dma alloc fail\n");
  834. ret = -ENOMEM;
  835. goto free_dma;
  836. }
  837. frame->mv.addr = dma_alloc_coherent(&dev->pci->dev,
  838. H264_MV_BUF_SIZE,
  839. &frame->mv.dma_addr,
  840. GFP_KERNEL | GFP_DMA32);
  841. if (!frame->mv.addr) {
  842. dev_err(&dev->pci->dev, "dma alloc fail\n");
  843. ret = -ENOMEM;
  844. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  845. frame->vlc.addr, frame->vlc.dma_addr);
  846. goto free_dma;
  847. }
  848. last_dma_allocated = i;
  849. }
  850. tw5864_encoder_tables_upload(dev);
  851. /* Picture is distorted without this block */
  852. /* use falling edge to sample 54M to 108M */
  853. tw_indir_writeb(TW5864_INDIR_VD_108_POL, TW5864_INDIR_VD_108_POL_BOTH);
  854. tw_indir_writeb(TW5864_INDIR_CLK0_SEL, 0x00);
  855. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL0, 0x02);
  856. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_DQS_SEL1, 0x02);
  857. tw_indir_writeb(TW5864_INDIR_DDRA_DLL_CLK90_SEL, 0x02);
  858. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL0, 0x02);
  859. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_DQS_SEL1, 0x02);
  860. tw_indir_writeb(TW5864_INDIR_DDRB_DLL_CLK90_SEL, 0x02);
  861. /* video input reset */
  862. tw_indir_writeb(TW5864_INDIR_RESET, 0);
  863. tw_indir_writeb(TW5864_INDIR_RESET, TW5864_INDIR_RESET_VD |
  864. TW5864_INDIR_RESET_DLL | TW5864_INDIR_RESET_MUX_CORE);
  865. msleep(20);
  866. /*
  867. * Select Part A mode for all channels.
  868. * tw_setl instead of tw_clearl for Part B mode.
  869. *
  870. * I guess "Part B" is primarily for downscaled version of same channel
  871. * which goes in Part A of same bus
  872. */
  873. tw_writel(TW5864_FULL_HALF_MODE_SEL, 0);
  874. tw_indir_writeb(TW5864_INDIR_PV_VD_CK_POL,
  875. TW5864_INDIR_PV_VD_CK_POL_VD(0) |
  876. TW5864_INDIR_PV_VD_CK_POL_VD(1) |
  877. TW5864_INDIR_PV_VD_CK_POL_VD(2) |
  878. TW5864_INDIR_PV_VD_CK_POL_VD(3));
  879. spin_lock_irqsave(&dev->slock, flags);
  880. dev->encoder_busy = 0;
  881. dev->h264_buf_r_index = 0;
  882. dev->h264_buf_w_index = 0;
  883. tw_writel(TW5864_VLC_STREAM_BASE_ADDR,
  884. dev->h264_buf[dev->h264_buf_w_index].vlc.dma_addr);
  885. tw_writel(TW5864_MV_STREAM_BASE_ADDR,
  886. dev->h264_buf[dev->h264_buf_w_index].mv.dma_addr);
  887. spin_unlock_irqrestore(&dev->slock, flags);
  888. tw_writel(TW5864_SEN_EN_CH, 0x000f);
  889. tw_writel(TW5864_H264EN_CH_EN, 0x000f);
  890. tw_writel(TW5864_H264EN_BUS0_MAP, 0x00000000);
  891. tw_writel(TW5864_H264EN_BUS1_MAP, 0x00001111);
  892. tw_writel(TW5864_H264EN_BUS2_MAP, 0x00002222);
  893. tw_writel(TW5864_H264EN_BUS3_MAP, 0x00003333);
  894. /*
  895. * Quote from Intersil (manufacturer):
  896. * 0x0038 is managed by HW, and by default it won't pass the pointer set
  897. * at 0x0010. So if you don't do encoding, 0x0038 should stay at '3'
  898. * (with 4 frames in buffer). If you encode one frame and then move
  899. * 0x0010 to '1' for example, HW will take one more frame and set it to
  900. * buffer #0, and then you should see 0x0038 is set to '0'. There is
  901. * only one HW encoder engine, so 4 channels cannot get encoded
  902. * simultaneously. But each channel does have its own buffer (for
  903. * original frames and reconstructed frames). So there is no problem to
  904. * manage encoding for 4 channels at same time and no need to force
  905. * I-frames in switching channels.
  906. * End of quote.
  907. *
  908. * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0 (for any channel), we
  909. * have no "rolling" (until we change this value).
  910. * If we set 0x0010 (TW5864_ENC_BUF_PTR_REC1) to 0x3, it starts to roll
  911. * continuously together with 0x0038.
  912. */
  913. tw_writel(TW5864_ENC_BUF_PTR_REC1, 0x00ff);
  914. tw_writel(TW5864_PCI_INTTM_SCALE, 0);
  915. tw_writel(TW5864_INTERLACING, TW5864_DI_EN);
  916. tw_writel(TW5864_MASTER_ENB_REG, TW5864_PCI_VLC_INTR_ENB);
  917. tw_writel(TW5864_PCI_INTR_CTL,
  918. TW5864_TIMER_INTR_ENB | TW5864_PCI_MAST_ENB |
  919. TW5864_MVD_VLC_MAST_ENB);
  920. dev->irqmask |= TW5864_INTR_VLC_DONE | TW5864_INTR_TIMER;
  921. tw5864_irqmask_apply(dev);
  922. tasklet_setup(&dev->tasklet, tw5864_handle_frame_task);
  923. for (i = 0; i < TW5864_INPUTS; i++) {
  924. dev->inputs[i].root = dev;
  925. dev->inputs[i].nr = i;
  926. ret = tw5864_video_input_init(&dev->inputs[i], video_nr[i]);
  927. if (ret)
  928. goto fini_video_inputs;
  929. last_input_nr_registered = i;
  930. }
  931. return 0;
  932. fini_video_inputs:
  933. for (i = last_input_nr_registered; i >= 0; i--)
  934. tw5864_video_input_fini(&dev->inputs[i]);
  935. tasklet_kill(&dev->tasklet);
  936. free_dma:
  937. for (i = last_dma_allocated; i >= 0; i--) {
  938. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  939. dev->h264_buf[i].vlc.addr,
  940. dev->h264_buf[i].vlc.dma_addr);
  941. dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
  942. dev->h264_buf[i].mv.addr,
  943. dev->h264_buf[i].mv.dma_addr);
  944. }
  945. return ret;
  946. }
  947. static int tw5864_video_input_init(struct tw5864_input *input, int video_nr)
  948. {
  949. struct tw5864_dev *dev = input->root;
  950. int ret;
  951. struct v4l2_ctrl_handler *hdl = &input->hdl;
  952. mutex_init(&input->lock);
  953. spin_lock_init(&input->slock);
  954. /* setup video buffers queue */
  955. INIT_LIST_HEAD(&input->active);
  956. input->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  957. input->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  958. input->vidq.io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
  959. input->vidq.ops = &tw5864_video_qops;
  960. input->vidq.mem_ops = &vb2_dma_contig_memops;
  961. input->vidq.drv_priv = input;
  962. input->vidq.gfp_flags = 0;
  963. input->vidq.buf_struct_size = sizeof(struct tw5864_buf);
  964. input->vidq.lock = &input->lock;
  965. input->vidq.min_buffers_needed = 2;
  966. input->vidq.dev = &input->root->pci->dev;
  967. ret = vb2_queue_init(&input->vidq);
  968. if (ret)
  969. goto free_mutex;
  970. input->vdev = tw5864_video_template;
  971. input->vdev.v4l2_dev = &input->root->v4l2_dev;
  972. input->vdev.lock = &input->lock;
  973. input->vdev.queue = &input->vidq;
  974. video_set_drvdata(&input->vdev, input);
  975. /* Initialize the device control structures */
  976. v4l2_ctrl_handler_init(hdl, 6);
  977. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  978. V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
  979. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  980. V4L2_CID_CONTRAST, 0, 255, 1, 100);
  981. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  982. V4L2_CID_SATURATION, 0, 255, 1, 128);
  983. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_HUE, -128, 127, 1, 0);
  984. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops, V4L2_CID_MPEG_VIDEO_GOP_SIZE,
  985. 1, MAX_GOP_SIZE, 1, GOP_SIZE);
  986. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  987. V4L2_CID_MPEG_VIDEO_H264_MIN_QP, 28, 51, 1, QP_VALUE);
  988. v4l2_ctrl_new_std_menu(hdl, &tw5864_ctrl_ops,
  989. V4L2_CID_DETECT_MD_MODE,
  990. V4L2_DETECT_MD_MODE_THRESHOLD_GRID, 0,
  991. V4L2_DETECT_MD_MODE_DISABLED);
  992. v4l2_ctrl_new_std(hdl, &tw5864_ctrl_ops,
  993. V4L2_CID_DETECT_MD_GLOBAL_THRESHOLD,
  994. tw5864_md_thresholds.min, tw5864_md_thresholds.max,
  995. tw5864_md_thresholds.step, tw5864_md_thresholds.def);
  996. input->md_threshold_grid_ctrl =
  997. v4l2_ctrl_new_custom(hdl, &tw5864_md_thresholds, NULL);
  998. if (hdl->error) {
  999. ret = hdl->error;
  1000. goto free_v4l2_hdl;
  1001. }
  1002. input->vdev.ctrl_handler = hdl;
  1003. v4l2_ctrl_handler_setup(hdl);
  1004. input->qp = QP_VALUE;
  1005. input->gop = GOP_SIZE;
  1006. input->frame_interval = 1;
  1007. ret = video_register_device(&input->vdev, VFL_TYPE_VIDEO, video_nr);
  1008. if (ret)
  1009. goto free_v4l2_hdl;
  1010. dev_info(&input->root->pci->dev, "Registered video device %s\n",
  1011. video_device_node_name(&input->vdev));
  1012. /*
  1013. * Set default video standard. Doesn't matter which, the detected value
  1014. * will be found out by VIDIOC_QUERYSTD handler.
  1015. */
  1016. input->v4l2_std = V4L2_STD_NTSC_M;
  1017. input->std = STD_NTSC;
  1018. tw_indir_writeb(TW5864_INDIR_VIN_E(video_nr), 0x07);
  1019. /* to initiate auto format recognition */
  1020. tw_indir_writeb(TW5864_INDIR_VIN_F(video_nr), 0xff);
  1021. return 0;
  1022. free_v4l2_hdl:
  1023. v4l2_ctrl_handler_free(hdl);
  1024. free_mutex:
  1025. mutex_destroy(&input->lock);
  1026. return ret;
  1027. }
  1028. static void tw5864_video_input_fini(struct tw5864_input *dev)
  1029. {
  1030. vb2_video_unregister_device(&dev->vdev);
  1031. v4l2_ctrl_handler_free(&dev->hdl);
  1032. }
  1033. void tw5864_video_fini(struct tw5864_dev *dev)
  1034. {
  1035. int i;
  1036. tasklet_kill(&dev->tasklet);
  1037. for (i = 0; i < TW5864_INPUTS; i++)
  1038. tw5864_video_input_fini(&dev->inputs[i]);
  1039. for (i = 0; i < H264_BUF_CNT; i++) {
  1040. dma_free_coherent(&dev->pci->dev, H264_VLC_BUF_SIZE,
  1041. dev->h264_buf[i].vlc.addr,
  1042. dev->h264_buf[i].vlc.dma_addr);
  1043. dma_free_coherent(&dev->pci->dev, H264_MV_BUF_SIZE,
  1044. dev->h264_buf[i].mv.addr,
  1045. dev->h264_buf[i].mv.dma_addr);
  1046. }
  1047. }
  1048. void tw5864_prepare_frame_headers(struct tw5864_input *input)
  1049. {
  1050. struct tw5864_buf *vb = input->vb;
  1051. u8 *dst;
  1052. size_t dst_space;
  1053. unsigned long flags;
  1054. if (!vb) {
  1055. spin_lock_irqsave(&input->slock, flags);
  1056. if (list_empty(&input->active)) {
  1057. spin_unlock_irqrestore(&input->slock, flags);
  1058. input->vb = NULL;
  1059. return;
  1060. }
  1061. vb = list_first_entry(&input->active, struct tw5864_buf, list);
  1062. list_del(&vb->list);
  1063. spin_unlock_irqrestore(&input->slock, flags);
  1064. }
  1065. dst = vb2_plane_vaddr(&vb->vb.vb2_buf, 0);
  1066. dst_space = vb2_plane_size(&vb->vb.vb2_buf, 0);
  1067. /*
  1068. * Low-level bitstream writing functions don't have a fine way to say
  1069. * correctly that supplied buffer is too small. So we just check there
  1070. * and warn, and don't care at lower level.
  1071. * Currently all headers take below 32 bytes.
  1072. * The buffer is supposed to have plenty of free space at this point,
  1073. * anyway.
  1074. */
  1075. if (WARN_ON_ONCE(dst_space < 128))
  1076. return;
  1077. /*
  1078. * Generate H264 headers:
  1079. * If this is first frame, put SPS and PPS
  1080. */
  1081. if (input->frame_gop_seqno == 0)
  1082. tw5864_h264_put_stream_header(&dst, &dst_space, input->qp,
  1083. input->width, input->height);
  1084. /* Put slice header */
  1085. tw5864_h264_put_slice_header(&dst, &dst_space, input->h264_idr_pic_id,
  1086. input->frame_gop_seqno,
  1087. &input->tail_nb_bits, &input->tail);
  1088. input->vb = vb;
  1089. input->buf_cur_ptr = dst;
  1090. input->buf_cur_space_left = dst_space;
  1091. }
  1092. /*
  1093. * Returns heuristic motion detection metric value from known components of
  1094. * hardware-provided Motion Vector Data.
  1095. */
  1096. static unsigned int tw5864_md_metric_from_mvd(u32 mvd)
  1097. {
  1098. /*
  1099. * Format of motion vector data exposed by tw5864, according to
  1100. * manufacturer:
  1101. * mv_x 10 bits
  1102. * mv_y 10 bits
  1103. * non_zero_members 8 bits
  1104. * mb_type 3 bits
  1105. * reserved 1 bit
  1106. *
  1107. * non_zero_members: number of non-zero residuals in each macro block
  1108. * after quantization
  1109. *
  1110. * unsigned int reserved = mvd >> 31;
  1111. * unsigned int mb_type = (mvd >> 28) & 0x7;
  1112. * unsigned int non_zero_members = (mvd >> 20) & 0xff;
  1113. */
  1114. unsigned int mv_y = (mvd >> 10) & 0x3ff;
  1115. unsigned int mv_x = mvd & 0x3ff;
  1116. /* heuristic: */
  1117. mv_x &= 0x0f;
  1118. mv_y &= 0x0f;
  1119. return mv_y + mv_x;
  1120. }
  1121. static int tw5864_is_motion_triggered(struct tw5864_h264_frame *frame)
  1122. {
  1123. struct tw5864_input *input = frame->input;
  1124. u32 *mv = (u32 *)frame->mv.addr;
  1125. int i;
  1126. int detected = 0;
  1127. for (i = 0; i < MD_CELLS; i++) {
  1128. const u16 thresh = input->md_threshold_grid_values[i];
  1129. const unsigned int metric = tw5864_md_metric_from_mvd(mv[i]);
  1130. if (metric > thresh)
  1131. detected = 1;
  1132. if (detected)
  1133. break;
  1134. }
  1135. return detected;
  1136. }
  1137. static void tw5864_handle_frame_task(struct tasklet_struct *t)
  1138. {
  1139. struct tw5864_dev *dev = from_tasklet(dev, t, tasklet);
  1140. unsigned long flags;
  1141. int batch_size = H264_BUF_CNT;
  1142. spin_lock_irqsave(&dev->slock, flags);
  1143. while (dev->h264_buf_r_index != dev->h264_buf_w_index && batch_size--) {
  1144. struct tw5864_h264_frame *frame =
  1145. &dev->h264_buf[dev->h264_buf_r_index];
  1146. spin_unlock_irqrestore(&dev->slock, flags);
  1147. dma_sync_single_for_cpu(&dev->pci->dev, frame->vlc.dma_addr,
  1148. H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
  1149. dma_sync_single_for_cpu(&dev->pci->dev, frame->mv.dma_addr,
  1150. H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
  1151. tw5864_handle_frame(frame);
  1152. dma_sync_single_for_device(&dev->pci->dev, frame->vlc.dma_addr,
  1153. H264_VLC_BUF_SIZE, DMA_FROM_DEVICE);
  1154. dma_sync_single_for_device(&dev->pci->dev, frame->mv.dma_addr,
  1155. H264_MV_BUF_SIZE, DMA_FROM_DEVICE);
  1156. spin_lock_irqsave(&dev->slock, flags);
  1157. dev->h264_buf_r_index++;
  1158. dev->h264_buf_r_index %= H264_BUF_CNT;
  1159. }
  1160. spin_unlock_irqrestore(&dev->slock, flags);
  1161. }
  1162. #ifdef DEBUG
  1163. static u32 tw5864_vlc_checksum(u32 *data, int len)
  1164. {
  1165. u32 val, count_len = len;
  1166. val = *data++;
  1167. while (((count_len >> 2) - 1) > 0) {
  1168. val ^= *data++;
  1169. count_len -= 4;
  1170. }
  1171. val ^= htonl((len >> 2));
  1172. return val;
  1173. }
  1174. #endif
  1175. static void tw5864_handle_frame(struct tw5864_h264_frame *frame)
  1176. {
  1177. #define SKIP_VLCBUF_BYTES 3
  1178. struct tw5864_input *input = frame->input;
  1179. struct tw5864_dev *dev = input->root;
  1180. struct tw5864_buf *vb;
  1181. struct vb2_v4l2_buffer *v4l2_buf;
  1182. int frame_len = frame->vlc_len - SKIP_VLCBUF_BYTES;
  1183. u8 *dst = input->buf_cur_ptr;
  1184. u8 tail_mask, vlc_mask = 0;
  1185. int i;
  1186. u8 vlc_first_byte = ((u8 *)(frame->vlc.addr + SKIP_VLCBUF_BYTES))[0];
  1187. unsigned long flags;
  1188. int zero_run;
  1189. u8 *src;
  1190. u8 *src_end;
  1191. #ifdef DEBUG
  1192. if (frame->checksum !=
  1193. tw5864_vlc_checksum((u32 *)frame->vlc.addr, frame_len))
  1194. dev_err(&dev->pci->dev,
  1195. "Checksum of encoded frame doesn't match!\n");
  1196. #endif
  1197. spin_lock_irqsave(&input->slock, flags);
  1198. vb = input->vb;
  1199. input->vb = NULL;
  1200. spin_unlock_irqrestore(&input->slock, flags);
  1201. if (!vb) { /* Gone because of disabling */
  1202. dev_dbg(&dev->pci->dev, "vb is empty, dropping frame\n");
  1203. return;
  1204. }
  1205. v4l2_buf = to_vb2_v4l2_buffer(&vb->vb.vb2_buf);
  1206. /*
  1207. * Check for space.
  1208. * Mind the overhead of startcode emulation prevention.
  1209. */
  1210. if (input->buf_cur_space_left < frame_len * 5 / 4) {
  1211. dev_err_once(&dev->pci->dev,
  1212. "Left space in vb2 buffer, %d bytes, is less than considered safely enough to put frame of length %d. Dropping this frame.\n",
  1213. input->buf_cur_space_left, frame_len);
  1214. return;
  1215. }
  1216. for (i = 0; i < 8 - input->tail_nb_bits; i++)
  1217. vlc_mask |= 1 << i;
  1218. tail_mask = (~vlc_mask) & 0xff;
  1219. dst[0] = (input->tail & tail_mask) | (vlc_first_byte & vlc_mask);
  1220. frame_len--;
  1221. dst++;
  1222. /* H.264 startcode emulation prevention */
  1223. src = frame->vlc.addr + SKIP_VLCBUF_BYTES + 1;
  1224. src_end = src + frame_len;
  1225. zero_run = 0;
  1226. for (; src < src_end; src++) {
  1227. if (zero_run < 2) {
  1228. if (*src == 0)
  1229. ++zero_run;
  1230. else
  1231. zero_run = 0;
  1232. } else {
  1233. if ((*src & ~0x03) == 0)
  1234. *dst++ = 0x03;
  1235. zero_run = *src == 0;
  1236. }
  1237. *dst++ = *src;
  1238. }
  1239. vb2_set_plane_payload(&vb->vb.vb2_buf, 0,
  1240. dst - (u8 *)vb2_plane_vaddr(&vb->vb.vb2_buf, 0));
  1241. vb->vb.vb2_buf.timestamp = frame->timestamp;
  1242. v4l2_buf->field = V4L2_FIELD_INTERLACED;
  1243. v4l2_buf->sequence = frame->seqno;
  1244. /* Check for motion flags */
  1245. if (frame->gop_seqno /* P-frame */ &&
  1246. tw5864_is_motion_triggered(frame)) {
  1247. struct v4l2_event ev = {
  1248. .type = V4L2_EVENT_MOTION_DET,
  1249. .u.motion_det = {
  1250. .flags = V4L2_EVENT_MD_FL_HAVE_FRAME_SEQ,
  1251. .frame_sequence = v4l2_buf->sequence,
  1252. },
  1253. };
  1254. v4l2_event_queue(&input->vdev, &ev);
  1255. }
  1256. vb2_buffer_done(&vb->vb.vb2_buf, VB2_BUF_STATE_DONE);
  1257. }
  1258. static v4l2_std_id tw5864_get_v4l2_std(enum tw5864_vid_std std)
  1259. {
  1260. switch (std) {
  1261. case STD_NTSC: return V4L2_STD_NTSC_M;
  1262. case STD_PAL: return V4L2_STD_PAL_B;
  1263. case STD_SECAM: return V4L2_STD_SECAM_B;
  1264. case STD_NTSC443: return V4L2_STD_NTSC_443;
  1265. case STD_PAL_M: return V4L2_STD_PAL_M;
  1266. case STD_PAL_CN: return V4L2_STD_PAL_Nc;
  1267. case STD_PAL_60: return V4L2_STD_PAL_60;
  1268. case STD_INVALID: return V4L2_STD_UNKNOWN;
  1269. }
  1270. return 0;
  1271. }
  1272. static enum tw5864_vid_std tw5864_from_v4l2_std(v4l2_std_id v4l2_std)
  1273. {
  1274. if (v4l2_std & V4L2_STD_NTSC_M)
  1275. return STD_NTSC;
  1276. if (v4l2_std & V4L2_STD_PAL_B)
  1277. return STD_PAL;
  1278. if (v4l2_std & V4L2_STD_SECAM_B)
  1279. return STD_SECAM;
  1280. if (v4l2_std & V4L2_STD_NTSC_443)
  1281. return STD_NTSC443;
  1282. if (v4l2_std & V4L2_STD_PAL_M)
  1283. return STD_PAL_M;
  1284. if (v4l2_std & V4L2_STD_PAL_Nc)
  1285. return STD_PAL_CN;
  1286. if (v4l2_std & V4L2_STD_PAL_60)
  1287. return STD_PAL_60;
  1288. return STD_INVALID;
  1289. }
  1290. static void tw5864_encoder_tables_upload(struct tw5864_dev *dev)
  1291. {
  1292. int i;
  1293. tw_writel(TW5864_VLC_RD, 0x1);
  1294. for (i = 0; i < VLC_LOOKUP_TABLE_LEN; i++) {
  1295. tw_writel((TW5864_VLC_STREAM_MEM_START + i * 4),
  1296. encoder_vlc_lookup_table[i]);
  1297. }
  1298. tw_writel(TW5864_VLC_RD, 0x0);
  1299. for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
  1300. tw_writel((TW5864_QUAN_TAB + i * 4),
  1301. forward_quantization_table[i]);
  1302. }
  1303. for (i = 0; i < QUANTIZATION_TABLE_LEN; i++) {
  1304. tw_writel((TW5864_QUAN_TAB + i * 4),
  1305. inverse_quantization_table[i]);
  1306. }
  1307. }