smipcie-main.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * SMI PCIe driver for DVBSky cards.
  4. *
  5. * Copyright (C) 2014 Max nibble <[email protected]>
  6. */
  7. #include "smipcie.h"
  8. #include "m88ds3103.h"
  9. #include "ts2020.h"
  10. #include "m88rs6000t.h"
  11. #include "si2168.h"
  12. #include "si2157.h"
  13. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  14. static int smi_hw_init(struct smi_dev *dev)
  15. {
  16. u32 port_mux, port_ctrl, int_stat;
  17. /* set port mux.*/
  18. port_mux = smi_read(MUX_MODE_CTRL);
  19. port_mux &= ~(rbPaMSMask);
  20. port_mux |= rbPaMSDtvNoGpio;
  21. port_mux &= ~(rbPbMSMask);
  22. port_mux |= rbPbMSDtvNoGpio;
  23. port_mux &= ~(0x0f0000);
  24. port_mux |= 0x50000;
  25. smi_write(MUX_MODE_CTRL, port_mux);
  26. /* set DTV register.*/
  27. /* Port A */
  28. port_ctrl = smi_read(VIDEO_CTRL_STATUS_A);
  29. port_ctrl &= ~0x01;
  30. smi_write(VIDEO_CTRL_STATUS_A, port_ctrl);
  31. port_ctrl = smi_read(MPEG2_CTRL_A);
  32. port_ctrl &= ~0x40;
  33. port_ctrl |= 0x80;
  34. smi_write(MPEG2_CTRL_A, port_ctrl);
  35. /* Port B */
  36. port_ctrl = smi_read(VIDEO_CTRL_STATUS_B);
  37. port_ctrl &= ~0x01;
  38. smi_write(VIDEO_CTRL_STATUS_B, port_ctrl);
  39. port_ctrl = smi_read(MPEG2_CTRL_B);
  40. port_ctrl &= ~0x40;
  41. port_ctrl |= 0x80;
  42. smi_write(MPEG2_CTRL_B, port_ctrl);
  43. /* disable and clear interrupt.*/
  44. smi_write(MSI_INT_ENA_CLR, ALL_INT);
  45. int_stat = smi_read(MSI_INT_STATUS);
  46. smi_write(MSI_INT_STATUS_CLR, int_stat);
  47. /* reset demod.*/
  48. smi_clear(PERIPHERAL_CTRL, 0x0303);
  49. msleep(50);
  50. smi_set(PERIPHERAL_CTRL, 0x0101);
  51. return 0;
  52. }
  53. /* i2c bit bus.*/
  54. static void smi_i2c_cfg(struct smi_dev *dev, u32 sw_ctl)
  55. {
  56. u32 dwCtrl;
  57. dwCtrl = smi_read(sw_ctl);
  58. dwCtrl &= ~0x18; /* disable output.*/
  59. dwCtrl |= 0x21; /* reset and software mode.*/
  60. dwCtrl &= ~0xff00;
  61. dwCtrl |= 0x6400;
  62. smi_write(sw_ctl, dwCtrl);
  63. msleep(20);
  64. dwCtrl = smi_read(sw_ctl);
  65. dwCtrl &= ~0x20;
  66. smi_write(sw_ctl, dwCtrl);
  67. }
  68. static void smi_i2c_setsda(struct smi_dev *dev, int state, u32 sw_ctl)
  69. {
  70. if (state) {
  71. /* set as input.*/
  72. smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
  73. } else {
  74. smi_clear(sw_ctl, SW_I2C_MSK_DAT_OUT);
  75. /* set as output.*/
  76. smi_set(sw_ctl, SW_I2C_MSK_DAT_EN);
  77. }
  78. }
  79. static void smi_i2c_setscl(void *data, int state, u32 sw_ctl)
  80. {
  81. struct smi_dev *dev = data;
  82. if (state) {
  83. /* set as input.*/
  84. smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
  85. } else {
  86. smi_clear(sw_ctl, SW_I2C_MSK_CLK_OUT);
  87. /* set as output.*/
  88. smi_set(sw_ctl, SW_I2C_MSK_CLK_EN);
  89. }
  90. }
  91. static int smi_i2c_getsda(void *data, u32 sw_ctl)
  92. {
  93. struct smi_dev *dev = data;
  94. /* set as input.*/
  95. smi_clear(sw_ctl, SW_I2C_MSK_DAT_EN);
  96. udelay(1);
  97. return (smi_read(sw_ctl) & SW_I2C_MSK_DAT_IN) ? 1 : 0;
  98. }
  99. static int smi_i2c_getscl(void *data, u32 sw_ctl)
  100. {
  101. struct smi_dev *dev = data;
  102. /* set as input.*/
  103. smi_clear(sw_ctl, SW_I2C_MSK_CLK_EN);
  104. udelay(1);
  105. return (smi_read(sw_ctl) & SW_I2C_MSK_CLK_IN) ? 1 : 0;
  106. }
  107. /* i2c 0.*/
  108. static void smi_i2c0_setsda(void *data, int state)
  109. {
  110. struct smi_dev *dev = data;
  111. smi_i2c_setsda(dev, state, I2C_A_SW_CTL);
  112. }
  113. static void smi_i2c0_setscl(void *data, int state)
  114. {
  115. struct smi_dev *dev = data;
  116. smi_i2c_setscl(dev, state, I2C_A_SW_CTL);
  117. }
  118. static int smi_i2c0_getsda(void *data)
  119. {
  120. struct smi_dev *dev = data;
  121. return smi_i2c_getsda(dev, I2C_A_SW_CTL);
  122. }
  123. static int smi_i2c0_getscl(void *data)
  124. {
  125. struct smi_dev *dev = data;
  126. return smi_i2c_getscl(dev, I2C_A_SW_CTL);
  127. }
  128. /* i2c 1.*/
  129. static void smi_i2c1_setsda(void *data, int state)
  130. {
  131. struct smi_dev *dev = data;
  132. smi_i2c_setsda(dev, state, I2C_B_SW_CTL);
  133. }
  134. static void smi_i2c1_setscl(void *data, int state)
  135. {
  136. struct smi_dev *dev = data;
  137. smi_i2c_setscl(dev, state, I2C_B_SW_CTL);
  138. }
  139. static int smi_i2c1_getsda(void *data)
  140. {
  141. struct smi_dev *dev = data;
  142. return smi_i2c_getsda(dev, I2C_B_SW_CTL);
  143. }
  144. static int smi_i2c1_getscl(void *data)
  145. {
  146. struct smi_dev *dev = data;
  147. return smi_i2c_getscl(dev, I2C_B_SW_CTL);
  148. }
  149. static int smi_i2c_init(struct smi_dev *dev)
  150. {
  151. int ret;
  152. /* i2c bus 0 */
  153. smi_i2c_cfg(dev, I2C_A_SW_CTL);
  154. i2c_set_adapdata(&dev->i2c_bus[0], dev);
  155. strscpy(dev->i2c_bus[0].name, "SMI-I2C0", sizeof(dev->i2c_bus[0].name));
  156. dev->i2c_bus[0].owner = THIS_MODULE;
  157. dev->i2c_bus[0].dev.parent = &dev->pci_dev->dev;
  158. dev->i2c_bus[0].algo_data = &dev->i2c_bit[0];
  159. dev->i2c_bit[0].data = dev;
  160. dev->i2c_bit[0].setsda = smi_i2c0_setsda;
  161. dev->i2c_bit[0].setscl = smi_i2c0_setscl;
  162. dev->i2c_bit[0].getsda = smi_i2c0_getsda;
  163. dev->i2c_bit[0].getscl = smi_i2c0_getscl;
  164. dev->i2c_bit[0].udelay = 12;
  165. dev->i2c_bit[0].timeout = 10;
  166. /* Raise SCL and SDA */
  167. smi_i2c0_setsda(dev, 1);
  168. smi_i2c0_setscl(dev, 1);
  169. ret = i2c_bit_add_bus(&dev->i2c_bus[0]);
  170. if (ret < 0)
  171. return ret;
  172. /* i2c bus 1 */
  173. smi_i2c_cfg(dev, I2C_B_SW_CTL);
  174. i2c_set_adapdata(&dev->i2c_bus[1], dev);
  175. strscpy(dev->i2c_bus[1].name, "SMI-I2C1", sizeof(dev->i2c_bus[1].name));
  176. dev->i2c_bus[1].owner = THIS_MODULE;
  177. dev->i2c_bus[1].dev.parent = &dev->pci_dev->dev;
  178. dev->i2c_bus[1].algo_data = &dev->i2c_bit[1];
  179. dev->i2c_bit[1].data = dev;
  180. dev->i2c_bit[1].setsda = smi_i2c1_setsda;
  181. dev->i2c_bit[1].setscl = smi_i2c1_setscl;
  182. dev->i2c_bit[1].getsda = smi_i2c1_getsda;
  183. dev->i2c_bit[1].getscl = smi_i2c1_getscl;
  184. dev->i2c_bit[1].udelay = 12;
  185. dev->i2c_bit[1].timeout = 10;
  186. /* Raise SCL and SDA */
  187. smi_i2c1_setsda(dev, 1);
  188. smi_i2c1_setscl(dev, 1);
  189. ret = i2c_bit_add_bus(&dev->i2c_bus[1]);
  190. if (ret < 0)
  191. i2c_del_adapter(&dev->i2c_bus[0]);
  192. return ret;
  193. }
  194. static void smi_i2c_exit(struct smi_dev *dev)
  195. {
  196. i2c_del_adapter(&dev->i2c_bus[0]);
  197. i2c_del_adapter(&dev->i2c_bus[1]);
  198. }
  199. static int smi_read_eeprom(struct i2c_adapter *i2c, u16 reg, u8 *data, u16 size)
  200. {
  201. int ret;
  202. u8 b0[2] = { (reg >> 8) & 0xff, reg & 0xff };
  203. struct i2c_msg msg[] = {
  204. { .addr = 0x50, .flags = 0,
  205. .buf = b0, .len = 2 },
  206. { .addr = 0x50, .flags = I2C_M_RD,
  207. .buf = data, .len = size }
  208. };
  209. ret = i2c_transfer(i2c, msg, 2);
  210. if (ret != 2) {
  211. dev_err(&i2c->dev, "%s: reg=0x%x (error=%d)\n",
  212. __func__, reg, ret);
  213. return ret;
  214. }
  215. return ret;
  216. }
  217. /* ts port interrupt operations */
  218. static void smi_port_disableInterrupt(struct smi_port *port)
  219. {
  220. struct smi_dev *dev = port->dev;
  221. smi_write(MSI_INT_ENA_CLR,
  222. (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
  223. }
  224. static void smi_port_enableInterrupt(struct smi_port *port)
  225. {
  226. struct smi_dev *dev = port->dev;
  227. smi_write(MSI_INT_ENA_SET,
  228. (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
  229. }
  230. static void smi_port_clearInterrupt(struct smi_port *port)
  231. {
  232. struct smi_dev *dev = port->dev;
  233. smi_write(MSI_INT_STATUS_CLR,
  234. (port->_dmaInterruptCH0 | port->_dmaInterruptCH1));
  235. }
  236. /* tasklet handler: DMA data to dmx.*/
  237. static void smi_dma_xfer(struct tasklet_struct *t)
  238. {
  239. struct smi_port *port = from_tasklet(port, t, tasklet);
  240. struct smi_dev *dev = port->dev;
  241. u32 intr_status, finishedData, dmaManagement;
  242. u8 dmaChan0State, dmaChan1State;
  243. intr_status = port->_int_status;
  244. dmaManagement = smi_read(port->DMA_MANAGEMENT);
  245. dmaChan0State = (u8)((dmaManagement & 0x00000030) >> 4);
  246. dmaChan1State = (u8)((dmaManagement & 0x00300000) >> 20);
  247. /* CH-0 DMA interrupt.*/
  248. if ((intr_status & port->_dmaInterruptCH0) && (dmaChan0State == 0x01)) {
  249. dev_dbg(&dev->pci_dev->dev,
  250. "Port[%d]-DMA CH0 engine complete successful !\n",
  251. port->idx);
  252. finishedData = smi_read(port->DMA_CHAN0_TRANS_STATE);
  253. finishedData &= 0x003FFFFF;
  254. /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
  255. * indicate dma total transfer length and
  256. * zero of [21:0] indicate dma total transfer length
  257. * equal to 0x400000 (4MB)*/
  258. if (finishedData == 0)
  259. finishedData = 0x00400000;
  260. if (finishedData != SMI_TS_DMA_BUF_SIZE) {
  261. dev_dbg(&dev->pci_dev->dev,
  262. "DMA CH0 engine complete length mismatched, finish data=%d !\n",
  263. finishedData);
  264. }
  265. dvb_dmx_swfilter_packets(&port->demux,
  266. port->cpu_addr[0], (finishedData / 188));
  267. /*dvb_dmx_swfilter(&port->demux,
  268. port->cpu_addr[0], finishedData);*/
  269. }
  270. /* CH-1 DMA interrupt.*/
  271. if ((intr_status & port->_dmaInterruptCH1) && (dmaChan1State == 0x01)) {
  272. dev_dbg(&dev->pci_dev->dev,
  273. "Port[%d]-DMA CH1 engine complete successful !\n",
  274. port->idx);
  275. finishedData = smi_read(port->DMA_CHAN1_TRANS_STATE);
  276. finishedData &= 0x003FFFFF;
  277. /* value of DMA_PORT0_CHAN0_TRANS_STATE register [21:0]
  278. * indicate dma total transfer length and
  279. * zero of [21:0] indicate dma total transfer length
  280. * equal to 0x400000 (4MB)*/
  281. if (finishedData == 0)
  282. finishedData = 0x00400000;
  283. if (finishedData != SMI_TS_DMA_BUF_SIZE) {
  284. dev_dbg(&dev->pci_dev->dev,
  285. "DMA CH1 engine complete length mismatched, finish data=%d !\n",
  286. finishedData);
  287. }
  288. dvb_dmx_swfilter_packets(&port->demux,
  289. port->cpu_addr[1], (finishedData / 188));
  290. /*dvb_dmx_swfilter(&port->demux,
  291. port->cpu_addr[1], finishedData);*/
  292. }
  293. /* restart DMA.*/
  294. if (intr_status & port->_dmaInterruptCH0)
  295. dmaManagement |= 0x00000002;
  296. if (intr_status & port->_dmaInterruptCH1)
  297. dmaManagement |= 0x00020000;
  298. smi_write(port->DMA_MANAGEMENT, dmaManagement);
  299. /* Re-enable interrupts */
  300. smi_port_enableInterrupt(port);
  301. }
  302. static void smi_port_dma_free(struct smi_port *port)
  303. {
  304. if (port->cpu_addr[0]) {
  305. dma_free_coherent(&port->dev->pci_dev->dev,
  306. SMI_TS_DMA_BUF_SIZE, port->cpu_addr[0],
  307. port->dma_addr[0]);
  308. port->cpu_addr[0] = NULL;
  309. }
  310. if (port->cpu_addr[1]) {
  311. dma_free_coherent(&port->dev->pci_dev->dev,
  312. SMI_TS_DMA_BUF_SIZE, port->cpu_addr[1],
  313. port->dma_addr[1]);
  314. port->cpu_addr[1] = NULL;
  315. }
  316. }
  317. static int smi_port_init(struct smi_port *port, int dmaChanUsed)
  318. {
  319. dev_dbg(&port->dev->pci_dev->dev,
  320. "%s, port %d, dmaused %d\n", __func__, port->idx, dmaChanUsed);
  321. port->enable = 0;
  322. if (port->idx == 0) {
  323. /* Port A */
  324. port->_dmaInterruptCH0 = dmaChanUsed & 0x01;
  325. port->_dmaInterruptCH1 = dmaChanUsed & 0x02;
  326. port->DMA_CHAN0_ADDR_LOW = DMA_PORTA_CHAN0_ADDR_LOW;
  327. port->DMA_CHAN0_ADDR_HI = DMA_PORTA_CHAN0_ADDR_HI;
  328. port->DMA_CHAN0_TRANS_STATE = DMA_PORTA_CHAN0_TRANS_STATE;
  329. port->DMA_CHAN0_CONTROL = DMA_PORTA_CHAN0_CONTROL;
  330. port->DMA_CHAN1_ADDR_LOW = DMA_PORTA_CHAN1_ADDR_LOW;
  331. port->DMA_CHAN1_ADDR_HI = DMA_PORTA_CHAN1_ADDR_HI;
  332. port->DMA_CHAN1_TRANS_STATE = DMA_PORTA_CHAN1_TRANS_STATE;
  333. port->DMA_CHAN1_CONTROL = DMA_PORTA_CHAN1_CONTROL;
  334. port->DMA_MANAGEMENT = DMA_PORTA_MANAGEMENT;
  335. } else {
  336. /* Port B */
  337. port->_dmaInterruptCH0 = (dmaChanUsed << 2) & 0x04;
  338. port->_dmaInterruptCH1 = (dmaChanUsed << 2) & 0x08;
  339. port->DMA_CHAN0_ADDR_LOW = DMA_PORTB_CHAN0_ADDR_LOW;
  340. port->DMA_CHAN0_ADDR_HI = DMA_PORTB_CHAN0_ADDR_HI;
  341. port->DMA_CHAN0_TRANS_STATE = DMA_PORTB_CHAN0_TRANS_STATE;
  342. port->DMA_CHAN0_CONTROL = DMA_PORTB_CHAN0_CONTROL;
  343. port->DMA_CHAN1_ADDR_LOW = DMA_PORTB_CHAN1_ADDR_LOW;
  344. port->DMA_CHAN1_ADDR_HI = DMA_PORTB_CHAN1_ADDR_HI;
  345. port->DMA_CHAN1_TRANS_STATE = DMA_PORTB_CHAN1_TRANS_STATE;
  346. port->DMA_CHAN1_CONTROL = DMA_PORTB_CHAN1_CONTROL;
  347. port->DMA_MANAGEMENT = DMA_PORTB_MANAGEMENT;
  348. }
  349. if (port->_dmaInterruptCH0) {
  350. port->cpu_addr[0] = dma_alloc_coherent(&port->dev->pci_dev->dev,
  351. SMI_TS_DMA_BUF_SIZE,
  352. &port->dma_addr[0],
  353. GFP_KERNEL);
  354. if (!port->cpu_addr[0]) {
  355. dev_err(&port->dev->pci_dev->dev,
  356. "Port[%d] DMA CH0 memory allocation failed!\n",
  357. port->idx);
  358. goto err;
  359. }
  360. }
  361. if (port->_dmaInterruptCH1) {
  362. port->cpu_addr[1] = dma_alloc_coherent(&port->dev->pci_dev->dev,
  363. SMI_TS_DMA_BUF_SIZE,
  364. &port->dma_addr[1],
  365. GFP_KERNEL);
  366. if (!port->cpu_addr[1]) {
  367. dev_err(&port->dev->pci_dev->dev,
  368. "Port[%d] DMA CH1 memory allocation failed!\n",
  369. port->idx);
  370. goto err;
  371. }
  372. }
  373. smi_port_disableInterrupt(port);
  374. tasklet_setup(&port->tasklet, smi_dma_xfer);
  375. tasklet_disable(&port->tasklet);
  376. port->enable = 1;
  377. return 0;
  378. err:
  379. smi_port_dma_free(port);
  380. return -ENOMEM;
  381. }
  382. static void smi_port_exit(struct smi_port *port)
  383. {
  384. smi_port_disableInterrupt(port);
  385. tasklet_kill(&port->tasklet);
  386. smi_port_dma_free(port);
  387. port->enable = 0;
  388. }
  389. static int smi_port_irq(struct smi_port *port, u32 int_status)
  390. {
  391. u32 port_req_irq = port->_dmaInterruptCH0 | port->_dmaInterruptCH1;
  392. int handled = 0;
  393. if (int_status & port_req_irq) {
  394. smi_port_disableInterrupt(port);
  395. port->_int_status = int_status;
  396. smi_port_clearInterrupt(port);
  397. tasklet_schedule(&port->tasklet);
  398. handled = 1;
  399. }
  400. return handled;
  401. }
  402. static irqreturn_t smi_irq_handler(int irq, void *dev_id)
  403. {
  404. struct smi_dev *dev = dev_id;
  405. struct smi_port *port0 = &dev->ts_port[0];
  406. struct smi_port *port1 = &dev->ts_port[1];
  407. struct smi_rc *ir = &dev->ir;
  408. int handled = 0;
  409. u32 intr_status = smi_read(MSI_INT_STATUS);
  410. /* ts0 interrupt.*/
  411. if (dev->info->ts_0)
  412. handled += smi_port_irq(port0, intr_status);
  413. /* ts1 interrupt.*/
  414. if (dev->info->ts_1)
  415. handled += smi_port_irq(port1, intr_status);
  416. /* ir interrupt.*/
  417. handled += smi_ir_irq(ir, intr_status);
  418. return IRQ_RETVAL(handled);
  419. }
  420. static struct i2c_client *smi_add_i2c_client(struct i2c_adapter *adapter,
  421. struct i2c_board_info *info)
  422. {
  423. struct i2c_client *client;
  424. request_module(info->type);
  425. client = i2c_new_client_device(adapter, info);
  426. if (!i2c_client_has_driver(client))
  427. goto err_add_i2c_client;
  428. if (!try_module_get(client->dev.driver->owner)) {
  429. i2c_unregister_device(client);
  430. goto err_add_i2c_client;
  431. }
  432. return client;
  433. err_add_i2c_client:
  434. client = NULL;
  435. return client;
  436. }
  437. static void smi_del_i2c_client(struct i2c_client *client)
  438. {
  439. module_put(client->dev.driver->owner);
  440. i2c_unregister_device(client);
  441. }
  442. static const struct m88ds3103_config smi_dvbsky_m88ds3103_cfg = {
  443. .i2c_addr = 0x68,
  444. .clock = 27000000,
  445. .i2c_wr_max = 33,
  446. .clock_out = 0,
  447. .ts_mode = M88DS3103_TS_PARALLEL,
  448. .ts_clk = 16000,
  449. .ts_clk_pol = 1,
  450. .agc = 0x99,
  451. .lnb_hv_pol = 0,
  452. .lnb_en_pol = 1,
  453. };
  454. static int smi_dvbsky_m88ds3103_fe_attach(struct smi_port *port)
  455. {
  456. int ret = 0;
  457. struct smi_dev *dev = port->dev;
  458. struct i2c_adapter *i2c;
  459. /* tuner I2C module */
  460. struct i2c_adapter *tuner_i2c_adapter;
  461. struct i2c_client *tuner_client;
  462. struct i2c_board_info tuner_info;
  463. struct ts2020_config ts2020_config = {};
  464. memset(&tuner_info, 0, sizeof(struct i2c_board_info));
  465. i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
  466. /* attach demod */
  467. port->fe = dvb_attach(m88ds3103_attach,
  468. &smi_dvbsky_m88ds3103_cfg, i2c, &tuner_i2c_adapter);
  469. if (!port->fe) {
  470. ret = -ENODEV;
  471. return ret;
  472. }
  473. /* attach tuner */
  474. ts2020_config.fe = port->fe;
  475. strscpy(tuner_info.type, "ts2020", I2C_NAME_SIZE);
  476. tuner_info.addr = 0x60;
  477. tuner_info.platform_data = &ts2020_config;
  478. tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
  479. if (!tuner_client) {
  480. ret = -ENODEV;
  481. goto err_tuner_i2c_device;
  482. }
  483. /* delegate signal strength measurement to tuner */
  484. port->fe->ops.read_signal_strength =
  485. port->fe->ops.tuner_ops.get_rf_strength;
  486. port->i2c_client_tuner = tuner_client;
  487. return ret;
  488. err_tuner_i2c_device:
  489. dvb_frontend_detach(port->fe);
  490. return ret;
  491. }
  492. static const struct m88ds3103_config smi_dvbsky_m88rs6000_cfg = {
  493. .i2c_addr = 0x69,
  494. .clock = 27000000,
  495. .i2c_wr_max = 33,
  496. .ts_mode = M88DS3103_TS_PARALLEL,
  497. .ts_clk = 16000,
  498. .ts_clk_pol = 1,
  499. .agc = 0x99,
  500. .lnb_hv_pol = 0,
  501. .lnb_en_pol = 1,
  502. };
  503. static int smi_dvbsky_m88rs6000_fe_attach(struct smi_port *port)
  504. {
  505. int ret = 0;
  506. struct smi_dev *dev = port->dev;
  507. struct i2c_adapter *i2c;
  508. /* tuner I2C module */
  509. struct i2c_adapter *tuner_i2c_adapter;
  510. struct i2c_client *tuner_client;
  511. struct i2c_board_info tuner_info;
  512. struct m88rs6000t_config m88rs6000t_config;
  513. memset(&tuner_info, 0, sizeof(struct i2c_board_info));
  514. i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
  515. /* attach demod */
  516. port->fe = dvb_attach(m88ds3103_attach,
  517. &smi_dvbsky_m88rs6000_cfg, i2c, &tuner_i2c_adapter);
  518. if (!port->fe) {
  519. ret = -ENODEV;
  520. return ret;
  521. }
  522. /* attach tuner */
  523. m88rs6000t_config.fe = port->fe;
  524. strscpy(tuner_info.type, "m88rs6000t", I2C_NAME_SIZE);
  525. tuner_info.addr = 0x21;
  526. tuner_info.platform_data = &m88rs6000t_config;
  527. tuner_client = smi_add_i2c_client(tuner_i2c_adapter, &tuner_info);
  528. if (!tuner_client) {
  529. ret = -ENODEV;
  530. goto err_tuner_i2c_device;
  531. }
  532. /* delegate signal strength measurement to tuner */
  533. port->fe->ops.read_signal_strength =
  534. port->fe->ops.tuner_ops.get_rf_strength;
  535. port->i2c_client_tuner = tuner_client;
  536. return ret;
  537. err_tuner_i2c_device:
  538. dvb_frontend_detach(port->fe);
  539. return ret;
  540. }
  541. static int smi_dvbsky_sit2_fe_attach(struct smi_port *port)
  542. {
  543. int ret = 0;
  544. struct smi_dev *dev = port->dev;
  545. struct i2c_adapter *i2c;
  546. struct i2c_adapter *tuner_i2c_adapter;
  547. struct i2c_client *client_tuner, *client_demod;
  548. struct i2c_board_info client_info;
  549. struct si2168_config si2168_config;
  550. struct si2157_config si2157_config;
  551. /* select i2c bus */
  552. i2c = (port->idx == 0) ? &dev->i2c_bus[0] : &dev->i2c_bus[1];
  553. /* attach demod */
  554. memset(&si2168_config, 0, sizeof(si2168_config));
  555. si2168_config.i2c_adapter = &tuner_i2c_adapter;
  556. si2168_config.fe = &port->fe;
  557. si2168_config.ts_mode = SI2168_TS_PARALLEL;
  558. memset(&client_info, 0, sizeof(struct i2c_board_info));
  559. strscpy(client_info.type, "si2168", I2C_NAME_SIZE);
  560. client_info.addr = 0x64;
  561. client_info.platform_data = &si2168_config;
  562. client_demod = smi_add_i2c_client(i2c, &client_info);
  563. if (!client_demod) {
  564. ret = -ENODEV;
  565. return ret;
  566. }
  567. port->i2c_client_demod = client_demod;
  568. /* attach tuner */
  569. memset(&si2157_config, 0, sizeof(si2157_config));
  570. si2157_config.fe = port->fe;
  571. si2157_config.if_port = 1;
  572. memset(&client_info, 0, sizeof(struct i2c_board_info));
  573. strscpy(client_info.type, "si2157", I2C_NAME_SIZE);
  574. client_info.addr = 0x60;
  575. client_info.platform_data = &si2157_config;
  576. client_tuner = smi_add_i2c_client(tuner_i2c_adapter, &client_info);
  577. if (!client_tuner) {
  578. smi_del_i2c_client(port->i2c_client_demod);
  579. port->i2c_client_demod = NULL;
  580. ret = -ENODEV;
  581. return ret;
  582. }
  583. port->i2c_client_tuner = client_tuner;
  584. return ret;
  585. }
  586. static int smi_fe_init(struct smi_port *port)
  587. {
  588. int ret = 0;
  589. struct smi_dev *dev = port->dev;
  590. struct dvb_adapter *adap = &port->dvb_adapter;
  591. u8 mac_ee[16];
  592. dev_dbg(&port->dev->pci_dev->dev,
  593. "%s: port %d, fe_type = %d\n",
  594. __func__, port->idx, port->fe_type);
  595. switch (port->fe_type) {
  596. case DVBSKY_FE_M88DS3103:
  597. ret = smi_dvbsky_m88ds3103_fe_attach(port);
  598. break;
  599. case DVBSKY_FE_M88RS6000:
  600. ret = smi_dvbsky_m88rs6000_fe_attach(port);
  601. break;
  602. case DVBSKY_FE_SIT2:
  603. ret = smi_dvbsky_sit2_fe_attach(port);
  604. break;
  605. }
  606. if (ret < 0)
  607. return ret;
  608. /* register dvb frontend */
  609. ret = dvb_register_frontend(adap, port->fe);
  610. if (ret < 0) {
  611. if (port->i2c_client_tuner)
  612. smi_del_i2c_client(port->i2c_client_tuner);
  613. if (port->i2c_client_demod)
  614. smi_del_i2c_client(port->i2c_client_demod);
  615. dvb_frontend_detach(port->fe);
  616. return ret;
  617. }
  618. /* init MAC.*/
  619. ret = smi_read_eeprom(&dev->i2c_bus[0], 0xc0, mac_ee, 16);
  620. dev_info(&port->dev->pci_dev->dev,
  621. "%s port %d MAC: %pM\n", dev->info->name,
  622. port->idx, mac_ee + (port->idx)*8);
  623. memcpy(adap->proposed_mac, mac_ee + (port->idx)*8, 6);
  624. return ret;
  625. }
  626. static void smi_fe_exit(struct smi_port *port)
  627. {
  628. dvb_unregister_frontend(port->fe);
  629. /* remove I2C demod and tuner */
  630. if (port->i2c_client_tuner)
  631. smi_del_i2c_client(port->i2c_client_tuner);
  632. if (port->i2c_client_demod)
  633. smi_del_i2c_client(port->i2c_client_demod);
  634. dvb_frontend_detach(port->fe);
  635. }
  636. static int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,
  637. int (*start_feed)(struct dvb_demux_feed *),
  638. int (*stop_feed)(struct dvb_demux_feed *),
  639. void *priv)
  640. {
  641. dvbdemux->priv = priv;
  642. dvbdemux->filternum = 256;
  643. dvbdemux->feednum = 256;
  644. dvbdemux->start_feed = start_feed;
  645. dvbdemux->stop_feed = stop_feed;
  646. dvbdemux->write_to_decoder = NULL;
  647. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  648. DMX_SECTION_FILTERING |
  649. DMX_MEMORY_BASED_FILTERING);
  650. return dvb_dmx_init(dvbdemux);
  651. }
  652. static int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,
  653. struct dvb_demux *dvbdemux,
  654. struct dmx_frontend *hw_frontend,
  655. struct dmx_frontend *mem_frontend,
  656. struct dvb_adapter *dvb_adapter)
  657. {
  658. int ret;
  659. dmxdev->filternum = 256;
  660. dmxdev->demux = &dvbdemux->dmx;
  661. dmxdev->capabilities = 0;
  662. ret = dvb_dmxdev_init(dmxdev, dvb_adapter);
  663. if (ret < 0)
  664. return ret;
  665. hw_frontend->source = DMX_FRONTEND_0;
  666. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, hw_frontend);
  667. mem_frontend->source = DMX_MEMORY_FE;
  668. dvbdemux->dmx.add_frontend(&dvbdemux->dmx, mem_frontend);
  669. return dvbdemux->dmx.connect_frontend(&dvbdemux->dmx, hw_frontend);
  670. }
  671. static u32 smi_config_DMA(struct smi_port *port)
  672. {
  673. struct smi_dev *dev = port->dev;
  674. u32 totalLength = 0, dmaMemPtrLow, dmaMemPtrHi, dmaCtlReg;
  675. u8 chanLatencyTimer = 0, dmaChanEnable = 1, dmaTransStart = 1;
  676. u32 dmaManagement = 0, tlpTransUnit = DMA_TRANS_UNIT_188;
  677. u8 tlpTc = 0, tlpTd = 1, tlpEp = 0, tlpAttr = 0;
  678. u64 mem;
  679. dmaManagement = smi_read(port->DMA_MANAGEMENT);
  680. /* Setup Channel-0 */
  681. if (port->_dmaInterruptCH0) {
  682. totalLength = SMI_TS_DMA_BUF_SIZE;
  683. mem = port->dma_addr[0];
  684. dmaMemPtrLow = mem & 0xffffffff;
  685. dmaMemPtrHi = mem >> 32;
  686. dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
  687. | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
  688. dmaManagement |= dmaChanEnable | (dmaTransStart << 1)
  689. | (chanLatencyTimer << 8);
  690. /* write DMA register, start DMA engine */
  691. smi_write(port->DMA_CHAN0_ADDR_LOW, dmaMemPtrLow);
  692. smi_write(port->DMA_CHAN0_ADDR_HI, dmaMemPtrHi);
  693. smi_write(port->DMA_CHAN0_CONTROL, dmaCtlReg);
  694. }
  695. /* Setup Channel-1 */
  696. if (port->_dmaInterruptCH1) {
  697. totalLength = SMI_TS_DMA_BUF_SIZE;
  698. mem = port->dma_addr[1];
  699. dmaMemPtrLow = mem & 0xffffffff;
  700. dmaMemPtrHi = mem >> 32;
  701. dmaCtlReg = (totalLength) | (tlpTransUnit << 22) | (tlpTc << 25)
  702. | (tlpTd << 28) | (tlpEp << 29) | (tlpAttr << 30);
  703. dmaManagement |= (dmaChanEnable << 16) | (dmaTransStart << 17)
  704. | (chanLatencyTimer << 24);
  705. /* write DMA register, start DMA engine */
  706. smi_write(port->DMA_CHAN1_ADDR_LOW, dmaMemPtrLow);
  707. smi_write(port->DMA_CHAN1_ADDR_HI, dmaMemPtrHi);
  708. smi_write(port->DMA_CHAN1_CONTROL, dmaCtlReg);
  709. }
  710. return dmaManagement;
  711. }
  712. static int smi_start_feed(struct dvb_demux_feed *dvbdmxfeed)
  713. {
  714. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  715. struct smi_port *port = dvbdmx->priv;
  716. struct smi_dev *dev = port->dev;
  717. u32 dmaManagement;
  718. if (port->users++ == 0) {
  719. dmaManagement = smi_config_DMA(port);
  720. smi_port_clearInterrupt(port);
  721. smi_port_enableInterrupt(port);
  722. smi_write(port->DMA_MANAGEMENT, dmaManagement);
  723. tasklet_enable(&port->tasklet);
  724. }
  725. return port->users;
  726. }
  727. static int smi_stop_feed(struct dvb_demux_feed *dvbdmxfeed)
  728. {
  729. struct dvb_demux *dvbdmx = dvbdmxfeed->demux;
  730. struct smi_port *port = dvbdmx->priv;
  731. struct smi_dev *dev = port->dev;
  732. if (--port->users)
  733. return port->users;
  734. tasklet_disable(&port->tasklet);
  735. smi_port_disableInterrupt(port);
  736. smi_clear(port->DMA_MANAGEMENT, 0x30003);
  737. return 0;
  738. }
  739. static int smi_dvb_init(struct smi_port *port)
  740. {
  741. int ret;
  742. struct dvb_adapter *adap = &port->dvb_adapter;
  743. struct dvb_demux *dvbdemux = &port->demux;
  744. dev_dbg(&port->dev->pci_dev->dev,
  745. "%s, port %d\n", __func__, port->idx);
  746. ret = dvb_register_adapter(adap, "SMI_DVB", THIS_MODULE,
  747. &port->dev->pci_dev->dev,
  748. adapter_nr);
  749. if (ret < 0) {
  750. dev_err(&port->dev->pci_dev->dev, "Fail to register DVB adapter.\n");
  751. return ret;
  752. }
  753. ret = my_dvb_dmx_ts_card_init(dvbdemux, "SW demux",
  754. smi_start_feed,
  755. smi_stop_feed, port);
  756. if (ret < 0)
  757. goto err_del_dvb_register_adapter;
  758. ret = my_dvb_dmxdev_ts_card_init(&port->dmxdev, &port->demux,
  759. &port->hw_frontend,
  760. &port->mem_frontend, adap);
  761. if (ret < 0)
  762. goto err_del_dvb_dmx;
  763. ret = dvb_net_init(adap, &port->dvbnet, port->dmxdev.demux);
  764. if (ret < 0)
  765. goto err_del_dvb_dmxdev;
  766. return 0;
  767. err_del_dvb_dmxdev:
  768. dvbdemux->dmx.close(&dvbdemux->dmx);
  769. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
  770. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
  771. dvb_dmxdev_release(&port->dmxdev);
  772. err_del_dvb_dmx:
  773. dvb_dmx_release(&port->demux);
  774. err_del_dvb_register_adapter:
  775. dvb_unregister_adapter(&port->dvb_adapter);
  776. return ret;
  777. }
  778. static void smi_dvb_exit(struct smi_port *port)
  779. {
  780. struct dvb_demux *dvbdemux = &port->demux;
  781. dvb_net_release(&port->dvbnet);
  782. dvbdemux->dmx.close(&dvbdemux->dmx);
  783. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->hw_frontend);
  784. dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, &port->mem_frontend);
  785. dvb_dmxdev_release(&port->dmxdev);
  786. dvb_dmx_release(&port->demux);
  787. dvb_unregister_adapter(&port->dvb_adapter);
  788. }
  789. static int smi_port_attach(struct smi_dev *dev,
  790. struct smi_port *port, int index)
  791. {
  792. int ret, dmachs;
  793. port->dev = dev;
  794. port->idx = index;
  795. port->fe_type = (index == 0) ? dev->info->fe_0 : dev->info->fe_1;
  796. dmachs = (index == 0) ? dev->info->ts_0 : dev->info->ts_1;
  797. /* port init.*/
  798. ret = smi_port_init(port, dmachs);
  799. if (ret < 0)
  800. return ret;
  801. /* dvb init.*/
  802. ret = smi_dvb_init(port);
  803. if (ret < 0)
  804. goto err_del_port_init;
  805. /* fe init.*/
  806. ret = smi_fe_init(port);
  807. if (ret < 0)
  808. goto err_del_dvb_init;
  809. return 0;
  810. err_del_dvb_init:
  811. smi_dvb_exit(port);
  812. err_del_port_init:
  813. smi_port_exit(port);
  814. return ret;
  815. }
  816. static void smi_port_detach(struct smi_port *port)
  817. {
  818. smi_fe_exit(port);
  819. smi_dvb_exit(port);
  820. smi_port_exit(port);
  821. }
  822. static int smi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  823. {
  824. struct smi_dev *dev;
  825. int ret = -ENOMEM;
  826. if (pci_enable_device(pdev) < 0)
  827. return -ENODEV;
  828. dev = kzalloc(sizeof(struct smi_dev), GFP_KERNEL);
  829. if (!dev) {
  830. ret = -ENOMEM;
  831. goto err_pci_disable_device;
  832. }
  833. dev->pci_dev = pdev;
  834. pci_set_drvdata(pdev, dev);
  835. dev->info = (struct smi_cfg_info *) id->driver_data;
  836. dev_info(&dev->pci_dev->dev,
  837. "card detected: %s\n", dev->info->name);
  838. dev->nr = dev->info->type;
  839. dev->lmmio = ioremap(pci_resource_start(dev->pci_dev, 0),
  840. pci_resource_len(dev->pci_dev, 0));
  841. if (!dev->lmmio) {
  842. ret = -ENOMEM;
  843. goto err_kfree;
  844. }
  845. /* should we set to 32bit DMA? */
  846. ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  847. if (ret < 0)
  848. goto err_pci_iounmap;
  849. pci_set_master(pdev);
  850. ret = smi_hw_init(dev);
  851. if (ret < 0)
  852. goto err_pci_iounmap;
  853. ret = smi_i2c_init(dev);
  854. if (ret < 0)
  855. goto err_pci_iounmap;
  856. if (dev->info->ts_0) {
  857. ret = smi_port_attach(dev, &dev->ts_port[0], 0);
  858. if (ret < 0)
  859. goto err_del_i2c_adaptor;
  860. }
  861. if (dev->info->ts_1) {
  862. ret = smi_port_attach(dev, &dev->ts_port[1], 1);
  863. if (ret < 0)
  864. goto err_del_port0_attach;
  865. }
  866. ret = smi_ir_init(dev);
  867. if (ret < 0)
  868. goto err_del_port1_attach;
  869. #ifdef CONFIG_PCI_MSI /* to do msi interrupt.???*/
  870. if (pci_msi_enabled())
  871. ret = pci_enable_msi(dev->pci_dev);
  872. if (ret)
  873. dev_info(&dev->pci_dev->dev, "MSI not available.\n");
  874. #endif
  875. ret = request_irq(dev->pci_dev->irq, smi_irq_handler,
  876. IRQF_SHARED, "SMI_PCIE", dev);
  877. if (ret < 0)
  878. goto err_del_ir;
  879. smi_ir_start(&dev->ir);
  880. return 0;
  881. err_del_ir:
  882. smi_ir_exit(dev);
  883. err_del_port1_attach:
  884. if (dev->info->ts_1)
  885. smi_port_detach(&dev->ts_port[1]);
  886. err_del_port0_attach:
  887. if (dev->info->ts_0)
  888. smi_port_detach(&dev->ts_port[0]);
  889. err_del_i2c_adaptor:
  890. smi_i2c_exit(dev);
  891. err_pci_iounmap:
  892. iounmap(dev->lmmio);
  893. err_kfree:
  894. pci_set_drvdata(pdev, NULL);
  895. kfree(dev);
  896. err_pci_disable_device:
  897. pci_disable_device(pdev);
  898. return ret;
  899. }
  900. static void smi_remove(struct pci_dev *pdev)
  901. {
  902. struct smi_dev *dev = pci_get_drvdata(pdev);
  903. smi_write(MSI_INT_ENA_CLR, ALL_INT);
  904. free_irq(dev->pci_dev->irq, dev);
  905. #ifdef CONFIG_PCI_MSI
  906. pci_disable_msi(dev->pci_dev);
  907. #endif
  908. if (dev->info->ts_1)
  909. smi_port_detach(&dev->ts_port[1]);
  910. if (dev->info->ts_0)
  911. smi_port_detach(&dev->ts_port[0]);
  912. smi_ir_exit(dev);
  913. smi_i2c_exit(dev);
  914. iounmap(dev->lmmio);
  915. pci_set_drvdata(pdev, NULL);
  916. pci_disable_device(pdev);
  917. kfree(dev);
  918. }
  919. /* DVBSky cards */
  920. static const struct smi_cfg_info dvbsky_s950_cfg = {
  921. .type = SMI_DVBSKY_S950,
  922. .name = "DVBSky S950 V3",
  923. .ts_0 = SMI_TS_NULL,
  924. .ts_1 = SMI_TS_DMA_BOTH,
  925. .fe_0 = DVBSKY_FE_NULL,
  926. .fe_1 = DVBSKY_FE_M88DS3103,
  927. .rc_map = RC_MAP_DVBSKY,
  928. };
  929. static const struct smi_cfg_info dvbsky_s952_cfg = {
  930. .type = SMI_DVBSKY_S952,
  931. .name = "DVBSky S952 V3",
  932. .ts_0 = SMI_TS_DMA_BOTH,
  933. .ts_1 = SMI_TS_DMA_BOTH,
  934. .fe_0 = DVBSKY_FE_M88RS6000,
  935. .fe_1 = DVBSKY_FE_M88RS6000,
  936. .rc_map = RC_MAP_DVBSKY,
  937. };
  938. static const struct smi_cfg_info dvbsky_t9580_cfg = {
  939. .type = SMI_DVBSKY_T9580,
  940. .name = "DVBSky T9580 V3",
  941. .ts_0 = SMI_TS_DMA_BOTH,
  942. .ts_1 = SMI_TS_DMA_BOTH,
  943. .fe_0 = DVBSKY_FE_SIT2,
  944. .fe_1 = DVBSKY_FE_M88DS3103,
  945. .rc_map = RC_MAP_DVBSKY,
  946. };
  947. static const struct smi_cfg_info technotrend_s2_4200_cfg = {
  948. .type = SMI_TECHNOTREND_S2_4200,
  949. .name = "TechnoTrend TT-budget S2-4200 Twin",
  950. .ts_0 = SMI_TS_DMA_BOTH,
  951. .ts_1 = SMI_TS_DMA_BOTH,
  952. .fe_0 = DVBSKY_FE_M88RS6000,
  953. .fe_1 = DVBSKY_FE_M88RS6000,
  954. .rc_map = RC_MAP_TT_1500,
  955. };
  956. /* PCI IDs */
  957. #define SMI_ID(_subvend, _subdev, _driverdata) { \
  958. .vendor = SMI_VID, .device = SMI_PID, \
  959. .subvendor = _subvend, .subdevice = _subdev, \
  960. .driver_data = (unsigned long)&_driverdata }
  961. static const struct pci_device_id smi_id_table[] = {
  962. SMI_ID(0x4254, 0x0550, dvbsky_s950_cfg),
  963. SMI_ID(0x4254, 0x0552, dvbsky_s952_cfg),
  964. SMI_ID(0x4254, 0x5580, dvbsky_t9580_cfg),
  965. SMI_ID(0x13c2, 0x3016, technotrend_s2_4200_cfg),
  966. {0}
  967. };
  968. MODULE_DEVICE_TABLE(pci, smi_id_table);
  969. static struct pci_driver smipcie_driver = {
  970. .name = "SMI PCIe driver",
  971. .id_table = smi_id_table,
  972. .probe = smi_probe,
  973. .remove = smi_remove,
  974. };
  975. module_pci_driver(smipcie_driver);
  976. MODULE_AUTHOR("Max nibble <[email protected]>");
  977. MODULE_DESCRIPTION("SMI PCIe driver");
  978. MODULE_LICENSE("GPL");