pt1.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * driver for Earthsoft PT1/PT2
  4. *
  5. * Copyright (C) 2009 HIRANO Takahito <[email protected]>
  6. *
  7. * based on pt1dvr - http://pt1dvr.sourceforge.jp/
  8. * by Tomoaki Ishikawa <[email protected]>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/sched.h>
  12. #include <linux/sched/signal.h>
  13. #include <linux/hrtimer.h>
  14. #include <linux/delay.h>
  15. #include <linux/module.h>
  16. #include <linux/slab.h>
  17. #include <linux/vmalloc.h>
  18. #include <linux/pci.h>
  19. #include <linux/kthread.h>
  20. #include <linux/freezer.h>
  21. #include <linux/ratelimit.h>
  22. #include <linux/string.h>
  23. #include <linux/i2c.h>
  24. #include <media/dvbdev.h>
  25. #include <media/dvb_demux.h>
  26. #include <media/dmxdev.h>
  27. #include <media/dvb_net.h>
  28. #include <media/dvb_frontend.h>
  29. #include "tc90522.h"
  30. #include "qm1d1b0004.h"
  31. #include "dvb-pll.h"
  32. #define DRIVER_NAME "earth-pt1"
  33. #define PT1_PAGE_SHIFT 12
  34. #define PT1_PAGE_SIZE (1 << PT1_PAGE_SHIFT)
  35. #define PT1_NR_UPACKETS 1024
  36. #define PT1_NR_BUFS 511
  37. struct pt1_buffer_page {
  38. __le32 upackets[PT1_NR_UPACKETS];
  39. };
  40. struct pt1_table_page {
  41. __le32 next_pfn;
  42. __le32 buf_pfns[PT1_NR_BUFS];
  43. };
  44. struct pt1_buffer {
  45. struct pt1_buffer_page *page;
  46. dma_addr_t addr;
  47. };
  48. struct pt1_table {
  49. struct pt1_table_page *page;
  50. dma_addr_t addr;
  51. struct pt1_buffer bufs[PT1_NR_BUFS];
  52. };
  53. enum pt1_fe_clk {
  54. PT1_FE_CLK_20MHZ, /* PT1 */
  55. PT1_FE_CLK_25MHZ, /* PT2 */
  56. };
  57. #define PT1_NR_ADAPS 4
  58. struct pt1_adapter;
  59. struct pt1 {
  60. struct pci_dev *pdev;
  61. void __iomem *regs;
  62. struct i2c_adapter i2c_adap;
  63. int i2c_running;
  64. struct pt1_adapter *adaps[PT1_NR_ADAPS];
  65. struct pt1_table *tables;
  66. struct task_struct *kthread;
  67. int table_index;
  68. int buf_index;
  69. struct mutex lock;
  70. int power;
  71. int reset;
  72. enum pt1_fe_clk fe_clk;
  73. };
  74. struct pt1_adapter {
  75. struct pt1 *pt1;
  76. int index;
  77. u8 *buf;
  78. int upacket_count;
  79. int packet_count;
  80. int st_count;
  81. struct dvb_adapter adap;
  82. struct dvb_demux demux;
  83. int users;
  84. struct dmxdev dmxdev;
  85. struct dvb_frontend *fe;
  86. struct i2c_client *demod_i2c_client;
  87. struct i2c_client *tuner_i2c_client;
  88. int (*orig_set_voltage)(struct dvb_frontend *fe,
  89. enum fe_sec_voltage voltage);
  90. int (*orig_sleep)(struct dvb_frontend *fe);
  91. int (*orig_init)(struct dvb_frontend *fe);
  92. enum fe_sec_voltage voltage;
  93. int sleep;
  94. };
  95. union pt1_tuner_config {
  96. struct qm1d1b0004_config qm1d1b0004;
  97. struct dvb_pll_config tda6651;
  98. };
  99. struct pt1_config {
  100. struct i2c_board_info demod_info;
  101. struct tc90522_config demod_cfg;
  102. struct i2c_board_info tuner_info;
  103. union pt1_tuner_config tuner_cfg;
  104. };
  105. static const struct pt1_config pt1_configs[PT1_NR_ADAPS] = {
  106. {
  107. .demod_info = {
  108. I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x1b),
  109. },
  110. .tuner_info = {
  111. I2C_BOARD_INFO("qm1d1b0004", 0x60),
  112. },
  113. },
  114. {
  115. .demod_info = {
  116. I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x1a),
  117. },
  118. .tuner_info = {
  119. I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
  120. },
  121. },
  122. {
  123. .demod_info = {
  124. I2C_BOARD_INFO(TC90522_I2C_DEV_SAT, 0x19),
  125. },
  126. .tuner_info = {
  127. I2C_BOARD_INFO("qm1d1b0004", 0x60),
  128. },
  129. },
  130. {
  131. .demod_info = {
  132. I2C_BOARD_INFO(TC90522_I2C_DEV_TER, 0x18),
  133. },
  134. .tuner_info = {
  135. I2C_BOARD_INFO("tda665x_earthpt1", 0x61),
  136. },
  137. },
  138. };
  139. static const u8 va1j5jf8007s_20mhz_configs[][2] = {
  140. {0x04, 0x02}, {0x0d, 0x55}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01},
  141. {0x1c, 0x0a}, {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0},
  142. {0x52, 0x89}, {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69},
  143. {0x87, 0x04}, {0x8e, 0x02}, {0xa3, 0xf7}, {0xa5, 0xc0},
  144. };
  145. static const u8 va1j5jf8007s_25mhz_configs[][2] = {
  146. {0x04, 0x02}, {0x11, 0x40}, {0x13, 0x80}, {0x17, 0x01}, {0x1c, 0x0a},
  147. {0x1d, 0xaa}, {0x1e, 0x20}, {0x1f, 0x88}, {0x51, 0xb0}, {0x52, 0x89},
  148. {0x53, 0xb3}, {0x5a, 0x2d}, {0x5b, 0xd3}, {0x85, 0x69}, {0x87, 0x04},
  149. {0x8e, 0x26}, {0xa3, 0xf7}, {0xa5, 0xc0},
  150. };
  151. static const u8 va1j5jf8007t_20mhz_configs[][2] = {
  152. {0x03, 0x90}, {0x14, 0x8f}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2},
  153. {0x22, 0x83}, {0x31, 0x0d}, {0x32, 0xe0}, {0x39, 0xd3}, {0x3a, 0x00},
  154. {0x3b, 0x11}, {0x3c, 0x3f},
  155. {0x5c, 0x40}, {0x5f, 0x80}, {0x75, 0x02}, {0x76, 0x4e}, {0x77, 0x03},
  156. {0xef, 0x01}
  157. };
  158. static const u8 va1j5jf8007t_25mhz_configs[][2] = {
  159. {0x03, 0x90}, {0x1c, 0x2a}, {0x1d, 0xa8}, {0x1e, 0xa2}, {0x22, 0x83},
  160. {0x3a, 0x04}, {0x3b, 0x11}, {0x3c, 0x3f}, {0x5c, 0x40}, {0x5f, 0x80},
  161. {0x75, 0x0a}, {0x76, 0x4c}, {0x77, 0x03}, {0xef, 0x01}
  162. };
  163. static int config_demod(struct i2c_client *cl, enum pt1_fe_clk clk)
  164. {
  165. int ret;
  166. bool is_sat;
  167. const u8 (*cfg_data)[2];
  168. int i, len;
  169. is_sat = !strncmp(cl->name, TC90522_I2C_DEV_SAT,
  170. strlen(TC90522_I2C_DEV_SAT));
  171. if (is_sat) {
  172. struct i2c_msg msg[2];
  173. u8 wbuf, rbuf;
  174. wbuf = 0x07;
  175. msg[0].addr = cl->addr;
  176. msg[0].flags = 0;
  177. msg[0].len = 1;
  178. msg[0].buf = &wbuf;
  179. msg[1].addr = cl->addr;
  180. msg[1].flags = I2C_M_RD;
  181. msg[1].len = 1;
  182. msg[1].buf = &rbuf;
  183. ret = i2c_transfer(cl->adapter, msg, 2);
  184. if (ret < 0)
  185. return ret;
  186. if (rbuf != 0x41)
  187. return -EIO;
  188. }
  189. /* frontend init */
  190. if (clk == PT1_FE_CLK_20MHZ) {
  191. if (is_sat) {
  192. cfg_data = va1j5jf8007s_20mhz_configs;
  193. len = ARRAY_SIZE(va1j5jf8007s_20mhz_configs);
  194. } else {
  195. cfg_data = va1j5jf8007t_20mhz_configs;
  196. len = ARRAY_SIZE(va1j5jf8007t_20mhz_configs);
  197. }
  198. } else {
  199. if (is_sat) {
  200. cfg_data = va1j5jf8007s_25mhz_configs;
  201. len = ARRAY_SIZE(va1j5jf8007s_25mhz_configs);
  202. } else {
  203. cfg_data = va1j5jf8007t_25mhz_configs;
  204. len = ARRAY_SIZE(va1j5jf8007t_25mhz_configs);
  205. }
  206. }
  207. for (i = 0; i < len; i++) {
  208. ret = i2c_master_send(cl, cfg_data[i], 2);
  209. if (ret < 0)
  210. return ret;
  211. }
  212. return 0;
  213. }
  214. /*
  215. * Init registers for (each pair of) terrestrial/satellite block in demod.
  216. * Note that resetting terr. block also resets its peer sat. block as well.
  217. * This function must be called before configuring any demod block
  218. * (before pt1_wakeup(), fe->ops.init()).
  219. */
  220. static int pt1_demod_block_init(struct pt1 *pt1)
  221. {
  222. struct i2c_client *cl;
  223. u8 buf[2] = {0x01, 0x80};
  224. int ret;
  225. int i;
  226. /* reset all terr. & sat. pairs first */
  227. for (i = 0; i < PT1_NR_ADAPS; i++) {
  228. cl = pt1->adaps[i]->demod_i2c_client;
  229. if (strncmp(cl->name, TC90522_I2C_DEV_TER,
  230. strlen(TC90522_I2C_DEV_TER)))
  231. continue;
  232. ret = i2c_master_send(cl, buf, 2);
  233. if (ret < 0)
  234. return ret;
  235. usleep_range(30000, 50000);
  236. }
  237. for (i = 0; i < PT1_NR_ADAPS; i++) {
  238. cl = pt1->adaps[i]->demod_i2c_client;
  239. if (strncmp(cl->name, TC90522_I2C_DEV_SAT,
  240. strlen(TC90522_I2C_DEV_SAT)))
  241. continue;
  242. ret = i2c_master_send(cl, buf, 2);
  243. if (ret < 0)
  244. return ret;
  245. usleep_range(30000, 50000);
  246. }
  247. return 0;
  248. }
  249. static void pt1_write_reg(struct pt1 *pt1, int reg, u32 data)
  250. {
  251. writel(data, pt1->regs + reg * 4);
  252. }
  253. static u32 pt1_read_reg(struct pt1 *pt1, int reg)
  254. {
  255. return readl(pt1->regs + reg * 4);
  256. }
  257. static unsigned int pt1_nr_tables = 8;
  258. module_param_named(nr_tables, pt1_nr_tables, uint, 0);
  259. static void pt1_increment_table_count(struct pt1 *pt1)
  260. {
  261. pt1_write_reg(pt1, 0, 0x00000020);
  262. }
  263. static void pt1_init_table_count(struct pt1 *pt1)
  264. {
  265. pt1_write_reg(pt1, 0, 0x00000010);
  266. }
  267. static void pt1_register_tables(struct pt1 *pt1, u32 first_pfn)
  268. {
  269. pt1_write_reg(pt1, 5, first_pfn);
  270. pt1_write_reg(pt1, 0, 0x0c000040);
  271. }
  272. static void pt1_unregister_tables(struct pt1 *pt1)
  273. {
  274. pt1_write_reg(pt1, 0, 0x08080000);
  275. }
  276. static int pt1_sync(struct pt1 *pt1)
  277. {
  278. int i;
  279. for (i = 0; i < 57; i++) {
  280. if (pt1_read_reg(pt1, 0) & 0x20000000)
  281. return 0;
  282. pt1_write_reg(pt1, 0, 0x00000008);
  283. }
  284. dev_err(&pt1->pdev->dev, "could not sync\n");
  285. return -EIO;
  286. }
  287. static u64 pt1_identify(struct pt1 *pt1)
  288. {
  289. int i;
  290. u64 id = 0;
  291. for (i = 0; i < 57; i++) {
  292. id |= (u64)(pt1_read_reg(pt1, 0) >> 30 & 1) << i;
  293. pt1_write_reg(pt1, 0, 0x00000008);
  294. }
  295. return id;
  296. }
  297. static int pt1_unlock(struct pt1 *pt1)
  298. {
  299. int i;
  300. pt1_write_reg(pt1, 0, 0x00000008);
  301. for (i = 0; i < 3; i++) {
  302. if (pt1_read_reg(pt1, 0) & 0x80000000)
  303. return 0;
  304. usleep_range(1000, 2000);
  305. }
  306. dev_err(&pt1->pdev->dev, "could not unlock\n");
  307. return -EIO;
  308. }
  309. static int pt1_reset_pci(struct pt1 *pt1)
  310. {
  311. int i;
  312. pt1_write_reg(pt1, 0, 0x01010000);
  313. pt1_write_reg(pt1, 0, 0x01000000);
  314. for (i = 0; i < 10; i++) {
  315. if (pt1_read_reg(pt1, 0) & 0x00000001)
  316. return 0;
  317. usleep_range(1000, 2000);
  318. }
  319. dev_err(&pt1->pdev->dev, "could not reset PCI\n");
  320. return -EIO;
  321. }
  322. static int pt1_reset_ram(struct pt1 *pt1)
  323. {
  324. int i;
  325. pt1_write_reg(pt1, 0, 0x02020000);
  326. pt1_write_reg(pt1, 0, 0x02000000);
  327. for (i = 0; i < 10; i++) {
  328. if (pt1_read_reg(pt1, 0) & 0x00000002)
  329. return 0;
  330. usleep_range(1000, 2000);
  331. }
  332. dev_err(&pt1->pdev->dev, "could not reset RAM\n");
  333. return -EIO;
  334. }
  335. static int pt1_do_enable_ram(struct pt1 *pt1)
  336. {
  337. int i, j;
  338. u32 status;
  339. status = pt1_read_reg(pt1, 0) & 0x00000004;
  340. pt1_write_reg(pt1, 0, 0x00000002);
  341. for (i = 0; i < 10; i++) {
  342. for (j = 0; j < 1024; j++) {
  343. if ((pt1_read_reg(pt1, 0) & 0x00000004) != status)
  344. return 0;
  345. }
  346. usleep_range(1000, 2000);
  347. }
  348. dev_err(&pt1->pdev->dev, "could not enable RAM\n");
  349. return -EIO;
  350. }
  351. static int pt1_enable_ram(struct pt1 *pt1)
  352. {
  353. int i, ret;
  354. int phase;
  355. usleep_range(1000, 2000);
  356. phase = pt1->pdev->device == 0x211a ? 128 : 166;
  357. for (i = 0; i < phase; i++) {
  358. ret = pt1_do_enable_ram(pt1);
  359. if (ret < 0)
  360. return ret;
  361. }
  362. return 0;
  363. }
  364. static void pt1_disable_ram(struct pt1 *pt1)
  365. {
  366. pt1_write_reg(pt1, 0, 0x0b0b0000);
  367. }
  368. static void pt1_set_stream(struct pt1 *pt1, int index, int enabled)
  369. {
  370. pt1_write_reg(pt1, 2, 1 << (index + 8) | enabled << index);
  371. }
  372. static void pt1_init_streams(struct pt1 *pt1)
  373. {
  374. int i;
  375. for (i = 0; i < PT1_NR_ADAPS; i++)
  376. pt1_set_stream(pt1, i, 0);
  377. }
  378. static int pt1_filter(struct pt1 *pt1, struct pt1_buffer_page *page)
  379. {
  380. u32 upacket;
  381. int i;
  382. int index;
  383. struct pt1_adapter *adap;
  384. int offset;
  385. u8 *buf;
  386. int sc;
  387. if (!page->upackets[PT1_NR_UPACKETS - 1])
  388. return 0;
  389. for (i = 0; i < PT1_NR_UPACKETS; i++) {
  390. upacket = le32_to_cpu(page->upackets[i]);
  391. index = (upacket >> 29) - 1;
  392. if (index < 0 || index >= PT1_NR_ADAPS)
  393. continue;
  394. adap = pt1->adaps[index];
  395. if (upacket >> 25 & 1)
  396. adap->upacket_count = 0;
  397. else if (!adap->upacket_count)
  398. continue;
  399. if (upacket >> 24 & 1)
  400. printk_ratelimited(KERN_INFO "earth-pt1: device buffer overflowing. table[%d] buf[%d]\n",
  401. pt1->table_index, pt1->buf_index);
  402. sc = upacket >> 26 & 0x7;
  403. if (adap->st_count != -1 && sc != ((adap->st_count + 1) & 0x7))
  404. printk_ratelimited(KERN_INFO "earth-pt1: data loss in streamID(adapter)[%d]\n",
  405. index);
  406. adap->st_count = sc;
  407. buf = adap->buf;
  408. offset = adap->packet_count * 188 + adap->upacket_count * 3;
  409. buf[offset] = upacket >> 16;
  410. buf[offset + 1] = upacket >> 8;
  411. if (adap->upacket_count != 62)
  412. buf[offset + 2] = upacket;
  413. if (++adap->upacket_count >= 63) {
  414. adap->upacket_count = 0;
  415. if (++adap->packet_count >= 21) {
  416. dvb_dmx_swfilter_packets(&adap->demux, buf, 21);
  417. adap->packet_count = 0;
  418. }
  419. }
  420. }
  421. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  422. return 1;
  423. }
  424. static int pt1_thread(void *data)
  425. {
  426. struct pt1 *pt1;
  427. struct pt1_buffer_page *page;
  428. bool was_frozen;
  429. #define PT1_FETCH_DELAY 10
  430. #define PT1_FETCH_DELAY_DELTA 2
  431. pt1 = data;
  432. set_freezable();
  433. while (!kthread_freezable_should_stop(&was_frozen)) {
  434. if (was_frozen) {
  435. int i;
  436. for (i = 0; i < PT1_NR_ADAPS; i++)
  437. pt1_set_stream(pt1, i, !!pt1->adaps[i]->users);
  438. }
  439. page = pt1->tables[pt1->table_index].bufs[pt1->buf_index].page;
  440. if (!pt1_filter(pt1, page)) {
  441. ktime_t delay;
  442. delay = ktime_set(0, PT1_FETCH_DELAY * NSEC_PER_MSEC);
  443. set_current_state(TASK_INTERRUPTIBLE);
  444. schedule_hrtimeout_range(&delay,
  445. PT1_FETCH_DELAY_DELTA * NSEC_PER_MSEC,
  446. HRTIMER_MODE_REL);
  447. continue;
  448. }
  449. if (++pt1->buf_index >= PT1_NR_BUFS) {
  450. pt1_increment_table_count(pt1);
  451. pt1->buf_index = 0;
  452. if (++pt1->table_index >= pt1_nr_tables)
  453. pt1->table_index = 0;
  454. }
  455. }
  456. return 0;
  457. }
  458. static void pt1_free_page(struct pt1 *pt1, void *page, dma_addr_t addr)
  459. {
  460. dma_free_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, page, addr);
  461. }
  462. static void *pt1_alloc_page(struct pt1 *pt1, dma_addr_t *addrp, u32 *pfnp)
  463. {
  464. void *page;
  465. dma_addr_t addr;
  466. page = dma_alloc_coherent(&pt1->pdev->dev, PT1_PAGE_SIZE, &addr,
  467. GFP_KERNEL);
  468. if (page == NULL)
  469. return NULL;
  470. BUG_ON(addr & (PT1_PAGE_SIZE - 1));
  471. BUG_ON(addr >> PT1_PAGE_SHIFT >> 31 >> 1);
  472. *addrp = addr;
  473. *pfnp = addr >> PT1_PAGE_SHIFT;
  474. return page;
  475. }
  476. static void pt1_cleanup_buffer(struct pt1 *pt1, struct pt1_buffer *buf)
  477. {
  478. pt1_free_page(pt1, buf->page, buf->addr);
  479. }
  480. static int
  481. pt1_init_buffer(struct pt1 *pt1, struct pt1_buffer *buf, u32 *pfnp)
  482. {
  483. struct pt1_buffer_page *page;
  484. dma_addr_t addr;
  485. page = pt1_alloc_page(pt1, &addr, pfnp);
  486. if (page == NULL)
  487. return -ENOMEM;
  488. page->upackets[PT1_NR_UPACKETS - 1] = 0;
  489. buf->page = page;
  490. buf->addr = addr;
  491. return 0;
  492. }
  493. static void pt1_cleanup_table(struct pt1 *pt1, struct pt1_table *table)
  494. {
  495. int i;
  496. for (i = 0; i < PT1_NR_BUFS; i++)
  497. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  498. pt1_free_page(pt1, table->page, table->addr);
  499. }
  500. static int
  501. pt1_init_table(struct pt1 *pt1, struct pt1_table *table, u32 *pfnp)
  502. {
  503. struct pt1_table_page *page;
  504. dma_addr_t addr;
  505. int i, ret;
  506. u32 buf_pfn;
  507. page = pt1_alloc_page(pt1, &addr, pfnp);
  508. if (page == NULL)
  509. return -ENOMEM;
  510. for (i = 0; i < PT1_NR_BUFS; i++) {
  511. ret = pt1_init_buffer(pt1, &table->bufs[i], &buf_pfn);
  512. if (ret < 0)
  513. goto err;
  514. page->buf_pfns[i] = cpu_to_le32(buf_pfn);
  515. }
  516. pt1_increment_table_count(pt1);
  517. table->page = page;
  518. table->addr = addr;
  519. return 0;
  520. err:
  521. while (i--)
  522. pt1_cleanup_buffer(pt1, &table->bufs[i]);
  523. pt1_free_page(pt1, page, addr);
  524. return ret;
  525. }
  526. static void pt1_cleanup_tables(struct pt1 *pt1)
  527. {
  528. struct pt1_table *tables;
  529. int i;
  530. tables = pt1->tables;
  531. pt1_unregister_tables(pt1);
  532. for (i = 0; i < pt1_nr_tables; i++)
  533. pt1_cleanup_table(pt1, &tables[i]);
  534. vfree(tables);
  535. }
  536. static int pt1_init_tables(struct pt1 *pt1)
  537. {
  538. struct pt1_table *tables;
  539. int i, ret;
  540. u32 first_pfn, pfn;
  541. if (!pt1_nr_tables)
  542. return 0;
  543. tables = vmalloc(array_size(pt1_nr_tables, sizeof(struct pt1_table)));
  544. if (tables == NULL)
  545. return -ENOMEM;
  546. pt1_init_table_count(pt1);
  547. i = 0;
  548. ret = pt1_init_table(pt1, &tables[0], &first_pfn);
  549. if (ret)
  550. goto err;
  551. i++;
  552. while (i < pt1_nr_tables) {
  553. ret = pt1_init_table(pt1, &tables[i], &pfn);
  554. if (ret)
  555. goto err;
  556. tables[i - 1].page->next_pfn = cpu_to_le32(pfn);
  557. i++;
  558. }
  559. tables[pt1_nr_tables - 1].page->next_pfn = cpu_to_le32(first_pfn);
  560. pt1_register_tables(pt1, first_pfn);
  561. pt1->tables = tables;
  562. return 0;
  563. err:
  564. while (i--)
  565. pt1_cleanup_table(pt1, &tables[i]);
  566. vfree(tables);
  567. return ret;
  568. }
  569. static int pt1_start_polling(struct pt1 *pt1)
  570. {
  571. int ret = 0;
  572. mutex_lock(&pt1->lock);
  573. if (!pt1->kthread) {
  574. pt1->kthread = kthread_run(pt1_thread, pt1, "earth-pt1");
  575. if (IS_ERR(pt1->kthread)) {
  576. ret = PTR_ERR(pt1->kthread);
  577. pt1->kthread = NULL;
  578. }
  579. }
  580. mutex_unlock(&pt1->lock);
  581. return ret;
  582. }
  583. static int pt1_start_feed(struct dvb_demux_feed *feed)
  584. {
  585. struct pt1_adapter *adap;
  586. adap = container_of(feed->demux, struct pt1_adapter, demux);
  587. if (!adap->users++) {
  588. int ret;
  589. ret = pt1_start_polling(adap->pt1);
  590. if (ret)
  591. return ret;
  592. pt1_set_stream(adap->pt1, adap->index, 1);
  593. }
  594. return 0;
  595. }
  596. static void pt1_stop_polling(struct pt1 *pt1)
  597. {
  598. int i, count;
  599. mutex_lock(&pt1->lock);
  600. for (i = 0, count = 0; i < PT1_NR_ADAPS; i++)
  601. count += pt1->adaps[i]->users;
  602. if (count == 0 && pt1->kthread) {
  603. kthread_stop(pt1->kthread);
  604. pt1->kthread = NULL;
  605. }
  606. mutex_unlock(&pt1->lock);
  607. }
  608. static int pt1_stop_feed(struct dvb_demux_feed *feed)
  609. {
  610. struct pt1_adapter *adap;
  611. adap = container_of(feed->demux, struct pt1_adapter, demux);
  612. if (!--adap->users) {
  613. pt1_set_stream(adap->pt1, adap->index, 0);
  614. pt1_stop_polling(adap->pt1);
  615. }
  616. return 0;
  617. }
  618. static void
  619. pt1_update_power(struct pt1 *pt1)
  620. {
  621. int bits;
  622. int i;
  623. struct pt1_adapter *adap;
  624. static const int sleep_bits[] = {
  625. 1 << 4,
  626. 1 << 6 | 1 << 7,
  627. 1 << 5,
  628. 1 << 6 | 1 << 8,
  629. };
  630. bits = pt1->power | !pt1->reset << 3;
  631. mutex_lock(&pt1->lock);
  632. for (i = 0; i < PT1_NR_ADAPS; i++) {
  633. adap = pt1->adaps[i];
  634. switch (adap->voltage) {
  635. case SEC_VOLTAGE_13: /* actually 11V */
  636. bits |= 1 << 2;
  637. break;
  638. case SEC_VOLTAGE_18: /* actually 15V */
  639. bits |= 1 << 1 | 1 << 2;
  640. break;
  641. default:
  642. break;
  643. }
  644. /* XXX: The bits should be changed depending on adap->sleep. */
  645. bits |= sleep_bits[i];
  646. }
  647. pt1_write_reg(pt1, 1, bits);
  648. mutex_unlock(&pt1->lock);
  649. }
  650. static int pt1_set_voltage(struct dvb_frontend *fe, enum fe_sec_voltage voltage)
  651. {
  652. struct pt1_adapter *adap;
  653. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  654. adap->voltage = voltage;
  655. pt1_update_power(adap->pt1);
  656. if (adap->orig_set_voltage)
  657. return adap->orig_set_voltage(fe, voltage);
  658. else
  659. return 0;
  660. }
  661. static int pt1_sleep(struct dvb_frontend *fe)
  662. {
  663. struct pt1_adapter *adap;
  664. int ret;
  665. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  666. ret = 0;
  667. if (adap->orig_sleep)
  668. ret = adap->orig_sleep(fe);
  669. adap->sleep = 1;
  670. pt1_update_power(adap->pt1);
  671. return ret;
  672. }
  673. static int pt1_wakeup(struct dvb_frontend *fe)
  674. {
  675. struct pt1_adapter *adap;
  676. int ret;
  677. adap = container_of(fe->dvb, struct pt1_adapter, adap);
  678. adap->sleep = 0;
  679. pt1_update_power(adap->pt1);
  680. usleep_range(1000, 2000);
  681. ret = config_demod(adap->demod_i2c_client, adap->pt1->fe_clk);
  682. if (ret == 0 && adap->orig_init)
  683. ret = adap->orig_init(fe);
  684. return ret;
  685. }
  686. static void pt1_free_adapter(struct pt1_adapter *adap)
  687. {
  688. adap->demux.dmx.close(&adap->demux.dmx);
  689. dvb_dmxdev_release(&adap->dmxdev);
  690. dvb_dmx_release(&adap->demux);
  691. dvb_unregister_adapter(&adap->adap);
  692. free_page((unsigned long)adap->buf);
  693. kfree(adap);
  694. }
  695. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  696. static struct pt1_adapter *
  697. pt1_alloc_adapter(struct pt1 *pt1)
  698. {
  699. struct pt1_adapter *adap;
  700. void *buf;
  701. struct dvb_adapter *dvb_adap;
  702. struct dvb_demux *demux;
  703. struct dmxdev *dmxdev;
  704. int ret;
  705. adap = kzalloc(sizeof(struct pt1_adapter), GFP_KERNEL);
  706. if (!adap) {
  707. ret = -ENOMEM;
  708. goto err;
  709. }
  710. adap->pt1 = pt1;
  711. adap->voltage = SEC_VOLTAGE_OFF;
  712. adap->sleep = 1;
  713. buf = (u8 *)__get_free_page(GFP_KERNEL);
  714. if (!buf) {
  715. ret = -ENOMEM;
  716. goto err_kfree;
  717. }
  718. adap->buf = buf;
  719. adap->upacket_count = 0;
  720. adap->packet_count = 0;
  721. adap->st_count = -1;
  722. dvb_adap = &adap->adap;
  723. dvb_adap->priv = adap;
  724. ret = dvb_register_adapter(dvb_adap, DRIVER_NAME, THIS_MODULE,
  725. &pt1->pdev->dev, adapter_nr);
  726. if (ret < 0)
  727. goto err_free_page;
  728. demux = &adap->demux;
  729. demux->dmx.capabilities = DMX_TS_FILTERING | DMX_SECTION_FILTERING;
  730. demux->priv = adap;
  731. demux->feednum = 256;
  732. demux->filternum = 256;
  733. demux->start_feed = pt1_start_feed;
  734. demux->stop_feed = pt1_stop_feed;
  735. demux->write_to_decoder = NULL;
  736. ret = dvb_dmx_init(demux);
  737. if (ret < 0)
  738. goto err_unregister_adapter;
  739. dmxdev = &adap->dmxdev;
  740. dmxdev->filternum = 256;
  741. dmxdev->demux = &demux->dmx;
  742. dmxdev->capabilities = 0;
  743. ret = dvb_dmxdev_init(dmxdev, dvb_adap);
  744. if (ret < 0)
  745. goto err_dmx_release;
  746. return adap;
  747. err_dmx_release:
  748. dvb_dmx_release(demux);
  749. err_unregister_adapter:
  750. dvb_unregister_adapter(dvb_adap);
  751. err_free_page:
  752. free_page((unsigned long)buf);
  753. err_kfree:
  754. kfree(adap);
  755. err:
  756. return ERR_PTR(ret);
  757. }
  758. static void pt1_cleanup_adapters(struct pt1 *pt1)
  759. {
  760. int i;
  761. for (i = 0; i < PT1_NR_ADAPS; i++)
  762. pt1_free_adapter(pt1->adaps[i]);
  763. }
  764. static int pt1_init_adapters(struct pt1 *pt1)
  765. {
  766. int i;
  767. struct pt1_adapter *adap;
  768. int ret;
  769. for (i = 0; i < PT1_NR_ADAPS; i++) {
  770. adap = pt1_alloc_adapter(pt1);
  771. if (IS_ERR(adap)) {
  772. ret = PTR_ERR(adap);
  773. goto err;
  774. }
  775. adap->index = i;
  776. pt1->adaps[i] = adap;
  777. }
  778. return 0;
  779. err:
  780. while (i--)
  781. pt1_free_adapter(pt1->adaps[i]);
  782. return ret;
  783. }
  784. static void pt1_cleanup_frontend(struct pt1_adapter *adap)
  785. {
  786. dvb_unregister_frontend(adap->fe);
  787. dvb_module_release(adap->tuner_i2c_client);
  788. dvb_module_release(adap->demod_i2c_client);
  789. }
  790. static int pt1_init_frontend(struct pt1_adapter *adap, struct dvb_frontend *fe)
  791. {
  792. int ret;
  793. adap->orig_set_voltage = fe->ops.set_voltage;
  794. adap->orig_sleep = fe->ops.sleep;
  795. adap->orig_init = fe->ops.init;
  796. fe->ops.set_voltage = pt1_set_voltage;
  797. fe->ops.sleep = pt1_sleep;
  798. fe->ops.init = pt1_wakeup;
  799. ret = dvb_register_frontend(&adap->adap, fe);
  800. if (ret < 0)
  801. return ret;
  802. adap->fe = fe;
  803. return 0;
  804. }
  805. static void pt1_cleanup_frontends(struct pt1 *pt1)
  806. {
  807. int i;
  808. for (i = 0; i < PT1_NR_ADAPS; i++)
  809. pt1_cleanup_frontend(pt1->adaps[i]);
  810. }
  811. static int pt1_init_frontends(struct pt1 *pt1)
  812. {
  813. int i;
  814. int ret;
  815. for (i = 0; i < ARRAY_SIZE(pt1_configs); i++) {
  816. const struct i2c_board_info *info;
  817. struct tc90522_config dcfg;
  818. struct i2c_client *cl;
  819. info = &pt1_configs[i].demod_info;
  820. dcfg = pt1_configs[i].demod_cfg;
  821. dcfg.tuner_i2c = NULL;
  822. ret = -ENODEV;
  823. cl = dvb_module_probe("tc90522", info->type, &pt1->i2c_adap,
  824. info->addr, &dcfg);
  825. if (!cl)
  826. goto fe_unregister;
  827. pt1->adaps[i]->demod_i2c_client = cl;
  828. if (!strncmp(cl->name, TC90522_I2C_DEV_SAT,
  829. strlen(TC90522_I2C_DEV_SAT))) {
  830. struct qm1d1b0004_config tcfg;
  831. info = &pt1_configs[i].tuner_info;
  832. tcfg = pt1_configs[i].tuner_cfg.qm1d1b0004;
  833. tcfg.fe = dcfg.fe;
  834. cl = dvb_module_probe("qm1d1b0004",
  835. info->type, dcfg.tuner_i2c,
  836. info->addr, &tcfg);
  837. } else {
  838. struct dvb_pll_config tcfg;
  839. info = &pt1_configs[i].tuner_info;
  840. tcfg = pt1_configs[i].tuner_cfg.tda6651;
  841. tcfg.fe = dcfg.fe;
  842. cl = dvb_module_probe("dvb_pll",
  843. info->type, dcfg.tuner_i2c,
  844. info->addr, &tcfg);
  845. }
  846. if (!cl)
  847. goto demod_release;
  848. pt1->adaps[i]->tuner_i2c_client = cl;
  849. ret = pt1_init_frontend(pt1->adaps[i], dcfg.fe);
  850. if (ret < 0)
  851. goto tuner_release;
  852. }
  853. ret = pt1_demod_block_init(pt1);
  854. if (ret < 0)
  855. goto fe_unregister;
  856. return 0;
  857. tuner_release:
  858. dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
  859. demod_release:
  860. dvb_module_release(pt1->adaps[i]->demod_i2c_client);
  861. fe_unregister:
  862. dev_warn(&pt1->pdev->dev, "failed to init FE(%d).\n", i);
  863. i--;
  864. for (; i >= 0; i--) {
  865. dvb_unregister_frontend(pt1->adaps[i]->fe);
  866. dvb_module_release(pt1->adaps[i]->tuner_i2c_client);
  867. dvb_module_release(pt1->adaps[i]->demod_i2c_client);
  868. }
  869. return ret;
  870. }
  871. static void pt1_i2c_emit(struct pt1 *pt1, int addr, int busy, int read_enable,
  872. int clock, int data, int next_addr)
  873. {
  874. pt1_write_reg(pt1, 4, addr << 18 | busy << 13 | read_enable << 12 |
  875. !clock << 11 | !data << 10 | next_addr);
  876. }
  877. static void pt1_i2c_write_bit(struct pt1 *pt1, int addr, int *addrp, int data)
  878. {
  879. pt1_i2c_emit(pt1, addr, 1, 0, 0, data, addr + 1);
  880. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, data, addr + 2);
  881. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, data, addr + 3);
  882. *addrp = addr + 3;
  883. }
  884. static void pt1_i2c_read_bit(struct pt1 *pt1, int addr, int *addrp)
  885. {
  886. pt1_i2c_emit(pt1, addr, 1, 0, 0, 1, addr + 1);
  887. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 1, addr + 2);
  888. pt1_i2c_emit(pt1, addr + 2, 1, 1, 1, 1, addr + 3);
  889. pt1_i2c_emit(pt1, addr + 3, 1, 0, 0, 1, addr + 4);
  890. *addrp = addr + 4;
  891. }
  892. static void pt1_i2c_write_byte(struct pt1 *pt1, int addr, int *addrp, int data)
  893. {
  894. int i;
  895. for (i = 0; i < 8; i++)
  896. pt1_i2c_write_bit(pt1, addr, &addr, data >> (7 - i) & 1);
  897. pt1_i2c_write_bit(pt1, addr, &addr, 1);
  898. *addrp = addr;
  899. }
  900. static void pt1_i2c_read_byte(struct pt1 *pt1, int addr, int *addrp, int last)
  901. {
  902. int i;
  903. for (i = 0; i < 8; i++)
  904. pt1_i2c_read_bit(pt1, addr, &addr);
  905. pt1_i2c_write_bit(pt1, addr, &addr, last);
  906. *addrp = addr;
  907. }
  908. static void pt1_i2c_prepare(struct pt1 *pt1, int addr, int *addrp)
  909. {
  910. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  911. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  912. pt1_i2c_emit(pt1, addr + 2, 1, 0, 0, 0, addr + 3);
  913. *addrp = addr + 3;
  914. }
  915. static void
  916. pt1_i2c_write_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  917. {
  918. int i;
  919. pt1_i2c_prepare(pt1, addr, &addr);
  920. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1);
  921. for (i = 0; i < msg->len; i++)
  922. pt1_i2c_write_byte(pt1, addr, &addr, msg->buf[i]);
  923. *addrp = addr;
  924. }
  925. static void
  926. pt1_i2c_read_msg(struct pt1 *pt1, int addr, int *addrp, struct i2c_msg *msg)
  927. {
  928. int i;
  929. pt1_i2c_prepare(pt1, addr, &addr);
  930. pt1_i2c_write_byte(pt1, addr, &addr, msg->addr << 1 | 1);
  931. for (i = 0; i < msg->len; i++)
  932. pt1_i2c_read_byte(pt1, addr, &addr, i == msg->len - 1);
  933. *addrp = addr;
  934. }
  935. static int pt1_i2c_end(struct pt1 *pt1, int addr)
  936. {
  937. pt1_i2c_emit(pt1, addr, 1, 0, 0, 0, addr + 1);
  938. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  939. pt1_i2c_emit(pt1, addr + 2, 1, 0, 1, 1, 0);
  940. pt1_write_reg(pt1, 0, 0x00000004);
  941. do {
  942. if (signal_pending(current))
  943. return -EINTR;
  944. usleep_range(1000, 2000);
  945. } while (pt1_read_reg(pt1, 0) & 0x00000080);
  946. return 0;
  947. }
  948. static void pt1_i2c_begin(struct pt1 *pt1, int *addrp)
  949. {
  950. int addr = 0;
  951. pt1_i2c_emit(pt1, addr, 0, 0, 1, 1, addr /* itself */);
  952. addr = addr + 1;
  953. if (!pt1->i2c_running) {
  954. pt1_i2c_emit(pt1, addr, 1, 0, 1, 1, addr + 1);
  955. pt1_i2c_emit(pt1, addr + 1, 1, 0, 1, 0, addr + 2);
  956. addr = addr + 2;
  957. pt1->i2c_running = 1;
  958. }
  959. *addrp = addr;
  960. }
  961. static int pt1_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
  962. {
  963. struct pt1 *pt1;
  964. int i;
  965. struct i2c_msg *msg, *next_msg;
  966. int addr, ret;
  967. u16 len;
  968. u32 word;
  969. pt1 = i2c_get_adapdata(adap);
  970. for (i = 0; i < num; i++) {
  971. msg = &msgs[i];
  972. if (msg->flags & I2C_M_RD)
  973. return -ENOTSUPP;
  974. if (i + 1 < num)
  975. next_msg = &msgs[i + 1];
  976. else
  977. next_msg = NULL;
  978. if (next_msg && next_msg->flags & I2C_M_RD) {
  979. i++;
  980. len = next_msg->len;
  981. if (len > 4)
  982. return -ENOTSUPP;
  983. pt1_i2c_begin(pt1, &addr);
  984. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  985. pt1_i2c_read_msg(pt1, addr, &addr, next_msg);
  986. ret = pt1_i2c_end(pt1, addr);
  987. if (ret < 0)
  988. return ret;
  989. word = pt1_read_reg(pt1, 2);
  990. while (len--) {
  991. next_msg->buf[len] = word;
  992. word >>= 8;
  993. }
  994. } else {
  995. pt1_i2c_begin(pt1, &addr);
  996. pt1_i2c_write_msg(pt1, addr, &addr, msg);
  997. ret = pt1_i2c_end(pt1, addr);
  998. if (ret < 0)
  999. return ret;
  1000. }
  1001. }
  1002. return num;
  1003. }
  1004. static u32 pt1_i2c_func(struct i2c_adapter *adap)
  1005. {
  1006. return I2C_FUNC_I2C;
  1007. }
  1008. static const struct i2c_algorithm pt1_i2c_algo = {
  1009. .master_xfer = pt1_i2c_xfer,
  1010. .functionality = pt1_i2c_func,
  1011. };
  1012. static void pt1_i2c_wait(struct pt1 *pt1)
  1013. {
  1014. int i;
  1015. for (i = 0; i < 128; i++)
  1016. pt1_i2c_emit(pt1, 0, 0, 0, 1, 1, 0);
  1017. }
  1018. static void pt1_i2c_init(struct pt1 *pt1)
  1019. {
  1020. int i;
  1021. for (i = 0; i < 1024; i++)
  1022. pt1_i2c_emit(pt1, i, 0, 0, 1, 1, 0);
  1023. }
  1024. #ifdef CONFIG_PM_SLEEP
  1025. static int pt1_suspend(struct device *dev)
  1026. {
  1027. struct pt1 *pt1 = dev_get_drvdata(dev);
  1028. pt1_init_streams(pt1);
  1029. pt1_disable_ram(pt1);
  1030. pt1->power = 0;
  1031. pt1->reset = 1;
  1032. pt1_update_power(pt1);
  1033. return 0;
  1034. }
  1035. static int pt1_resume(struct device *dev)
  1036. {
  1037. struct pt1 *pt1 = dev_get_drvdata(dev);
  1038. int ret;
  1039. int i;
  1040. pt1->power = 0;
  1041. pt1->reset = 1;
  1042. pt1_update_power(pt1);
  1043. pt1_i2c_init(pt1);
  1044. pt1_i2c_wait(pt1);
  1045. ret = pt1_sync(pt1);
  1046. if (ret < 0)
  1047. goto resume_err;
  1048. pt1_identify(pt1);
  1049. ret = pt1_unlock(pt1);
  1050. if (ret < 0)
  1051. goto resume_err;
  1052. ret = pt1_reset_pci(pt1);
  1053. if (ret < 0)
  1054. goto resume_err;
  1055. ret = pt1_reset_ram(pt1);
  1056. if (ret < 0)
  1057. goto resume_err;
  1058. ret = pt1_enable_ram(pt1);
  1059. if (ret < 0)
  1060. goto resume_err;
  1061. pt1_init_streams(pt1);
  1062. pt1->power = 1;
  1063. pt1_update_power(pt1);
  1064. msleep(20);
  1065. pt1->reset = 0;
  1066. pt1_update_power(pt1);
  1067. usleep_range(1000, 2000);
  1068. ret = pt1_demod_block_init(pt1);
  1069. if (ret < 0)
  1070. goto resume_err;
  1071. for (i = 0; i < PT1_NR_ADAPS; i++)
  1072. dvb_frontend_reinitialise(pt1->adaps[i]->fe);
  1073. pt1_init_table_count(pt1);
  1074. for (i = 0; i < pt1_nr_tables; i++) {
  1075. int j;
  1076. for (j = 0; j < PT1_NR_BUFS; j++)
  1077. pt1->tables[i].bufs[j].page->upackets[PT1_NR_UPACKETS-1]
  1078. = 0;
  1079. pt1_increment_table_count(pt1);
  1080. }
  1081. pt1_register_tables(pt1, pt1->tables[0].addr >> PT1_PAGE_SHIFT);
  1082. pt1->table_index = 0;
  1083. pt1->buf_index = 0;
  1084. for (i = 0; i < PT1_NR_ADAPS; i++) {
  1085. pt1->adaps[i]->upacket_count = 0;
  1086. pt1->adaps[i]->packet_count = 0;
  1087. pt1->adaps[i]->st_count = -1;
  1088. }
  1089. return 0;
  1090. resume_err:
  1091. dev_info(&pt1->pdev->dev, "failed to resume PT1/PT2.");
  1092. return 0; /* resume anyway */
  1093. }
  1094. #endif /* CONFIG_PM_SLEEP */
  1095. static void pt1_remove(struct pci_dev *pdev)
  1096. {
  1097. struct pt1 *pt1;
  1098. void __iomem *regs;
  1099. pt1 = pci_get_drvdata(pdev);
  1100. regs = pt1->regs;
  1101. if (pt1->kthread)
  1102. kthread_stop(pt1->kthread);
  1103. pt1_cleanup_tables(pt1);
  1104. pt1_cleanup_frontends(pt1);
  1105. pt1_disable_ram(pt1);
  1106. pt1->power = 0;
  1107. pt1->reset = 1;
  1108. pt1_update_power(pt1);
  1109. pt1_cleanup_adapters(pt1);
  1110. i2c_del_adapter(&pt1->i2c_adap);
  1111. kfree(pt1);
  1112. pci_iounmap(pdev, regs);
  1113. pci_release_regions(pdev);
  1114. pci_disable_device(pdev);
  1115. }
  1116. static int pt1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  1117. {
  1118. int ret;
  1119. void __iomem *regs;
  1120. struct pt1 *pt1;
  1121. struct i2c_adapter *i2c_adap;
  1122. ret = pci_enable_device(pdev);
  1123. if (ret < 0)
  1124. goto err;
  1125. ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  1126. if (ret < 0)
  1127. goto err_pci_disable_device;
  1128. pci_set_master(pdev);
  1129. ret = pci_request_regions(pdev, DRIVER_NAME);
  1130. if (ret < 0)
  1131. goto err_pci_disable_device;
  1132. regs = pci_iomap(pdev, 0, 0);
  1133. if (!regs) {
  1134. ret = -EIO;
  1135. goto err_pci_release_regions;
  1136. }
  1137. pt1 = kzalloc(sizeof(struct pt1), GFP_KERNEL);
  1138. if (!pt1) {
  1139. ret = -ENOMEM;
  1140. goto err_pci_iounmap;
  1141. }
  1142. mutex_init(&pt1->lock);
  1143. pt1->pdev = pdev;
  1144. pt1->regs = regs;
  1145. pt1->fe_clk = (pdev->device == 0x211a) ?
  1146. PT1_FE_CLK_20MHZ : PT1_FE_CLK_25MHZ;
  1147. pci_set_drvdata(pdev, pt1);
  1148. ret = pt1_init_adapters(pt1);
  1149. if (ret < 0)
  1150. goto err_kfree;
  1151. mutex_init(&pt1->lock);
  1152. pt1->power = 0;
  1153. pt1->reset = 1;
  1154. pt1_update_power(pt1);
  1155. i2c_adap = &pt1->i2c_adap;
  1156. i2c_adap->algo = &pt1_i2c_algo;
  1157. i2c_adap->algo_data = NULL;
  1158. i2c_adap->dev.parent = &pdev->dev;
  1159. strscpy(i2c_adap->name, DRIVER_NAME, sizeof(i2c_adap->name));
  1160. i2c_set_adapdata(i2c_adap, pt1);
  1161. ret = i2c_add_adapter(i2c_adap);
  1162. if (ret < 0)
  1163. goto err_pt1_cleanup_adapters;
  1164. pt1_i2c_init(pt1);
  1165. pt1_i2c_wait(pt1);
  1166. ret = pt1_sync(pt1);
  1167. if (ret < 0)
  1168. goto err_i2c_del_adapter;
  1169. pt1_identify(pt1);
  1170. ret = pt1_unlock(pt1);
  1171. if (ret < 0)
  1172. goto err_i2c_del_adapter;
  1173. ret = pt1_reset_pci(pt1);
  1174. if (ret < 0)
  1175. goto err_i2c_del_adapter;
  1176. ret = pt1_reset_ram(pt1);
  1177. if (ret < 0)
  1178. goto err_i2c_del_adapter;
  1179. ret = pt1_enable_ram(pt1);
  1180. if (ret < 0)
  1181. goto err_i2c_del_adapter;
  1182. pt1_init_streams(pt1);
  1183. pt1->power = 1;
  1184. pt1_update_power(pt1);
  1185. msleep(20);
  1186. pt1->reset = 0;
  1187. pt1_update_power(pt1);
  1188. usleep_range(1000, 2000);
  1189. ret = pt1_init_frontends(pt1);
  1190. if (ret < 0)
  1191. goto err_pt1_disable_ram;
  1192. ret = pt1_init_tables(pt1);
  1193. if (ret < 0)
  1194. goto err_pt1_cleanup_frontends;
  1195. return 0;
  1196. err_pt1_cleanup_frontends:
  1197. pt1_cleanup_frontends(pt1);
  1198. err_pt1_disable_ram:
  1199. pt1_disable_ram(pt1);
  1200. pt1->power = 0;
  1201. pt1->reset = 1;
  1202. pt1_update_power(pt1);
  1203. err_i2c_del_adapter:
  1204. i2c_del_adapter(i2c_adap);
  1205. err_pt1_cleanup_adapters:
  1206. pt1_cleanup_adapters(pt1);
  1207. err_kfree:
  1208. kfree(pt1);
  1209. err_pci_iounmap:
  1210. pci_iounmap(pdev, regs);
  1211. err_pci_release_regions:
  1212. pci_release_regions(pdev);
  1213. err_pci_disable_device:
  1214. pci_disable_device(pdev);
  1215. err:
  1216. return ret;
  1217. }
  1218. static const struct pci_device_id pt1_id_table[] = {
  1219. { PCI_DEVICE(0x10ee, 0x211a) },
  1220. { PCI_DEVICE(0x10ee, 0x222a) },
  1221. { },
  1222. };
  1223. MODULE_DEVICE_TABLE(pci, pt1_id_table);
  1224. static SIMPLE_DEV_PM_OPS(pt1_pm_ops, pt1_suspend, pt1_resume);
  1225. static struct pci_driver pt1_driver = {
  1226. .name = DRIVER_NAME,
  1227. .probe = pt1_probe,
  1228. .remove = pt1_remove,
  1229. .id_table = pt1_id_table,
  1230. .driver.pm = &pt1_pm_ops,
  1231. };
  1232. module_pci_driver(pt1_driver);
  1233. MODULE_AUTHOR("Takahito HIRANO <[email protected]>");
  1234. MODULE_DESCRIPTION("Earthsoft PT1/PT2 Driver");
  1235. MODULE_LICENSE("GPL");