dm1105.c 29 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip
  4. *
  5. * Copyright (C) 2008 Igor M. Liplianin <[email protected]>
  6. */
  7. #include <linux/i2c.h>
  8. #include <linux/i2c-algo-bit.h>
  9. #include <linux/init.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/slab.h>
  16. #include <media/rc-core.h>
  17. #include <media/demux.h>
  18. #include <media/dmxdev.h>
  19. #include <media/dvb_demux.h>
  20. #include <media/dvb_frontend.h>
  21. #include <media/dvb_net.h>
  22. #include <media/dvbdev.h>
  23. #include "dvb-pll.h"
  24. #include "stv0299.h"
  25. #include "stv0288.h"
  26. #include "stb6000.h"
  27. #include "si21xx.h"
  28. #include "cx24116.h"
  29. #include "z0194a.h"
  30. #include "ts2020.h"
  31. #include "ds3000.h"
  32. #define MODULE_NAME "dm1105"
  33. #define UNSET (-1U)
  34. #define DM1105_BOARD_NOAUTO UNSET
  35. #define DM1105_BOARD_UNKNOWN 0
  36. #define DM1105_BOARD_DVBWORLD_2002 1
  37. #define DM1105_BOARD_DVBWORLD_2004 2
  38. #define DM1105_BOARD_AXESS_DM05 3
  39. #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4
  40. /* ----------------------------------------------- */
  41. /*
  42. * PCI ID's
  43. */
  44. #ifndef PCI_VENDOR_ID_TRIGEM
  45. #define PCI_VENDOR_ID_TRIGEM 0x109f
  46. #endif
  47. #ifndef PCI_VENDOR_ID_AXESS
  48. #define PCI_VENDOR_ID_AXESS 0x195d
  49. #endif
  50. #ifndef PCI_DEVICE_ID_DM1105
  51. #define PCI_DEVICE_ID_DM1105 0x036f
  52. #endif
  53. #ifndef PCI_DEVICE_ID_DW2002
  54. #define PCI_DEVICE_ID_DW2002 0x2002
  55. #endif
  56. #ifndef PCI_DEVICE_ID_DW2004
  57. #define PCI_DEVICE_ID_DW2004 0x2004
  58. #endif
  59. #ifndef PCI_DEVICE_ID_DM05
  60. #define PCI_DEVICE_ID_DM05 0x1105
  61. #endif
  62. /* ----------------------------------------------- */
  63. /* sdmc dm1105 registers */
  64. /* TS Control */
  65. #define DM1105_TSCTR 0x00
  66. #define DM1105_DTALENTH 0x04
  67. /* GPIO Interface */
  68. #define DM1105_GPIOVAL 0x08
  69. #define DM1105_GPIOCTR 0x0c
  70. /* PID serial number */
  71. #define DM1105_PIDN 0x10
  72. /* Odd-even secret key select */
  73. #define DM1105_CWSEL 0x14
  74. /* Host Command Interface */
  75. #define DM1105_HOST_CTR 0x18
  76. #define DM1105_HOST_AD 0x1c
  77. /* PCI Interface */
  78. #define DM1105_CR 0x30
  79. #define DM1105_RST 0x34
  80. #define DM1105_STADR 0x38
  81. #define DM1105_RLEN 0x3c
  82. #define DM1105_WRP 0x40
  83. #define DM1105_INTCNT 0x44
  84. #define DM1105_INTMAK 0x48
  85. #define DM1105_INTSTS 0x4c
  86. /* CW Value */
  87. #define DM1105_ODD 0x50
  88. #define DM1105_EVEN 0x58
  89. /* PID Value */
  90. #define DM1105_PID 0x60
  91. /* IR Control */
  92. #define DM1105_IRCTR 0x64
  93. #define DM1105_IRMODE 0x68
  94. #define DM1105_SYSTEMCODE 0x6c
  95. #define DM1105_IRCODE 0x70
  96. /* Unknown Values */
  97. #define DM1105_ENCRYPT 0x74
  98. #define DM1105_VER 0x7c
  99. /* I2C Interface */
  100. #define DM1105_I2CCTR 0x80
  101. #define DM1105_I2CSTS 0x81
  102. #define DM1105_I2CDAT 0x82
  103. #define DM1105_I2C_RA 0x83
  104. /* ----------------------------------------------- */
  105. /* Interrupt Mask Bits */
  106. #define INTMAK_TSIRQM 0x01
  107. #define INTMAK_HIRQM 0x04
  108. #define INTMAK_IRM 0x08
  109. #define INTMAK_ALLMASK (INTMAK_TSIRQM | \
  110. INTMAK_HIRQM | \
  111. INTMAK_IRM)
  112. #define INTMAK_NONEMASK 0x00
  113. /* Interrupt Status Bits */
  114. #define INTSTS_TSIRQ 0x01
  115. #define INTSTS_HIRQ 0x04
  116. #define INTSTS_IR 0x08
  117. /* IR Control Bits */
  118. #define DM1105_IR_EN 0x01
  119. #define DM1105_SYS_CHK 0x02
  120. #define DM1105_REP_FLG 0x08
  121. /* EEPROM addr */
  122. #define IIC_24C01_addr 0xa0
  123. /* Max board count */
  124. #define DM1105_MAX 0x04
  125. #define DRIVER_NAME "dm1105"
  126. #define DM1105_I2C_GPIO_NAME "dm1105-gpio"
  127. #define DM1105_DMA_PACKETS 47
  128. #define DM1105_DMA_PACKET_LENGTH (128*4)
  129. #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS)
  130. /* */
  131. #define GPIO08 (1 << 8)
  132. #define GPIO13 (1 << 13)
  133. #define GPIO14 (1 << 14)
  134. #define GPIO15 (1 << 15)
  135. #define GPIO16 (1 << 16)
  136. #define GPIO17 (1 << 17)
  137. #define GPIO_ALL 0x03ffff
  138. /* GPIO's for LNB power control */
  139. #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  140. #define DM1105_LNB_OFF GPIO17
  141. #define DM1105_LNB_13V (GPIO16 | GPIO08)
  142. #define DM1105_LNB_18V GPIO08
  143. /* GPIO's for LNB power control for Axess DM05 */
  144. #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  145. #define DM05_LNB_OFF GPIO17/* actually 13v */
  146. #define DM05_LNB_13V GPIO17
  147. #define DM05_LNB_18V (GPIO17 | GPIO16)
  148. /* GPIO's for LNB power control for unbranded with I2C on GPIO */
  149. #define UNBR_LNB_MASK (GPIO17 | GPIO16)
  150. #define UNBR_LNB_OFF 0
  151. #define UNBR_LNB_13V GPIO17
  152. #define UNBR_LNB_18V (GPIO17 | GPIO16)
  153. static unsigned int card[] = {[0 ... 3] = UNSET };
  154. module_param_array(card, int, NULL, 0444);
  155. MODULE_PARM_DESC(card, "card type");
  156. static int ir_debug;
  157. module_param(ir_debug, int, 0644);
  158. MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
  159. static unsigned int dm1105_devcount;
  160. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  161. struct dm1105_board {
  162. char *name;
  163. struct {
  164. u32 mask, off, v13, v18;
  165. } lnb;
  166. u32 gpio_scl, gpio_sda;
  167. };
  168. struct dm1105_subid {
  169. u16 subvendor;
  170. u16 subdevice;
  171. u32 card;
  172. };
  173. static const struct dm1105_board dm1105_boards[] = {
  174. [DM1105_BOARD_UNKNOWN] = {
  175. .name = "UNKNOWN/GENERIC",
  176. .lnb = {
  177. .mask = DM1105_LNB_MASK,
  178. .off = DM1105_LNB_OFF,
  179. .v13 = DM1105_LNB_13V,
  180. .v18 = DM1105_LNB_18V,
  181. },
  182. },
  183. [DM1105_BOARD_DVBWORLD_2002] = {
  184. .name = "DVBWorld PCI 2002",
  185. .lnb = {
  186. .mask = DM1105_LNB_MASK,
  187. .off = DM1105_LNB_OFF,
  188. .v13 = DM1105_LNB_13V,
  189. .v18 = DM1105_LNB_18V,
  190. },
  191. },
  192. [DM1105_BOARD_DVBWORLD_2004] = {
  193. .name = "DVBWorld PCI 2004",
  194. .lnb = {
  195. .mask = DM1105_LNB_MASK,
  196. .off = DM1105_LNB_OFF,
  197. .v13 = DM1105_LNB_13V,
  198. .v18 = DM1105_LNB_18V,
  199. },
  200. },
  201. [DM1105_BOARD_AXESS_DM05] = {
  202. .name = "Axess/EasyTv DM05",
  203. .lnb = {
  204. .mask = DM05_LNB_MASK,
  205. .off = DM05_LNB_OFF,
  206. .v13 = DM05_LNB_13V,
  207. .v18 = DM05_LNB_18V,
  208. },
  209. },
  210. [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = {
  211. .name = "Unbranded DM1105 with i2c on GPIOs",
  212. .lnb = {
  213. .mask = UNBR_LNB_MASK,
  214. .off = UNBR_LNB_OFF,
  215. .v13 = UNBR_LNB_13V,
  216. .v18 = UNBR_LNB_18V,
  217. },
  218. .gpio_scl = GPIO14,
  219. .gpio_sda = GPIO13,
  220. },
  221. };
  222. static const struct dm1105_subid dm1105_subids[] = {
  223. {
  224. .subvendor = 0x0000,
  225. .subdevice = 0x2002,
  226. .card = DM1105_BOARD_DVBWORLD_2002,
  227. }, {
  228. .subvendor = 0x0001,
  229. .subdevice = 0x2002,
  230. .card = DM1105_BOARD_DVBWORLD_2002,
  231. }, {
  232. .subvendor = 0x0000,
  233. .subdevice = 0x2004,
  234. .card = DM1105_BOARD_DVBWORLD_2004,
  235. }, {
  236. .subvendor = 0x0001,
  237. .subdevice = 0x2004,
  238. .card = DM1105_BOARD_DVBWORLD_2004,
  239. }, {
  240. .subvendor = 0x195d,
  241. .subdevice = 0x1105,
  242. .card = DM1105_BOARD_AXESS_DM05,
  243. },
  244. };
  245. static void dm1105_card_list(struct pci_dev *pci)
  246. {
  247. int i;
  248. if (0 == pci->subsystem_vendor &&
  249. 0 == pci->subsystem_device) {
  250. printk(KERN_ERR
  251. "dm1105: Your board has no valid PCI Subsystem ID\n"
  252. "dm1105: and thus can't be autodetected\n"
  253. "dm1105: Please pass card=<n> insmod option to\n"
  254. "dm1105: workaround that. Redirect complaints to\n"
  255. "dm1105: the vendor of the TV card. Best regards,\n"
  256. "dm1105: -- tux\n");
  257. } else {
  258. printk(KERN_ERR
  259. "dm1105: Your board isn't known (yet) to the driver.\n"
  260. "dm1105: You can try to pick one of the existing\n"
  261. "dm1105: card configs via card=<n> insmod option.\n"
  262. "dm1105: Updating to the latest version might help\n"
  263. "dm1105: as well.\n");
  264. }
  265. printk(KERN_ERR "Here is a list of valid choices for the card=<n> insmod option:\n");
  266. for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++)
  267. printk(KERN_ERR "dm1105: card=%d -> %s\n",
  268. i, dm1105_boards[i].name);
  269. }
  270. /* infrared remote control */
  271. struct infrared {
  272. struct rc_dev *dev;
  273. char input_phys[32];
  274. struct work_struct work;
  275. u32 ir_command;
  276. };
  277. struct dm1105_dev {
  278. /* pci */
  279. struct pci_dev *pdev;
  280. u8 __iomem *io_mem;
  281. /* ir */
  282. struct infrared ir;
  283. /* dvb */
  284. struct dmx_frontend hw_frontend;
  285. struct dmx_frontend mem_frontend;
  286. struct dmxdev dmxdev;
  287. struct dvb_adapter dvb_adapter;
  288. struct dvb_demux demux;
  289. struct dvb_frontend *fe;
  290. struct dvb_net dvbnet;
  291. unsigned int full_ts_users;
  292. unsigned int boardnr;
  293. int nr;
  294. /* i2c */
  295. struct i2c_adapter i2c_adap;
  296. struct i2c_adapter i2c_bb_adap;
  297. struct i2c_algo_bit_data i2c_bit;
  298. /* irq */
  299. struct work_struct work;
  300. struct workqueue_struct *wq;
  301. char wqn[16];
  302. /* dma */
  303. dma_addr_t dma_addr;
  304. unsigned char *ts_buf;
  305. u32 wrp;
  306. u32 nextwrp;
  307. u32 buffer_size;
  308. unsigned int PacketErrorCount;
  309. unsigned int dmarst;
  310. spinlock_t lock;
  311. };
  312. #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg]))
  313. #define dm_readb(reg) inb(dm_io_mem(reg))
  314. #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg)))
  315. #define dm_readw(reg) inw(dm_io_mem(reg))
  316. #define dm_writew(reg, value) outw((value), (dm_io_mem(reg)))
  317. #define dm_readl(reg) inl(dm_io_mem(reg))
  318. #define dm_writel(reg, value) outl((value), (dm_io_mem(reg)))
  319. #define dm_andorl(reg, mask, value) \
  320. outl((inl(dm_io_mem(reg)) & ~(mask)) |\
  321. ((value) & (mask)), (dm_io_mem(reg)))
  322. #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit))
  323. #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0)
  324. /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines,
  325. so we can use only 3 GPIO's from GPIO15 to GPIO17.
  326. Here I don't check whether HOST is enebled as it is not implemented yet.
  327. */
  328. static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask)
  329. {
  330. if (mask & 0xfffc0000)
  331. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  332. if (mask & 0x0003ffff)
  333. dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff);
  334. }
  335. static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask)
  336. {
  337. if (mask & 0xfffc0000)
  338. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  339. if (mask & 0x0003ffff)
  340. dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff);
  341. }
  342. static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val)
  343. {
  344. if (mask & 0xfffc0000)
  345. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  346. if (mask & 0x0003ffff)
  347. dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val);
  348. }
  349. static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask)
  350. {
  351. if (mask & 0xfffc0000)
  352. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  353. if (mask & 0x0003ffff)
  354. return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff;
  355. return 0;
  356. }
  357. static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput)
  358. {
  359. if (mask & 0xfffc0000)
  360. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  361. if ((mask & 0x0003ffff) && asoutput)
  362. dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff);
  363. else if ((mask & 0x0003ffff) && !asoutput)
  364. dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff);
  365. }
  366. static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state)
  367. {
  368. if (state)
  369. dm1105_gpio_enable(dev, line, 0);
  370. else {
  371. dm1105_gpio_enable(dev, line, 1);
  372. dm1105_gpio_clear(dev, line);
  373. }
  374. }
  375. static void dm1105_setsda(void *data, int state)
  376. {
  377. struct dm1105_dev *dev = data;
  378. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state);
  379. }
  380. static void dm1105_setscl(void *data, int state)
  381. {
  382. struct dm1105_dev *dev = data;
  383. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state);
  384. }
  385. static int dm1105_getsda(void *data)
  386. {
  387. struct dm1105_dev *dev = data;
  388. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda)
  389. ? 1 : 0;
  390. }
  391. static int dm1105_getscl(void *data)
  392. {
  393. struct dm1105_dev *dev = data;
  394. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl)
  395. ? 1 : 0;
  396. }
  397. static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
  398. struct i2c_msg *msgs, int num)
  399. {
  400. struct dm1105_dev *dev ;
  401. int addr, rc, i, j, k, len, byte, data;
  402. u8 status;
  403. dev = i2c_adap->algo_data;
  404. for (i = 0; i < num; i++) {
  405. dm_writeb(DM1105_I2CCTR, 0x00);
  406. if (msgs[i].flags & I2C_M_RD) {
  407. /* read bytes */
  408. addr = msgs[i].addr << 1;
  409. addr |= 1;
  410. dm_writeb(DM1105_I2CDAT, addr);
  411. for (byte = 0; byte < msgs[i].len; byte++)
  412. dm_writeb(DM1105_I2CDAT + byte + 1, 0);
  413. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  414. for (j = 0; j < 55; j++) {
  415. mdelay(10);
  416. status = dm_readb(DM1105_I2CSTS);
  417. if ((status & 0xc0) == 0x40)
  418. break;
  419. }
  420. if (j >= 55)
  421. return -1;
  422. for (byte = 0; byte < msgs[i].len; byte++) {
  423. rc = dm_readb(DM1105_I2CDAT + byte + 1);
  424. if (rc < 0)
  425. goto err;
  426. msgs[i].buf[byte] = rc;
  427. }
  428. } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {
  429. /* prepared for cx24116 firmware */
  430. /* Write in small blocks */
  431. len = msgs[i].len - 1;
  432. k = 1;
  433. do {
  434. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  435. dm_writeb(DM1105_I2CDAT + 1, 0xf7);
  436. for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {
  437. data = msgs[i].buf[k + byte];
  438. dm_writeb(DM1105_I2CDAT + byte + 2, data);
  439. }
  440. dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));
  441. for (j = 0; j < 25; j++) {
  442. mdelay(10);
  443. status = dm_readb(DM1105_I2CSTS);
  444. if ((status & 0xc0) == 0x40)
  445. break;
  446. }
  447. if (j >= 25)
  448. return -1;
  449. k += 48;
  450. len -= 48;
  451. } while (len > 0);
  452. } else {
  453. /* write bytes */
  454. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  455. for (byte = 0; byte < msgs[i].len; byte++) {
  456. data = msgs[i].buf[byte];
  457. dm_writeb(DM1105_I2CDAT + byte + 1, data);
  458. }
  459. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  460. for (j = 0; j < 25; j++) {
  461. mdelay(10);
  462. status = dm_readb(DM1105_I2CSTS);
  463. if ((status & 0xc0) == 0x40)
  464. break;
  465. }
  466. if (j >= 25)
  467. return -1;
  468. }
  469. }
  470. return num;
  471. err:
  472. return rc;
  473. }
  474. static u32 functionality(struct i2c_adapter *adap)
  475. {
  476. return I2C_FUNC_I2C;
  477. }
  478. static const struct i2c_algorithm dm1105_algo = {
  479. .master_xfer = dm1105_i2c_xfer,
  480. .functionality = functionality,
  481. };
  482. static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed)
  483. {
  484. return container_of(feed->demux, struct dm1105_dev, demux);
  485. }
  486. static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe)
  487. {
  488. return container_of(fe->dvb, struct dm1105_dev, dvb_adapter);
  489. }
  490. static int dm1105_set_voltage(struct dvb_frontend *fe,
  491. enum fe_sec_voltage voltage)
  492. {
  493. struct dm1105_dev *dev = frontend_to_dm1105_dev(fe);
  494. dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1);
  495. if (voltage == SEC_VOLTAGE_18)
  496. dm1105_gpio_andor(dev,
  497. dm1105_boards[dev->boardnr].lnb.mask,
  498. dm1105_boards[dev->boardnr].lnb.v18);
  499. else if (voltage == SEC_VOLTAGE_13)
  500. dm1105_gpio_andor(dev,
  501. dm1105_boards[dev->boardnr].lnb.mask,
  502. dm1105_boards[dev->boardnr].lnb.v13);
  503. else
  504. dm1105_gpio_andor(dev,
  505. dm1105_boards[dev->boardnr].lnb.mask,
  506. dm1105_boards[dev->boardnr].lnb.off);
  507. return 0;
  508. }
  509. static void dm1105_set_dma_addr(struct dm1105_dev *dev)
  510. {
  511. dm_writel(DM1105_STADR, (__force u32)cpu_to_le32(dev->dma_addr));
  512. }
  513. static int dm1105_dma_map(struct dm1105_dev *dev)
  514. {
  515. dev->ts_buf = dma_alloc_coherent(&dev->pdev->dev,
  516. 6 * DM1105_DMA_BYTES, &dev->dma_addr,
  517. GFP_KERNEL);
  518. return !dev->ts_buf;
  519. }
  520. static void dm1105_dma_unmap(struct dm1105_dev *dev)
  521. {
  522. dma_free_coherent(&dev->pdev->dev, 6 * DM1105_DMA_BYTES, dev->ts_buf,
  523. dev->dma_addr);
  524. }
  525. static void dm1105_enable_irqs(struct dm1105_dev *dev)
  526. {
  527. dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);
  528. dm_writeb(DM1105_CR, 1);
  529. }
  530. static void dm1105_disable_irqs(struct dm1105_dev *dev)
  531. {
  532. dm_writeb(DM1105_INTMAK, INTMAK_IRM);
  533. dm_writeb(DM1105_CR, 0);
  534. }
  535. static int dm1105_start_feed(struct dvb_demux_feed *f)
  536. {
  537. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  538. if (dev->full_ts_users++ == 0)
  539. dm1105_enable_irqs(dev);
  540. return 0;
  541. }
  542. static int dm1105_stop_feed(struct dvb_demux_feed *f)
  543. {
  544. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  545. if (--dev->full_ts_users == 0)
  546. dm1105_disable_irqs(dev);
  547. return 0;
  548. }
  549. /* ir work handler */
  550. static void dm1105_emit_key(struct work_struct *work)
  551. {
  552. struct infrared *ir = container_of(work, struct infrared, work);
  553. u32 ircom = ir->ir_command;
  554. u8 data;
  555. if (ir_debug)
  556. printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom);
  557. data = (ircom >> 8) & 0x7f;
  558. /* FIXME: UNKNOWN because we don't generate a full NEC scancode (yet?) */
  559. rc_keydown(ir->dev, RC_PROTO_UNKNOWN, data, 0);
  560. }
  561. /* work handler */
  562. static void dm1105_dmx_buffer(struct work_struct *work)
  563. {
  564. struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work);
  565. unsigned int nbpackets;
  566. u32 oldwrp = dev->wrp;
  567. u32 nextwrp = dev->nextwrp;
  568. if (!((dev->ts_buf[oldwrp] == 0x47) &&
  569. (dev->ts_buf[oldwrp + 188] == 0x47) &&
  570. (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) {
  571. dev->PacketErrorCount++;
  572. /* bad packet found */
  573. if ((dev->PacketErrorCount >= 2) &&
  574. (dev->dmarst == 0)) {
  575. dm_writeb(DM1105_RST, 1);
  576. dev->wrp = 0;
  577. dev->PacketErrorCount = 0;
  578. dev->dmarst = 0;
  579. return;
  580. }
  581. }
  582. if (nextwrp < oldwrp) {
  583. memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp);
  584. nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188;
  585. } else
  586. nbpackets = (nextwrp - oldwrp) / 188;
  587. dev->wrp = nextwrp;
  588. dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets);
  589. }
  590. static irqreturn_t dm1105_irq(int irq, void *dev_id)
  591. {
  592. struct dm1105_dev *dev = dev_id;
  593. /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */
  594. unsigned int intsts = dm_readb(DM1105_INTSTS);
  595. dm_writeb(DM1105_INTSTS, intsts);
  596. switch (intsts) {
  597. case INTSTS_TSIRQ:
  598. case (INTSTS_TSIRQ | INTSTS_IR):
  599. dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR);
  600. queue_work(dev->wq, &dev->work);
  601. break;
  602. case INTSTS_IR:
  603. dev->ir.ir_command = dm_readl(DM1105_IRCODE);
  604. schedule_work(&dev->ir.work);
  605. break;
  606. }
  607. return IRQ_HANDLED;
  608. }
  609. static int dm1105_ir_init(struct dm1105_dev *dm1105)
  610. {
  611. struct rc_dev *dev;
  612. int err = -ENOMEM;
  613. dev = rc_allocate_device(RC_DRIVER_SCANCODE);
  614. if (!dev)
  615. return -ENOMEM;
  616. snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys),
  617. "pci-%s/ir0", pci_name(dm1105->pdev));
  618. dev->driver_name = MODULE_NAME;
  619. dev->map_name = RC_MAP_DM1105_NEC;
  620. dev->device_name = "DVB on-card IR receiver";
  621. dev->input_phys = dm1105->ir.input_phys;
  622. dev->input_id.bustype = BUS_PCI;
  623. dev->input_id.version = 1;
  624. if (dm1105->pdev->subsystem_vendor) {
  625. dev->input_id.vendor = dm1105->pdev->subsystem_vendor;
  626. dev->input_id.product = dm1105->pdev->subsystem_device;
  627. } else {
  628. dev->input_id.vendor = dm1105->pdev->vendor;
  629. dev->input_id.product = dm1105->pdev->device;
  630. }
  631. dev->dev.parent = &dm1105->pdev->dev;
  632. INIT_WORK(&dm1105->ir.work, dm1105_emit_key);
  633. err = rc_register_device(dev);
  634. if (err < 0) {
  635. rc_free_device(dev);
  636. return err;
  637. }
  638. dm1105->ir.dev = dev;
  639. return 0;
  640. }
  641. static void dm1105_ir_exit(struct dm1105_dev *dm1105)
  642. {
  643. rc_unregister_device(dm1105->ir.dev);
  644. }
  645. static int dm1105_hw_init(struct dm1105_dev *dev)
  646. {
  647. dm1105_disable_irqs(dev);
  648. dm_writeb(DM1105_HOST_CTR, 0);
  649. /*DATALEN 188,*/
  650. dm_writeb(DM1105_DTALENTH, 188);
  651. /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/
  652. dm_writew(DM1105_TSCTR, 0xc10a);
  653. /* map DMA and set address */
  654. dm1105_dma_map(dev);
  655. dm1105_set_dma_addr(dev);
  656. /* big buffer */
  657. dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES);
  658. dm_writeb(DM1105_INTCNT, 47);
  659. /* IR NEC mode enable */
  660. dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));
  661. dm_writeb(DM1105_IRMODE, 0);
  662. dm_writew(DM1105_SYSTEMCODE, 0);
  663. return 0;
  664. }
  665. static void dm1105_hw_exit(struct dm1105_dev *dev)
  666. {
  667. dm1105_disable_irqs(dev);
  668. /* IR disable */
  669. dm_writeb(DM1105_IRCTR, 0);
  670. dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);
  671. dm1105_dma_unmap(dev);
  672. }
  673. static const struct stv0299_config sharp_z0194a_config = {
  674. .demod_address = 0x68,
  675. .inittab = sharp_z0194a_inittab,
  676. .mclk = 88000000UL,
  677. .invert = 1,
  678. .skip_reinit = 0,
  679. .lock_output = STV0299_LOCKOUTPUT_1,
  680. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  681. .min_delay_ms = 100,
  682. .set_symbol_rate = sharp_z0194a_set_symbol_rate,
  683. };
  684. static struct stv0288_config earda_config = {
  685. .demod_address = 0x68,
  686. .min_delay_ms = 100,
  687. };
  688. static struct si21xx_config serit_config = {
  689. .demod_address = 0x68,
  690. .min_delay_ms = 100,
  691. };
  692. static struct cx24116_config serit_sp2633_config = {
  693. .demod_address = 0x55,
  694. };
  695. static struct ds3000_config dvbworld_ds3000_config = {
  696. .demod_address = 0x68,
  697. };
  698. static struct ts2020_config dvbworld_ts2020_config = {
  699. .tuner_address = 0x60,
  700. .clk_out_div = 1,
  701. };
  702. static int frontend_init(struct dm1105_dev *dev)
  703. {
  704. int ret;
  705. switch (dev->boardnr) {
  706. case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO:
  707. dm1105_gpio_enable(dev, GPIO15, 1);
  708. dm1105_gpio_clear(dev, GPIO15);
  709. msleep(100);
  710. dm1105_gpio_set(dev, GPIO15);
  711. msleep(200);
  712. dev->fe = dvb_attach(
  713. stv0299_attach, &sharp_z0194a_config,
  714. &dev->i2c_bb_adap);
  715. if (dev->fe) {
  716. dev->fe->ops.set_voltage = dm1105_set_voltage;
  717. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  718. &dev->i2c_bb_adap, DVB_PLL_OPERA1);
  719. break;
  720. }
  721. dev->fe = dvb_attach(
  722. stv0288_attach, &earda_config,
  723. &dev->i2c_bb_adap);
  724. if (dev->fe) {
  725. dev->fe->ops.set_voltage = dm1105_set_voltage;
  726. dvb_attach(stb6000_attach, dev->fe, 0x61,
  727. &dev->i2c_bb_adap);
  728. break;
  729. }
  730. dev->fe = dvb_attach(
  731. si21xx_attach, &serit_config,
  732. &dev->i2c_bb_adap);
  733. if (dev->fe)
  734. dev->fe->ops.set_voltage = dm1105_set_voltage;
  735. break;
  736. case DM1105_BOARD_DVBWORLD_2004:
  737. dev->fe = dvb_attach(
  738. cx24116_attach, &serit_sp2633_config,
  739. &dev->i2c_adap);
  740. if (dev->fe) {
  741. dev->fe->ops.set_voltage = dm1105_set_voltage;
  742. break;
  743. }
  744. dev->fe = dvb_attach(
  745. ds3000_attach, &dvbworld_ds3000_config,
  746. &dev->i2c_adap);
  747. if (dev->fe) {
  748. dvb_attach(ts2020_attach, dev->fe,
  749. &dvbworld_ts2020_config, &dev->i2c_adap);
  750. dev->fe->ops.set_voltage = dm1105_set_voltage;
  751. }
  752. break;
  753. case DM1105_BOARD_DVBWORLD_2002:
  754. case DM1105_BOARD_AXESS_DM05:
  755. default:
  756. dev->fe = dvb_attach(
  757. stv0299_attach, &sharp_z0194a_config,
  758. &dev->i2c_adap);
  759. if (dev->fe) {
  760. dev->fe->ops.set_voltage = dm1105_set_voltage;
  761. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  762. &dev->i2c_adap, DVB_PLL_OPERA1);
  763. break;
  764. }
  765. dev->fe = dvb_attach(
  766. stv0288_attach, &earda_config,
  767. &dev->i2c_adap);
  768. if (dev->fe) {
  769. dev->fe->ops.set_voltage = dm1105_set_voltage;
  770. dvb_attach(stb6000_attach, dev->fe, 0x61,
  771. &dev->i2c_adap);
  772. break;
  773. }
  774. dev->fe = dvb_attach(
  775. si21xx_attach, &serit_config,
  776. &dev->i2c_adap);
  777. if (dev->fe)
  778. dev->fe->ops.set_voltage = dm1105_set_voltage;
  779. }
  780. if (!dev->fe) {
  781. dev_err(&dev->pdev->dev, "could not attach frontend\n");
  782. return -ENODEV;
  783. }
  784. ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe);
  785. if (ret < 0) {
  786. if (dev->fe->ops.release)
  787. dev->fe->ops.release(dev->fe);
  788. dev->fe = NULL;
  789. return ret;
  790. }
  791. return 0;
  792. }
  793. static void dm1105_read_mac(struct dm1105_dev *dev, u8 *mac)
  794. {
  795. static u8 command[1] = { 0x28 };
  796. struct i2c_msg msg[] = {
  797. {
  798. .addr = IIC_24C01_addr >> 1,
  799. .flags = 0,
  800. .buf = command,
  801. .len = 1
  802. }, {
  803. .addr = IIC_24C01_addr >> 1,
  804. .flags = I2C_M_RD,
  805. .buf = mac,
  806. .len = 6
  807. },
  808. };
  809. dm1105_i2c_xfer(&dev->i2c_adap, msg , 2);
  810. dev_info(&dev->pdev->dev, "MAC %pM\n", mac);
  811. }
  812. static int dm1105_probe(struct pci_dev *pdev,
  813. const struct pci_device_id *ent)
  814. {
  815. struct dm1105_dev *dev;
  816. struct dvb_adapter *dvb_adapter;
  817. struct dvb_demux *dvbdemux;
  818. struct dmx_demux *dmx;
  819. int ret = -ENOMEM;
  820. int i;
  821. if (dm1105_devcount >= ARRAY_SIZE(card))
  822. return -ENODEV;
  823. dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL);
  824. if (!dev)
  825. return -ENOMEM;
  826. /* board config */
  827. dev->nr = dm1105_devcount;
  828. dev->boardnr = UNSET;
  829. if (card[dev->nr] < ARRAY_SIZE(dm1105_boards))
  830. dev->boardnr = card[dev->nr];
  831. for (i = 0; UNSET == dev->boardnr &&
  832. i < ARRAY_SIZE(dm1105_subids); i++)
  833. if (pdev->subsystem_vendor ==
  834. dm1105_subids[i].subvendor &&
  835. pdev->subsystem_device ==
  836. dm1105_subids[i].subdevice)
  837. dev->boardnr = dm1105_subids[i].card;
  838. if (UNSET == dev->boardnr) {
  839. dev->boardnr = DM1105_BOARD_UNKNOWN;
  840. dm1105_card_list(pdev);
  841. }
  842. dm1105_devcount++;
  843. dev->pdev = pdev;
  844. dev->buffer_size = 5 * DM1105_DMA_BYTES;
  845. dev->PacketErrorCount = 0;
  846. dev->dmarst = 0;
  847. ret = pci_enable_device(pdev);
  848. if (ret < 0)
  849. goto err_kfree;
  850. ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
  851. if (ret < 0)
  852. goto err_pci_disable_device;
  853. pci_set_master(pdev);
  854. ret = pci_request_regions(pdev, DRIVER_NAME);
  855. if (ret < 0)
  856. goto err_pci_disable_device;
  857. dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
  858. if (!dev->io_mem) {
  859. ret = -EIO;
  860. goto err_pci_release_regions;
  861. }
  862. spin_lock_init(&dev->lock);
  863. pci_set_drvdata(pdev, dev);
  864. ret = dm1105_hw_init(dev);
  865. if (ret < 0)
  866. goto err_pci_iounmap;
  867. /* i2c */
  868. i2c_set_adapdata(&dev->i2c_adap, dev);
  869. strscpy(dev->i2c_adap.name, DRIVER_NAME, sizeof(dev->i2c_adap.name));
  870. dev->i2c_adap.owner = THIS_MODULE;
  871. dev->i2c_adap.dev.parent = &pdev->dev;
  872. dev->i2c_adap.algo = &dm1105_algo;
  873. dev->i2c_adap.algo_data = dev;
  874. ret = i2c_add_adapter(&dev->i2c_adap);
  875. if (ret < 0)
  876. goto err_dm1105_hw_exit;
  877. i2c_set_adapdata(&dev->i2c_bb_adap, dev);
  878. strscpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME,
  879. sizeof(dev->i2c_bb_adap.name));
  880. dev->i2c_bb_adap.owner = THIS_MODULE;
  881. dev->i2c_bb_adap.dev.parent = &pdev->dev;
  882. dev->i2c_bb_adap.algo_data = &dev->i2c_bit;
  883. dev->i2c_bit.data = dev;
  884. dev->i2c_bit.setsda = dm1105_setsda;
  885. dev->i2c_bit.setscl = dm1105_setscl;
  886. dev->i2c_bit.getsda = dm1105_getsda;
  887. dev->i2c_bit.getscl = dm1105_getscl;
  888. dev->i2c_bit.udelay = 10;
  889. dev->i2c_bit.timeout = 10;
  890. /* Raise SCL and SDA */
  891. dm1105_setsda(dev, 1);
  892. dm1105_setscl(dev, 1);
  893. ret = i2c_bit_add_bus(&dev->i2c_bb_adap);
  894. if (ret < 0)
  895. goto err_i2c_del_adapter;
  896. /* dvb */
  897. ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME,
  898. THIS_MODULE, &pdev->dev, adapter_nr);
  899. if (ret < 0)
  900. goto err_i2c_del_adapters;
  901. dvb_adapter = &dev->dvb_adapter;
  902. dm1105_read_mac(dev, dvb_adapter->proposed_mac);
  903. dvbdemux = &dev->demux;
  904. dvbdemux->filternum = 256;
  905. dvbdemux->feednum = 256;
  906. dvbdemux->start_feed = dm1105_start_feed;
  907. dvbdemux->stop_feed = dm1105_stop_feed;
  908. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  909. DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
  910. ret = dvb_dmx_init(dvbdemux);
  911. if (ret < 0)
  912. goto err_dvb_unregister_adapter;
  913. dmx = &dvbdemux->dmx;
  914. dev->dmxdev.filternum = 256;
  915. dev->dmxdev.demux = dmx;
  916. dev->dmxdev.capabilities = 0;
  917. ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter);
  918. if (ret < 0)
  919. goto err_dvb_dmx_release;
  920. dev->hw_frontend.source = DMX_FRONTEND_0;
  921. ret = dmx->add_frontend(dmx, &dev->hw_frontend);
  922. if (ret < 0)
  923. goto err_dvb_dmxdev_release;
  924. dev->mem_frontend.source = DMX_MEMORY_FE;
  925. ret = dmx->add_frontend(dmx, &dev->mem_frontend);
  926. if (ret < 0)
  927. goto err_remove_hw_frontend;
  928. ret = dmx->connect_frontend(dmx, &dev->hw_frontend);
  929. if (ret < 0)
  930. goto err_remove_mem_frontend;
  931. ret = dvb_net_init(dvb_adapter, &dev->dvbnet, dmx);
  932. if (ret < 0)
  933. goto err_disconnect_frontend;
  934. ret = frontend_init(dev);
  935. if (ret < 0)
  936. goto err_dvb_net;
  937. dm1105_ir_init(dev);
  938. INIT_WORK(&dev->work, dm1105_dmx_buffer);
  939. sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num);
  940. dev->wq = create_singlethread_workqueue(dev->wqn);
  941. if (!dev->wq) {
  942. ret = -ENOMEM;
  943. goto err_dvb_net;
  944. }
  945. ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED,
  946. DRIVER_NAME, dev);
  947. if (ret < 0)
  948. goto err_workqueue;
  949. return 0;
  950. err_workqueue:
  951. destroy_workqueue(dev->wq);
  952. err_dvb_net:
  953. dvb_net_release(&dev->dvbnet);
  954. err_disconnect_frontend:
  955. dmx->disconnect_frontend(dmx);
  956. err_remove_mem_frontend:
  957. dmx->remove_frontend(dmx, &dev->mem_frontend);
  958. err_remove_hw_frontend:
  959. dmx->remove_frontend(dmx, &dev->hw_frontend);
  960. err_dvb_dmxdev_release:
  961. dvb_dmxdev_release(&dev->dmxdev);
  962. err_dvb_dmx_release:
  963. dvb_dmx_release(dvbdemux);
  964. err_dvb_unregister_adapter:
  965. dvb_unregister_adapter(dvb_adapter);
  966. err_i2c_del_adapters:
  967. i2c_del_adapter(&dev->i2c_bb_adap);
  968. err_i2c_del_adapter:
  969. i2c_del_adapter(&dev->i2c_adap);
  970. err_dm1105_hw_exit:
  971. dm1105_hw_exit(dev);
  972. err_pci_iounmap:
  973. pci_iounmap(pdev, dev->io_mem);
  974. err_pci_release_regions:
  975. pci_release_regions(pdev);
  976. err_pci_disable_device:
  977. pci_disable_device(pdev);
  978. err_kfree:
  979. kfree(dev);
  980. return ret;
  981. }
  982. static void dm1105_remove(struct pci_dev *pdev)
  983. {
  984. struct dm1105_dev *dev = pci_get_drvdata(pdev);
  985. struct dvb_adapter *dvb_adapter = &dev->dvb_adapter;
  986. struct dvb_demux *dvbdemux = &dev->demux;
  987. struct dmx_demux *dmx = &dvbdemux->dmx;
  988. cancel_work_sync(&dev->ir.work);
  989. dm1105_ir_exit(dev);
  990. dmx->close(dmx);
  991. dvb_net_release(&dev->dvbnet);
  992. if (dev->fe)
  993. dvb_unregister_frontend(dev->fe);
  994. dmx->disconnect_frontend(dmx);
  995. dmx->remove_frontend(dmx, &dev->mem_frontend);
  996. dmx->remove_frontend(dmx, &dev->hw_frontend);
  997. dvb_dmxdev_release(&dev->dmxdev);
  998. dvb_dmx_release(dvbdemux);
  999. dvb_unregister_adapter(dvb_adapter);
  1000. i2c_del_adapter(&dev->i2c_adap);
  1001. dm1105_hw_exit(dev);
  1002. free_irq(pdev->irq, dev);
  1003. pci_iounmap(pdev, dev->io_mem);
  1004. pci_release_regions(pdev);
  1005. pci_disable_device(pdev);
  1006. dm1105_devcount--;
  1007. kfree(dev);
  1008. }
  1009. static const struct pci_device_id dm1105_id_table[] = {
  1010. {
  1011. .vendor = PCI_VENDOR_ID_TRIGEM,
  1012. .device = PCI_DEVICE_ID_DM1105,
  1013. .subvendor = PCI_ANY_ID,
  1014. .subdevice = PCI_ANY_ID,
  1015. }, {
  1016. .vendor = PCI_VENDOR_ID_AXESS,
  1017. .device = PCI_DEVICE_ID_DM05,
  1018. .subvendor = PCI_ANY_ID,
  1019. .subdevice = PCI_ANY_ID,
  1020. }, {
  1021. /* empty */
  1022. },
  1023. };
  1024. MODULE_DEVICE_TABLE(pci, dm1105_id_table);
  1025. static struct pci_driver dm1105_driver = {
  1026. .name = DRIVER_NAME,
  1027. .id_table = dm1105_id_table,
  1028. .probe = dm1105_probe,
  1029. .remove = dm1105_remove,
  1030. };
  1031. module_pci_driver(dm1105_driver);
  1032. MODULE_AUTHOR("Igor M. Liplianin <[email protected]>");
  1033. MODULE_DESCRIPTION("SDMC DM1105 DVB driver");
  1034. MODULE_LICENSE("GPL");