cx18-av-audio.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * cx18 ADEC audio functions
  4. *
  5. * Derived from cx25840-audio.c
  6. *
  7. * Copyright (C) 2007 Hans Verkuil <[email protected]>
  8. * Copyright (C) 2008 Andy Walls <[email protected]>
  9. */
  10. #include "cx18-driver.h"
  11. static int set_audclk_freq(struct cx18 *cx, u32 freq)
  12. {
  13. struct cx18_av_state *state = &cx->av_state;
  14. if (freq != 32000 && freq != 44100 && freq != 48000)
  15. return -EINVAL;
  16. /*
  17. * The PLL parameters are based on the external crystal frequency that
  18. * would ideally be:
  19. *
  20. * NTSC Color subcarrier freq * 8 =
  21. * 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
  22. *
  23. * The accidents of history and rationale that explain from where this
  24. * combination of magic numbers originate can be found in:
  25. *
  26. * [1] Abrahams, I. C., "Choice of Chrominance Subcarrier Frequency in
  27. * the NTSC Standards", Proceedings of the I-R-E, January 1954, pp 79-80
  28. *
  29. * [2] Abrahams, I. C., "The 'Frequency Interleaving' Principle in the
  30. * NTSC Standards", Proceedings of the I-R-E, January 1954, pp 81-83
  31. *
  32. * As Mike Bradley has rightly pointed out, it's not the exact crystal
  33. * frequency that matters, only that all parts of the driver and
  34. * firmware are using the same value (close to the ideal value).
  35. *
  36. * Since I have a strong suspicion that, if the firmware ever assumes a
  37. * crystal value at all, it will assume 28.636360 MHz, the crystal
  38. * freq used in calculations in this driver will be:
  39. *
  40. * xtal_freq = 28.636360 MHz
  41. *
  42. * an error of less than 0.13 ppm which is way, way better than any off
  43. * the shelf crystal will have for accuracy anyway.
  44. *
  45. * Below I aim to run the PLLs' VCOs near 400 MHz to minimize error.
  46. *
  47. * Many thanks to Jeff Campbell and Mike Bradley for their extensive
  48. * investigation, experimentation, testing, and suggested solutions of
  49. * audio/video sync problems with SVideo and CVBS captures.
  50. */
  51. if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
  52. switch (freq) {
  53. case 32000:
  54. /*
  55. * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  56. * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
  57. */
  58. cx18_av_write4(cx, 0x108, 0x200d040f);
  59. /* VID_PLL Fraction = 0x2be2fe */
  60. /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  61. cx18_av_write4(cx, 0x10c, 0x002be2fe);
  62. /* AUX_PLL Fraction = 0x176740c */
  63. /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/
  64. cx18_av_write4(cx, 0x110, 0x0176740c);
  65. /* src3/4/6_ctl */
  66. /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */
  67. cx18_av_write4(cx, 0x900, 0x0801f77f);
  68. cx18_av_write4(cx, 0x904, 0x0801f77f);
  69. cx18_av_write4(cx, 0x90c, 0x0801f77f);
  70. /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
  71. cx18_av_write(cx, 0x127, 0x60);
  72. /* AUD_COUNT = 0x2fff = 8 samples * 4 * 384 - 1 */
  73. cx18_av_write4(cx, 0x12c, 0x11202fff);
  74. /*
  75. * EN_AV_LOCK = 0
  76. * VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
  77. * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
  78. */
  79. cx18_av_write4(cx, 0x128, 0xa00d2ef8);
  80. break;
  81. case 44100:
  82. /*
  83. * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  84. * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18
  85. */
  86. cx18_av_write4(cx, 0x108, 0x180e040f);
  87. /* VID_PLL Fraction = 0x2be2fe */
  88. /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  89. cx18_av_write4(cx, 0x10c, 0x002be2fe);
  90. /* AUX_PLL Fraction = 0x062a1f2 */
  91. /* xtal * 0xe.3150f90/0x18 = 44100 * 384: 406 MHz p-pd*/
  92. cx18_av_write4(cx, 0x110, 0x0062a1f2);
  93. /* src3/4/6_ctl */
  94. /* 0x1.6d59 = (4 * xtal/8*2/455) / 44100 */
  95. cx18_av_write4(cx, 0x900, 0x08016d59);
  96. cx18_av_write4(cx, 0x904, 0x08016d59);
  97. cx18_av_write4(cx, 0x90c, 0x08016d59);
  98. /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x18 */
  99. cx18_av_write(cx, 0x127, 0x58);
  100. /* AUD_COUNT = 0x92ff = 49 samples * 2 * 384 - 1 */
  101. cx18_av_write4(cx, 0x12c, 0x112092ff);
  102. /*
  103. * EN_AV_LOCK = 0
  104. * VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
  105. * ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
  106. */
  107. cx18_av_write4(cx, 0x128, 0xa01d4bf8);
  108. break;
  109. case 48000:
  110. /*
  111. * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  112. * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16
  113. */
  114. cx18_av_write4(cx, 0x108, 0x160e040f);
  115. /* VID_PLL Fraction = 0x2be2fe */
  116. /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  117. cx18_av_write4(cx, 0x10c, 0x002be2fe);
  118. /* AUX_PLL Fraction = 0x05227ad */
  119. /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz p-pd*/
  120. cx18_av_write4(cx, 0x110, 0x005227ad);
  121. /* src3/4/6_ctl */
  122. /* 0x1.4faa = (4 * xtal/8*2/455) / 48000 */
  123. cx18_av_write4(cx, 0x900, 0x08014faa);
  124. cx18_av_write4(cx, 0x904, 0x08014faa);
  125. cx18_av_write4(cx, 0x90c, 0x08014faa);
  126. /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */
  127. cx18_av_write(cx, 0x127, 0x56);
  128. /* AUD_COUNT = 0x5fff = 4 samples * 16 * 384 - 1 */
  129. cx18_av_write4(cx, 0x12c, 0x11205fff);
  130. /*
  131. * EN_AV_LOCK = 0
  132. * VID_COUNT = 0x1193f8 = 143999.000 * 8 =
  133. * ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
  134. */
  135. cx18_av_write4(cx, 0x128, 0xa01193f8);
  136. break;
  137. }
  138. } else {
  139. switch (freq) {
  140. case 32000:
  141. /*
  142. * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  143. * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30
  144. */
  145. cx18_av_write4(cx, 0x108, 0x300d040f);
  146. /* VID_PLL Fraction = 0x2be2fe */
  147. /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  148. cx18_av_write4(cx, 0x10c, 0x002be2fe);
  149. /* AUX_PLL Fraction = 0x176740c */
  150. /* xtal * 0xd.bb3a060/0x30 = 32000 * 256: 393 MHz p-pd*/
  151. cx18_av_write4(cx, 0x110, 0x0176740c);
  152. /* src1_ctl */
  153. /* 0x1.0000 = 32000/32000 */
  154. cx18_av_write4(cx, 0x8f8, 0x08010000);
  155. /* src3/4/6_ctl */
  156. /* 0x2.0000 = 2 * (32000/32000) */
  157. cx18_av_write4(cx, 0x900, 0x08020000);
  158. cx18_av_write4(cx, 0x904, 0x08020000);
  159. cx18_av_write4(cx, 0x90c, 0x08020000);
  160. /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x30 */
  161. cx18_av_write(cx, 0x127, 0x70);
  162. /* AUD_COUNT = 0x1fff = 8 samples * 4 * 256 - 1 */
  163. cx18_av_write4(cx, 0x12c, 0x11201fff);
  164. /*
  165. * EN_AV_LOCK = 0
  166. * VID_COUNT = 0x0d2ef8 = 107999.000 * 8 =
  167. * ((8 samples/32,000) * (13,500,000 * 8) * 4 - 1) * 8
  168. */
  169. cx18_av_write4(cx, 0x128, 0xa00d2ef8);
  170. break;
  171. case 44100:
  172. /*
  173. * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  174. * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24
  175. */
  176. cx18_av_write4(cx, 0x108, 0x240e040f);
  177. /* VID_PLL Fraction = 0x2be2fe */
  178. /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  179. cx18_av_write4(cx, 0x10c, 0x002be2fe);
  180. /* AUX_PLL Fraction = 0x062a1f2 */
  181. /* xtal * 0xe.3150f90/0x24 = 44100 * 256: 406 MHz p-pd*/
  182. cx18_av_write4(cx, 0x110, 0x0062a1f2);
  183. /* src1_ctl */
  184. /* 0x1.60cd = 44100/32000 */
  185. cx18_av_write4(cx, 0x8f8, 0x080160cd);
  186. /* src3/4/6_ctl */
  187. /* 0x1.7385 = 2 * (32000/44100) */
  188. cx18_av_write4(cx, 0x900, 0x08017385);
  189. cx18_av_write4(cx, 0x904, 0x08017385);
  190. cx18_av_write4(cx, 0x90c, 0x08017385);
  191. /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x24 */
  192. cx18_av_write(cx, 0x127, 0x64);
  193. /* AUD_COUNT = 0x61ff = 49 samples * 2 * 256 - 1 */
  194. cx18_av_write4(cx, 0x12c, 0x112061ff);
  195. /*
  196. * EN_AV_LOCK = 0
  197. * VID_COUNT = 0x1d4bf8 = 239999.000 * 8 =
  198. * ((49 samples/44,100) * (13,500,000 * 8) * 2 - 1) * 8
  199. */
  200. cx18_av_write4(cx, 0x128, 0xa01d4bf8);
  201. break;
  202. case 48000:
  203. /*
  204. * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
  205. * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20
  206. */
  207. cx18_av_write4(cx, 0x108, 0x200d040f);
  208. /* VID_PLL Fraction = 0x2be2fe */
  209. /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/
  210. cx18_av_write4(cx, 0x10c, 0x002be2fe);
  211. /* AUX_PLL Fraction = 0x176740c */
  212. /* xtal * 0xd.bb3a060/0x20 = 48000 * 256: 393 MHz p-pd*/
  213. cx18_av_write4(cx, 0x110, 0x0176740c);
  214. /* src1_ctl */
  215. /* 0x1.8000 = 48000/32000 */
  216. cx18_av_write4(cx, 0x8f8, 0x08018000);
  217. /* src3/4/6_ctl */
  218. /* 0x1.5555 = 2 * (32000/48000) */
  219. cx18_av_write4(cx, 0x900, 0x08015555);
  220. cx18_av_write4(cx, 0x904, 0x08015555);
  221. cx18_av_write4(cx, 0x90c, 0x08015555);
  222. /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x20 */
  223. cx18_av_write(cx, 0x127, 0x60);
  224. /* AUD_COUNT = 0x3fff = 4 samples * 16 * 256 - 1 */
  225. cx18_av_write4(cx, 0x12c, 0x11203fff);
  226. /*
  227. * EN_AV_LOCK = 0
  228. * VID_COUNT = 0x1193f8 = 143999.000 * 8 =
  229. * ((4 samples/48,000) * (13,500,000 * 8) * 16 - 1) * 8
  230. */
  231. cx18_av_write4(cx, 0x128, 0xa01193f8);
  232. break;
  233. }
  234. }
  235. state->audclk_freq = freq;
  236. return 0;
  237. }
  238. void cx18_av_audio_set_path(struct cx18 *cx)
  239. {
  240. struct cx18_av_state *state = &cx->av_state;
  241. u8 v;
  242. /* stop microcontroller */
  243. v = cx18_av_read(cx, 0x803) & ~0x10;
  244. cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
  245. /* assert soft reset */
  246. v = cx18_av_read(cx, 0x810) | 0x01;
  247. cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
  248. /* Mute everything to prevent the PFFT! */
  249. cx18_av_write(cx, 0x8d3, 0x1f);
  250. if (state->aud_input <= CX18_AV_AUDIO_SERIAL2) {
  251. /* Set Path1 to Serial Audio Input */
  252. cx18_av_write4(cx, 0x8d0, 0x01011012);
  253. /* The microcontroller should not be started for the
  254. * non-tuner inputs: autodetection is specific for
  255. * TV audio. */
  256. } else {
  257. /* Set Path1 to Analog Demod Main Channel */
  258. cx18_av_write4(cx, 0x8d0, 0x1f063870);
  259. }
  260. set_audclk_freq(cx, state->audclk_freq);
  261. /* deassert soft reset */
  262. v = cx18_av_read(cx, 0x810) & ~0x01;
  263. cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
  264. if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
  265. /* When the microcontroller detects the
  266. * audio format, it will unmute the lines */
  267. v = cx18_av_read(cx, 0x803) | 0x10;
  268. cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
  269. }
  270. }
  271. static void set_volume(struct cx18 *cx, int volume)
  272. {
  273. /* First convert the volume to msp3400 values (0-127) */
  274. int vol = volume >> 9;
  275. /* now scale it up to cx18_av values
  276. * -114dB to -96dB maps to 0
  277. * this should be 19, but in my testing that was 4dB too loud */
  278. if (vol <= 23)
  279. vol = 0;
  280. else
  281. vol -= 23;
  282. /* PATH1_VOLUME */
  283. cx18_av_write(cx, 0x8d4, 228 - (vol * 2));
  284. }
  285. static void set_bass(struct cx18 *cx, int bass)
  286. {
  287. /* PATH1_EQ_BASS_VOL */
  288. cx18_av_and_or(cx, 0x8d9, ~0x3f, 48 - (bass * 48 / 0xffff));
  289. }
  290. static void set_treble(struct cx18 *cx, int treble)
  291. {
  292. /* PATH1_EQ_TREBLE_VOL */
  293. cx18_av_and_or(cx, 0x8db, ~0x3f, 48 - (treble * 48 / 0xffff));
  294. }
  295. static void set_balance(struct cx18 *cx, int balance)
  296. {
  297. int bal = balance >> 8;
  298. if (bal > 0x80) {
  299. /* PATH1_BAL_LEFT */
  300. cx18_av_and_or(cx, 0x8d5, 0x7f, 0x80);
  301. /* PATH1_BAL_LEVEL */
  302. cx18_av_and_or(cx, 0x8d5, ~0x7f, bal & 0x7f);
  303. } else {
  304. /* PATH1_BAL_LEFT */
  305. cx18_av_and_or(cx, 0x8d5, 0x7f, 0x00);
  306. /* PATH1_BAL_LEVEL */
  307. cx18_av_and_or(cx, 0x8d5, ~0x7f, 0x80 - bal);
  308. }
  309. }
  310. static void set_mute(struct cx18 *cx, int mute)
  311. {
  312. struct cx18_av_state *state = &cx->av_state;
  313. u8 v;
  314. if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
  315. /* Must turn off microcontroller in order to mute sound.
  316. * Not sure if this is the best method, but it does work.
  317. * If the microcontroller is running, then it will undo any
  318. * changes to the mute register. */
  319. v = cx18_av_read(cx, 0x803);
  320. if (mute) {
  321. /* disable microcontroller */
  322. v &= ~0x10;
  323. cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
  324. cx18_av_write(cx, 0x8d3, 0x1f);
  325. } else {
  326. /* enable microcontroller */
  327. v |= 0x10;
  328. cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
  329. }
  330. } else {
  331. /* SRC1_MUTE_EN */
  332. cx18_av_and_or(cx, 0x8d3, ~0x2, mute ? 0x02 : 0x00);
  333. }
  334. }
  335. int cx18_av_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
  336. {
  337. struct cx18 *cx = v4l2_get_subdevdata(sd);
  338. struct cx18_av_state *state = &cx->av_state;
  339. int retval;
  340. u8 v;
  341. if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
  342. v = cx18_av_read(cx, 0x803) & ~0x10;
  343. cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
  344. cx18_av_write(cx, 0x8d3, 0x1f);
  345. }
  346. v = cx18_av_read(cx, 0x810) | 0x1;
  347. cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
  348. retval = set_audclk_freq(cx, freq);
  349. v = cx18_av_read(cx, 0x810) & ~0x1;
  350. cx18_av_write_expect(cx, 0x810, v, v, 0x0f);
  351. if (state->aud_input > CX18_AV_AUDIO_SERIAL2) {
  352. v = cx18_av_read(cx, 0x803) | 0x10;
  353. cx18_av_write_expect(cx, 0x803, v, v, 0x1f);
  354. }
  355. return retval;
  356. }
  357. static int cx18_av_audio_s_ctrl(struct v4l2_ctrl *ctrl)
  358. {
  359. struct v4l2_subdev *sd = to_sd(ctrl);
  360. struct cx18 *cx = v4l2_get_subdevdata(sd);
  361. switch (ctrl->id) {
  362. case V4L2_CID_AUDIO_VOLUME:
  363. set_volume(cx, ctrl->val);
  364. break;
  365. case V4L2_CID_AUDIO_BASS:
  366. set_bass(cx, ctrl->val);
  367. break;
  368. case V4L2_CID_AUDIO_TREBLE:
  369. set_treble(cx, ctrl->val);
  370. break;
  371. case V4L2_CID_AUDIO_BALANCE:
  372. set_balance(cx, ctrl->val);
  373. break;
  374. case V4L2_CID_AUDIO_MUTE:
  375. set_mute(cx, ctrl->val);
  376. break;
  377. default:
  378. return -EINVAL;
  379. }
  380. return 0;
  381. }
  382. const struct v4l2_ctrl_ops cx18_av_audio_ctrl_ops = {
  383. .s_ctrl = cx18_av_audio_s_ctrl,
  384. };