ov7670.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * A V4L2 driver for OmniVision OV7670 cameras.
  4. *
  5. * Copyright 2006 One Laptop Per Child Association, Inc. Written
  6. * by Jonathan Corbet with substantial inspiration from Mark
  7. * McClelland's ovcamchip code.
  8. *
  9. * Copyright 2006-7 Jonathan Corbet <[email protected]>
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/slab.h>
  15. #include <linux/i2c.h>
  16. #include <linux/delay.h>
  17. #include <linux/videodev2.h>
  18. #include <linux/gpio.h>
  19. #include <linux/gpio/consumer.h>
  20. #include <media/v4l2-device.h>
  21. #include <media/v4l2-event.h>
  22. #include <media/v4l2-ctrls.h>
  23. #include <media/v4l2-fwnode.h>
  24. #include <media/v4l2-mediabus.h>
  25. #include <media/v4l2-image-sizes.h>
  26. #include <media/i2c/ov7670.h>
  27. MODULE_AUTHOR("Jonathan Corbet <[email protected]>");
  28. MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
  29. MODULE_LICENSE("GPL");
  30. static bool debug;
  31. module_param(debug, bool, 0644);
  32. MODULE_PARM_DESC(debug, "Debug level (0-1)");
  33. /*
  34. * The 7670 sits on i2c with ID 0x42
  35. */
  36. #define OV7670_I2C_ADDR 0x42
  37. #define PLL_FACTOR 4
  38. /* Registers */
  39. #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
  40. #define REG_BLUE 0x01 /* blue gain */
  41. #define REG_RED 0x02 /* red gain */
  42. #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
  43. #define REG_COM1 0x04 /* Control 1 */
  44. #define COM1_CCIR656 0x40 /* CCIR656 enable */
  45. #define REG_BAVE 0x05 /* U/B Average level */
  46. #define REG_GbAVE 0x06 /* Y/Gb Average level */
  47. #define REG_AECHH 0x07 /* AEC MS 5 bits */
  48. #define REG_RAVE 0x08 /* V/R Average level */
  49. #define REG_COM2 0x09 /* Control 2 */
  50. #define COM2_SSLEEP 0x10 /* Soft sleep mode */
  51. #define REG_PID 0x0a /* Product ID MSB */
  52. #define REG_VER 0x0b /* Product ID LSB */
  53. #define REG_COM3 0x0c /* Control 3 */
  54. #define COM3_SWAP 0x40 /* Byte swap */
  55. #define COM3_SCALEEN 0x08 /* Enable scaling */
  56. #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
  57. #define REG_COM4 0x0d /* Control 4 */
  58. #define REG_COM5 0x0e /* All "reserved" */
  59. #define REG_COM6 0x0f /* Control 6 */
  60. #define REG_AECH 0x10 /* More bits of AEC value */
  61. #define REG_CLKRC 0x11 /* Clocl control */
  62. #define CLK_EXT 0x40 /* Use external clock directly */
  63. #define CLK_SCALE 0x3f /* Mask for internal clock scale */
  64. #define REG_COM7 0x12 /* Control 7 */
  65. #define COM7_RESET 0x80 /* Register reset */
  66. #define COM7_FMT_MASK 0x38
  67. #define COM7_FMT_VGA 0x00
  68. #define COM7_FMT_CIF 0x20 /* CIF format */
  69. #define COM7_FMT_QVGA 0x10 /* QVGA format */
  70. #define COM7_FMT_QCIF 0x08 /* QCIF format */
  71. #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
  72. #define COM7_YUV 0x00 /* YUV */
  73. #define COM7_BAYER 0x01 /* Bayer format */
  74. #define COM7_PBAYER 0x05 /* "Processed bayer" */
  75. #define REG_COM8 0x13 /* Control 8 */
  76. #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
  77. #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
  78. #define COM8_BFILT 0x20 /* Band filter enable */
  79. #define COM8_AGC 0x04 /* Auto gain enable */
  80. #define COM8_AWB 0x02 /* White balance enable */
  81. #define COM8_AEC 0x01 /* Auto exposure enable */
  82. #define REG_COM9 0x14 /* Control 9 - gain ceiling */
  83. #define REG_COM10 0x15 /* Control 10 */
  84. #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
  85. #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
  86. #define COM10_HREF_REV 0x08 /* Reverse HREF */
  87. #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
  88. #define COM10_VS_NEG 0x02 /* VSYNC negative */
  89. #define COM10_HS_NEG 0x01 /* HSYNC negative */
  90. #define REG_HSTART 0x17 /* Horiz start high bits */
  91. #define REG_HSTOP 0x18 /* Horiz stop high bits */
  92. #define REG_VSTART 0x19 /* Vert start high bits */
  93. #define REG_VSTOP 0x1a /* Vert stop high bits */
  94. #define REG_PSHFT 0x1b /* Pixel delay after HREF */
  95. #define REG_MIDH 0x1c /* Manuf. ID high */
  96. #define REG_MIDL 0x1d /* Manuf. ID low */
  97. #define REG_MVFP 0x1e /* Mirror / vflip */
  98. #define MVFP_MIRROR 0x20 /* Mirror image */
  99. #define MVFP_FLIP 0x10 /* Vertical flip */
  100. #define REG_AEW 0x24 /* AGC upper limit */
  101. #define REG_AEB 0x25 /* AGC lower limit */
  102. #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
  103. #define REG_HSYST 0x30 /* HSYNC rising edge delay */
  104. #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
  105. #define REG_HREF 0x32 /* HREF pieces */
  106. #define REG_TSLB 0x3a /* lots of stuff */
  107. #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
  108. #define REG_COM11 0x3b /* Control 11 */
  109. #define COM11_NIGHT 0x80 /* NIght mode enable */
  110. #define COM11_NMFR 0x60 /* Two bit NM frame rate */
  111. #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
  112. #define COM11_50HZ 0x08 /* Manual 50Hz select */
  113. #define COM11_EXP 0x02
  114. #define REG_COM12 0x3c /* Control 12 */
  115. #define COM12_HREF 0x80 /* HREF always */
  116. #define REG_COM13 0x3d /* Control 13 */
  117. #define COM13_GAMMA 0x80 /* Gamma enable */
  118. #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
  119. #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
  120. #define REG_COM14 0x3e /* Control 14 */
  121. #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
  122. #define REG_EDGE 0x3f /* Edge enhancement factor */
  123. #define REG_COM15 0x40 /* Control 15 */
  124. #define COM15_R10F0 0x00 /* Data range 10 to F0 */
  125. #define COM15_R01FE 0x80 /* 01 to FE */
  126. #define COM15_R00FF 0xc0 /* 00 to FF */
  127. #define COM15_RGB565 0x10 /* RGB565 output */
  128. #define COM15_RGB555 0x30 /* RGB555 output */
  129. #define REG_COM16 0x41 /* Control 16 */
  130. #define COM16_AWBGAIN 0x08 /* AWB gain enable */
  131. #define REG_COM17 0x42 /* Control 17 */
  132. #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
  133. #define COM17_CBAR 0x08 /* DSP Color bar */
  134. /*
  135. * This matrix defines how the colors are generated, must be
  136. * tweaked to adjust hue and saturation.
  137. *
  138. * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
  139. *
  140. * They are nine-bit signed quantities, with the sign bit
  141. * stored in 0x58. Sign for v-red is bit 0, and up from there.
  142. */
  143. #define REG_CMATRIX_BASE 0x4f
  144. #define CMATRIX_LEN 6
  145. #define REG_CMATRIX_SIGN 0x58
  146. #define REG_BRIGHT 0x55 /* Brightness */
  147. #define REG_CONTRAS 0x56 /* Contrast control */
  148. #define REG_GFIX 0x69 /* Fix gain control */
  149. #define REG_DBLV 0x6b /* PLL control an debugging */
  150. #define DBLV_BYPASS 0x0a /* Bypass PLL */
  151. #define DBLV_X4 0x4a /* clock x4 */
  152. #define DBLV_X6 0x8a /* clock x6 */
  153. #define DBLV_X8 0xca /* clock x8 */
  154. #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */
  155. #define TEST_PATTTERN_0 0x80
  156. #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */
  157. #define TEST_PATTTERN_1 0x80
  158. #define REG_REG76 0x76 /* OV's name */
  159. #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
  160. #define R76_WHTPCOR 0x40 /* White pixel correction enable */
  161. #define REG_RGB444 0x8c /* RGB 444 control */
  162. #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
  163. #define R444_RGBX 0x01 /* Empty nibble at end */
  164. #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
  165. #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
  166. #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
  167. #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
  168. #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
  169. #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
  170. #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
  171. #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
  172. #define REG_BD60MAX 0xab /* 60hz banding step limit */
  173. enum ov7670_model {
  174. MODEL_OV7670 = 0,
  175. MODEL_OV7675,
  176. };
  177. struct ov7670_win_size {
  178. int width;
  179. int height;
  180. unsigned char com7_bit;
  181. int hstart; /* Start/stop values for the camera. Note */
  182. int hstop; /* that they do not always make complete */
  183. int vstart; /* sense to humans, but evidently the sensor */
  184. int vstop; /* will do the right thing... */
  185. struct regval_list *regs; /* Regs to tweak */
  186. };
  187. struct ov7670_devtype {
  188. /* formats supported for each model */
  189. struct ov7670_win_size *win_sizes;
  190. unsigned int n_win_sizes;
  191. /* callbacks for frame rate control */
  192. int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
  193. void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
  194. };
  195. /*
  196. * Information we maintain about a known sensor.
  197. */
  198. struct ov7670_format_struct; /* coming later */
  199. struct ov7670_info {
  200. struct v4l2_subdev sd;
  201. #if defined(CONFIG_MEDIA_CONTROLLER)
  202. struct media_pad pad;
  203. #endif
  204. struct v4l2_ctrl_handler hdl;
  205. struct {
  206. /* gain cluster */
  207. struct v4l2_ctrl *auto_gain;
  208. struct v4l2_ctrl *gain;
  209. };
  210. struct {
  211. /* exposure cluster */
  212. struct v4l2_ctrl *auto_exposure;
  213. struct v4l2_ctrl *exposure;
  214. };
  215. struct {
  216. /* saturation/hue cluster */
  217. struct v4l2_ctrl *saturation;
  218. struct v4l2_ctrl *hue;
  219. };
  220. struct v4l2_mbus_framefmt format;
  221. struct ov7670_format_struct *fmt; /* Current format */
  222. struct ov7670_win_size *wsize;
  223. struct clk *clk;
  224. int on;
  225. struct gpio_desc *resetb_gpio;
  226. struct gpio_desc *pwdn_gpio;
  227. unsigned int mbus_config; /* Media bus configuration flags */
  228. int min_width; /* Filter out smaller sizes */
  229. int min_height; /* Filter out smaller sizes */
  230. int clock_speed; /* External clock speed (MHz) */
  231. u8 clkrc; /* Clock divider value */
  232. bool use_smbus; /* Use smbus I/O instead of I2C */
  233. bool pll_bypass;
  234. bool pclk_hb_disable;
  235. const struct ov7670_devtype *devtype; /* Device specifics */
  236. };
  237. static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
  238. {
  239. return container_of(sd, struct ov7670_info, sd);
  240. }
  241. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  242. {
  243. return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
  244. }
  245. /*
  246. * The default register settings, as obtained from OmniVision. There
  247. * is really no making sense of most of these - lots of "reserved" values
  248. * and such.
  249. *
  250. * These settings give VGA YUYV.
  251. */
  252. struct regval_list {
  253. unsigned char reg_num;
  254. unsigned char value;
  255. };
  256. static struct regval_list ov7670_default_regs[] = {
  257. { REG_COM7, COM7_RESET },
  258. /*
  259. * Clock scale: 3 = 15fps
  260. * 2 = 20fps
  261. * 1 = 30fps
  262. */
  263. { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
  264. { REG_TSLB, 0x04 }, /* OV */
  265. { REG_COM7, 0 }, /* VGA */
  266. /*
  267. * Set the hardware window. These values from OV don't entirely
  268. * make sense - hstop is less than hstart. But they work...
  269. */
  270. { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
  271. { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
  272. { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
  273. { REG_COM3, 0 }, { REG_COM14, 0 },
  274. /* Mystery scaling numbers */
  275. { REG_SCALING_XSC, 0x3a },
  276. { REG_SCALING_YSC, 0x35 },
  277. { 0x72, 0x11 }, { 0x73, 0xf0 },
  278. { 0xa2, 0x02 }, { REG_COM10, 0x0 },
  279. /* Gamma curve values */
  280. { 0x7a, 0x20 }, { 0x7b, 0x10 },
  281. { 0x7c, 0x1e }, { 0x7d, 0x35 },
  282. { 0x7e, 0x5a }, { 0x7f, 0x69 },
  283. { 0x80, 0x76 }, { 0x81, 0x80 },
  284. { 0x82, 0x88 }, { 0x83, 0x8f },
  285. { 0x84, 0x96 }, { 0x85, 0xa3 },
  286. { 0x86, 0xaf }, { 0x87, 0xc4 },
  287. { 0x88, 0xd7 }, { 0x89, 0xe8 },
  288. /* AGC and AEC parameters. Note we start by disabling those features,
  289. then turn them only after tweaking the values. */
  290. { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
  291. { REG_GAIN, 0 }, { REG_AECH, 0 },
  292. { REG_COM4, 0x40 }, /* magic reserved bit */
  293. { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
  294. { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
  295. { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
  296. { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
  297. { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
  298. { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
  299. { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
  300. { REG_HAECC7, 0x94 },
  301. { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
  302. /* Almost all of these are magic "reserved" values. */
  303. { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
  304. { 0x16, 0x02 }, { REG_MVFP, 0x07 },
  305. { 0x21, 0x02 }, { 0x22, 0x91 },
  306. { 0x29, 0x07 }, { 0x33, 0x0b },
  307. { 0x35, 0x0b }, { 0x37, 0x1d },
  308. { 0x38, 0x71 }, { 0x39, 0x2a },
  309. { REG_COM12, 0x78 }, { 0x4d, 0x40 },
  310. { 0x4e, 0x20 }, { REG_GFIX, 0 },
  311. { 0x6b, 0x4a }, { 0x74, 0x10 },
  312. { 0x8d, 0x4f }, { 0x8e, 0 },
  313. { 0x8f, 0 }, { 0x90, 0 },
  314. { 0x91, 0 }, { 0x96, 0 },
  315. { 0x9a, 0 }, { 0xb0, 0x84 },
  316. { 0xb1, 0x0c }, { 0xb2, 0x0e },
  317. { 0xb3, 0x82 }, { 0xb8, 0x0a },
  318. /* More reserved magic, some of which tweaks white balance */
  319. { 0x43, 0x0a }, { 0x44, 0xf0 },
  320. { 0x45, 0x34 }, { 0x46, 0x58 },
  321. { 0x47, 0x28 }, { 0x48, 0x3a },
  322. { 0x59, 0x88 }, { 0x5a, 0x88 },
  323. { 0x5b, 0x44 }, { 0x5c, 0x67 },
  324. { 0x5d, 0x49 }, { 0x5e, 0x0e },
  325. { 0x6c, 0x0a }, { 0x6d, 0x55 },
  326. { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
  327. { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
  328. { REG_RED, 0x60 },
  329. { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
  330. /* Matrix coefficients */
  331. { 0x4f, 0x80 }, { 0x50, 0x80 },
  332. { 0x51, 0 }, { 0x52, 0x22 },
  333. { 0x53, 0x5e }, { 0x54, 0x80 },
  334. { 0x58, 0x9e },
  335. { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
  336. { 0x75, 0x05 }, { 0x76, 0xe1 },
  337. { 0x4c, 0 }, { 0x77, 0x01 },
  338. { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
  339. { 0xc9, 0x60 }, { REG_COM16, 0x38 },
  340. { 0x56, 0x40 },
  341. { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
  342. { 0xa4, 0x88 }, { 0x96, 0 },
  343. { 0x97, 0x30 }, { 0x98, 0x20 },
  344. { 0x99, 0x30 }, { 0x9a, 0x84 },
  345. { 0x9b, 0x29 }, { 0x9c, 0x03 },
  346. { 0x9d, 0x4c }, { 0x9e, 0x3f },
  347. { 0x78, 0x04 },
  348. /* Extra-weird stuff. Some sort of multiplexor register */
  349. { 0x79, 0x01 }, { 0xc8, 0xf0 },
  350. { 0x79, 0x0f }, { 0xc8, 0x00 },
  351. { 0x79, 0x10 }, { 0xc8, 0x7e },
  352. { 0x79, 0x0a }, { 0xc8, 0x80 },
  353. { 0x79, 0x0b }, { 0xc8, 0x01 },
  354. { 0x79, 0x0c }, { 0xc8, 0x0f },
  355. { 0x79, 0x0d }, { 0xc8, 0x20 },
  356. { 0x79, 0x09 }, { 0xc8, 0x80 },
  357. { 0x79, 0x02 }, { 0xc8, 0xc0 },
  358. { 0x79, 0x03 }, { 0xc8, 0x40 },
  359. { 0x79, 0x05 }, { 0xc8, 0x30 },
  360. { 0x79, 0x26 },
  361. { 0xff, 0xff }, /* END MARKER */
  362. };
  363. /*
  364. * Here we'll try to encapsulate the changes for just the output
  365. * video format.
  366. *
  367. * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
  368. *
  369. * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
  370. */
  371. static struct regval_list ov7670_fmt_yuv422[] = {
  372. { REG_COM7, 0x0 }, /* Selects YUV mode */
  373. { REG_RGB444, 0 }, /* No RGB444 please */
  374. { REG_COM1, 0 }, /* CCIR601 */
  375. { REG_COM15, COM15_R00FF },
  376. { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
  377. { 0x4f, 0x80 }, /* "matrix coefficient 1" */
  378. { 0x50, 0x80 }, /* "matrix coefficient 2" */
  379. { 0x51, 0 }, /* vb */
  380. { 0x52, 0x22 }, /* "matrix coefficient 4" */
  381. { 0x53, 0x5e }, /* "matrix coefficient 5" */
  382. { 0x54, 0x80 }, /* "matrix coefficient 6" */
  383. { REG_COM13, COM13_GAMMA|COM13_UVSAT },
  384. { 0xff, 0xff },
  385. };
  386. static struct regval_list ov7670_fmt_rgb565[] = {
  387. { REG_COM7, COM7_RGB }, /* Selects RGB mode */
  388. { REG_RGB444, 0 }, /* No RGB444 please */
  389. { REG_COM1, 0x0 }, /* CCIR601 */
  390. { REG_COM15, COM15_RGB565 },
  391. { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
  392. { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
  393. { 0x50, 0xb3 }, /* "matrix coefficient 2" */
  394. { 0x51, 0 }, /* vb */
  395. { 0x52, 0x3d }, /* "matrix coefficient 4" */
  396. { 0x53, 0xa7 }, /* "matrix coefficient 5" */
  397. { 0x54, 0xe4 }, /* "matrix coefficient 6" */
  398. { REG_COM13, COM13_GAMMA|COM13_UVSAT },
  399. { 0xff, 0xff },
  400. };
  401. static struct regval_list ov7670_fmt_rgb444[] = {
  402. { REG_COM7, COM7_RGB }, /* Selects RGB mode */
  403. { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
  404. { REG_COM1, 0x0 }, /* CCIR601 */
  405. { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
  406. { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
  407. { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
  408. { 0x50, 0xb3 }, /* "matrix coefficient 2" */
  409. { 0x51, 0 }, /* vb */
  410. { 0x52, 0x3d }, /* "matrix coefficient 4" */
  411. { 0x53, 0xa7 }, /* "matrix coefficient 5" */
  412. { 0x54, 0xe4 }, /* "matrix coefficient 6" */
  413. { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
  414. { 0xff, 0xff },
  415. };
  416. static struct regval_list ov7670_fmt_raw[] = {
  417. { REG_COM7, COM7_BAYER },
  418. { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
  419. { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
  420. { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
  421. { 0xff, 0xff },
  422. };
  423. /*
  424. * Low-level register I/O.
  425. *
  426. * Note that there are two versions of these. On the XO 1, the
  427. * i2c controller only does SMBUS, so that's what we use. The
  428. * ov7670 is not really an SMBUS device, though, so the communication
  429. * is not always entirely reliable.
  430. */
  431. static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
  432. unsigned char *value)
  433. {
  434. struct i2c_client *client = v4l2_get_subdevdata(sd);
  435. int ret;
  436. ret = i2c_smbus_read_byte_data(client, reg);
  437. if (ret >= 0) {
  438. *value = (unsigned char)ret;
  439. ret = 0;
  440. }
  441. return ret;
  442. }
  443. static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
  444. unsigned char value)
  445. {
  446. struct i2c_client *client = v4l2_get_subdevdata(sd);
  447. int ret = i2c_smbus_write_byte_data(client, reg, value);
  448. if (reg == REG_COM7 && (value & COM7_RESET))
  449. msleep(5); /* Wait for reset to run */
  450. return ret;
  451. }
  452. /*
  453. * On most platforms, we'd rather do straight i2c I/O.
  454. */
  455. static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
  456. unsigned char *value)
  457. {
  458. struct i2c_client *client = v4l2_get_subdevdata(sd);
  459. u8 data = reg;
  460. struct i2c_msg msg;
  461. int ret;
  462. /*
  463. * Send out the register address...
  464. */
  465. msg.addr = client->addr;
  466. msg.flags = 0;
  467. msg.len = 1;
  468. msg.buf = &data;
  469. ret = i2c_transfer(client->adapter, &msg, 1);
  470. if (ret < 0) {
  471. printk(KERN_ERR "Error %d on register write\n", ret);
  472. return ret;
  473. }
  474. /*
  475. * ...then read back the result.
  476. */
  477. msg.flags = I2C_M_RD;
  478. ret = i2c_transfer(client->adapter, &msg, 1);
  479. if (ret >= 0) {
  480. *value = data;
  481. ret = 0;
  482. }
  483. return ret;
  484. }
  485. static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
  486. unsigned char value)
  487. {
  488. struct i2c_client *client = v4l2_get_subdevdata(sd);
  489. struct i2c_msg msg;
  490. unsigned char data[2] = { reg, value };
  491. int ret;
  492. msg.addr = client->addr;
  493. msg.flags = 0;
  494. msg.len = 2;
  495. msg.buf = data;
  496. ret = i2c_transfer(client->adapter, &msg, 1);
  497. if (ret > 0)
  498. ret = 0;
  499. if (reg == REG_COM7 && (value & COM7_RESET))
  500. msleep(5); /* Wait for reset to run */
  501. return ret;
  502. }
  503. static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
  504. unsigned char *value)
  505. {
  506. struct ov7670_info *info = to_state(sd);
  507. if (info->use_smbus)
  508. return ov7670_read_smbus(sd, reg, value);
  509. else
  510. return ov7670_read_i2c(sd, reg, value);
  511. }
  512. static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
  513. unsigned char value)
  514. {
  515. struct ov7670_info *info = to_state(sd);
  516. if (info->use_smbus)
  517. return ov7670_write_smbus(sd, reg, value);
  518. else
  519. return ov7670_write_i2c(sd, reg, value);
  520. }
  521. static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
  522. unsigned char mask, unsigned char value)
  523. {
  524. unsigned char orig;
  525. int ret;
  526. ret = ov7670_read(sd, reg, &orig);
  527. if (ret)
  528. return ret;
  529. return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
  530. }
  531. /*
  532. * Write a list of register settings; ff/ff stops the process.
  533. */
  534. static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
  535. {
  536. while (vals->reg_num != 0xff || vals->value != 0xff) {
  537. int ret = ov7670_write(sd, vals->reg_num, vals->value);
  538. if (ret < 0)
  539. return ret;
  540. vals++;
  541. }
  542. return 0;
  543. }
  544. /*
  545. * Stuff that knows about the sensor.
  546. */
  547. static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
  548. {
  549. ov7670_write(sd, REG_COM7, COM7_RESET);
  550. msleep(1);
  551. return 0;
  552. }
  553. static int ov7670_init(struct v4l2_subdev *sd, u32 val)
  554. {
  555. return ov7670_write_array(sd, ov7670_default_regs);
  556. }
  557. static int ov7670_detect(struct v4l2_subdev *sd)
  558. {
  559. unsigned char v;
  560. int ret;
  561. ret = ov7670_init(sd, 0);
  562. if (ret < 0)
  563. return ret;
  564. ret = ov7670_read(sd, REG_MIDH, &v);
  565. if (ret < 0)
  566. return ret;
  567. if (v != 0x7f) /* OV manuf. id. */
  568. return -ENODEV;
  569. ret = ov7670_read(sd, REG_MIDL, &v);
  570. if (ret < 0)
  571. return ret;
  572. if (v != 0xa2)
  573. return -ENODEV;
  574. /*
  575. * OK, we know we have an OmniVision chip...but which one?
  576. */
  577. ret = ov7670_read(sd, REG_PID, &v);
  578. if (ret < 0)
  579. return ret;
  580. if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
  581. return -ENODEV;
  582. ret = ov7670_read(sd, REG_VER, &v);
  583. if (ret < 0)
  584. return ret;
  585. if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
  586. return -ENODEV;
  587. return 0;
  588. }
  589. /*
  590. * Store information about the video data format. The color matrix
  591. * is deeply tied into the format, so keep the relevant values here.
  592. * The magic matrix numbers come from OmniVision.
  593. */
  594. static struct ov7670_format_struct {
  595. u32 mbus_code;
  596. enum v4l2_colorspace colorspace;
  597. struct regval_list *regs;
  598. int cmatrix[CMATRIX_LEN];
  599. } ov7670_formats[] = {
  600. {
  601. .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
  602. .colorspace = V4L2_COLORSPACE_SRGB,
  603. .regs = ov7670_fmt_yuv422,
  604. .cmatrix = { 128, -128, 0, -34, -94, 128 },
  605. },
  606. {
  607. .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
  608. .colorspace = V4L2_COLORSPACE_SRGB,
  609. .regs = ov7670_fmt_rgb444,
  610. .cmatrix = { 179, -179, 0, -61, -176, 228 },
  611. },
  612. {
  613. .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
  614. .colorspace = V4L2_COLORSPACE_SRGB,
  615. .regs = ov7670_fmt_rgb565,
  616. .cmatrix = { 179, -179, 0, -61, -176, 228 },
  617. },
  618. {
  619. .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
  620. .colorspace = V4L2_COLORSPACE_SRGB,
  621. .regs = ov7670_fmt_raw,
  622. .cmatrix = { 0, 0, 0, 0, 0, 0 },
  623. },
  624. };
  625. #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
  626. /*
  627. * Then there is the issue of window sizes. Try to capture the info here.
  628. */
  629. /*
  630. * QCIF mode is done (by OV) in a very strange way - it actually looks like
  631. * VGA with weird scaling options - they do *not* use the canned QCIF mode
  632. * which is allegedly provided by the sensor. So here's the weird register
  633. * settings.
  634. */
  635. static struct regval_list ov7670_qcif_regs[] = {
  636. { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
  637. { REG_COM3, COM3_DCWEN },
  638. { REG_COM14, COM14_DCWEN | 0x01},
  639. { 0x73, 0xf1 },
  640. { 0xa2, 0x52 },
  641. { 0x7b, 0x1c },
  642. { 0x7c, 0x28 },
  643. { 0x7d, 0x3c },
  644. { 0x7f, 0x69 },
  645. { REG_COM9, 0x38 },
  646. { 0xa1, 0x0b },
  647. { 0x74, 0x19 },
  648. { 0x9a, 0x80 },
  649. { 0x43, 0x14 },
  650. { REG_COM13, 0xc0 },
  651. { 0xff, 0xff },
  652. };
  653. static struct ov7670_win_size ov7670_win_sizes[] = {
  654. /* VGA */
  655. {
  656. .width = VGA_WIDTH,
  657. .height = VGA_HEIGHT,
  658. .com7_bit = COM7_FMT_VGA,
  659. .hstart = 158, /* These values from */
  660. .hstop = 14, /* Omnivision */
  661. .vstart = 10,
  662. .vstop = 490,
  663. .regs = NULL,
  664. },
  665. /* CIF */
  666. {
  667. .width = CIF_WIDTH,
  668. .height = CIF_HEIGHT,
  669. .com7_bit = COM7_FMT_CIF,
  670. .hstart = 170, /* Empirically determined */
  671. .hstop = 90,
  672. .vstart = 14,
  673. .vstop = 494,
  674. .regs = NULL,
  675. },
  676. /* QVGA */
  677. {
  678. .width = QVGA_WIDTH,
  679. .height = QVGA_HEIGHT,
  680. .com7_bit = COM7_FMT_QVGA,
  681. .hstart = 168, /* Empirically determined */
  682. .hstop = 24,
  683. .vstart = 12,
  684. .vstop = 492,
  685. .regs = NULL,
  686. },
  687. /* QCIF */
  688. {
  689. .width = QCIF_WIDTH,
  690. .height = QCIF_HEIGHT,
  691. .com7_bit = COM7_FMT_VGA, /* see comment above */
  692. .hstart = 456, /* Empirically determined */
  693. .hstop = 24,
  694. .vstart = 14,
  695. .vstop = 494,
  696. .regs = ov7670_qcif_regs,
  697. }
  698. };
  699. static struct ov7670_win_size ov7675_win_sizes[] = {
  700. /*
  701. * Currently, only VGA is supported. Theoretically it could be possible
  702. * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
  703. * base and tweak them empirically could be required.
  704. */
  705. {
  706. .width = VGA_WIDTH,
  707. .height = VGA_HEIGHT,
  708. .com7_bit = COM7_FMT_VGA,
  709. .hstart = 158, /* These values from */
  710. .hstop = 14, /* Omnivision */
  711. .vstart = 14, /* Empirically determined */
  712. .vstop = 494,
  713. .regs = NULL,
  714. }
  715. };
  716. static void ov7675_get_framerate(struct v4l2_subdev *sd,
  717. struct v4l2_fract *tpf)
  718. {
  719. struct ov7670_info *info = to_state(sd);
  720. u32 clkrc = info->clkrc;
  721. int pll_factor;
  722. if (info->pll_bypass)
  723. pll_factor = 1;
  724. else
  725. pll_factor = PLL_FACTOR;
  726. clkrc++;
  727. if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
  728. clkrc = (clkrc >> 1);
  729. tpf->numerator = 1;
  730. tpf->denominator = (5 * pll_factor * info->clock_speed) /
  731. (4 * clkrc);
  732. }
  733. static int ov7675_apply_framerate(struct v4l2_subdev *sd)
  734. {
  735. struct ov7670_info *info = to_state(sd);
  736. int ret;
  737. ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
  738. if (ret < 0)
  739. return ret;
  740. return ov7670_write(sd, REG_DBLV,
  741. info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
  742. }
  743. static int ov7675_set_framerate(struct v4l2_subdev *sd,
  744. struct v4l2_fract *tpf)
  745. {
  746. struct ov7670_info *info = to_state(sd);
  747. u32 clkrc;
  748. int pll_factor;
  749. /*
  750. * The formula is fps = 5/4*pixclk for YUV/RGB and
  751. * fps = 5/2*pixclk for RAW.
  752. *
  753. * pixclk = clock_speed / (clkrc + 1) * PLLfactor
  754. *
  755. */
  756. if (tpf->numerator == 0 || tpf->denominator == 0) {
  757. clkrc = 0;
  758. } else {
  759. pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
  760. clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
  761. (4 * tpf->denominator);
  762. if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
  763. clkrc = (clkrc << 1);
  764. clkrc--;
  765. }
  766. /*
  767. * The datasheet claims that clkrc = 0 will divide the input clock by 1
  768. * but we've checked with an oscilloscope that it divides by 2 instead.
  769. * So, if clkrc = 0 just bypass the divider.
  770. */
  771. if (clkrc <= 0)
  772. clkrc = CLK_EXT;
  773. else if (clkrc > CLK_SCALE)
  774. clkrc = CLK_SCALE;
  775. info->clkrc = clkrc;
  776. /* Recalculate frame rate */
  777. ov7675_get_framerate(sd, tpf);
  778. /*
  779. * If the device is not powered up by the host driver do
  780. * not apply any changes to H/W at this time. Instead
  781. * the framerate will be restored right after power-up.
  782. */
  783. if (info->on)
  784. return ov7675_apply_framerate(sd);
  785. return 0;
  786. }
  787. static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
  788. struct v4l2_fract *tpf)
  789. {
  790. struct ov7670_info *info = to_state(sd);
  791. tpf->numerator = 1;
  792. tpf->denominator = info->clock_speed;
  793. if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
  794. tpf->denominator /= (info->clkrc & CLK_SCALE);
  795. }
  796. static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
  797. struct v4l2_fract *tpf)
  798. {
  799. struct ov7670_info *info = to_state(sd);
  800. int div;
  801. if (tpf->numerator == 0 || tpf->denominator == 0)
  802. div = 1; /* Reset to full rate */
  803. else
  804. div = (tpf->numerator * info->clock_speed) / tpf->denominator;
  805. if (div == 0)
  806. div = 1;
  807. else if (div > CLK_SCALE)
  808. div = CLK_SCALE;
  809. info->clkrc = (info->clkrc & 0x80) | div;
  810. tpf->numerator = 1;
  811. tpf->denominator = info->clock_speed / div;
  812. /*
  813. * If the device is not powered up by the host driver do
  814. * not apply any changes to H/W at this time. Instead
  815. * the framerate will be restored right after power-up.
  816. */
  817. if (info->on)
  818. return ov7670_write(sd, REG_CLKRC, info->clkrc);
  819. return 0;
  820. }
  821. /*
  822. * Store a set of start/stop values into the camera.
  823. */
  824. static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
  825. int vstart, int vstop)
  826. {
  827. int ret;
  828. unsigned char v;
  829. /*
  830. * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
  831. * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
  832. * a mystery "edge offset" value in the top two bits of href.
  833. */
  834. ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
  835. if (ret)
  836. return ret;
  837. ret = ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
  838. if (ret)
  839. return ret;
  840. ret = ov7670_read(sd, REG_HREF, &v);
  841. if (ret)
  842. return ret;
  843. v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
  844. msleep(10);
  845. ret = ov7670_write(sd, REG_HREF, v);
  846. if (ret)
  847. return ret;
  848. /* Vertical: similar arrangement, but only 10 bits. */
  849. ret = ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
  850. if (ret)
  851. return ret;
  852. ret = ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
  853. if (ret)
  854. return ret;
  855. ret = ov7670_read(sd, REG_VREF, &v);
  856. if (ret)
  857. return ret;
  858. v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
  859. msleep(10);
  860. return ov7670_write(sd, REG_VREF, v);
  861. }
  862. static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
  863. struct v4l2_subdev_state *sd_state,
  864. struct v4l2_subdev_mbus_code_enum *code)
  865. {
  866. if (code->pad || code->index >= N_OV7670_FMTS)
  867. return -EINVAL;
  868. code->code = ov7670_formats[code->index].mbus_code;
  869. return 0;
  870. }
  871. static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
  872. struct v4l2_mbus_framefmt *fmt,
  873. struct ov7670_format_struct **ret_fmt,
  874. struct ov7670_win_size **ret_wsize)
  875. {
  876. int index, i;
  877. struct ov7670_win_size *wsize;
  878. struct ov7670_info *info = to_state(sd);
  879. unsigned int n_win_sizes = info->devtype->n_win_sizes;
  880. unsigned int win_sizes_limit = n_win_sizes;
  881. for (index = 0; index < N_OV7670_FMTS; index++)
  882. if (ov7670_formats[index].mbus_code == fmt->code)
  883. break;
  884. if (index >= N_OV7670_FMTS) {
  885. /* default to first format */
  886. index = 0;
  887. fmt->code = ov7670_formats[0].mbus_code;
  888. }
  889. if (ret_fmt != NULL)
  890. *ret_fmt = ov7670_formats + index;
  891. /*
  892. * Fields: the OV devices claim to be progressive.
  893. */
  894. fmt->field = V4L2_FIELD_NONE;
  895. /*
  896. * Don't consider values that don't match min_height and min_width
  897. * constraints.
  898. */
  899. if (info->min_width || info->min_height)
  900. for (i = 0; i < n_win_sizes; i++) {
  901. wsize = info->devtype->win_sizes + i;
  902. if (wsize->width < info->min_width ||
  903. wsize->height < info->min_height) {
  904. win_sizes_limit = i;
  905. break;
  906. }
  907. }
  908. /*
  909. * Round requested image size down to the nearest
  910. * we support, but not below the smallest.
  911. */
  912. for (wsize = info->devtype->win_sizes;
  913. wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
  914. if (fmt->width >= wsize->width && fmt->height >= wsize->height)
  915. break;
  916. if (wsize >= info->devtype->win_sizes + win_sizes_limit)
  917. wsize--; /* Take the smallest one */
  918. if (ret_wsize != NULL)
  919. *ret_wsize = wsize;
  920. /*
  921. * Note the size we'll actually handle.
  922. */
  923. fmt->width = wsize->width;
  924. fmt->height = wsize->height;
  925. fmt->colorspace = ov7670_formats[index].colorspace;
  926. info->format = *fmt;
  927. return 0;
  928. }
  929. static int ov7670_apply_fmt(struct v4l2_subdev *sd)
  930. {
  931. struct ov7670_info *info = to_state(sd);
  932. struct ov7670_win_size *wsize = info->wsize;
  933. unsigned char com7, com10 = 0;
  934. int ret;
  935. /*
  936. * COM7 is a pain in the ass, it doesn't like to be read then
  937. * quickly written afterward. But we have everything we need
  938. * to set it absolutely here, as long as the format-specific
  939. * register sets list it first.
  940. */
  941. com7 = info->fmt->regs[0].value;
  942. com7 |= wsize->com7_bit;
  943. ret = ov7670_write(sd, REG_COM7, com7);
  944. if (ret)
  945. return ret;
  946. /*
  947. * Configure the media bus through COM10 register
  948. */
  949. if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  950. com10 |= COM10_VS_NEG;
  951. if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  952. com10 |= COM10_HREF_REV;
  953. if (info->pclk_hb_disable)
  954. com10 |= COM10_PCLK_HB;
  955. ret = ov7670_write(sd, REG_COM10, com10);
  956. if (ret)
  957. return ret;
  958. /*
  959. * Now write the rest of the array. Also store start/stops
  960. */
  961. ret = ov7670_write_array(sd, info->fmt->regs + 1);
  962. if (ret)
  963. return ret;
  964. ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
  965. wsize->vstop);
  966. if (ret)
  967. return ret;
  968. if (wsize->regs) {
  969. ret = ov7670_write_array(sd, wsize->regs);
  970. if (ret)
  971. return ret;
  972. }
  973. /*
  974. * If we're running RGB565, we must rewrite clkrc after setting
  975. * the other parameters or the image looks poor. If we're *not*
  976. * doing RGB565, we must not rewrite clkrc or the image looks
  977. * *really* poor.
  978. *
  979. * (Update) Now that we retain clkrc state, we should be able
  980. * to write it unconditionally, and that will make the frame
  981. * rate persistent too.
  982. */
  983. ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
  984. if (ret)
  985. return ret;
  986. return 0;
  987. }
  988. /*
  989. * Set a format.
  990. */
  991. static int ov7670_set_fmt(struct v4l2_subdev *sd,
  992. struct v4l2_subdev_state *sd_state,
  993. struct v4l2_subdev_format *format)
  994. {
  995. struct ov7670_info *info = to_state(sd);
  996. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  997. struct v4l2_mbus_framefmt *mbus_fmt;
  998. #endif
  999. int ret;
  1000. if (format->pad)
  1001. return -EINVAL;
  1002. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1003. ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
  1004. if (ret)
  1005. return ret;
  1006. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1007. mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state,
  1008. format->pad);
  1009. *mbus_fmt = format->format;
  1010. #endif
  1011. return 0;
  1012. }
  1013. ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
  1014. if (ret)
  1015. return ret;
  1016. /*
  1017. * If the device is not powered up by the host driver do
  1018. * not apply any changes to H/W at this time. Instead
  1019. * the frame format will be restored right after power-up.
  1020. */
  1021. if (info->on)
  1022. return ov7670_apply_fmt(sd);
  1023. return 0;
  1024. }
  1025. static int ov7670_get_fmt(struct v4l2_subdev *sd,
  1026. struct v4l2_subdev_state *sd_state,
  1027. struct v4l2_subdev_format *format)
  1028. {
  1029. struct ov7670_info *info = to_state(sd);
  1030. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1031. struct v4l2_mbus_framefmt *mbus_fmt;
  1032. #endif
  1033. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1034. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1035. mbus_fmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
  1036. format->format = *mbus_fmt;
  1037. return 0;
  1038. #else
  1039. return -EINVAL;
  1040. #endif
  1041. } else {
  1042. format->format = info->format;
  1043. }
  1044. return 0;
  1045. }
  1046. /*
  1047. * Implement G/S_PARM. There is a "high quality" mode we could try
  1048. * to do someday; for now, we just do the frame rate tweak.
  1049. */
  1050. static int ov7670_g_frame_interval(struct v4l2_subdev *sd,
  1051. struct v4l2_subdev_frame_interval *ival)
  1052. {
  1053. struct ov7670_info *info = to_state(sd);
  1054. info->devtype->get_framerate(sd, &ival->interval);
  1055. return 0;
  1056. }
  1057. static int ov7670_s_frame_interval(struct v4l2_subdev *sd,
  1058. struct v4l2_subdev_frame_interval *ival)
  1059. {
  1060. struct v4l2_fract *tpf = &ival->interval;
  1061. struct ov7670_info *info = to_state(sd);
  1062. return info->devtype->set_framerate(sd, tpf);
  1063. }
  1064. /*
  1065. * Frame intervals. Since frame rates are controlled with the clock
  1066. * divider, we can only do 30/n for integer n values. So no continuous
  1067. * or stepwise options. Here we just pick a handful of logical values.
  1068. */
  1069. static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
  1070. static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
  1071. struct v4l2_subdev_state *sd_state,
  1072. struct v4l2_subdev_frame_interval_enum *fie)
  1073. {
  1074. struct ov7670_info *info = to_state(sd);
  1075. unsigned int n_win_sizes = info->devtype->n_win_sizes;
  1076. int i;
  1077. if (fie->pad)
  1078. return -EINVAL;
  1079. if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
  1080. return -EINVAL;
  1081. /*
  1082. * Check if the width/height is valid.
  1083. *
  1084. * If a minimum width/height was requested, filter out the capture
  1085. * windows that fall outside that.
  1086. */
  1087. for (i = 0; i < n_win_sizes; i++) {
  1088. struct ov7670_win_size *win = &info->devtype->win_sizes[i];
  1089. if (info->min_width && win->width < info->min_width)
  1090. continue;
  1091. if (info->min_height && win->height < info->min_height)
  1092. continue;
  1093. if (fie->width == win->width && fie->height == win->height)
  1094. break;
  1095. }
  1096. if (i == n_win_sizes)
  1097. return -EINVAL;
  1098. fie->interval.numerator = 1;
  1099. fie->interval.denominator = ov7670_frame_rates[fie->index];
  1100. return 0;
  1101. }
  1102. /*
  1103. * Frame size enumeration
  1104. */
  1105. static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
  1106. struct v4l2_subdev_state *sd_state,
  1107. struct v4l2_subdev_frame_size_enum *fse)
  1108. {
  1109. struct ov7670_info *info = to_state(sd);
  1110. int i;
  1111. int num_valid = -1;
  1112. __u32 index = fse->index;
  1113. unsigned int n_win_sizes = info->devtype->n_win_sizes;
  1114. if (fse->pad)
  1115. return -EINVAL;
  1116. /*
  1117. * If a minimum width/height was requested, filter out the capture
  1118. * windows that fall outside that.
  1119. */
  1120. for (i = 0; i < n_win_sizes; i++) {
  1121. struct ov7670_win_size *win = &info->devtype->win_sizes[i];
  1122. if (info->min_width && win->width < info->min_width)
  1123. continue;
  1124. if (info->min_height && win->height < info->min_height)
  1125. continue;
  1126. if (index == ++num_valid) {
  1127. fse->min_width = fse->max_width = win->width;
  1128. fse->min_height = fse->max_height = win->height;
  1129. return 0;
  1130. }
  1131. }
  1132. return -EINVAL;
  1133. }
  1134. /*
  1135. * Code for dealing with controls.
  1136. */
  1137. static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
  1138. int matrix[CMATRIX_LEN])
  1139. {
  1140. int i, ret;
  1141. unsigned char signbits = 0;
  1142. /*
  1143. * Weird crap seems to exist in the upper part of
  1144. * the sign bits register, so let's preserve it.
  1145. */
  1146. ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
  1147. signbits &= 0xc0;
  1148. for (i = 0; i < CMATRIX_LEN; i++) {
  1149. unsigned char raw;
  1150. if (matrix[i] < 0) {
  1151. signbits |= (1 << i);
  1152. if (matrix[i] < -255)
  1153. raw = 0xff;
  1154. else
  1155. raw = (-1 * matrix[i]) & 0xff;
  1156. } else {
  1157. if (matrix[i] > 255)
  1158. raw = 0xff;
  1159. else
  1160. raw = matrix[i] & 0xff;
  1161. }
  1162. ret = ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
  1163. if (ret)
  1164. return ret;
  1165. }
  1166. return ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
  1167. }
  1168. /*
  1169. * Hue also requires messing with the color matrix. It also requires
  1170. * trig functions, which tend not to be well supported in the kernel.
  1171. * So here is a simple table of sine values, 0-90 degrees, in steps
  1172. * of five degrees. Values are multiplied by 1000.
  1173. *
  1174. * The following naive approximate trig functions require an argument
  1175. * carefully limited to -180 <= theta <= 180.
  1176. */
  1177. #define SIN_STEP 5
  1178. static const int ov7670_sin_table[] = {
  1179. 0, 87, 173, 258, 342, 422,
  1180. 499, 573, 642, 707, 766, 819,
  1181. 866, 906, 939, 965, 984, 996,
  1182. 1000
  1183. };
  1184. static int ov7670_sine(int theta)
  1185. {
  1186. int chs = 1;
  1187. int sine;
  1188. if (theta < 0) {
  1189. theta = -theta;
  1190. chs = -1;
  1191. }
  1192. if (theta <= 90)
  1193. sine = ov7670_sin_table[theta/SIN_STEP];
  1194. else {
  1195. theta -= 90;
  1196. sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
  1197. }
  1198. return sine*chs;
  1199. }
  1200. static int ov7670_cosine(int theta)
  1201. {
  1202. theta = 90 - theta;
  1203. if (theta > 180)
  1204. theta -= 360;
  1205. else if (theta < -180)
  1206. theta += 360;
  1207. return ov7670_sine(theta);
  1208. }
  1209. static void ov7670_calc_cmatrix(struct ov7670_info *info,
  1210. int matrix[CMATRIX_LEN], int sat, int hue)
  1211. {
  1212. int i;
  1213. /*
  1214. * Apply the current saturation setting first.
  1215. */
  1216. for (i = 0; i < CMATRIX_LEN; i++)
  1217. matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
  1218. /*
  1219. * Then, if need be, rotate the hue value.
  1220. */
  1221. if (hue != 0) {
  1222. int sinth, costh, tmpmatrix[CMATRIX_LEN];
  1223. memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
  1224. sinth = ov7670_sine(hue);
  1225. costh = ov7670_cosine(hue);
  1226. matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
  1227. matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
  1228. matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
  1229. matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
  1230. matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
  1231. matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
  1232. }
  1233. }
  1234. static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
  1235. {
  1236. struct ov7670_info *info = to_state(sd);
  1237. int matrix[CMATRIX_LEN];
  1238. ov7670_calc_cmatrix(info, matrix, sat, hue);
  1239. return ov7670_store_cmatrix(sd, matrix);
  1240. }
  1241. /*
  1242. * Some weird registers seem to store values in a sign/magnitude format!
  1243. */
  1244. static unsigned char ov7670_abs_to_sm(unsigned char v)
  1245. {
  1246. if (v > 127)
  1247. return v & 0x7f;
  1248. return (128 - v) | 0x80;
  1249. }
  1250. static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
  1251. {
  1252. unsigned char com8 = 0, v;
  1253. ov7670_read(sd, REG_COM8, &com8);
  1254. com8 &= ~COM8_AEC;
  1255. ov7670_write(sd, REG_COM8, com8);
  1256. v = ov7670_abs_to_sm(value);
  1257. return ov7670_write(sd, REG_BRIGHT, v);
  1258. }
  1259. static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
  1260. {
  1261. return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
  1262. }
  1263. static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
  1264. {
  1265. unsigned char v = 0;
  1266. int ret;
  1267. ret = ov7670_read(sd, REG_MVFP, &v);
  1268. if (ret)
  1269. return ret;
  1270. if (value)
  1271. v |= MVFP_MIRROR;
  1272. else
  1273. v &= ~MVFP_MIRROR;
  1274. msleep(10); /* FIXME */
  1275. return ov7670_write(sd, REG_MVFP, v);
  1276. }
  1277. static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
  1278. {
  1279. unsigned char v = 0;
  1280. int ret;
  1281. ret = ov7670_read(sd, REG_MVFP, &v);
  1282. if (ret)
  1283. return ret;
  1284. if (value)
  1285. v |= MVFP_FLIP;
  1286. else
  1287. v &= ~MVFP_FLIP;
  1288. msleep(10); /* FIXME */
  1289. return ov7670_write(sd, REG_MVFP, v);
  1290. }
  1291. /*
  1292. * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
  1293. * the data sheet, the VREF parts should be the most significant, but
  1294. * experience shows otherwise. There seems to be little value in
  1295. * messing with the VREF bits, so we leave them alone.
  1296. */
  1297. static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
  1298. {
  1299. int ret;
  1300. unsigned char gain;
  1301. ret = ov7670_read(sd, REG_GAIN, &gain);
  1302. if (ret)
  1303. return ret;
  1304. *value = gain;
  1305. return 0;
  1306. }
  1307. static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
  1308. {
  1309. int ret;
  1310. unsigned char com8;
  1311. ret = ov7670_write(sd, REG_GAIN, value & 0xff);
  1312. if (ret)
  1313. return ret;
  1314. /* Have to turn off AGC as well */
  1315. ret = ov7670_read(sd, REG_COM8, &com8);
  1316. if (ret)
  1317. return ret;
  1318. return ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
  1319. }
  1320. /*
  1321. * Tweak autogain.
  1322. */
  1323. static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
  1324. {
  1325. int ret;
  1326. unsigned char com8;
  1327. ret = ov7670_read(sd, REG_COM8, &com8);
  1328. if (ret == 0) {
  1329. if (value)
  1330. com8 |= COM8_AGC;
  1331. else
  1332. com8 &= ~COM8_AGC;
  1333. ret = ov7670_write(sd, REG_COM8, com8);
  1334. }
  1335. return ret;
  1336. }
  1337. static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
  1338. {
  1339. int ret;
  1340. unsigned char com1, com8, aech, aechh;
  1341. ret = ov7670_read(sd, REG_COM1, &com1) +
  1342. ov7670_read(sd, REG_COM8, &com8) +
  1343. ov7670_read(sd, REG_AECHH, &aechh);
  1344. if (ret)
  1345. return ret;
  1346. com1 = (com1 & 0xfc) | (value & 0x03);
  1347. aech = (value >> 2) & 0xff;
  1348. aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
  1349. ret = ov7670_write(sd, REG_COM1, com1) +
  1350. ov7670_write(sd, REG_AECH, aech) +
  1351. ov7670_write(sd, REG_AECHH, aechh);
  1352. /* Have to turn off AEC as well */
  1353. if (ret == 0)
  1354. ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
  1355. return ret;
  1356. }
  1357. /*
  1358. * Tweak autoexposure.
  1359. */
  1360. static int ov7670_s_autoexp(struct v4l2_subdev *sd,
  1361. enum v4l2_exposure_auto_type value)
  1362. {
  1363. int ret;
  1364. unsigned char com8;
  1365. ret = ov7670_read(sd, REG_COM8, &com8);
  1366. if (ret == 0) {
  1367. if (value == V4L2_EXPOSURE_AUTO)
  1368. com8 |= COM8_AEC;
  1369. else
  1370. com8 &= ~COM8_AEC;
  1371. ret = ov7670_write(sd, REG_COM8, com8);
  1372. }
  1373. return ret;
  1374. }
  1375. static const char * const ov7670_test_pattern_menu[] = {
  1376. "No test output",
  1377. "Shifting \"1\"",
  1378. "8-bar color bar",
  1379. "Fade to gray color bar",
  1380. };
  1381. static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
  1382. {
  1383. int ret;
  1384. ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
  1385. value & BIT(0) ? TEST_PATTTERN_0 : 0);
  1386. if (ret)
  1387. return ret;
  1388. return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
  1389. value & BIT(1) ? TEST_PATTTERN_1 : 0);
  1390. }
  1391. static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
  1392. {
  1393. struct v4l2_subdev *sd = to_sd(ctrl);
  1394. struct ov7670_info *info = to_state(sd);
  1395. switch (ctrl->id) {
  1396. case V4L2_CID_AUTOGAIN:
  1397. return ov7670_g_gain(sd, &info->gain->val);
  1398. }
  1399. return -EINVAL;
  1400. }
  1401. static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
  1402. {
  1403. struct v4l2_subdev *sd = to_sd(ctrl);
  1404. struct ov7670_info *info = to_state(sd);
  1405. switch (ctrl->id) {
  1406. case V4L2_CID_BRIGHTNESS:
  1407. return ov7670_s_brightness(sd, ctrl->val);
  1408. case V4L2_CID_CONTRAST:
  1409. return ov7670_s_contrast(sd, ctrl->val);
  1410. case V4L2_CID_SATURATION:
  1411. return ov7670_s_sat_hue(sd,
  1412. info->saturation->val, info->hue->val);
  1413. case V4L2_CID_VFLIP:
  1414. return ov7670_s_vflip(sd, ctrl->val);
  1415. case V4L2_CID_HFLIP:
  1416. return ov7670_s_hflip(sd, ctrl->val);
  1417. case V4L2_CID_AUTOGAIN:
  1418. /* Only set manual gain if auto gain is not explicitly
  1419. turned on. */
  1420. if (!ctrl->val) {
  1421. /* ov7670_s_gain turns off auto gain */
  1422. return ov7670_s_gain(sd, info->gain->val);
  1423. }
  1424. return ov7670_s_autogain(sd, ctrl->val);
  1425. case V4L2_CID_EXPOSURE_AUTO:
  1426. /* Only set manual exposure if auto exposure is not explicitly
  1427. turned on. */
  1428. if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
  1429. /* ov7670_s_exp turns off auto exposure */
  1430. return ov7670_s_exp(sd, info->exposure->val);
  1431. }
  1432. return ov7670_s_autoexp(sd, ctrl->val);
  1433. case V4L2_CID_TEST_PATTERN:
  1434. return ov7670_s_test_pattern(sd, ctrl->val);
  1435. }
  1436. return -EINVAL;
  1437. }
  1438. static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
  1439. .s_ctrl = ov7670_s_ctrl,
  1440. .g_volatile_ctrl = ov7670_g_volatile_ctrl,
  1441. };
  1442. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1443. static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
  1444. {
  1445. unsigned char val = 0;
  1446. int ret;
  1447. ret = ov7670_read(sd, reg->reg & 0xff, &val);
  1448. reg->val = val;
  1449. reg->size = 1;
  1450. return ret;
  1451. }
  1452. static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
  1453. {
  1454. ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
  1455. return 0;
  1456. }
  1457. #endif
  1458. static void ov7670_power_on(struct v4l2_subdev *sd)
  1459. {
  1460. struct ov7670_info *info = to_state(sd);
  1461. if (info->on)
  1462. return;
  1463. clk_prepare_enable(info->clk);
  1464. if (info->pwdn_gpio)
  1465. gpiod_set_value(info->pwdn_gpio, 0);
  1466. if (info->resetb_gpio) {
  1467. gpiod_set_value(info->resetb_gpio, 1);
  1468. usleep_range(500, 1000);
  1469. gpiod_set_value(info->resetb_gpio, 0);
  1470. }
  1471. if (info->pwdn_gpio || info->resetb_gpio || info->clk)
  1472. usleep_range(3000, 5000);
  1473. info->on = true;
  1474. }
  1475. static void ov7670_power_off(struct v4l2_subdev *sd)
  1476. {
  1477. struct ov7670_info *info = to_state(sd);
  1478. if (!info->on)
  1479. return;
  1480. clk_disable_unprepare(info->clk);
  1481. if (info->pwdn_gpio)
  1482. gpiod_set_value(info->pwdn_gpio, 1);
  1483. info->on = false;
  1484. }
  1485. static int ov7670_s_power(struct v4l2_subdev *sd, int on)
  1486. {
  1487. struct ov7670_info *info = to_state(sd);
  1488. if (info->on == on)
  1489. return 0;
  1490. if (on) {
  1491. ov7670_power_on(sd);
  1492. ov7670_init(sd, 0);
  1493. ov7670_apply_fmt(sd);
  1494. ov7675_apply_framerate(sd);
  1495. v4l2_ctrl_handler_setup(&info->hdl);
  1496. } else {
  1497. ov7670_power_off(sd);
  1498. }
  1499. return 0;
  1500. }
  1501. static void ov7670_get_default_format(struct v4l2_subdev *sd,
  1502. struct v4l2_mbus_framefmt *format)
  1503. {
  1504. struct ov7670_info *info = to_state(sd);
  1505. format->width = info->devtype->win_sizes[0].width;
  1506. format->height = info->devtype->win_sizes[0].height;
  1507. format->colorspace = info->fmt->colorspace;
  1508. format->code = info->fmt->mbus_code;
  1509. format->field = V4L2_FIELD_NONE;
  1510. }
  1511. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1512. static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1513. {
  1514. struct v4l2_mbus_framefmt *format =
  1515. v4l2_subdev_get_try_format(sd, fh->state, 0);
  1516. ov7670_get_default_format(sd, format);
  1517. return 0;
  1518. }
  1519. #endif
  1520. /* ----------------------------------------------------------------------- */
  1521. static const struct v4l2_subdev_core_ops ov7670_core_ops = {
  1522. .reset = ov7670_reset,
  1523. .init = ov7670_init,
  1524. .s_power = ov7670_s_power,
  1525. .log_status = v4l2_ctrl_subdev_log_status,
  1526. .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
  1527. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  1528. #ifdef CONFIG_VIDEO_ADV_DEBUG
  1529. .g_register = ov7670_g_register,
  1530. .s_register = ov7670_s_register,
  1531. #endif
  1532. };
  1533. static const struct v4l2_subdev_video_ops ov7670_video_ops = {
  1534. .s_frame_interval = ov7670_s_frame_interval,
  1535. .g_frame_interval = ov7670_g_frame_interval,
  1536. };
  1537. static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
  1538. .enum_frame_interval = ov7670_enum_frame_interval,
  1539. .enum_frame_size = ov7670_enum_frame_size,
  1540. .enum_mbus_code = ov7670_enum_mbus_code,
  1541. .get_fmt = ov7670_get_fmt,
  1542. .set_fmt = ov7670_set_fmt,
  1543. };
  1544. static const struct v4l2_subdev_ops ov7670_ops = {
  1545. .core = &ov7670_core_ops,
  1546. .video = &ov7670_video_ops,
  1547. .pad = &ov7670_pad_ops,
  1548. };
  1549. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1550. static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
  1551. .open = ov7670_open,
  1552. };
  1553. #endif
  1554. /* ----------------------------------------------------------------------- */
  1555. static const struct ov7670_devtype ov7670_devdata[] = {
  1556. [MODEL_OV7670] = {
  1557. .win_sizes = ov7670_win_sizes,
  1558. .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
  1559. .set_framerate = ov7670_set_framerate_legacy,
  1560. .get_framerate = ov7670_get_framerate_legacy,
  1561. },
  1562. [MODEL_OV7675] = {
  1563. .win_sizes = ov7675_win_sizes,
  1564. .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
  1565. .set_framerate = ov7675_set_framerate,
  1566. .get_framerate = ov7675_get_framerate,
  1567. },
  1568. };
  1569. static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
  1570. {
  1571. info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
  1572. GPIOD_OUT_LOW);
  1573. if (IS_ERR(info->pwdn_gpio)) {
  1574. dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
  1575. return PTR_ERR(info->pwdn_gpio);
  1576. }
  1577. info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
  1578. GPIOD_OUT_LOW);
  1579. if (IS_ERR(info->resetb_gpio)) {
  1580. dev_info(&client->dev, "can't get %s GPIO\n", "reset");
  1581. return PTR_ERR(info->resetb_gpio);
  1582. }
  1583. usleep_range(3000, 5000);
  1584. return 0;
  1585. }
  1586. /*
  1587. * ov7670_parse_dt() - Parse device tree to collect mbus configuration
  1588. * properties
  1589. */
  1590. static int ov7670_parse_dt(struct device *dev,
  1591. struct ov7670_info *info)
  1592. {
  1593. struct fwnode_handle *fwnode = dev_fwnode(dev);
  1594. struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
  1595. struct fwnode_handle *ep;
  1596. int ret;
  1597. if (!fwnode)
  1598. return -EINVAL;
  1599. info->pclk_hb_disable = false;
  1600. if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
  1601. info->pclk_hb_disable = true;
  1602. ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
  1603. if (!ep)
  1604. return -EINVAL;
  1605. ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
  1606. fwnode_handle_put(ep);
  1607. if (ret)
  1608. return ret;
  1609. if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
  1610. dev_err(dev, "Unsupported media bus type\n");
  1611. return -EINVAL;
  1612. }
  1613. info->mbus_config = bus_cfg.bus.parallel.flags;
  1614. return 0;
  1615. }
  1616. static int ov7670_probe(struct i2c_client *client,
  1617. const struct i2c_device_id *id)
  1618. {
  1619. struct v4l2_fract tpf;
  1620. struct v4l2_subdev *sd;
  1621. struct ov7670_info *info;
  1622. int ret;
  1623. info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
  1624. if (info == NULL)
  1625. return -ENOMEM;
  1626. sd = &info->sd;
  1627. v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
  1628. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1629. sd->internal_ops = &ov7670_subdev_internal_ops;
  1630. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
  1631. #endif
  1632. info->clock_speed = 30; /* default: a guess */
  1633. if (dev_fwnode(&client->dev)) {
  1634. ret = ov7670_parse_dt(&client->dev, info);
  1635. if (ret)
  1636. return ret;
  1637. } else if (client->dev.platform_data) {
  1638. struct ov7670_config *config = client->dev.platform_data;
  1639. /*
  1640. * Must apply configuration before initializing device, because it
  1641. * selects I/O method.
  1642. */
  1643. info->min_width = config->min_width;
  1644. info->min_height = config->min_height;
  1645. info->use_smbus = config->use_smbus;
  1646. if (config->clock_speed)
  1647. info->clock_speed = config->clock_speed;
  1648. if (config->pll_bypass)
  1649. info->pll_bypass = true;
  1650. if (config->pclk_hb_disable)
  1651. info->pclk_hb_disable = true;
  1652. }
  1653. info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */
  1654. if (IS_ERR(info->clk)) {
  1655. ret = PTR_ERR(info->clk);
  1656. if (ret == -ENOENT)
  1657. info->clk = NULL;
  1658. else
  1659. return ret;
  1660. }
  1661. ret = ov7670_init_gpio(client, info);
  1662. if (ret)
  1663. return ret;
  1664. ov7670_power_on(sd);
  1665. if (info->clk) {
  1666. info->clock_speed = clk_get_rate(info->clk) / 1000000;
  1667. if (info->clock_speed < 10 || info->clock_speed > 48) {
  1668. ret = -EINVAL;
  1669. goto power_off;
  1670. }
  1671. }
  1672. /* Make sure it's an ov7670 */
  1673. ret = ov7670_detect(sd);
  1674. if (ret) {
  1675. v4l_dbg(1, debug, client,
  1676. "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
  1677. client->addr << 1, client->adapter->name);
  1678. goto power_off;
  1679. }
  1680. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1681. client->addr << 1, client->adapter->name);
  1682. info->devtype = &ov7670_devdata[id->driver_data];
  1683. info->fmt = &ov7670_formats[0];
  1684. info->wsize = &info->devtype->win_sizes[0];
  1685. ov7670_get_default_format(sd, &info->format);
  1686. info->clkrc = 0;
  1687. /* Set default frame rate to 30 fps */
  1688. tpf.numerator = 1;
  1689. tpf.denominator = 30;
  1690. info->devtype->set_framerate(sd, &tpf);
  1691. v4l2_ctrl_handler_init(&info->hdl, 10);
  1692. v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1693. V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
  1694. v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1695. V4L2_CID_CONTRAST, 0, 127, 1, 64);
  1696. v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1697. V4L2_CID_VFLIP, 0, 1, 1, 0);
  1698. v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1699. V4L2_CID_HFLIP, 0, 1, 1, 0);
  1700. info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1701. V4L2_CID_SATURATION, 0, 256, 1, 128);
  1702. info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1703. V4L2_CID_HUE, -180, 180, 5, 0);
  1704. info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1705. V4L2_CID_GAIN, 0, 255, 1, 128);
  1706. info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1707. V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
  1708. info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
  1709. V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
  1710. info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
  1711. V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
  1712. V4L2_EXPOSURE_AUTO);
  1713. v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
  1714. V4L2_CID_TEST_PATTERN,
  1715. ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
  1716. ov7670_test_pattern_menu);
  1717. sd->ctrl_handler = &info->hdl;
  1718. if (info->hdl.error) {
  1719. ret = info->hdl.error;
  1720. goto hdl_free;
  1721. }
  1722. /*
  1723. * We have checked empirically that hw allows to read back the gain
  1724. * value chosen by auto gain but that's not the case for auto exposure.
  1725. */
  1726. v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
  1727. v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
  1728. V4L2_EXPOSURE_MANUAL, false);
  1729. v4l2_ctrl_cluster(2, &info->saturation);
  1730. #if defined(CONFIG_MEDIA_CONTROLLER)
  1731. info->pad.flags = MEDIA_PAD_FL_SOURCE;
  1732. info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1733. ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
  1734. if (ret < 0)
  1735. goto hdl_free;
  1736. #endif
  1737. v4l2_ctrl_handler_setup(&info->hdl);
  1738. ret = v4l2_async_register_subdev(&info->sd);
  1739. if (ret < 0)
  1740. goto entity_cleanup;
  1741. ov7670_power_off(sd);
  1742. return 0;
  1743. entity_cleanup:
  1744. media_entity_cleanup(&info->sd.entity);
  1745. hdl_free:
  1746. v4l2_ctrl_handler_free(&info->hdl);
  1747. power_off:
  1748. ov7670_power_off(sd);
  1749. return ret;
  1750. }
  1751. static void ov7670_remove(struct i2c_client *client)
  1752. {
  1753. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1754. struct ov7670_info *info = to_state(sd);
  1755. v4l2_async_unregister_subdev(sd);
  1756. v4l2_ctrl_handler_free(&info->hdl);
  1757. media_entity_cleanup(&info->sd.entity);
  1758. }
  1759. static const struct i2c_device_id ov7670_id[] = {
  1760. { "ov7670", MODEL_OV7670 },
  1761. { "ov7675", MODEL_OV7675 },
  1762. { }
  1763. };
  1764. MODULE_DEVICE_TABLE(i2c, ov7670_id);
  1765. #if IS_ENABLED(CONFIG_OF)
  1766. static const struct of_device_id ov7670_of_match[] = {
  1767. { .compatible = "ovti,ov7670", },
  1768. { /* sentinel */ },
  1769. };
  1770. MODULE_DEVICE_TABLE(of, ov7670_of_match);
  1771. #endif
  1772. static struct i2c_driver ov7670_driver = {
  1773. .driver = {
  1774. .name = "ov7670",
  1775. .of_match_table = of_match_ptr(ov7670_of_match),
  1776. },
  1777. .probe = ov7670_probe,
  1778. .remove = ov7670_remove,
  1779. .id_table = ov7670_id,
  1780. };
  1781. module_i2c_driver(ov7670_driver);