ov6650.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
  4. *
  5. * Copyright (C) 2010 Janusz Krzysztofik <[email protected]>
  6. *
  7. * Based on OmniVision OV96xx Camera Driver
  8. * Copyright (C) 2009 Marek Vasut <[email protected]>
  9. *
  10. * Based on ov772x camera driver:
  11. * Copyright (C) 2008 Renesas Solutions Corp.
  12. * Kuninori Morimoto <[email protected]>
  13. *
  14. * Based on ov7670 and soc_camera_platform driver,
  15. * Copyright 2006-7 Jonathan Corbet <[email protected]>
  16. * Copyright (C) 2008 Magnus Damm
  17. * Copyright (C) 2008, Guennadi Liakhovetski <[email protected]>
  18. *
  19. * Hardware specific bits initially based on former work by Matt Callow
  20. * drivers/media/video/omap/sensor_ov6650.c
  21. * Copyright (C) 2006 Matt Callow
  22. */
  23. #include <linux/bitops.h>
  24. #include <linux/clk.h>
  25. #include <linux/delay.h>
  26. #include <linux/i2c.h>
  27. #include <linux/slab.h>
  28. #include <linux/v4l2-mediabus.h>
  29. #include <linux/module.h>
  30. #include <media/v4l2-ctrls.h>
  31. #include <media/v4l2-device.h>
  32. /* Register definitions */
  33. #define REG_GAIN 0x00 /* range 00 - 3F */
  34. #define REG_BLUE 0x01
  35. #define REG_RED 0x02
  36. #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
  37. #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
  38. #define REG_BRT 0x06
  39. #define REG_PIDH 0x0a
  40. #define REG_PIDL 0x0b
  41. #define REG_AECH 0x10
  42. #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
  43. /* [7:6] Input system clock (MHz)*/
  44. /* 00=8, 01=12, 10=16, 11=24 */
  45. /* [5:0]: Internal Clock Pre-Scaler */
  46. #define REG_COMA 0x12 /* [7] Reset */
  47. #define REG_COMB 0x13
  48. #define REG_COMC 0x14
  49. #define REG_COMD 0x15
  50. #define REG_COML 0x16
  51. #define REG_HSTRT 0x17
  52. #define REG_HSTOP 0x18
  53. #define REG_VSTRT 0x19
  54. #define REG_VSTOP 0x1a
  55. #define REG_PSHFT 0x1b
  56. #define REG_MIDH 0x1c
  57. #define REG_MIDL 0x1d
  58. #define REG_HSYNS 0x1e
  59. #define REG_HSYNE 0x1f
  60. #define REG_COME 0x20
  61. #define REG_YOFF 0x21
  62. #define REG_UOFF 0x22
  63. #define REG_VOFF 0x23
  64. #define REG_AEW 0x24
  65. #define REG_AEB 0x25
  66. #define REG_COMF 0x26
  67. #define REG_COMG 0x27
  68. #define REG_COMH 0x28
  69. #define REG_COMI 0x29
  70. #define REG_FRARL 0x2b
  71. #define REG_COMJ 0x2c
  72. #define REG_COMK 0x2d
  73. #define REG_AVGY 0x2e
  74. #define REG_REF0 0x2f
  75. #define REG_REF1 0x30
  76. #define REG_REF2 0x31
  77. #define REG_FRAJH 0x32
  78. #define REG_FRAJL 0x33
  79. #define REG_FACT 0x34
  80. #define REG_L1AEC 0x35
  81. #define REG_AVGU 0x36
  82. #define REG_AVGV 0x37
  83. #define REG_SPCB 0x60
  84. #define REG_SPCC 0x61
  85. #define REG_GAM1 0x62
  86. #define REG_GAM2 0x63
  87. #define REG_GAM3 0x64
  88. #define REG_SPCD 0x65
  89. #define REG_SPCE 0x68
  90. #define REG_ADCL 0x69
  91. #define REG_RMCO 0x6c
  92. #define REG_GMCO 0x6d
  93. #define REG_BMCO 0x6e
  94. /* Register bits, values, etc. */
  95. #define OV6650_PIDH 0x66 /* high byte of product ID number */
  96. #define OV6650_PIDL 0x50 /* low byte of product ID number */
  97. #define OV6650_MIDH 0x7F /* high byte of mfg ID */
  98. #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
  99. #define DEF_GAIN 0x00
  100. #define DEF_BLUE 0x80
  101. #define DEF_RED 0x80
  102. #define SAT_SHIFT 4
  103. #define SAT_MASK (0xf << SAT_SHIFT)
  104. #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
  105. #define HUE_EN BIT(5)
  106. #define HUE_MASK 0x1f
  107. #define DEF_HUE 0x10
  108. #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
  109. #define DEF_AECH 0x4D
  110. #define CLKRC_8MHz 0x00
  111. #define CLKRC_12MHz 0x40
  112. #define CLKRC_16MHz 0x80
  113. #define CLKRC_24MHz 0xc0
  114. #define CLKRC_DIV_MASK 0x3f
  115. #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
  116. #define DEF_CLKRC 0x00
  117. #define COMA_RESET BIT(7)
  118. #define COMA_QCIF BIT(5)
  119. #define COMA_RAW_RGB BIT(4)
  120. #define COMA_RGB BIT(3)
  121. #define COMA_BW BIT(2)
  122. #define COMA_WORD_SWAP BIT(1)
  123. #define COMA_BYTE_SWAP BIT(0)
  124. #define DEF_COMA 0x00
  125. #define COMB_FLIP_V BIT(7)
  126. #define COMB_FLIP_H BIT(5)
  127. #define COMB_BAND_FILTER BIT(4)
  128. #define COMB_AWB BIT(2)
  129. #define COMB_AGC BIT(1)
  130. #define COMB_AEC BIT(0)
  131. #define DEF_COMB 0x5f
  132. #define COML_ONE_CHANNEL BIT(7)
  133. #define DEF_HSTRT 0x24
  134. #define DEF_HSTOP 0xd4
  135. #define DEF_VSTRT 0x04
  136. #define DEF_VSTOP 0x94
  137. #define COMF_HREF_LOW BIT(4)
  138. #define COMJ_PCLK_RISING BIT(4)
  139. #define COMJ_VSYNC_HIGH BIT(0)
  140. /* supported resolutions */
  141. #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
  142. #define W_CIF (W_QCIF << 1)
  143. #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
  144. #define H_CIF (H_QCIF << 1)
  145. #define FRAME_RATE_MAX 30
  146. struct ov6650_reg {
  147. u8 reg;
  148. u8 val;
  149. };
  150. struct ov6650 {
  151. struct v4l2_subdev subdev;
  152. struct v4l2_ctrl_handler hdl;
  153. struct {
  154. /* exposure/autoexposure cluster */
  155. struct v4l2_ctrl *autoexposure;
  156. struct v4l2_ctrl *exposure;
  157. };
  158. struct {
  159. /* gain/autogain cluster */
  160. struct v4l2_ctrl *autogain;
  161. struct v4l2_ctrl *gain;
  162. };
  163. struct {
  164. /* blue/red/autowhitebalance cluster */
  165. struct v4l2_ctrl *autowb;
  166. struct v4l2_ctrl *blue;
  167. struct v4l2_ctrl *red;
  168. };
  169. struct clk *clk;
  170. bool half_scale; /* scale down output by 2 */
  171. struct v4l2_rect rect; /* sensor cropping window */
  172. struct v4l2_fract tpf; /* as requested with s_frame_interval */
  173. u32 code;
  174. };
  175. struct ov6650_xclk {
  176. unsigned long rate;
  177. u8 clkrc;
  178. };
  179. static const struct ov6650_xclk ov6650_xclk[] = {
  180. {
  181. .rate = 8000000,
  182. .clkrc = CLKRC_8MHz,
  183. },
  184. {
  185. .rate = 12000000,
  186. .clkrc = CLKRC_12MHz,
  187. },
  188. {
  189. .rate = 16000000,
  190. .clkrc = CLKRC_16MHz,
  191. },
  192. {
  193. .rate = 24000000,
  194. .clkrc = CLKRC_24MHz,
  195. },
  196. };
  197. static u32 ov6650_codes[] = {
  198. MEDIA_BUS_FMT_YUYV8_2X8,
  199. MEDIA_BUS_FMT_UYVY8_2X8,
  200. MEDIA_BUS_FMT_YVYU8_2X8,
  201. MEDIA_BUS_FMT_VYUY8_2X8,
  202. MEDIA_BUS_FMT_SBGGR8_1X8,
  203. MEDIA_BUS_FMT_Y8_1X8,
  204. };
  205. static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
  206. .width = W_CIF,
  207. .height = H_CIF,
  208. .code = MEDIA_BUS_FMT_SBGGR8_1X8,
  209. .colorspace = V4L2_COLORSPACE_SRGB,
  210. .field = V4L2_FIELD_NONE,
  211. .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
  212. .quantization = V4L2_QUANTIZATION_DEFAULT,
  213. .xfer_func = V4L2_XFER_FUNC_DEFAULT,
  214. };
  215. /* read a register */
  216. static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
  217. {
  218. int ret;
  219. u8 data = reg;
  220. struct i2c_msg msg = {
  221. .addr = client->addr,
  222. .flags = 0,
  223. .len = 1,
  224. .buf = &data,
  225. };
  226. ret = i2c_transfer(client->adapter, &msg, 1);
  227. if (ret < 0)
  228. goto err;
  229. msg.flags = I2C_M_RD;
  230. ret = i2c_transfer(client->adapter, &msg, 1);
  231. if (ret < 0)
  232. goto err;
  233. *val = data;
  234. return 0;
  235. err:
  236. dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
  237. return ret;
  238. }
  239. /* write a register */
  240. static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
  241. {
  242. int ret;
  243. unsigned char data[2] = { reg, val };
  244. struct i2c_msg msg = {
  245. .addr = client->addr,
  246. .flags = 0,
  247. .len = 2,
  248. .buf = data,
  249. };
  250. ret = i2c_transfer(client->adapter, &msg, 1);
  251. udelay(100);
  252. if (ret < 0) {
  253. dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
  254. return ret;
  255. }
  256. return 0;
  257. }
  258. /* Read a register, alter its bits, write it back */
  259. static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
  260. {
  261. u8 val;
  262. int ret;
  263. ret = ov6650_reg_read(client, reg, &val);
  264. if (ret) {
  265. dev_err(&client->dev,
  266. "[Read]-Modify-Write of register 0x%02x failed!\n",
  267. reg);
  268. return ret;
  269. }
  270. val &= ~mask;
  271. val |= set;
  272. ret = ov6650_reg_write(client, reg, val);
  273. if (ret)
  274. dev_err(&client->dev,
  275. "Read-Modify-[Write] of register 0x%02x failed!\n",
  276. reg);
  277. return ret;
  278. }
  279. static struct ov6650 *to_ov6650(const struct i2c_client *client)
  280. {
  281. return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
  282. }
  283. /* Start/Stop streaming from the device */
  284. static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
  285. {
  286. return 0;
  287. }
  288. /* Get status of additional camera capabilities */
  289. static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
  290. {
  291. struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
  292. struct v4l2_subdev *sd = &priv->subdev;
  293. struct i2c_client *client = v4l2_get_subdevdata(sd);
  294. uint8_t reg, reg2;
  295. int ret;
  296. switch (ctrl->id) {
  297. case V4L2_CID_AUTOGAIN:
  298. ret = ov6650_reg_read(client, REG_GAIN, &reg);
  299. if (!ret)
  300. priv->gain->val = reg;
  301. return ret;
  302. case V4L2_CID_AUTO_WHITE_BALANCE:
  303. ret = ov6650_reg_read(client, REG_BLUE, &reg);
  304. if (!ret)
  305. ret = ov6650_reg_read(client, REG_RED, &reg2);
  306. if (!ret) {
  307. priv->blue->val = reg;
  308. priv->red->val = reg2;
  309. }
  310. return ret;
  311. case V4L2_CID_EXPOSURE_AUTO:
  312. ret = ov6650_reg_read(client, REG_AECH, &reg);
  313. if (!ret)
  314. priv->exposure->val = reg;
  315. return ret;
  316. }
  317. return -EINVAL;
  318. }
  319. /* Set status of additional camera capabilities */
  320. static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
  321. {
  322. struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
  323. struct v4l2_subdev *sd = &priv->subdev;
  324. struct i2c_client *client = v4l2_get_subdevdata(sd);
  325. int ret;
  326. switch (ctrl->id) {
  327. case V4L2_CID_AUTOGAIN:
  328. ret = ov6650_reg_rmw(client, REG_COMB,
  329. ctrl->val ? COMB_AGC : 0, COMB_AGC);
  330. if (!ret && !ctrl->val)
  331. ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
  332. return ret;
  333. case V4L2_CID_AUTO_WHITE_BALANCE:
  334. ret = ov6650_reg_rmw(client, REG_COMB,
  335. ctrl->val ? COMB_AWB : 0, COMB_AWB);
  336. if (!ret && !ctrl->val) {
  337. ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
  338. if (!ret)
  339. ret = ov6650_reg_write(client, REG_RED,
  340. priv->red->val);
  341. }
  342. return ret;
  343. case V4L2_CID_SATURATION:
  344. return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
  345. SAT_MASK);
  346. case V4L2_CID_HUE:
  347. return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
  348. HUE_MASK);
  349. case V4L2_CID_BRIGHTNESS:
  350. return ov6650_reg_write(client, REG_BRT, ctrl->val);
  351. case V4L2_CID_EXPOSURE_AUTO:
  352. ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
  353. V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
  354. if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
  355. ret = ov6650_reg_write(client, REG_AECH,
  356. priv->exposure->val);
  357. return ret;
  358. case V4L2_CID_GAMMA:
  359. return ov6650_reg_write(client, REG_GAM1, ctrl->val);
  360. case V4L2_CID_VFLIP:
  361. return ov6650_reg_rmw(client, REG_COMB,
  362. ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
  363. case V4L2_CID_HFLIP:
  364. return ov6650_reg_rmw(client, REG_COMB,
  365. ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
  366. }
  367. return -EINVAL;
  368. }
  369. #ifdef CONFIG_VIDEO_ADV_DEBUG
  370. static int ov6650_get_register(struct v4l2_subdev *sd,
  371. struct v4l2_dbg_register *reg)
  372. {
  373. struct i2c_client *client = v4l2_get_subdevdata(sd);
  374. int ret;
  375. u8 val;
  376. if (reg->reg & ~0xff)
  377. return -EINVAL;
  378. reg->size = 1;
  379. ret = ov6650_reg_read(client, reg->reg, &val);
  380. if (!ret)
  381. reg->val = (__u64)val;
  382. return ret;
  383. }
  384. static int ov6650_set_register(struct v4l2_subdev *sd,
  385. const struct v4l2_dbg_register *reg)
  386. {
  387. struct i2c_client *client = v4l2_get_subdevdata(sd);
  388. if (reg->reg & ~0xff || reg->val & ~0xff)
  389. return -EINVAL;
  390. return ov6650_reg_write(client, reg->reg, reg->val);
  391. }
  392. #endif
  393. static int ov6650_s_power(struct v4l2_subdev *sd, int on)
  394. {
  395. struct i2c_client *client = v4l2_get_subdevdata(sd);
  396. struct ov6650 *priv = to_ov6650(client);
  397. int ret = 0;
  398. if (on)
  399. ret = clk_prepare_enable(priv->clk);
  400. else
  401. clk_disable_unprepare(priv->clk);
  402. return ret;
  403. }
  404. static int ov6650_get_selection(struct v4l2_subdev *sd,
  405. struct v4l2_subdev_state *sd_state,
  406. struct v4l2_subdev_selection *sel)
  407. {
  408. struct i2c_client *client = v4l2_get_subdevdata(sd);
  409. struct ov6650 *priv = to_ov6650(client);
  410. struct v4l2_rect *rect;
  411. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  412. /* pre-select try crop rectangle */
  413. rect = &sd_state->pads->try_crop;
  414. } else {
  415. /* pre-select active crop rectangle */
  416. rect = &priv->rect;
  417. }
  418. switch (sel->target) {
  419. case V4L2_SEL_TGT_CROP_BOUNDS:
  420. sel->r.left = DEF_HSTRT << 1;
  421. sel->r.top = DEF_VSTRT << 1;
  422. sel->r.width = W_CIF;
  423. sel->r.height = H_CIF;
  424. return 0;
  425. case V4L2_SEL_TGT_CROP:
  426. /* use selected crop rectangle */
  427. sel->r = *rect;
  428. return 0;
  429. default:
  430. return -EINVAL;
  431. }
  432. }
  433. static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
  434. {
  435. return width > rect->width >> 1 || height > rect->height >> 1;
  436. }
  437. static void ov6650_bind_align_crop_rectangle(struct v4l2_rect *rect)
  438. {
  439. v4l_bound_align_image(&rect->width, 2, W_CIF, 1,
  440. &rect->height, 2, H_CIF, 1, 0);
  441. v4l_bound_align_image(&rect->left, DEF_HSTRT << 1,
  442. (DEF_HSTRT << 1) + W_CIF - (__s32)rect->width, 1,
  443. &rect->top, DEF_VSTRT << 1,
  444. (DEF_VSTRT << 1) + H_CIF - (__s32)rect->height,
  445. 1, 0);
  446. }
  447. static int ov6650_set_selection(struct v4l2_subdev *sd,
  448. struct v4l2_subdev_state *sd_state,
  449. struct v4l2_subdev_selection *sel)
  450. {
  451. struct i2c_client *client = v4l2_get_subdevdata(sd);
  452. struct ov6650 *priv = to_ov6650(client);
  453. int ret;
  454. if (sel->target != V4L2_SEL_TGT_CROP)
  455. return -EINVAL;
  456. ov6650_bind_align_crop_rectangle(&sel->r);
  457. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  458. struct v4l2_rect *crop = &sd_state->pads->try_crop;
  459. struct v4l2_mbus_framefmt *mf = &sd_state->pads->try_fmt;
  460. /* detect current pad config scaling factor */
  461. bool half_scale = !is_unscaled_ok(mf->width, mf->height, crop);
  462. /* store new crop rectangle */
  463. *crop = sel->r;
  464. /* adjust frame size */
  465. mf->width = crop->width >> half_scale;
  466. mf->height = crop->height >> half_scale;
  467. return 0;
  468. }
  469. /* V4L2_SUBDEV_FORMAT_ACTIVE */
  470. /* apply new crop rectangle */
  471. ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
  472. if (!ret) {
  473. priv->rect.width += priv->rect.left - sel->r.left;
  474. priv->rect.left = sel->r.left;
  475. ret = ov6650_reg_write(client, REG_HSTOP,
  476. (sel->r.left + sel->r.width) >> 1);
  477. }
  478. if (!ret) {
  479. priv->rect.width = sel->r.width;
  480. ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
  481. }
  482. if (!ret) {
  483. priv->rect.height += priv->rect.top - sel->r.top;
  484. priv->rect.top = sel->r.top;
  485. ret = ov6650_reg_write(client, REG_VSTOP,
  486. (sel->r.top + sel->r.height) >> 1);
  487. }
  488. if (!ret)
  489. priv->rect.height = sel->r.height;
  490. return ret;
  491. }
  492. static int ov6650_get_fmt(struct v4l2_subdev *sd,
  493. struct v4l2_subdev_state *sd_state,
  494. struct v4l2_subdev_format *format)
  495. {
  496. struct v4l2_mbus_framefmt *mf = &format->format;
  497. struct i2c_client *client = v4l2_get_subdevdata(sd);
  498. struct ov6650 *priv = to_ov6650(client);
  499. if (format->pad)
  500. return -EINVAL;
  501. /* initialize response with default media bus frame format */
  502. *mf = ov6650_def_fmt;
  503. /* update media bus format code and frame size */
  504. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  505. mf->width = sd_state->pads->try_fmt.width;
  506. mf->height = sd_state->pads->try_fmt.height;
  507. mf->code = sd_state->pads->try_fmt.code;
  508. } else {
  509. mf->width = priv->rect.width >> priv->half_scale;
  510. mf->height = priv->rect.height >> priv->half_scale;
  511. mf->code = priv->code;
  512. }
  513. return 0;
  514. }
  515. #define to_clkrc(div) ((div) - 1)
  516. /* set the format we will capture in */
  517. static int ov6650_s_fmt(struct v4l2_subdev *sd, u32 code, bool half_scale)
  518. {
  519. struct i2c_client *client = v4l2_get_subdevdata(sd);
  520. struct ov6650 *priv = to_ov6650(client);
  521. u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask;
  522. int ret;
  523. /* select color matrix configuration for given color encoding */
  524. switch (code) {
  525. case MEDIA_BUS_FMT_Y8_1X8:
  526. dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
  527. coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
  528. coma_set |= COMA_BW;
  529. break;
  530. case MEDIA_BUS_FMT_YUYV8_2X8:
  531. dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
  532. coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
  533. coma_set |= COMA_WORD_SWAP;
  534. break;
  535. case MEDIA_BUS_FMT_YVYU8_2X8:
  536. dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
  537. coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
  538. COMA_BYTE_SWAP;
  539. break;
  540. case MEDIA_BUS_FMT_UYVY8_2X8:
  541. dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
  542. if (half_scale) {
  543. coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
  544. coma_set |= COMA_BYTE_SWAP;
  545. } else {
  546. coma_mask |= COMA_RGB | COMA_BW;
  547. coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
  548. }
  549. break;
  550. case MEDIA_BUS_FMT_VYUY8_2X8:
  551. dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
  552. if (half_scale) {
  553. coma_mask |= COMA_RGB | COMA_BW;
  554. coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
  555. } else {
  556. coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
  557. coma_set |= COMA_BYTE_SWAP;
  558. }
  559. break;
  560. case MEDIA_BUS_FMT_SBGGR8_1X8:
  561. dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
  562. coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
  563. coma_set |= COMA_RAW_RGB | COMA_RGB;
  564. break;
  565. default:
  566. dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
  567. return -EINVAL;
  568. }
  569. if (code == MEDIA_BUS_FMT_Y8_1X8 ||
  570. code == MEDIA_BUS_FMT_SBGGR8_1X8) {
  571. coml_mask = COML_ONE_CHANNEL;
  572. coml_set = 0;
  573. } else {
  574. coml_mask = 0;
  575. coml_set = COML_ONE_CHANNEL;
  576. }
  577. if (half_scale) {
  578. dev_dbg(&client->dev, "max resolution: QCIF\n");
  579. coma_set |= COMA_QCIF;
  580. } else {
  581. dev_dbg(&client->dev, "max resolution: CIF\n");
  582. coma_mask |= COMA_QCIF;
  583. }
  584. ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
  585. if (!ret) {
  586. priv->half_scale = half_scale;
  587. ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
  588. }
  589. if (!ret)
  590. priv->code = code;
  591. return ret;
  592. }
  593. static int ov6650_set_fmt(struct v4l2_subdev *sd,
  594. struct v4l2_subdev_state *sd_state,
  595. struct v4l2_subdev_format *format)
  596. {
  597. struct v4l2_mbus_framefmt *mf = &format->format;
  598. struct i2c_client *client = v4l2_get_subdevdata(sd);
  599. struct ov6650 *priv = to_ov6650(client);
  600. struct v4l2_rect *crop;
  601. bool half_scale;
  602. if (format->pad)
  603. return -EINVAL;
  604. switch (mf->code) {
  605. case MEDIA_BUS_FMT_Y10_1X10:
  606. mf->code = MEDIA_BUS_FMT_Y8_1X8;
  607. fallthrough;
  608. case MEDIA_BUS_FMT_Y8_1X8:
  609. case MEDIA_BUS_FMT_YVYU8_2X8:
  610. case MEDIA_BUS_FMT_YUYV8_2X8:
  611. case MEDIA_BUS_FMT_VYUY8_2X8:
  612. case MEDIA_BUS_FMT_UYVY8_2X8:
  613. break;
  614. default:
  615. mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
  616. fallthrough;
  617. case MEDIA_BUS_FMT_SBGGR8_1X8:
  618. break;
  619. }
  620. if (format->which == V4L2_SUBDEV_FORMAT_TRY)
  621. crop = &sd_state->pads->try_crop;
  622. else
  623. crop = &priv->rect;
  624. half_scale = !is_unscaled_ok(mf->width, mf->height, crop);
  625. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  626. /* store new mbus frame format code and size in pad config */
  627. sd_state->pads->try_fmt.width = crop->width >> half_scale;
  628. sd_state->pads->try_fmt.height = crop->height >> half_scale;
  629. sd_state->pads->try_fmt.code = mf->code;
  630. /* return default mbus frame format updated with pad config */
  631. *mf = ov6650_def_fmt;
  632. mf->width = sd_state->pads->try_fmt.width;
  633. mf->height = sd_state->pads->try_fmt.height;
  634. mf->code = sd_state->pads->try_fmt.code;
  635. } else {
  636. int ret = 0;
  637. /* apply new media bus frame format and scaling if changed */
  638. if (mf->code != priv->code || half_scale != priv->half_scale)
  639. ret = ov6650_s_fmt(sd, mf->code, half_scale);
  640. if (ret)
  641. return ret;
  642. /* return default format updated with active size and code */
  643. *mf = ov6650_def_fmt;
  644. mf->width = priv->rect.width >> priv->half_scale;
  645. mf->height = priv->rect.height >> priv->half_scale;
  646. mf->code = priv->code;
  647. }
  648. return 0;
  649. }
  650. static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
  651. struct v4l2_subdev_state *sd_state,
  652. struct v4l2_subdev_mbus_code_enum *code)
  653. {
  654. if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
  655. return -EINVAL;
  656. code->code = ov6650_codes[code->index];
  657. return 0;
  658. }
  659. static int ov6650_enum_frame_interval(struct v4l2_subdev *sd,
  660. struct v4l2_subdev_state *sd_state,
  661. struct v4l2_subdev_frame_interval_enum *fie)
  662. {
  663. int i;
  664. /* enumerate supported frame intervals not exceeding 1 second */
  665. if (fie->index > CLKRC_DIV_MASK ||
  666. GET_CLKRC_DIV(fie->index) > FRAME_RATE_MAX)
  667. return -EINVAL;
  668. for (i = 0; i < ARRAY_SIZE(ov6650_codes); i++)
  669. if (fie->code == ov6650_codes[i])
  670. break;
  671. if (i == ARRAY_SIZE(ov6650_codes))
  672. return -EINVAL;
  673. if (!fie->width || fie->width > W_CIF ||
  674. !fie->height || fie->height > H_CIF)
  675. return -EINVAL;
  676. fie->interval.numerator = GET_CLKRC_DIV(fie->index);
  677. fie->interval.denominator = FRAME_RATE_MAX;
  678. return 0;
  679. }
  680. static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
  681. struct v4l2_subdev_frame_interval *ival)
  682. {
  683. struct i2c_client *client = v4l2_get_subdevdata(sd);
  684. struct ov6650 *priv = to_ov6650(client);
  685. ival->interval = priv->tpf;
  686. dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
  687. ival->interval.numerator, ival->interval.denominator);
  688. return 0;
  689. }
  690. static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
  691. struct v4l2_subdev_frame_interval *ival)
  692. {
  693. struct i2c_client *client = v4l2_get_subdevdata(sd);
  694. struct ov6650 *priv = to_ov6650(client);
  695. struct v4l2_fract *tpf = &ival->interval;
  696. int div, ret;
  697. if (tpf->numerator == 0 || tpf->denominator == 0)
  698. div = 1; /* Reset to full rate */
  699. else
  700. div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
  701. if (div == 0)
  702. div = 1;
  703. else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
  704. div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
  705. ret = ov6650_reg_rmw(client, REG_CLKRC, to_clkrc(div), CLKRC_DIV_MASK);
  706. if (!ret) {
  707. priv->tpf.numerator = div;
  708. priv->tpf.denominator = FRAME_RATE_MAX;
  709. *tpf = priv->tpf;
  710. }
  711. return ret;
  712. }
  713. /* Soft reset the camera. This has nothing to do with the RESET pin! */
  714. static int ov6650_reset(struct i2c_client *client)
  715. {
  716. int ret;
  717. dev_dbg(&client->dev, "reset\n");
  718. ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
  719. if (ret)
  720. dev_err(&client->dev,
  721. "An error occurred while entering soft reset!\n");
  722. return ret;
  723. }
  724. /* program default register values */
  725. static int ov6650_prog_dflt(struct i2c_client *client, u8 clkrc)
  726. {
  727. int ret;
  728. dev_dbg(&client->dev, "initializing\n");
  729. ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
  730. if (!ret)
  731. ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
  732. if (!ret)
  733. ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
  734. return ret;
  735. }
  736. static int ov6650_video_probe(struct v4l2_subdev *sd)
  737. {
  738. struct i2c_client *client = v4l2_get_subdevdata(sd);
  739. struct ov6650 *priv = to_ov6650(client);
  740. const struct ov6650_xclk *xclk = NULL;
  741. unsigned long rate;
  742. u8 pidh, pidl, midh, midl;
  743. int i, ret = 0;
  744. priv->clk = devm_clk_get(&client->dev, NULL);
  745. if (IS_ERR(priv->clk)) {
  746. ret = PTR_ERR(priv->clk);
  747. dev_err(&client->dev, "clk request err: %d\n", ret);
  748. return ret;
  749. }
  750. rate = clk_get_rate(priv->clk);
  751. for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) {
  752. if (rate != ov6650_xclk[i].rate)
  753. continue;
  754. xclk = &ov6650_xclk[i];
  755. dev_info(&client->dev, "using host default clock rate %lukHz\n",
  756. rate / 1000);
  757. break;
  758. }
  759. for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) {
  760. ret = clk_set_rate(priv->clk, ov6650_xclk[i].rate);
  761. if (ret || clk_get_rate(priv->clk) != ov6650_xclk[i].rate)
  762. continue;
  763. xclk = &ov6650_xclk[i];
  764. dev_info(&client->dev, "using negotiated clock rate %lukHz\n",
  765. xclk->rate / 1000);
  766. break;
  767. }
  768. if (!xclk) {
  769. dev_err(&client->dev, "unable to get supported clock rate\n");
  770. if (!ret)
  771. ret = -EINVAL;
  772. return ret;
  773. }
  774. ret = ov6650_s_power(sd, 1);
  775. if (ret < 0)
  776. return ret;
  777. msleep(20);
  778. /*
  779. * check and show product ID and manufacturer ID
  780. */
  781. ret = ov6650_reg_read(client, REG_PIDH, &pidh);
  782. if (!ret)
  783. ret = ov6650_reg_read(client, REG_PIDL, &pidl);
  784. if (!ret)
  785. ret = ov6650_reg_read(client, REG_MIDH, &midh);
  786. if (!ret)
  787. ret = ov6650_reg_read(client, REG_MIDL, &midl);
  788. if (ret)
  789. goto done;
  790. if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
  791. dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
  792. pidh, pidl);
  793. ret = -ENODEV;
  794. goto done;
  795. }
  796. dev_info(&client->dev,
  797. "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
  798. pidh, pidl, midh, midl);
  799. ret = ov6650_reset(client);
  800. if (!ret)
  801. ret = ov6650_prog_dflt(client, xclk->clkrc);
  802. if (!ret) {
  803. /* driver default frame format, no scaling */
  804. ret = ov6650_s_fmt(sd, ov6650_def_fmt.code, false);
  805. }
  806. if (!ret)
  807. ret = v4l2_ctrl_handler_setup(&priv->hdl);
  808. done:
  809. ov6650_s_power(sd, 0);
  810. return ret;
  811. }
  812. static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
  813. .g_volatile_ctrl = ov6550_g_volatile_ctrl,
  814. .s_ctrl = ov6550_s_ctrl,
  815. };
  816. static const struct v4l2_subdev_core_ops ov6650_core_ops = {
  817. #ifdef CONFIG_VIDEO_ADV_DEBUG
  818. .g_register = ov6650_get_register,
  819. .s_register = ov6650_set_register,
  820. #endif
  821. .s_power = ov6650_s_power,
  822. };
  823. /* Request bus settings on camera side */
  824. static int ov6650_get_mbus_config(struct v4l2_subdev *sd,
  825. unsigned int pad,
  826. struct v4l2_mbus_config *cfg)
  827. {
  828. struct i2c_client *client = v4l2_get_subdevdata(sd);
  829. u8 comj, comf;
  830. int ret;
  831. ret = ov6650_reg_read(client, REG_COMJ, &comj);
  832. if (ret)
  833. return ret;
  834. ret = ov6650_reg_read(client, REG_COMF, &comf);
  835. if (ret)
  836. return ret;
  837. cfg->type = V4L2_MBUS_PARALLEL;
  838. cfg->bus.parallel.flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH
  839. | ((comj & COMJ_VSYNC_HIGH) ? V4L2_MBUS_VSYNC_ACTIVE_HIGH
  840. : V4L2_MBUS_VSYNC_ACTIVE_LOW)
  841. | ((comf & COMF_HREF_LOW) ? V4L2_MBUS_HSYNC_ACTIVE_LOW
  842. : V4L2_MBUS_HSYNC_ACTIVE_HIGH)
  843. | ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING
  844. : V4L2_MBUS_PCLK_SAMPLE_FALLING);
  845. return 0;
  846. }
  847. static const struct v4l2_subdev_video_ops ov6650_video_ops = {
  848. .s_stream = ov6650_s_stream,
  849. .g_frame_interval = ov6650_g_frame_interval,
  850. .s_frame_interval = ov6650_s_frame_interval,
  851. };
  852. static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
  853. .enum_mbus_code = ov6650_enum_mbus_code,
  854. .enum_frame_interval = ov6650_enum_frame_interval,
  855. .get_selection = ov6650_get_selection,
  856. .set_selection = ov6650_set_selection,
  857. .get_fmt = ov6650_get_fmt,
  858. .set_fmt = ov6650_set_fmt,
  859. .get_mbus_config = ov6650_get_mbus_config,
  860. };
  861. static const struct v4l2_subdev_ops ov6650_subdev_ops = {
  862. .core = &ov6650_core_ops,
  863. .video = &ov6650_video_ops,
  864. .pad = &ov6650_pad_ops,
  865. };
  866. static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
  867. .registered = ov6650_video_probe,
  868. };
  869. /*
  870. * i2c_driver function
  871. */
  872. static int ov6650_probe(struct i2c_client *client,
  873. const struct i2c_device_id *did)
  874. {
  875. struct ov6650 *priv;
  876. int ret;
  877. priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
  878. if (!priv)
  879. return -ENOMEM;
  880. v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
  881. v4l2_ctrl_handler_init(&priv->hdl, 13);
  882. v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  883. V4L2_CID_VFLIP, 0, 1, 1, 0);
  884. v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  885. V4L2_CID_HFLIP, 0, 1, 1, 0);
  886. priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  887. V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
  888. priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  889. V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
  890. priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  891. V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
  892. priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  893. V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
  894. priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  895. V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
  896. v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  897. V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
  898. v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  899. V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
  900. v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  901. V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
  902. priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
  903. &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
  904. V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
  905. priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  906. V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
  907. v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
  908. V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
  909. priv->subdev.ctrl_handler = &priv->hdl;
  910. if (priv->hdl.error) {
  911. ret = priv->hdl.error;
  912. goto ectlhdlfree;
  913. }
  914. v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
  915. v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
  916. v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
  917. V4L2_EXPOSURE_MANUAL, true);
  918. priv->rect.left = DEF_HSTRT << 1;
  919. priv->rect.top = DEF_VSTRT << 1;
  920. priv->rect.width = W_CIF;
  921. priv->rect.height = H_CIF;
  922. /* Hardware default frame interval */
  923. priv->tpf.numerator = GET_CLKRC_DIV(DEF_CLKRC);
  924. priv->tpf.denominator = FRAME_RATE_MAX;
  925. priv->subdev.internal_ops = &ov6650_internal_ops;
  926. ret = v4l2_async_register_subdev(&priv->subdev);
  927. if (!ret)
  928. return 0;
  929. ectlhdlfree:
  930. v4l2_ctrl_handler_free(&priv->hdl);
  931. return ret;
  932. }
  933. static void ov6650_remove(struct i2c_client *client)
  934. {
  935. struct ov6650 *priv = to_ov6650(client);
  936. v4l2_async_unregister_subdev(&priv->subdev);
  937. v4l2_ctrl_handler_free(&priv->hdl);
  938. }
  939. static const struct i2c_device_id ov6650_id[] = {
  940. { "ov6650", 0 },
  941. { }
  942. };
  943. MODULE_DEVICE_TABLE(i2c, ov6650_id);
  944. static struct i2c_driver ov6650_i2c_driver = {
  945. .driver = {
  946. .name = "ov6650",
  947. },
  948. .probe = ov6650_probe,
  949. .remove = ov6650_remove,
  950. .id_table = ov6650_id,
  951. };
  952. module_i2c_driver(ov6650_i2c_driver);
  953. MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor");
  954. MODULE_AUTHOR("Janusz Krzysztofik <[email protected]");
  955. MODULE_LICENSE("GPL v2");