ov2659.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Omnivision OV2659 CMOS Image Sensor driver
  4. *
  5. * Copyright (C) 2015 Texas Instruments, Inc.
  6. *
  7. * Benoit Parrot <[email protected]>
  8. * Lad, Prabhakar <[email protected]>
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/i2c.h>
  14. #include <linux/module.h>
  15. #include <linux/of_graph.h>
  16. #include <linux/pm_runtime.h>
  17. #include <media/i2c/ov2659.h>
  18. #include <media/v4l2-ctrls.h>
  19. #include <media/v4l2-event.h>
  20. #include <media/v4l2-fwnode.h>
  21. #include <media/v4l2-image-sizes.h>
  22. #include <media/v4l2-subdev.h>
  23. #define DRIVER_NAME "ov2659"
  24. /*
  25. * OV2659 register definitions
  26. */
  27. #define REG_SOFTWARE_STANDBY 0x0100
  28. #define REG_SOFTWARE_RESET 0x0103
  29. #define REG_IO_CTRL00 0x3000
  30. #define REG_IO_CTRL01 0x3001
  31. #define REG_IO_CTRL02 0x3002
  32. #define REG_OUTPUT_VALUE00 0x3008
  33. #define REG_OUTPUT_VALUE01 0x3009
  34. #define REG_OUTPUT_VALUE02 0x300d
  35. #define REG_OUTPUT_SELECT00 0x300e
  36. #define REG_OUTPUT_SELECT01 0x300f
  37. #define REG_OUTPUT_SELECT02 0x3010
  38. #define REG_OUTPUT_DRIVE 0x3011
  39. #define REG_INPUT_READOUT00 0x302d
  40. #define REG_INPUT_READOUT01 0x302e
  41. #define REG_INPUT_READOUT02 0x302f
  42. #define REG_SC_PLL_CTRL0 0x3003
  43. #define REG_SC_PLL_CTRL1 0x3004
  44. #define REG_SC_PLL_CTRL2 0x3005
  45. #define REG_SC_PLL_CTRL3 0x3006
  46. #define REG_SC_CHIP_ID_H 0x300a
  47. #define REG_SC_CHIP_ID_L 0x300b
  48. #define REG_SC_PWC 0x3014
  49. #define REG_SC_CLKRST0 0x301a
  50. #define REG_SC_CLKRST1 0x301b
  51. #define REG_SC_CLKRST2 0x301c
  52. #define REG_SC_CLKRST3 0x301d
  53. #define REG_SC_SUB_ID 0x302a
  54. #define REG_SC_SCCB_ID 0x302b
  55. #define REG_GROUP_ADDRESS_00 0x3200
  56. #define REG_GROUP_ADDRESS_01 0x3201
  57. #define REG_GROUP_ADDRESS_02 0x3202
  58. #define REG_GROUP_ADDRESS_03 0x3203
  59. #define REG_GROUP_ACCESS 0x3208
  60. #define REG_AWB_R_GAIN_H 0x3400
  61. #define REG_AWB_R_GAIN_L 0x3401
  62. #define REG_AWB_G_GAIN_H 0x3402
  63. #define REG_AWB_G_GAIN_L 0x3403
  64. #define REG_AWB_B_GAIN_H 0x3404
  65. #define REG_AWB_B_GAIN_L 0x3405
  66. #define REG_AWB_MANUAL_CONTROL 0x3406
  67. #define REG_TIMING_HS_H 0x3800
  68. #define REG_TIMING_HS_L 0x3801
  69. #define REG_TIMING_VS_H 0x3802
  70. #define REG_TIMING_VS_L 0x3803
  71. #define REG_TIMING_HW_H 0x3804
  72. #define REG_TIMING_HW_L 0x3805
  73. #define REG_TIMING_VH_H 0x3806
  74. #define REG_TIMING_VH_L 0x3807
  75. #define REG_TIMING_DVPHO_H 0x3808
  76. #define REG_TIMING_DVPHO_L 0x3809
  77. #define REG_TIMING_DVPVO_H 0x380a
  78. #define REG_TIMING_DVPVO_L 0x380b
  79. #define REG_TIMING_HTS_H 0x380c
  80. #define REG_TIMING_HTS_L 0x380d
  81. #define REG_TIMING_VTS_H 0x380e
  82. #define REG_TIMING_VTS_L 0x380f
  83. #define REG_TIMING_HOFFS_H 0x3810
  84. #define REG_TIMING_HOFFS_L 0x3811
  85. #define REG_TIMING_VOFFS_H 0x3812
  86. #define REG_TIMING_VOFFS_L 0x3813
  87. #define REG_TIMING_XINC 0x3814
  88. #define REG_TIMING_YINC 0x3815
  89. #define REG_TIMING_VERT_FORMAT 0x3820
  90. #define REG_TIMING_HORIZ_FORMAT 0x3821
  91. #define REG_FORMAT_CTRL00 0x4300
  92. #define REG_VFIFO_READ_START_H 0x4608
  93. #define REG_VFIFO_READ_START_L 0x4609
  94. #define REG_DVP_CTRL02 0x4708
  95. #define REG_ISP_CTRL00 0x5000
  96. #define REG_ISP_CTRL01 0x5001
  97. #define REG_ISP_CTRL02 0x5002
  98. #define REG_LENC_RED_X0_H 0x500c
  99. #define REG_LENC_RED_X0_L 0x500d
  100. #define REG_LENC_RED_Y0_H 0x500e
  101. #define REG_LENC_RED_Y0_L 0x500f
  102. #define REG_LENC_RED_A1 0x5010
  103. #define REG_LENC_RED_B1 0x5011
  104. #define REG_LENC_RED_A2_B2 0x5012
  105. #define REG_LENC_GREEN_X0_H 0x5013
  106. #define REG_LENC_GREEN_X0_L 0x5014
  107. #define REG_LENC_GREEN_Y0_H 0x5015
  108. #define REG_LENC_GREEN_Y0_L 0x5016
  109. #define REG_LENC_GREEN_A1 0x5017
  110. #define REG_LENC_GREEN_B1 0x5018
  111. #define REG_LENC_GREEN_A2_B2 0x5019
  112. #define REG_LENC_BLUE_X0_H 0x501a
  113. #define REG_LENC_BLUE_X0_L 0x501b
  114. #define REG_LENC_BLUE_Y0_H 0x501c
  115. #define REG_LENC_BLUE_Y0_L 0x501d
  116. #define REG_LENC_BLUE_A1 0x501e
  117. #define REG_LENC_BLUE_B1 0x501f
  118. #define REG_LENC_BLUE_A2_B2 0x5020
  119. #define REG_AWB_CTRL00 0x5035
  120. #define REG_AWB_CTRL01 0x5036
  121. #define REG_AWB_CTRL02 0x5037
  122. #define REG_AWB_CTRL03 0x5038
  123. #define REG_AWB_CTRL04 0x5039
  124. #define REG_AWB_LOCAL_LIMIT 0x503a
  125. #define REG_AWB_CTRL12 0x5049
  126. #define REG_AWB_CTRL13 0x504a
  127. #define REG_AWB_CTRL14 0x504b
  128. #define REG_SHARPENMT_THRESH1 0x5064
  129. #define REG_SHARPENMT_THRESH2 0x5065
  130. #define REG_SHARPENMT_OFFSET1 0x5066
  131. #define REG_SHARPENMT_OFFSET2 0x5067
  132. #define REG_DENOISE_THRESH1 0x5068
  133. #define REG_DENOISE_THRESH2 0x5069
  134. #define REG_DENOISE_OFFSET1 0x506a
  135. #define REG_DENOISE_OFFSET2 0x506b
  136. #define REG_SHARPEN_THRESH1 0x506c
  137. #define REG_SHARPEN_THRESH2 0x506d
  138. #define REG_CIP_CTRL00 0x506e
  139. #define REG_CIP_CTRL01 0x506f
  140. #define REG_CMX_SIGN 0x5079
  141. #define REG_CMX_MISC_CTRL 0x507a
  142. #define REG_PRE_ISP_CTRL00 0x50a0
  143. #define TEST_PATTERN_ENABLE BIT(7)
  144. #define VERTICAL_COLOR_BAR_MASK 0x53
  145. #define REG_NULL 0x0000 /* Array end token */
  146. #define OV265X_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
  147. #define OV2659_ID 0x2656
  148. struct sensor_register {
  149. u16 addr;
  150. u8 value;
  151. };
  152. struct ov2659_framesize {
  153. u16 width;
  154. u16 height;
  155. u16 max_exp_lines;
  156. const struct sensor_register *regs;
  157. };
  158. struct ov2659_pll_ctrl {
  159. u8 ctrl1;
  160. u8 ctrl2;
  161. u8 ctrl3;
  162. };
  163. struct ov2659_pixfmt {
  164. u32 code;
  165. /* Output format Register Value (REG_FORMAT_CTRL00) */
  166. struct sensor_register *format_ctrl_regs;
  167. };
  168. struct pll_ctrl_reg {
  169. unsigned int div;
  170. unsigned char reg;
  171. };
  172. struct ov2659 {
  173. struct v4l2_subdev sd;
  174. struct media_pad pad;
  175. struct v4l2_mbus_framefmt format;
  176. unsigned int xvclk_frequency;
  177. const struct ov2659_platform_data *pdata;
  178. struct mutex lock;
  179. struct i2c_client *client;
  180. struct v4l2_ctrl_handler ctrls;
  181. struct v4l2_ctrl *link_frequency;
  182. struct clk *clk;
  183. const struct ov2659_framesize *frame_size;
  184. struct sensor_register *format_ctrl_regs;
  185. struct ov2659_pll_ctrl pll;
  186. int streaming;
  187. /* used to control the sensor PWDN pin */
  188. struct gpio_desc *pwdn_gpio;
  189. /* used to control the sensor RESETB pin */
  190. struct gpio_desc *resetb_gpio;
  191. };
  192. static const struct sensor_register ov2659_init_regs[] = {
  193. { REG_IO_CTRL00, 0x03 },
  194. { REG_IO_CTRL01, 0xff },
  195. { REG_IO_CTRL02, 0xe0 },
  196. { 0x3633, 0x3d },
  197. { 0x3620, 0x02 },
  198. { 0x3631, 0x11 },
  199. { 0x3612, 0x04 },
  200. { 0x3630, 0x20 },
  201. { 0x4702, 0x02 },
  202. { 0x370c, 0x34 },
  203. { REG_TIMING_HS_H, 0x00 },
  204. { REG_TIMING_HS_L, 0x00 },
  205. { REG_TIMING_VS_H, 0x00 },
  206. { REG_TIMING_VS_L, 0x00 },
  207. { REG_TIMING_HW_H, 0x06 },
  208. { REG_TIMING_HW_L, 0x5f },
  209. { REG_TIMING_VH_H, 0x04 },
  210. { REG_TIMING_VH_L, 0xb7 },
  211. { REG_TIMING_DVPHO_H, 0x03 },
  212. { REG_TIMING_DVPHO_L, 0x20 },
  213. { REG_TIMING_DVPVO_H, 0x02 },
  214. { REG_TIMING_DVPVO_L, 0x58 },
  215. { REG_TIMING_HTS_H, 0x05 },
  216. { REG_TIMING_HTS_L, 0x14 },
  217. { REG_TIMING_VTS_H, 0x02 },
  218. { REG_TIMING_VTS_L, 0x68 },
  219. { REG_TIMING_HOFFS_L, 0x08 },
  220. { REG_TIMING_VOFFS_L, 0x02 },
  221. { REG_TIMING_XINC, 0x31 },
  222. { REG_TIMING_YINC, 0x31 },
  223. { 0x3a02, 0x02 },
  224. { 0x3a03, 0x68 },
  225. { 0x3a08, 0x00 },
  226. { 0x3a09, 0x5c },
  227. { 0x3a0a, 0x00 },
  228. { 0x3a0b, 0x4d },
  229. { 0x3a0d, 0x08 },
  230. { 0x3a0e, 0x06 },
  231. { 0x3a14, 0x02 },
  232. { 0x3a15, 0x28 },
  233. { REG_DVP_CTRL02, 0x01 },
  234. { 0x3623, 0x00 },
  235. { 0x3634, 0x76 },
  236. { 0x3701, 0x44 },
  237. { 0x3702, 0x18 },
  238. { 0x3703, 0x24 },
  239. { 0x3704, 0x24 },
  240. { 0x3705, 0x0c },
  241. { REG_TIMING_VERT_FORMAT, 0x81 },
  242. { REG_TIMING_HORIZ_FORMAT, 0x01 },
  243. { 0x370a, 0x52 },
  244. { REG_VFIFO_READ_START_H, 0x00 },
  245. { REG_VFIFO_READ_START_L, 0x80 },
  246. { REG_FORMAT_CTRL00, 0x30 },
  247. { 0x5086, 0x02 },
  248. { REG_ISP_CTRL00, 0xfb },
  249. { REG_ISP_CTRL01, 0x1f },
  250. { REG_ISP_CTRL02, 0x00 },
  251. { 0x5025, 0x0e },
  252. { 0x5026, 0x18 },
  253. { 0x5027, 0x34 },
  254. { 0x5028, 0x4c },
  255. { 0x5029, 0x62 },
  256. { 0x502a, 0x74 },
  257. { 0x502b, 0x85 },
  258. { 0x502c, 0x92 },
  259. { 0x502d, 0x9e },
  260. { 0x502e, 0xb2 },
  261. { 0x502f, 0xc0 },
  262. { 0x5030, 0xcc },
  263. { 0x5031, 0xe0 },
  264. { 0x5032, 0xee },
  265. { 0x5033, 0xf6 },
  266. { 0x5034, 0x11 },
  267. { 0x5070, 0x1c },
  268. { 0x5071, 0x5b },
  269. { 0x5072, 0x05 },
  270. { 0x5073, 0x20 },
  271. { 0x5074, 0x94 },
  272. { 0x5075, 0xb4 },
  273. { 0x5076, 0xb4 },
  274. { 0x5077, 0xaf },
  275. { 0x5078, 0x05 },
  276. { REG_CMX_SIGN, 0x98 },
  277. { REG_CMX_MISC_CTRL, 0x21 },
  278. { REG_AWB_CTRL00, 0x6a },
  279. { REG_AWB_CTRL01, 0x11 },
  280. { REG_AWB_CTRL02, 0x92 },
  281. { REG_AWB_CTRL03, 0x21 },
  282. { REG_AWB_CTRL04, 0xe1 },
  283. { REG_AWB_LOCAL_LIMIT, 0x01 },
  284. { 0x503c, 0x05 },
  285. { 0x503d, 0x08 },
  286. { 0x503e, 0x08 },
  287. { 0x503f, 0x64 },
  288. { 0x5040, 0x58 },
  289. { 0x5041, 0x2a },
  290. { 0x5042, 0xc5 },
  291. { 0x5043, 0x2e },
  292. { 0x5044, 0x3a },
  293. { 0x5045, 0x3c },
  294. { 0x5046, 0x44 },
  295. { 0x5047, 0xf8 },
  296. { 0x5048, 0x08 },
  297. { REG_AWB_CTRL12, 0x70 },
  298. { REG_AWB_CTRL13, 0xf0 },
  299. { REG_AWB_CTRL14, 0xf0 },
  300. { REG_LENC_RED_X0_H, 0x03 },
  301. { REG_LENC_RED_X0_L, 0x20 },
  302. { REG_LENC_RED_Y0_H, 0x02 },
  303. { REG_LENC_RED_Y0_L, 0x5c },
  304. { REG_LENC_RED_A1, 0x48 },
  305. { REG_LENC_RED_B1, 0x00 },
  306. { REG_LENC_RED_A2_B2, 0x66 },
  307. { REG_LENC_GREEN_X0_H, 0x03 },
  308. { REG_LENC_GREEN_X0_L, 0x30 },
  309. { REG_LENC_GREEN_Y0_H, 0x02 },
  310. { REG_LENC_GREEN_Y0_L, 0x7c },
  311. { REG_LENC_GREEN_A1, 0x40 },
  312. { REG_LENC_GREEN_B1, 0x00 },
  313. { REG_LENC_GREEN_A2_B2, 0x66 },
  314. { REG_LENC_BLUE_X0_H, 0x03 },
  315. { REG_LENC_BLUE_X0_L, 0x10 },
  316. { REG_LENC_BLUE_Y0_H, 0x02 },
  317. { REG_LENC_BLUE_Y0_L, 0x7c },
  318. { REG_LENC_BLUE_A1, 0x3a },
  319. { REG_LENC_BLUE_B1, 0x00 },
  320. { REG_LENC_BLUE_A2_B2, 0x66 },
  321. { REG_CIP_CTRL00, 0x44 },
  322. { REG_SHARPENMT_THRESH1, 0x08 },
  323. { REG_SHARPENMT_THRESH2, 0x10 },
  324. { REG_SHARPENMT_OFFSET1, 0x12 },
  325. { REG_SHARPENMT_OFFSET2, 0x02 },
  326. { REG_SHARPEN_THRESH1, 0x08 },
  327. { REG_SHARPEN_THRESH2, 0x10 },
  328. { REG_CIP_CTRL01, 0xa6 },
  329. { REG_DENOISE_THRESH1, 0x08 },
  330. { REG_DENOISE_THRESH2, 0x10 },
  331. { REG_DENOISE_OFFSET1, 0x04 },
  332. { REG_DENOISE_OFFSET2, 0x12 },
  333. { 0x507e, 0x40 },
  334. { 0x507f, 0x20 },
  335. { 0x507b, 0x02 },
  336. { REG_CMX_MISC_CTRL, 0x01 },
  337. { 0x5084, 0x0c },
  338. { 0x5085, 0x3e },
  339. { 0x5005, 0x80 },
  340. { 0x3a0f, 0x30 },
  341. { 0x3a10, 0x28 },
  342. { 0x3a1b, 0x32 },
  343. { 0x3a1e, 0x26 },
  344. { 0x3a11, 0x60 },
  345. { 0x3a1f, 0x14 },
  346. { 0x5060, 0x69 },
  347. { 0x5061, 0x7d },
  348. { 0x5062, 0x7d },
  349. { 0x5063, 0x69 },
  350. { REG_NULL, 0x00 },
  351. };
  352. /* 1280X720 720p */
  353. static struct sensor_register ov2659_720p[] = {
  354. { REG_TIMING_HS_H, 0x00 },
  355. { REG_TIMING_HS_L, 0xa0 },
  356. { REG_TIMING_VS_H, 0x00 },
  357. { REG_TIMING_VS_L, 0xf0 },
  358. { REG_TIMING_HW_H, 0x05 },
  359. { REG_TIMING_HW_L, 0xbf },
  360. { REG_TIMING_VH_H, 0x03 },
  361. { REG_TIMING_VH_L, 0xcb },
  362. { REG_TIMING_DVPHO_H, 0x05 },
  363. { REG_TIMING_DVPHO_L, 0x00 },
  364. { REG_TIMING_DVPVO_H, 0x02 },
  365. { REG_TIMING_DVPVO_L, 0xd0 },
  366. { REG_TIMING_HTS_H, 0x06 },
  367. { REG_TIMING_HTS_L, 0x4c },
  368. { REG_TIMING_VTS_H, 0x02 },
  369. { REG_TIMING_VTS_L, 0xe8 },
  370. { REG_TIMING_HOFFS_L, 0x10 },
  371. { REG_TIMING_VOFFS_L, 0x06 },
  372. { REG_TIMING_XINC, 0x11 },
  373. { REG_TIMING_YINC, 0x11 },
  374. { REG_TIMING_VERT_FORMAT, 0x80 },
  375. { REG_TIMING_HORIZ_FORMAT, 0x00 },
  376. { 0x370a, 0x12 },
  377. { 0x3a03, 0xe8 },
  378. { 0x3a09, 0x6f },
  379. { 0x3a0b, 0x5d },
  380. { 0x3a15, 0x9a },
  381. { REG_VFIFO_READ_START_H, 0x00 },
  382. { REG_VFIFO_READ_START_L, 0x80 },
  383. { REG_ISP_CTRL02, 0x00 },
  384. { REG_NULL, 0x00 },
  385. };
  386. /* 1600X1200 UXGA */
  387. static struct sensor_register ov2659_uxga[] = {
  388. { REG_TIMING_HS_H, 0x00 },
  389. { REG_TIMING_HS_L, 0x00 },
  390. { REG_TIMING_VS_H, 0x00 },
  391. { REG_TIMING_VS_L, 0x00 },
  392. { REG_TIMING_HW_H, 0x06 },
  393. { REG_TIMING_HW_L, 0x5f },
  394. { REG_TIMING_VH_H, 0x04 },
  395. { REG_TIMING_VH_L, 0xbb },
  396. { REG_TIMING_DVPHO_H, 0x06 },
  397. { REG_TIMING_DVPHO_L, 0x40 },
  398. { REG_TIMING_DVPVO_H, 0x04 },
  399. { REG_TIMING_DVPVO_L, 0xb0 },
  400. { REG_TIMING_HTS_H, 0x07 },
  401. { REG_TIMING_HTS_L, 0x9f },
  402. { REG_TIMING_VTS_H, 0x04 },
  403. { REG_TIMING_VTS_L, 0xd0 },
  404. { REG_TIMING_HOFFS_L, 0x10 },
  405. { REG_TIMING_VOFFS_L, 0x06 },
  406. { REG_TIMING_XINC, 0x11 },
  407. { REG_TIMING_YINC, 0x11 },
  408. { 0x3a02, 0x04 },
  409. { 0x3a03, 0xd0 },
  410. { 0x3a08, 0x00 },
  411. { 0x3a09, 0xb8 },
  412. { 0x3a0a, 0x00 },
  413. { 0x3a0b, 0x9a },
  414. { 0x3a0d, 0x08 },
  415. { 0x3a0e, 0x06 },
  416. { 0x3a14, 0x04 },
  417. { 0x3a15, 0x50 },
  418. { 0x3623, 0x00 },
  419. { 0x3634, 0x44 },
  420. { 0x3701, 0x44 },
  421. { 0x3702, 0x30 },
  422. { 0x3703, 0x48 },
  423. { 0x3704, 0x48 },
  424. { 0x3705, 0x18 },
  425. { REG_TIMING_VERT_FORMAT, 0x80 },
  426. { REG_TIMING_HORIZ_FORMAT, 0x00 },
  427. { 0x370a, 0x12 },
  428. { REG_VFIFO_READ_START_H, 0x00 },
  429. { REG_VFIFO_READ_START_L, 0x80 },
  430. { REG_ISP_CTRL02, 0x00 },
  431. { REG_NULL, 0x00 },
  432. };
  433. /* 1280X1024 SXGA */
  434. static struct sensor_register ov2659_sxga[] = {
  435. { REG_TIMING_HS_H, 0x00 },
  436. { REG_TIMING_HS_L, 0x00 },
  437. { REG_TIMING_VS_H, 0x00 },
  438. { REG_TIMING_VS_L, 0x00 },
  439. { REG_TIMING_HW_H, 0x06 },
  440. { REG_TIMING_HW_L, 0x5f },
  441. { REG_TIMING_VH_H, 0x04 },
  442. { REG_TIMING_VH_L, 0xb7 },
  443. { REG_TIMING_DVPHO_H, 0x05 },
  444. { REG_TIMING_DVPHO_L, 0x00 },
  445. { REG_TIMING_DVPVO_H, 0x04 },
  446. { REG_TIMING_DVPVO_L, 0x00 },
  447. { REG_TIMING_HTS_H, 0x07 },
  448. { REG_TIMING_HTS_L, 0x9c },
  449. { REG_TIMING_VTS_H, 0x04 },
  450. { REG_TIMING_VTS_L, 0xd0 },
  451. { REG_TIMING_HOFFS_L, 0x10 },
  452. { REG_TIMING_VOFFS_L, 0x06 },
  453. { REG_TIMING_XINC, 0x11 },
  454. { REG_TIMING_YINC, 0x11 },
  455. { 0x3a02, 0x02 },
  456. { 0x3a03, 0x68 },
  457. { 0x3a08, 0x00 },
  458. { 0x3a09, 0x5c },
  459. { 0x3a0a, 0x00 },
  460. { 0x3a0b, 0x4d },
  461. { 0x3a0d, 0x08 },
  462. { 0x3a0e, 0x06 },
  463. { 0x3a14, 0x02 },
  464. { 0x3a15, 0x28 },
  465. { 0x3623, 0x00 },
  466. { 0x3634, 0x76 },
  467. { 0x3701, 0x44 },
  468. { 0x3702, 0x18 },
  469. { 0x3703, 0x24 },
  470. { 0x3704, 0x24 },
  471. { 0x3705, 0x0c },
  472. { REG_TIMING_VERT_FORMAT, 0x80 },
  473. { REG_TIMING_HORIZ_FORMAT, 0x00 },
  474. { 0x370a, 0x52 },
  475. { REG_VFIFO_READ_START_H, 0x00 },
  476. { REG_VFIFO_READ_START_L, 0x80 },
  477. { REG_ISP_CTRL02, 0x00 },
  478. { REG_NULL, 0x00 },
  479. };
  480. /* 1024X768 SXGA */
  481. static struct sensor_register ov2659_xga[] = {
  482. { REG_TIMING_HS_H, 0x00 },
  483. { REG_TIMING_HS_L, 0x00 },
  484. { REG_TIMING_VS_H, 0x00 },
  485. { REG_TIMING_VS_L, 0x00 },
  486. { REG_TIMING_HW_H, 0x06 },
  487. { REG_TIMING_HW_L, 0x5f },
  488. { REG_TIMING_VH_H, 0x04 },
  489. { REG_TIMING_VH_L, 0xb7 },
  490. { REG_TIMING_DVPHO_H, 0x04 },
  491. { REG_TIMING_DVPHO_L, 0x00 },
  492. { REG_TIMING_DVPVO_H, 0x03 },
  493. { REG_TIMING_DVPVO_L, 0x00 },
  494. { REG_TIMING_HTS_H, 0x07 },
  495. { REG_TIMING_HTS_L, 0x9c },
  496. { REG_TIMING_VTS_H, 0x04 },
  497. { REG_TIMING_VTS_L, 0xd0 },
  498. { REG_TIMING_HOFFS_L, 0x10 },
  499. { REG_TIMING_VOFFS_L, 0x06 },
  500. { REG_TIMING_XINC, 0x11 },
  501. { REG_TIMING_YINC, 0x11 },
  502. { 0x3a02, 0x02 },
  503. { 0x3a03, 0x68 },
  504. { 0x3a08, 0x00 },
  505. { 0x3a09, 0x5c },
  506. { 0x3a0a, 0x00 },
  507. { 0x3a0b, 0x4d },
  508. { 0x3a0d, 0x08 },
  509. { 0x3a0e, 0x06 },
  510. { 0x3a14, 0x02 },
  511. { 0x3a15, 0x28 },
  512. { 0x3623, 0x00 },
  513. { 0x3634, 0x76 },
  514. { 0x3701, 0x44 },
  515. { 0x3702, 0x18 },
  516. { 0x3703, 0x24 },
  517. { 0x3704, 0x24 },
  518. { 0x3705, 0x0c },
  519. { REG_TIMING_VERT_FORMAT, 0x80 },
  520. { REG_TIMING_HORIZ_FORMAT, 0x00 },
  521. { 0x370a, 0x52 },
  522. { REG_VFIFO_READ_START_H, 0x00 },
  523. { REG_VFIFO_READ_START_L, 0x80 },
  524. { REG_ISP_CTRL02, 0x00 },
  525. { REG_NULL, 0x00 },
  526. };
  527. /* 800X600 SVGA */
  528. static struct sensor_register ov2659_svga[] = {
  529. { REG_TIMING_HS_H, 0x00 },
  530. { REG_TIMING_HS_L, 0x00 },
  531. { REG_TIMING_VS_H, 0x00 },
  532. { REG_TIMING_VS_L, 0x00 },
  533. { REG_TIMING_HW_H, 0x06 },
  534. { REG_TIMING_HW_L, 0x5f },
  535. { REG_TIMING_VH_H, 0x04 },
  536. { REG_TIMING_VH_L, 0xb7 },
  537. { REG_TIMING_DVPHO_H, 0x03 },
  538. { REG_TIMING_DVPHO_L, 0x20 },
  539. { REG_TIMING_DVPVO_H, 0x02 },
  540. { REG_TIMING_DVPVO_L, 0x58 },
  541. { REG_TIMING_HTS_H, 0x05 },
  542. { REG_TIMING_HTS_L, 0x14 },
  543. { REG_TIMING_VTS_H, 0x02 },
  544. { REG_TIMING_VTS_L, 0x68 },
  545. { REG_TIMING_HOFFS_L, 0x08 },
  546. { REG_TIMING_VOFFS_L, 0x02 },
  547. { REG_TIMING_XINC, 0x31 },
  548. { REG_TIMING_YINC, 0x31 },
  549. { 0x3a02, 0x02 },
  550. { 0x3a03, 0x68 },
  551. { 0x3a08, 0x00 },
  552. { 0x3a09, 0x5c },
  553. { 0x3a0a, 0x00 },
  554. { 0x3a0b, 0x4d },
  555. { 0x3a0d, 0x08 },
  556. { 0x3a0e, 0x06 },
  557. { 0x3a14, 0x02 },
  558. { 0x3a15, 0x28 },
  559. { 0x3623, 0x00 },
  560. { 0x3634, 0x76 },
  561. { 0x3701, 0x44 },
  562. { 0x3702, 0x18 },
  563. { 0x3703, 0x24 },
  564. { 0x3704, 0x24 },
  565. { 0x3705, 0x0c },
  566. { REG_TIMING_VERT_FORMAT, 0x81 },
  567. { REG_TIMING_HORIZ_FORMAT, 0x01 },
  568. { 0x370a, 0x52 },
  569. { REG_VFIFO_READ_START_H, 0x00 },
  570. { REG_VFIFO_READ_START_L, 0x80 },
  571. { REG_ISP_CTRL02, 0x00 },
  572. { REG_NULL, 0x00 },
  573. };
  574. /* 640X480 VGA */
  575. static struct sensor_register ov2659_vga[] = {
  576. { REG_TIMING_HS_H, 0x00 },
  577. { REG_TIMING_HS_L, 0x00 },
  578. { REG_TIMING_VS_H, 0x00 },
  579. { REG_TIMING_VS_L, 0x00 },
  580. { REG_TIMING_HW_H, 0x06 },
  581. { REG_TIMING_HW_L, 0x5f },
  582. { REG_TIMING_VH_H, 0x04 },
  583. { REG_TIMING_VH_L, 0xb7 },
  584. { REG_TIMING_DVPHO_H, 0x02 },
  585. { REG_TIMING_DVPHO_L, 0x80 },
  586. { REG_TIMING_DVPVO_H, 0x01 },
  587. { REG_TIMING_DVPVO_L, 0xe0 },
  588. { REG_TIMING_HTS_H, 0x05 },
  589. { REG_TIMING_HTS_L, 0x14 },
  590. { REG_TIMING_VTS_H, 0x02 },
  591. { REG_TIMING_VTS_L, 0x68 },
  592. { REG_TIMING_HOFFS_L, 0x08 },
  593. { REG_TIMING_VOFFS_L, 0x02 },
  594. { REG_TIMING_XINC, 0x31 },
  595. { REG_TIMING_YINC, 0x31 },
  596. { 0x3a02, 0x02 },
  597. { 0x3a03, 0x68 },
  598. { 0x3a08, 0x00 },
  599. { 0x3a09, 0x5c },
  600. { 0x3a0a, 0x00 },
  601. { 0x3a0b, 0x4d },
  602. { 0x3a0d, 0x08 },
  603. { 0x3a0e, 0x06 },
  604. { 0x3a14, 0x02 },
  605. { 0x3a15, 0x28 },
  606. { 0x3623, 0x00 },
  607. { 0x3634, 0x76 },
  608. { 0x3701, 0x44 },
  609. { 0x3702, 0x18 },
  610. { 0x3703, 0x24 },
  611. { 0x3704, 0x24 },
  612. { 0x3705, 0x0c },
  613. { REG_TIMING_VERT_FORMAT, 0x81 },
  614. { REG_TIMING_HORIZ_FORMAT, 0x01 },
  615. { 0x370a, 0x52 },
  616. { REG_VFIFO_READ_START_H, 0x00 },
  617. { REG_VFIFO_READ_START_L, 0xa0 },
  618. { REG_ISP_CTRL02, 0x10 },
  619. { REG_NULL, 0x00 },
  620. };
  621. /* 320X240 QVGA */
  622. static struct sensor_register ov2659_qvga[] = {
  623. { REG_TIMING_HS_H, 0x00 },
  624. { REG_TIMING_HS_L, 0x00 },
  625. { REG_TIMING_VS_H, 0x00 },
  626. { REG_TIMING_VS_L, 0x00 },
  627. { REG_TIMING_HW_H, 0x06 },
  628. { REG_TIMING_HW_L, 0x5f },
  629. { REG_TIMING_VH_H, 0x04 },
  630. { REG_TIMING_VH_L, 0xb7 },
  631. { REG_TIMING_DVPHO_H, 0x01 },
  632. { REG_TIMING_DVPHO_L, 0x40 },
  633. { REG_TIMING_DVPVO_H, 0x00 },
  634. { REG_TIMING_DVPVO_L, 0xf0 },
  635. { REG_TIMING_HTS_H, 0x05 },
  636. { REG_TIMING_HTS_L, 0x14 },
  637. { REG_TIMING_VTS_H, 0x02 },
  638. { REG_TIMING_VTS_L, 0x68 },
  639. { REG_TIMING_HOFFS_L, 0x08 },
  640. { REG_TIMING_VOFFS_L, 0x02 },
  641. { REG_TIMING_XINC, 0x31 },
  642. { REG_TIMING_YINC, 0x31 },
  643. { 0x3a02, 0x02 },
  644. { 0x3a03, 0x68 },
  645. { 0x3a08, 0x00 },
  646. { 0x3a09, 0x5c },
  647. { 0x3a0a, 0x00 },
  648. { 0x3a0b, 0x4d },
  649. { 0x3a0d, 0x08 },
  650. { 0x3a0e, 0x06 },
  651. { 0x3a14, 0x02 },
  652. { 0x3a15, 0x28 },
  653. { 0x3623, 0x00 },
  654. { 0x3634, 0x76 },
  655. { 0x3701, 0x44 },
  656. { 0x3702, 0x18 },
  657. { 0x3703, 0x24 },
  658. { 0x3704, 0x24 },
  659. { 0x3705, 0x0c },
  660. { REG_TIMING_VERT_FORMAT, 0x81 },
  661. { REG_TIMING_HORIZ_FORMAT, 0x01 },
  662. { 0x370a, 0x52 },
  663. { REG_VFIFO_READ_START_H, 0x00 },
  664. { REG_VFIFO_READ_START_L, 0xa0 },
  665. { REG_ISP_CTRL02, 0x10 },
  666. { REG_NULL, 0x00 },
  667. };
  668. static const struct pll_ctrl_reg ctrl3[] = {
  669. { 1, 0x00 },
  670. { 2, 0x02 },
  671. { 3, 0x03 },
  672. { 4, 0x06 },
  673. { 6, 0x0d },
  674. { 8, 0x0e },
  675. { 12, 0x0f },
  676. { 16, 0x12 },
  677. { 24, 0x13 },
  678. { 32, 0x16 },
  679. { 48, 0x1b },
  680. { 64, 0x1e },
  681. { 96, 0x1f },
  682. { 0, 0x00 },
  683. };
  684. static const struct pll_ctrl_reg ctrl1[] = {
  685. { 2, 0x10 },
  686. { 4, 0x20 },
  687. { 6, 0x30 },
  688. { 8, 0x40 },
  689. { 10, 0x50 },
  690. { 12, 0x60 },
  691. { 14, 0x70 },
  692. { 16, 0x80 },
  693. { 18, 0x90 },
  694. { 20, 0xa0 },
  695. { 22, 0xb0 },
  696. { 24, 0xc0 },
  697. { 26, 0xd0 },
  698. { 28, 0xe0 },
  699. { 30, 0xf0 },
  700. { 0, 0x00 },
  701. };
  702. static const struct ov2659_framesize ov2659_framesizes[] = {
  703. { /* QVGA */
  704. .width = 320,
  705. .height = 240,
  706. .regs = ov2659_qvga,
  707. .max_exp_lines = 248,
  708. }, { /* VGA */
  709. .width = 640,
  710. .height = 480,
  711. .regs = ov2659_vga,
  712. .max_exp_lines = 498,
  713. }, { /* SVGA */
  714. .width = 800,
  715. .height = 600,
  716. .regs = ov2659_svga,
  717. .max_exp_lines = 498,
  718. }, { /* XGA */
  719. .width = 1024,
  720. .height = 768,
  721. .regs = ov2659_xga,
  722. .max_exp_lines = 498,
  723. }, { /* 720P */
  724. .width = 1280,
  725. .height = 720,
  726. .regs = ov2659_720p,
  727. .max_exp_lines = 498,
  728. }, { /* SXGA */
  729. .width = 1280,
  730. .height = 1024,
  731. .regs = ov2659_sxga,
  732. .max_exp_lines = 1048,
  733. }, { /* UXGA */
  734. .width = 1600,
  735. .height = 1200,
  736. .regs = ov2659_uxga,
  737. .max_exp_lines = 498,
  738. },
  739. };
  740. /* YUV422 YUYV*/
  741. static struct sensor_register ov2659_format_yuyv[] = {
  742. { REG_FORMAT_CTRL00, 0x30 },
  743. { REG_NULL, 0x0 },
  744. };
  745. /* YUV422 UYVY */
  746. static struct sensor_register ov2659_format_uyvy[] = {
  747. { REG_FORMAT_CTRL00, 0x32 },
  748. { REG_NULL, 0x0 },
  749. };
  750. /* Raw Bayer BGGR */
  751. static struct sensor_register ov2659_format_bggr[] = {
  752. { REG_FORMAT_CTRL00, 0x00 },
  753. { REG_NULL, 0x0 },
  754. };
  755. /* RGB565 */
  756. static struct sensor_register ov2659_format_rgb565[] = {
  757. { REG_FORMAT_CTRL00, 0x60 },
  758. { REG_NULL, 0x0 },
  759. };
  760. static const struct ov2659_pixfmt ov2659_formats[] = {
  761. {
  762. .code = MEDIA_BUS_FMT_YUYV8_2X8,
  763. .format_ctrl_regs = ov2659_format_yuyv,
  764. }, {
  765. .code = MEDIA_BUS_FMT_UYVY8_2X8,
  766. .format_ctrl_regs = ov2659_format_uyvy,
  767. }, {
  768. .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
  769. .format_ctrl_regs = ov2659_format_rgb565,
  770. }, {
  771. .code = MEDIA_BUS_FMT_SBGGR8_1X8,
  772. .format_ctrl_regs = ov2659_format_bggr,
  773. },
  774. };
  775. static inline struct ov2659 *to_ov2659(struct v4l2_subdev *sd)
  776. {
  777. return container_of(sd, struct ov2659, sd);
  778. }
  779. /* sensor register write */
  780. static int ov2659_write(struct i2c_client *client, u16 reg, u8 val)
  781. {
  782. struct i2c_msg msg;
  783. u8 buf[3];
  784. int ret;
  785. buf[0] = reg >> 8;
  786. buf[1] = reg & 0xFF;
  787. buf[2] = val;
  788. msg.addr = client->addr;
  789. msg.flags = client->flags;
  790. msg.buf = buf;
  791. msg.len = sizeof(buf);
  792. ret = i2c_transfer(client->adapter, &msg, 1);
  793. if (ret >= 0)
  794. return 0;
  795. dev_dbg(&client->dev,
  796. "ov2659 write reg(0x%x val:0x%x) failed !\n", reg, val);
  797. return ret;
  798. }
  799. /* sensor register read */
  800. static int ov2659_read(struct i2c_client *client, u16 reg, u8 *val)
  801. {
  802. struct i2c_msg msg[2];
  803. u8 buf[2];
  804. int ret;
  805. buf[0] = reg >> 8;
  806. buf[1] = reg & 0xFF;
  807. msg[0].addr = client->addr;
  808. msg[0].flags = client->flags;
  809. msg[0].buf = buf;
  810. msg[0].len = sizeof(buf);
  811. msg[1].addr = client->addr;
  812. msg[1].flags = client->flags | I2C_M_RD;
  813. msg[1].buf = buf;
  814. msg[1].len = 1;
  815. ret = i2c_transfer(client->adapter, msg, 2);
  816. if (ret >= 0) {
  817. *val = buf[0];
  818. return 0;
  819. }
  820. dev_dbg(&client->dev,
  821. "ov2659 read reg(0x%x val:0x%x) failed !\n", reg, *val);
  822. return ret;
  823. }
  824. static int ov2659_write_array(struct i2c_client *client,
  825. const struct sensor_register *regs)
  826. {
  827. int i, ret = 0;
  828. for (i = 0; ret == 0 && regs[i].addr; i++)
  829. ret = ov2659_write(client, regs[i].addr, regs[i].value);
  830. return ret;
  831. }
  832. static void ov2659_pll_calc_params(struct ov2659 *ov2659)
  833. {
  834. const struct ov2659_platform_data *pdata = ov2659->pdata;
  835. u8 ctrl1_reg = 0, ctrl2_reg = 0, ctrl3_reg = 0;
  836. struct i2c_client *client = ov2659->client;
  837. unsigned int desired = pdata->link_frequency;
  838. u32 prediv, postdiv, mult;
  839. u32 bestdelta = -1;
  840. u32 delta, actual;
  841. int i, j;
  842. for (i = 0; ctrl1[i].div != 0; i++) {
  843. postdiv = ctrl1[i].div;
  844. for (j = 0; ctrl3[j].div != 0; j++) {
  845. prediv = ctrl3[j].div;
  846. for (mult = 1; mult <= 63; mult++) {
  847. actual = ov2659->xvclk_frequency;
  848. actual *= mult;
  849. actual /= prediv;
  850. actual /= postdiv;
  851. delta = actual - desired;
  852. delta = abs(delta);
  853. if ((delta < bestdelta) || (bestdelta == -1)) {
  854. bestdelta = delta;
  855. ctrl1_reg = ctrl1[i].reg;
  856. ctrl2_reg = mult;
  857. ctrl3_reg = ctrl3[j].reg;
  858. }
  859. }
  860. }
  861. }
  862. ov2659->pll.ctrl1 = ctrl1_reg;
  863. ov2659->pll.ctrl2 = ctrl2_reg;
  864. ov2659->pll.ctrl3 = ctrl3_reg;
  865. dev_dbg(&client->dev,
  866. "Actual reg config: ctrl1_reg: %02x ctrl2_reg: %02x ctrl3_reg: %02x\n",
  867. ctrl1_reg, ctrl2_reg, ctrl3_reg);
  868. }
  869. static int ov2659_set_pixel_clock(struct ov2659 *ov2659)
  870. {
  871. struct i2c_client *client = ov2659->client;
  872. struct sensor_register pll_regs[] = {
  873. {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
  874. {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
  875. {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
  876. {REG_NULL, 0x00},
  877. };
  878. dev_dbg(&client->dev, "%s\n", __func__);
  879. return ov2659_write_array(client, pll_regs);
  880. };
  881. static void ov2659_get_default_format(struct v4l2_mbus_framefmt *format)
  882. {
  883. format->width = ov2659_framesizes[2].width;
  884. format->height = ov2659_framesizes[2].height;
  885. format->colorspace = V4L2_COLORSPACE_SRGB;
  886. format->code = ov2659_formats[0].code;
  887. format->field = V4L2_FIELD_NONE;
  888. }
  889. static void ov2659_set_streaming(struct ov2659 *ov2659, int on)
  890. {
  891. struct i2c_client *client = ov2659->client;
  892. int ret;
  893. on = !!on;
  894. dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
  895. ret = ov2659_write(client, REG_SOFTWARE_STANDBY, on);
  896. if (ret)
  897. dev_err(&client->dev, "ov2659 soft standby failed\n");
  898. }
  899. static int ov2659_init(struct v4l2_subdev *sd, u32 val)
  900. {
  901. struct i2c_client *client = v4l2_get_subdevdata(sd);
  902. return ov2659_write_array(client, ov2659_init_regs);
  903. }
  904. /*
  905. * V4L2 subdev video and pad level operations
  906. */
  907. static int ov2659_enum_mbus_code(struct v4l2_subdev *sd,
  908. struct v4l2_subdev_state *sd_state,
  909. struct v4l2_subdev_mbus_code_enum *code)
  910. {
  911. struct i2c_client *client = v4l2_get_subdevdata(sd);
  912. dev_dbg(&client->dev, "%s:\n", __func__);
  913. if (code->index >= ARRAY_SIZE(ov2659_formats))
  914. return -EINVAL;
  915. code->code = ov2659_formats[code->index].code;
  916. return 0;
  917. }
  918. static int ov2659_enum_frame_sizes(struct v4l2_subdev *sd,
  919. struct v4l2_subdev_state *sd_state,
  920. struct v4l2_subdev_frame_size_enum *fse)
  921. {
  922. struct i2c_client *client = v4l2_get_subdevdata(sd);
  923. int i = ARRAY_SIZE(ov2659_formats);
  924. dev_dbg(&client->dev, "%s:\n", __func__);
  925. if (fse->index >= ARRAY_SIZE(ov2659_framesizes))
  926. return -EINVAL;
  927. while (--i)
  928. if (fse->code == ov2659_formats[i].code)
  929. break;
  930. fse->code = ov2659_formats[i].code;
  931. fse->min_width = ov2659_framesizes[fse->index].width;
  932. fse->max_width = fse->min_width;
  933. fse->max_height = ov2659_framesizes[fse->index].height;
  934. fse->min_height = fse->max_height;
  935. return 0;
  936. }
  937. static int ov2659_get_fmt(struct v4l2_subdev *sd,
  938. struct v4l2_subdev_state *sd_state,
  939. struct v4l2_subdev_format *fmt)
  940. {
  941. struct i2c_client *client = v4l2_get_subdevdata(sd);
  942. struct ov2659 *ov2659 = to_ov2659(sd);
  943. dev_dbg(&client->dev, "ov2659_get_fmt\n");
  944. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  945. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  946. struct v4l2_mbus_framefmt *mf;
  947. mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
  948. mutex_lock(&ov2659->lock);
  949. fmt->format = *mf;
  950. mutex_unlock(&ov2659->lock);
  951. return 0;
  952. #else
  953. return -EINVAL;
  954. #endif
  955. }
  956. mutex_lock(&ov2659->lock);
  957. fmt->format = ov2659->format;
  958. mutex_unlock(&ov2659->lock);
  959. dev_dbg(&client->dev, "ov2659_get_fmt: %x %dx%d\n",
  960. ov2659->format.code, ov2659->format.width,
  961. ov2659->format.height);
  962. return 0;
  963. }
  964. static void __ov2659_try_frame_size(struct v4l2_mbus_framefmt *mf,
  965. const struct ov2659_framesize **size)
  966. {
  967. const struct ov2659_framesize *fsize = &ov2659_framesizes[0];
  968. const struct ov2659_framesize *match = NULL;
  969. int i = ARRAY_SIZE(ov2659_framesizes);
  970. unsigned int min_err = UINT_MAX;
  971. while (i--) {
  972. int err = abs(fsize->width - mf->width)
  973. + abs(fsize->height - mf->height);
  974. if ((err < min_err) && (fsize->regs[0].addr)) {
  975. min_err = err;
  976. match = fsize;
  977. }
  978. fsize++;
  979. }
  980. if (!match)
  981. match = &ov2659_framesizes[2];
  982. mf->width = match->width;
  983. mf->height = match->height;
  984. if (size)
  985. *size = match;
  986. }
  987. static int ov2659_set_fmt(struct v4l2_subdev *sd,
  988. struct v4l2_subdev_state *sd_state,
  989. struct v4l2_subdev_format *fmt)
  990. {
  991. struct i2c_client *client = v4l2_get_subdevdata(sd);
  992. int index = ARRAY_SIZE(ov2659_formats);
  993. struct v4l2_mbus_framefmt *mf = &fmt->format;
  994. const struct ov2659_framesize *size = NULL;
  995. struct ov2659 *ov2659 = to_ov2659(sd);
  996. int ret = 0;
  997. dev_dbg(&client->dev, "ov2659_set_fmt\n");
  998. __ov2659_try_frame_size(mf, &size);
  999. while (--index >= 0)
  1000. if (ov2659_formats[index].code == mf->code)
  1001. break;
  1002. if (index < 0) {
  1003. index = 0;
  1004. mf->code = ov2659_formats[index].code;
  1005. }
  1006. mf->colorspace = V4L2_COLORSPACE_SRGB;
  1007. mf->field = V4L2_FIELD_NONE;
  1008. mutex_lock(&ov2659->lock);
  1009. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  1010. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1011. mf = v4l2_subdev_get_try_format(sd, sd_state, fmt->pad);
  1012. *mf = fmt->format;
  1013. #endif
  1014. } else {
  1015. s64 val;
  1016. if (ov2659->streaming) {
  1017. mutex_unlock(&ov2659->lock);
  1018. return -EBUSY;
  1019. }
  1020. ov2659->frame_size = size;
  1021. ov2659->format = fmt->format;
  1022. ov2659->format_ctrl_regs =
  1023. ov2659_formats[index].format_ctrl_regs;
  1024. if (ov2659->format.code != MEDIA_BUS_FMT_SBGGR8_1X8)
  1025. val = ov2659->pdata->link_frequency / 2;
  1026. else
  1027. val = ov2659->pdata->link_frequency;
  1028. ret = v4l2_ctrl_s_ctrl_int64(ov2659->link_frequency, val);
  1029. if (ret < 0)
  1030. dev_warn(&client->dev,
  1031. "failed to set link_frequency rate (%d)\n",
  1032. ret);
  1033. }
  1034. mutex_unlock(&ov2659->lock);
  1035. return ret;
  1036. }
  1037. static int ov2659_set_frame_size(struct ov2659 *ov2659)
  1038. {
  1039. struct i2c_client *client = ov2659->client;
  1040. dev_dbg(&client->dev, "%s\n", __func__);
  1041. return ov2659_write_array(ov2659->client, ov2659->frame_size->regs);
  1042. }
  1043. static int ov2659_set_format(struct ov2659 *ov2659)
  1044. {
  1045. struct i2c_client *client = ov2659->client;
  1046. dev_dbg(&client->dev, "%s\n", __func__);
  1047. return ov2659_write_array(ov2659->client, ov2659->format_ctrl_regs);
  1048. }
  1049. static int ov2659_s_stream(struct v4l2_subdev *sd, int on)
  1050. {
  1051. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1052. struct ov2659 *ov2659 = to_ov2659(sd);
  1053. int ret = 0;
  1054. dev_dbg(&client->dev, "%s: on: %d\n", __func__, on);
  1055. mutex_lock(&ov2659->lock);
  1056. on = !!on;
  1057. if (ov2659->streaming == on)
  1058. goto unlock;
  1059. if (!on) {
  1060. /* Stop Streaming Sequence */
  1061. ov2659_set_streaming(ov2659, 0);
  1062. ov2659->streaming = on;
  1063. pm_runtime_put(&client->dev);
  1064. goto unlock;
  1065. }
  1066. ret = pm_runtime_resume_and_get(&client->dev);
  1067. if (ret < 0)
  1068. goto unlock;
  1069. ret = ov2659_init(sd, 0);
  1070. if (!ret)
  1071. ret = ov2659_set_pixel_clock(ov2659);
  1072. if (!ret)
  1073. ret = ov2659_set_frame_size(ov2659);
  1074. if (!ret)
  1075. ret = ov2659_set_format(ov2659);
  1076. if (!ret) {
  1077. ov2659_set_streaming(ov2659, 1);
  1078. ov2659->streaming = on;
  1079. }
  1080. unlock:
  1081. mutex_unlock(&ov2659->lock);
  1082. return ret;
  1083. }
  1084. static int ov2659_set_test_pattern(struct ov2659 *ov2659, int value)
  1085. {
  1086. struct i2c_client *client = v4l2_get_subdevdata(&ov2659->sd);
  1087. int ret;
  1088. u8 val;
  1089. ret = ov2659_read(client, REG_PRE_ISP_CTRL00, &val);
  1090. if (ret < 0)
  1091. return ret;
  1092. switch (value) {
  1093. case 0:
  1094. val &= ~TEST_PATTERN_ENABLE;
  1095. break;
  1096. case 1:
  1097. val &= VERTICAL_COLOR_BAR_MASK;
  1098. val |= TEST_PATTERN_ENABLE;
  1099. break;
  1100. }
  1101. return ov2659_write(client, REG_PRE_ISP_CTRL00, val);
  1102. }
  1103. static int ov2659_s_ctrl(struct v4l2_ctrl *ctrl)
  1104. {
  1105. struct ov2659 *ov2659 =
  1106. container_of(ctrl->handler, struct ov2659, ctrls);
  1107. struct i2c_client *client = ov2659->client;
  1108. /* V4L2 controls values will be applied only when power is already up */
  1109. if (!pm_runtime_get_if_in_use(&client->dev))
  1110. return 0;
  1111. switch (ctrl->id) {
  1112. case V4L2_CID_TEST_PATTERN:
  1113. return ov2659_set_test_pattern(ov2659, ctrl->val);
  1114. }
  1115. pm_runtime_put(&client->dev);
  1116. return 0;
  1117. }
  1118. static const struct v4l2_ctrl_ops ov2659_ctrl_ops = {
  1119. .s_ctrl = ov2659_s_ctrl,
  1120. };
  1121. static const char * const ov2659_test_pattern_menu[] = {
  1122. "Disabled",
  1123. "Vertical Color Bars",
  1124. };
  1125. static int ov2659_power_off(struct device *dev)
  1126. {
  1127. struct i2c_client *client = to_i2c_client(dev);
  1128. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1129. struct ov2659 *ov2659 = to_ov2659(sd);
  1130. dev_dbg(&client->dev, "%s:\n", __func__);
  1131. gpiod_set_value(ov2659->pwdn_gpio, 1);
  1132. clk_disable_unprepare(ov2659->clk);
  1133. return 0;
  1134. }
  1135. static int ov2659_power_on(struct device *dev)
  1136. {
  1137. struct i2c_client *client = to_i2c_client(dev);
  1138. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1139. struct ov2659 *ov2659 = to_ov2659(sd);
  1140. int ret;
  1141. dev_dbg(&client->dev, "%s:\n", __func__);
  1142. ret = clk_prepare_enable(ov2659->clk);
  1143. if (ret) {
  1144. dev_err(&client->dev, "%s: failed to enable clock\n",
  1145. __func__);
  1146. return ret;
  1147. }
  1148. gpiod_set_value(ov2659->pwdn_gpio, 0);
  1149. if (ov2659->resetb_gpio) {
  1150. gpiod_set_value(ov2659->resetb_gpio, 1);
  1151. usleep_range(500, 1000);
  1152. gpiod_set_value(ov2659->resetb_gpio, 0);
  1153. usleep_range(3000, 5000);
  1154. }
  1155. return 0;
  1156. }
  1157. /* -----------------------------------------------------------------------------
  1158. * V4L2 subdev internal operations
  1159. */
  1160. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1161. static int ov2659_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1162. {
  1163. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1164. struct v4l2_mbus_framefmt *format =
  1165. v4l2_subdev_get_try_format(sd, fh->state, 0);
  1166. dev_dbg(&client->dev, "%s:\n", __func__);
  1167. ov2659_get_default_format(format);
  1168. return 0;
  1169. }
  1170. #endif
  1171. static const struct v4l2_subdev_core_ops ov2659_subdev_core_ops = {
  1172. .log_status = v4l2_ctrl_subdev_log_status,
  1173. .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
  1174. .unsubscribe_event = v4l2_event_subdev_unsubscribe,
  1175. };
  1176. static const struct v4l2_subdev_video_ops ov2659_subdev_video_ops = {
  1177. .s_stream = ov2659_s_stream,
  1178. };
  1179. static const struct v4l2_subdev_pad_ops ov2659_subdev_pad_ops = {
  1180. .enum_mbus_code = ov2659_enum_mbus_code,
  1181. .enum_frame_size = ov2659_enum_frame_sizes,
  1182. .get_fmt = ov2659_get_fmt,
  1183. .set_fmt = ov2659_set_fmt,
  1184. };
  1185. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1186. static const struct v4l2_subdev_ops ov2659_subdev_ops = {
  1187. .core = &ov2659_subdev_core_ops,
  1188. .video = &ov2659_subdev_video_ops,
  1189. .pad = &ov2659_subdev_pad_ops,
  1190. };
  1191. static const struct v4l2_subdev_internal_ops ov2659_subdev_internal_ops = {
  1192. .open = ov2659_open,
  1193. };
  1194. #endif
  1195. static int ov2659_detect(struct v4l2_subdev *sd)
  1196. {
  1197. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1198. u8 pid = 0;
  1199. u8 ver = 0;
  1200. int ret;
  1201. dev_dbg(&client->dev, "%s:\n", __func__);
  1202. ret = ov2659_write(client, REG_SOFTWARE_RESET, 0x01);
  1203. if (ret != 0) {
  1204. dev_err(&client->dev, "Sensor soft reset failed\n");
  1205. return -ENODEV;
  1206. }
  1207. usleep_range(1000, 2000);
  1208. /* Check sensor revision */
  1209. ret = ov2659_read(client, REG_SC_CHIP_ID_H, &pid);
  1210. if (!ret)
  1211. ret = ov2659_read(client, REG_SC_CHIP_ID_L, &ver);
  1212. if (!ret) {
  1213. unsigned short id;
  1214. id = OV265X_ID(pid, ver);
  1215. if (id != OV2659_ID) {
  1216. dev_err(&client->dev,
  1217. "Sensor detection failed (%04X)\n", id);
  1218. ret = -ENODEV;
  1219. } else {
  1220. dev_info(&client->dev, "Found OV%04X sensor\n", id);
  1221. }
  1222. }
  1223. return ret;
  1224. }
  1225. static struct ov2659_platform_data *
  1226. ov2659_get_pdata(struct i2c_client *client)
  1227. {
  1228. struct ov2659_platform_data *pdata;
  1229. struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
  1230. struct device_node *endpoint;
  1231. int ret;
  1232. if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
  1233. return client->dev.platform_data;
  1234. endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
  1235. if (!endpoint)
  1236. return NULL;
  1237. ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(endpoint),
  1238. &bus_cfg);
  1239. if (ret) {
  1240. pdata = NULL;
  1241. goto done;
  1242. }
  1243. pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
  1244. if (!pdata)
  1245. goto done;
  1246. if (!bus_cfg.nr_of_link_frequencies) {
  1247. dev_err(&client->dev,
  1248. "link-frequencies property not found or too many\n");
  1249. pdata = NULL;
  1250. goto done;
  1251. }
  1252. pdata->link_frequency = bus_cfg.link_frequencies[0];
  1253. done:
  1254. v4l2_fwnode_endpoint_free(&bus_cfg);
  1255. of_node_put(endpoint);
  1256. return pdata;
  1257. }
  1258. static int ov2659_probe(struct i2c_client *client)
  1259. {
  1260. const struct ov2659_platform_data *pdata = ov2659_get_pdata(client);
  1261. struct v4l2_subdev *sd;
  1262. struct ov2659 *ov2659;
  1263. int ret;
  1264. if (!pdata) {
  1265. dev_err(&client->dev, "platform data not specified\n");
  1266. return -EINVAL;
  1267. }
  1268. ov2659 = devm_kzalloc(&client->dev, sizeof(*ov2659), GFP_KERNEL);
  1269. if (!ov2659)
  1270. return -ENOMEM;
  1271. ov2659->pdata = pdata;
  1272. ov2659->client = client;
  1273. ov2659->clk = devm_clk_get(&client->dev, "xvclk");
  1274. if (IS_ERR(ov2659->clk))
  1275. return PTR_ERR(ov2659->clk);
  1276. ov2659->xvclk_frequency = clk_get_rate(ov2659->clk);
  1277. if (ov2659->xvclk_frequency < 6000000 ||
  1278. ov2659->xvclk_frequency > 27000000)
  1279. return -EINVAL;
  1280. /* Optional gpio don't fail if not present */
  1281. ov2659->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
  1282. GPIOD_OUT_LOW);
  1283. if (IS_ERR(ov2659->pwdn_gpio))
  1284. return PTR_ERR(ov2659->pwdn_gpio);
  1285. /* Optional gpio don't fail if not present */
  1286. ov2659->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
  1287. GPIOD_OUT_HIGH);
  1288. if (IS_ERR(ov2659->resetb_gpio))
  1289. return PTR_ERR(ov2659->resetb_gpio);
  1290. v4l2_ctrl_handler_init(&ov2659->ctrls, 2);
  1291. ov2659->link_frequency =
  1292. v4l2_ctrl_new_std(&ov2659->ctrls, &ov2659_ctrl_ops,
  1293. V4L2_CID_PIXEL_RATE,
  1294. pdata->link_frequency / 2,
  1295. pdata->link_frequency, 1,
  1296. pdata->link_frequency);
  1297. v4l2_ctrl_new_std_menu_items(&ov2659->ctrls, &ov2659_ctrl_ops,
  1298. V4L2_CID_TEST_PATTERN,
  1299. ARRAY_SIZE(ov2659_test_pattern_menu) - 1,
  1300. 0, 0, ov2659_test_pattern_menu);
  1301. ov2659->sd.ctrl_handler = &ov2659->ctrls;
  1302. if (ov2659->ctrls.error) {
  1303. dev_err(&client->dev, "%s: control initialization error %d\n",
  1304. __func__, ov2659->ctrls.error);
  1305. return ov2659->ctrls.error;
  1306. }
  1307. sd = &ov2659->sd;
  1308. client->flags |= I2C_CLIENT_SCCB;
  1309. #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
  1310. v4l2_i2c_subdev_init(sd, client, &ov2659_subdev_ops);
  1311. sd->internal_ops = &ov2659_subdev_internal_ops;
  1312. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
  1313. V4L2_SUBDEV_FL_HAS_EVENTS;
  1314. #endif
  1315. #if defined(CONFIG_MEDIA_CONTROLLER)
  1316. ov2659->pad.flags = MEDIA_PAD_FL_SOURCE;
  1317. sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1318. ret = media_entity_pads_init(&sd->entity, 1, &ov2659->pad);
  1319. if (ret < 0) {
  1320. v4l2_ctrl_handler_free(&ov2659->ctrls);
  1321. return ret;
  1322. }
  1323. #endif
  1324. mutex_init(&ov2659->lock);
  1325. ov2659_get_default_format(&ov2659->format);
  1326. ov2659->frame_size = &ov2659_framesizes[2];
  1327. ov2659->format_ctrl_regs = ov2659_formats[0].format_ctrl_regs;
  1328. ret = ov2659_power_on(&client->dev);
  1329. if (ret < 0)
  1330. goto error;
  1331. ret = ov2659_detect(sd);
  1332. if (ret < 0)
  1333. goto error;
  1334. /* Calculate the PLL register value needed */
  1335. ov2659_pll_calc_params(ov2659);
  1336. ret = v4l2_async_register_subdev(&ov2659->sd);
  1337. if (ret)
  1338. goto error;
  1339. dev_info(&client->dev, "%s sensor driver registered !!\n", sd->name);
  1340. pm_runtime_set_active(&client->dev);
  1341. pm_runtime_enable(&client->dev);
  1342. pm_runtime_idle(&client->dev);
  1343. return 0;
  1344. error:
  1345. v4l2_ctrl_handler_free(&ov2659->ctrls);
  1346. ov2659_power_off(&client->dev);
  1347. media_entity_cleanup(&sd->entity);
  1348. mutex_destroy(&ov2659->lock);
  1349. return ret;
  1350. }
  1351. static void ov2659_remove(struct i2c_client *client)
  1352. {
  1353. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1354. struct ov2659 *ov2659 = to_ov2659(sd);
  1355. v4l2_ctrl_handler_free(&ov2659->ctrls);
  1356. v4l2_async_unregister_subdev(sd);
  1357. media_entity_cleanup(&sd->entity);
  1358. mutex_destroy(&ov2659->lock);
  1359. pm_runtime_disable(&client->dev);
  1360. if (!pm_runtime_status_suspended(&client->dev))
  1361. ov2659_power_off(&client->dev);
  1362. pm_runtime_set_suspended(&client->dev);
  1363. }
  1364. static const struct dev_pm_ops ov2659_pm_ops = {
  1365. SET_RUNTIME_PM_OPS(ov2659_power_off, ov2659_power_on, NULL)
  1366. };
  1367. static const struct i2c_device_id ov2659_id[] = {
  1368. { "ov2659", 0 },
  1369. { /* sentinel */ },
  1370. };
  1371. MODULE_DEVICE_TABLE(i2c, ov2659_id);
  1372. #if IS_ENABLED(CONFIG_OF)
  1373. static const struct of_device_id ov2659_of_match[] = {
  1374. { .compatible = "ovti,ov2659", },
  1375. { /* sentinel */ },
  1376. };
  1377. MODULE_DEVICE_TABLE(of, ov2659_of_match);
  1378. #endif
  1379. static struct i2c_driver ov2659_i2c_driver = {
  1380. .driver = {
  1381. .name = DRIVER_NAME,
  1382. .pm = &ov2659_pm_ops,
  1383. .of_match_table = of_match_ptr(ov2659_of_match),
  1384. },
  1385. .probe_new = ov2659_probe,
  1386. .remove = ov2659_remove,
  1387. .id_table = ov2659_id,
  1388. };
  1389. module_i2c_driver(ov2659_i2c_driver);
  1390. MODULE_AUTHOR("Benoit Parrot <[email protected]>");
  1391. MODULE_DESCRIPTION("OV2659 CMOS Image Sensor driver");
  1392. MODULE_LICENSE("GPL v2");