m5mols_controls.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Controls for M-5MOLS 8M Pixel camera sensor with ISP
  4. *
  5. * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  6. * Author: HeungJun Kim <[email protected]>
  7. *
  8. * Copyright (C) 2009 Samsung Electronics Co., Ltd.
  9. * Author: Dongsoo Nathaniel Kim <[email protected]>
  10. */
  11. #include <linux/i2c.h>
  12. #include <linux/delay.h>
  13. #include <linux/videodev2.h>
  14. #include <media/v4l2-ctrls.h>
  15. #include "m5mols.h"
  16. #include "m5mols_reg.h"
  17. static struct m5mols_scenemode m5mols_default_scenemode[] = {
  18. [REG_SCENE_NORMAL] = {
  19. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  20. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  21. REG_AF_NORMAL, REG_FD_OFF,
  22. REG_MCC_NORMAL, REG_LIGHT_OFF, REG_FLASH_OFF,
  23. 5, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  24. },
  25. [REG_SCENE_PORTRAIT] = {
  26. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  27. REG_CHROMA_ON, 3, REG_EDGE_ON, 4,
  28. REG_AF_NORMAL, BIT_FD_EN | BIT_FD_DRAW_FACE_FRAME,
  29. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  30. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  31. },
  32. [REG_SCENE_LANDSCAPE] = {
  33. REG_AE_ALL, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  34. REG_CHROMA_ON, 4, REG_EDGE_ON, 6,
  35. REG_AF_NORMAL, REG_FD_OFF,
  36. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  37. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  38. },
  39. [REG_SCENE_SPORTS] = {
  40. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  41. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  42. REG_AF_NORMAL, REG_FD_OFF,
  43. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  44. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  45. },
  46. [REG_SCENE_PARTY_INDOOR] = {
  47. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  48. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  49. REG_AF_NORMAL, REG_FD_OFF,
  50. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  51. 6, REG_ISO_200, REG_CAP_NONE, REG_WDR_OFF,
  52. },
  53. [REG_SCENE_BEACH_SNOW] = {
  54. REG_AE_CENTER, REG_AE_INDEX_10_POS, REG_AWB_AUTO, 0,
  55. REG_CHROMA_ON, 4, REG_EDGE_ON, 5,
  56. REG_AF_NORMAL, REG_FD_OFF,
  57. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  58. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  59. },
  60. [REG_SCENE_SUNSET] = {
  61. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  62. REG_AWB_DAYLIGHT,
  63. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  64. REG_AF_NORMAL, REG_FD_OFF,
  65. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  66. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  67. },
  68. [REG_SCENE_DAWN_DUSK] = {
  69. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_PRESET,
  70. REG_AWB_FLUORESCENT_1,
  71. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  72. REG_AF_NORMAL, REG_FD_OFF,
  73. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  74. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  75. },
  76. [REG_SCENE_FALL] = {
  77. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  78. REG_CHROMA_ON, 5, REG_EDGE_ON, 5,
  79. REG_AF_NORMAL, REG_FD_OFF,
  80. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  81. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  82. },
  83. [REG_SCENE_NIGHT] = {
  84. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  85. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  86. REG_AF_NORMAL, REG_FD_OFF,
  87. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  88. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  89. },
  90. [REG_SCENE_AGAINST_LIGHT] = {
  91. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  92. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  93. REG_AF_NORMAL, REG_FD_OFF,
  94. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  95. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  96. },
  97. [REG_SCENE_FIRE] = {
  98. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  99. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  100. REG_AF_NORMAL, REG_FD_OFF,
  101. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  102. 6, REG_ISO_50, REG_CAP_NONE, REG_WDR_OFF,
  103. },
  104. [REG_SCENE_TEXT] = {
  105. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  106. REG_CHROMA_ON, 3, REG_EDGE_ON, 7,
  107. REG_AF_MACRO, REG_FD_OFF,
  108. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  109. 6, REG_ISO_AUTO, REG_CAP_ANTI_SHAKE, REG_WDR_ON,
  110. },
  111. [REG_SCENE_CANDLE] = {
  112. REG_AE_CENTER, REG_AE_INDEX_00, REG_AWB_AUTO, 0,
  113. REG_CHROMA_ON, 3, REG_EDGE_ON, 5,
  114. REG_AF_NORMAL, REG_FD_OFF,
  115. REG_MCC_OFF, REG_LIGHT_OFF, REG_FLASH_OFF,
  116. 6, REG_ISO_AUTO, REG_CAP_NONE, REG_WDR_OFF,
  117. },
  118. };
  119. /**
  120. * m5mols_do_scenemode() - Change current scenemode
  121. * @info: M-5MOLS driver data structure
  122. * @mode: Desired mode of the scenemode
  123. *
  124. * WARNING: The execution order is important. Do not change the order.
  125. */
  126. int m5mols_do_scenemode(struct m5mols_info *info, u8 mode)
  127. {
  128. struct v4l2_subdev *sd = &info->sd;
  129. struct m5mols_scenemode scenemode = m5mols_default_scenemode[mode];
  130. int ret;
  131. if (mode > REG_SCENE_CANDLE)
  132. return -EINVAL;
  133. ret = v4l2_ctrl_s_ctrl(info->lock_3a, 0);
  134. if (!ret)
  135. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, mode);
  136. if (!ret)
  137. ret = m5mols_write(sd, AE_EV_PRESET_CAPTURE, mode);
  138. if (!ret)
  139. ret = m5mols_write(sd, AE_MODE, scenemode.metering);
  140. if (!ret)
  141. ret = m5mols_write(sd, AE_INDEX, scenemode.ev_bias);
  142. if (!ret)
  143. ret = m5mols_write(sd, AWB_MODE, scenemode.wb_mode);
  144. if (!ret)
  145. ret = m5mols_write(sd, AWB_MANUAL, scenemode.wb_preset);
  146. if (!ret)
  147. ret = m5mols_write(sd, MON_CHROMA_EN, scenemode.chroma_en);
  148. if (!ret)
  149. ret = m5mols_write(sd, MON_CHROMA_LVL, scenemode.chroma_lvl);
  150. if (!ret)
  151. ret = m5mols_write(sd, MON_EDGE_EN, scenemode.edge_en);
  152. if (!ret)
  153. ret = m5mols_write(sd, MON_EDGE_LVL, scenemode.edge_lvl);
  154. if (!ret && is_available_af(info))
  155. ret = m5mols_write(sd, AF_MODE, scenemode.af_range);
  156. if (!ret && is_available_af(info))
  157. ret = m5mols_write(sd, FD_CTL, scenemode.fd_mode);
  158. if (!ret)
  159. ret = m5mols_write(sd, MON_TONE_CTL, scenemode.tone);
  160. if (!ret)
  161. ret = m5mols_write(sd, AE_ISO, scenemode.iso);
  162. if (!ret)
  163. ret = m5mols_set_mode(info, REG_CAPTURE);
  164. if (!ret)
  165. ret = m5mols_write(sd, CAPP_WDR_EN, scenemode.wdr);
  166. if (!ret)
  167. ret = m5mols_write(sd, CAPP_MCC_MODE, scenemode.mcc);
  168. if (!ret)
  169. ret = m5mols_write(sd, CAPP_LIGHT_CTRL, scenemode.light);
  170. if (!ret)
  171. ret = m5mols_write(sd, CAPP_FLASH_CTRL, scenemode.flash);
  172. if (!ret)
  173. ret = m5mols_write(sd, CAPC_MODE, scenemode.capt_mode);
  174. if (!ret)
  175. ret = m5mols_set_mode(info, REG_MONITOR);
  176. return ret;
  177. }
  178. static int m5mols_3a_lock(struct m5mols_info *info, struct v4l2_ctrl *ctrl)
  179. {
  180. bool af_lock = ctrl->val & V4L2_LOCK_FOCUS;
  181. int ret = 0;
  182. if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) {
  183. bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
  184. ret = m5mols_write(&info->sd, AE_LOCK, ae_lock ?
  185. REG_AE_LOCK : REG_AE_UNLOCK);
  186. if (ret)
  187. return ret;
  188. }
  189. if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
  190. && info->auto_wb->val) {
  191. bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
  192. ret = m5mols_write(&info->sd, AWB_LOCK, awb_lock ?
  193. REG_AWB_LOCK : REG_AWB_UNLOCK);
  194. if (ret)
  195. return ret;
  196. }
  197. if (!info->ver.af || !af_lock)
  198. return ret;
  199. if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS)
  200. ret = m5mols_write(&info->sd, AF_EXECUTE, REG_AF_STOP);
  201. return ret;
  202. }
  203. static int m5mols_set_metering_mode(struct m5mols_info *info, int mode)
  204. {
  205. unsigned int metering;
  206. switch (mode) {
  207. case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED:
  208. metering = REG_AE_CENTER;
  209. break;
  210. case V4L2_EXPOSURE_METERING_SPOT:
  211. metering = REG_AE_SPOT;
  212. break;
  213. default:
  214. metering = REG_AE_ALL;
  215. break;
  216. }
  217. return m5mols_write(&info->sd, AE_MODE, metering);
  218. }
  219. static int m5mols_set_exposure(struct m5mols_info *info, int exposure)
  220. {
  221. struct v4l2_subdev *sd = &info->sd;
  222. int ret = 0;
  223. if (exposure == V4L2_EXPOSURE_AUTO) {
  224. /* Unlock auto exposure */
  225. info->lock_3a->val &= ~V4L2_LOCK_EXPOSURE;
  226. m5mols_3a_lock(info, info->lock_3a);
  227. ret = m5mols_set_metering_mode(info, info->metering->val);
  228. if (ret < 0)
  229. return ret;
  230. v4l2_dbg(1, m5mols_debug, sd,
  231. "%s: exposure bias: %#x, metering: %#x\n",
  232. __func__, info->exposure_bias->val,
  233. info->metering->val);
  234. return m5mols_write(sd, AE_INDEX, info->exposure_bias->val);
  235. }
  236. if (exposure == V4L2_EXPOSURE_MANUAL) {
  237. ret = m5mols_write(sd, AE_MODE, REG_AE_OFF);
  238. if (ret == 0)
  239. ret = m5mols_write(sd, AE_MAN_GAIN_MON,
  240. info->exposure->val);
  241. if (ret == 0)
  242. ret = m5mols_write(sd, AE_MAN_GAIN_CAP,
  243. info->exposure->val);
  244. v4l2_dbg(1, m5mols_debug, sd, "%s: exposure: %#x\n",
  245. __func__, info->exposure->val);
  246. }
  247. return ret;
  248. }
  249. static int m5mols_set_white_balance(struct m5mols_info *info, int val)
  250. {
  251. static const unsigned short wb[][2] = {
  252. { V4L2_WHITE_BALANCE_INCANDESCENT, REG_AWB_INCANDESCENT },
  253. { V4L2_WHITE_BALANCE_FLUORESCENT, REG_AWB_FLUORESCENT_1 },
  254. { V4L2_WHITE_BALANCE_FLUORESCENT_H, REG_AWB_FLUORESCENT_2 },
  255. { V4L2_WHITE_BALANCE_HORIZON, REG_AWB_HORIZON },
  256. { V4L2_WHITE_BALANCE_DAYLIGHT, REG_AWB_DAYLIGHT },
  257. { V4L2_WHITE_BALANCE_FLASH, REG_AWB_LEDLIGHT },
  258. { V4L2_WHITE_BALANCE_CLOUDY, REG_AWB_CLOUDY },
  259. { V4L2_WHITE_BALANCE_SHADE, REG_AWB_SHADE },
  260. { V4L2_WHITE_BALANCE_AUTO, REG_AWB_AUTO },
  261. };
  262. int i;
  263. struct v4l2_subdev *sd = &info->sd;
  264. int ret = -EINVAL;
  265. for (i = 0; i < ARRAY_SIZE(wb); i++) {
  266. int awb;
  267. if (wb[i][0] != val)
  268. continue;
  269. v4l2_dbg(1, m5mols_debug, sd,
  270. "Setting white balance to: %#x\n", wb[i][0]);
  271. awb = wb[i][0] == V4L2_WHITE_BALANCE_AUTO;
  272. ret = m5mols_write(sd, AWB_MODE, awb ? REG_AWB_AUTO :
  273. REG_AWB_PRESET);
  274. if (ret < 0)
  275. return ret;
  276. if (!awb)
  277. ret = m5mols_write(sd, AWB_MANUAL, wb[i][1]);
  278. }
  279. return ret;
  280. }
  281. static int m5mols_set_saturation(struct m5mols_info *info, int val)
  282. {
  283. int ret = m5mols_write(&info->sd, MON_CHROMA_LVL, val);
  284. if (ret < 0)
  285. return ret;
  286. return m5mols_write(&info->sd, MON_CHROMA_EN, REG_CHROMA_ON);
  287. }
  288. static int m5mols_set_color_effect(struct m5mols_info *info, int val)
  289. {
  290. unsigned int m_effect = REG_COLOR_EFFECT_OFF;
  291. unsigned int p_effect = REG_EFFECT_OFF;
  292. unsigned int cfix_r = 0, cfix_b = 0;
  293. struct v4l2_subdev *sd = &info->sd;
  294. int ret = 0;
  295. switch (val) {
  296. case V4L2_COLORFX_BW:
  297. m_effect = REG_COLOR_EFFECT_ON;
  298. break;
  299. case V4L2_COLORFX_NEGATIVE:
  300. p_effect = REG_EFFECT_NEGA;
  301. break;
  302. case V4L2_COLORFX_EMBOSS:
  303. p_effect = REG_EFFECT_EMBOSS;
  304. break;
  305. case V4L2_COLORFX_SEPIA:
  306. m_effect = REG_COLOR_EFFECT_ON;
  307. cfix_r = REG_CFIXR_SEPIA;
  308. cfix_b = REG_CFIXB_SEPIA;
  309. break;
  310. }
  311. ret = m5mols_write(sd, PARM_EFFECT, p_effect);
  312. if (!ret)
  313. ret = m5mols_write(sd, MON_EFFECT, m_effect);
  314. if (ret == 0 && m_effect == REG_COLOR_EFFECT_ON) {
  315. ret = m5mols_write(sd, MON_CFIXR, cfix_r);
  316. if (!ret)
  317. ret = m5mols_write(sd, MON_CFIXB, cfix_b);
  318. }
  319. v4l2_dbg(1, m5mols_debug, sd,
  320. "p_effect: %#x, m_effect: %#x, r: %#x, b: %#x (%d)\n",
  321. p_effect, m_effect, cfix_r, cfix_b, ret);
  322. return ret;
  323. }
  324. static int m5mols_set_iso(struct m5mols_info *info, int auto_iso)
  325. {
  326. u32 iso = auto_iso ? 0 : info->iso->val + 1;
  327. return m5mols_write(&info->sd, AE_ISO, iso);
  328. }
  329. static int m5mols_set_wdr(struct m5mols_info *info, int wdr)
  330. {
  331. int ret;
  332. ret = m5mols_write(&info->sd, MON_TONE_CTL, wdr ? 9 : 5);
  333. if (ret < 0)
  334. return ret;
  335. ret = m5mols_set_mode(info, REG_CAPTURE);
  336. if (ret < 0)
  337. return ret;
  338. return m5mols_write(&info->sd, CAPP_WDR_EN, wdr);
  339. }
  340. static int m5mols_set_stabilization(struct m5mols_info *info, int val)
  341. {
  342. struct v4l2_subdev *sd = &info->sd;
  343. unsigned int evp = val ? 0xe : 0x0;
  344. int ret;
  345. ret = m5mols_write(sd, AE_EV_PRESET_MONITOR, evp);
  346. if (ret < 0)
  347. return ret;
  348. return m5mols_write(sd, AE_EV_PRESET_CAPTURE, evp);
  349. }
  350. static int m5mols_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
  351. {
  352. struct v4l2_subdev *sd = to_sd(ctrl);
  353. struct m5mols_info *info = to_m5mols(sd);
  354. int ret = 0;
  355. u8 status = REG_ISO_AUTO;
  356. v4l2_dbg(1, m5mols_debug, sd, "%s: ctrl: %s (%d)\n",
  357. __func__, ctrl->name, info->isp_ready);
  358. if (!info->isp_ready)
  359. return -EBUSY;
  360. switch (ctrl->id) {
  361. case V4L2_CID_ISO_SENSITIVITY_AUTO:
  362. ret = m5mols_read_u8(sd, AE_ISO, &status);
  363. if (ret == 0)
  364. ctrl->val = !status;
  365. if (status != REG_ISO_AUTO)
  366. info->iso->val = status - 1;
  367. break;
  368. case V4L2_CID_3A_LOCK:
  369. ctrl->val &= ~0x7;
  370. ret = m5mols_read_u8(sd, AE_LOCK, &status);
  371. if (ret)
  372. return ret;
  373. if (status)
  374. info->lock_3a->val |= V4L2_LOCK_EXPOSURE;
  375. ret = m5mols_read_u8(sd, AWB_LOCK, &status);
  376. if (ret)
  377. return ret;
  378. if (status)
  379. info->lock_3a->val |= V4L2_LOCK_EXPOSURE;
  380. ret = m5mols_read_u8(sd, AF_EXECUTE, &status);
  381. if (!status)
  382. info->lock_3a->val |= V4L2_LOCK_EXPOSURE;
  383. break;
  384. }
  385. return ret;
  386. }
  387. static int m5mols_s_ctrl(struct v4l2_ctrl *ctrl)
  388. {
  389. unsigned int ctrl_mode = m5mols_get_ctrl_mode(ctrl);
  390. struct v4l2_subdev *sd = to_sd(ctrl);
  391. struct m5mols_info *info = to_m5mols(sd);
  392. int last_mode = info->mode;
  393. int ret = 0;
  394. /*
  395. * If needed, defer restoring the controls until
  396. * the device is fully initialized.
  397. */
  398. if (!info->isp_ready) {
  399. info->ctrl_sync = 0;
  400. return 0;
  401. }
  402. v4l2_dbg(1, m5mols_debug, sd, "%s: %s, val: %d, priv: %p\n",
  403. __func__, ctrl->name, ctrl->val, ctrl->priv);
  404. if (ctrl_mode && ctrl_mode != info->mode) {
  405. ret = m5mols_set_mode(info, ctrl_mode);
  406. if (ret < 0)
  407. return ret;
  408. }
  409. switch (ctrl->id) {
  410. case V4L2_CID_3A_LOCK:
  411. ret = m5mols_3a_lock(info, ctrl);
  412. break;
  413. case V4L2_CID_ZOOM_ABSOLUTE:
  414. ret = m5mols_write(sd, MON_ZOOM, ctrl->val);
  415. break;
  416. case V4L2_CID_EXPOSURE_AUTO:
  417. ret = m5mols_set_exposure(info, ctrl->val);
  418. break;
  419. case V4L2_CID_ISO_SENSITIVITY:
  420. ret = m5mols_set_iso(info, ctrl->val);
  421. break;
  422. case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
  423. ret = m5mols_set_white_balance(info, ctrl->val);
  424. break;
  425. case V4L2_CID_SATURATION:
  426. ret = m5mols_set_saturation(info, ctrl->val);
  427. break;
  428. case V4L2_CID_COLORFX:
  429. ret = m5mols_set_color_effect(info, ctrl->val);
  430. break;
  431. case V4L2_CID_WIDE_DYNAMIC_RANGE:
  432. ret = m5mols_set_wdr(info, ctrl->val);
  433. break;
  434. case V4L2_CID_IMAGE_STABILIZATION:
  435. ret = m5mols_set_stabilization(info, ctrl->val);
  436. break;
  437. case V4L2_CID_JPEG_COMPRESSION_QUALITY:
  438. ret = m5mols_write(sd, CAPP_JPEG_RATIO, ctrl->val);
  439. break;
  440. }
  441. if (ret == 0 && info->mode != last_mode)
  442. ret = m5mols_set_mode(info, last_mode);
  443. return ret;
  444. }
  445. static const struct v4l2_ctrl_ops m5mols_ctrl_ops = {
  446. .g_volatile_ctrl = m5mols_g_volatile_ctrl,
  447. .s_ctrl = m5mols_s_ctrl,
  448. };
  449. /* Supported manual ISO values */
  450. static const s64 iso_qmenu[] = {
  451. /* AE_ISO: 0x01...0x07 (ISO: 50...3200) */
  452. 50000, 100000, 200000, 400000, 800000, 1600000, 3200000
  453. };
  454. /* Supported Exposure Bias values, -2.0EV...+2.0EV */
  455. static const s64 ev_bias_qmenu[] = {
  456. /* AE_INDEX: 0x00...0x08 */
  457. -2000, -1500, -1000, -500, 0, 500, 1000, 1500, 2000
  458. };
  459. int m5mols_init_controls(struct v4l2_subdev *sd)
  460. {
  461. struct m5mols_info *info = to_m5mols(sd);
  462. u16 exposure_max;
  463. u16 zoom_step;
  464. int ret;
  465. /* Determine the firmware dependent control range and step values */
  466. ret = m5mols_read_u16(sd, AE_MAX_GAIN_MON, &exposure_max);
  467. if (ret < 0)
  468. return ret;
  469. zoom_step = is_manufacturer(info, REG_SAMSUNG_OPTICS) ? 31 : 1;
  470. v4l2_ctrl_handler_init(&info->handle, 20);
  471. info->auto_wb = v4l2_ctrl_new_std_menu(&info->handle,
  472. &m5mols_ctrl_ops, V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
  473. 9, ~0x3fe, V4L2_WHITE_BALANCE_AUTO);
  474. /* Exposure control cluster */
  475. info->auto_exposure = v4l2_ctrl_new_std_menu(&info->handle,
  476. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
  477. 1, ~0x03, V4L2_EXPOSURE_AUTO);
  478. info->exposure = v4l2_ctrl_new_std(&info->handle,
  479. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE,
  480. 0, exposure_max, 1, exposure_max / 2);
  481. info->exposure_bias = v4l2_ctrl_new_int_menu(&info->handle,
  482. &m5mols_ctrl_ops, V4L2_CID_AUTO_EXPOSURE_BIAS,
  483. ARRAY_SIZE(ev_bias_qmenu) - 1,
  484. ARRAY_SIZE(ev_bias_qmenu)/2 - 1,
  485. ev_bias_qmenu);
  486. info->metering = v4l2_ctrl_new_std_menu(&info->handle,
  487. &m5mols_ctrl_ops, V4L2_CID_EXPOSURE_METERING,
  488. 2, ~0x7, V4L2_EXPOSURE_METERING_AVERAGE);
  489. /* ISO control cluster */
  490. info->auto_iso = v4l2_ctrl_new_std_menu(&info->handle, &m5mols_ctrl_ops,
  491. V4L2_CID_ISO_SENSITIVITY_AUTO, 1, ~0x03, 1);
  492. info->iso = v4l2_ctrl_new_int_menu(&info->handle, &m5mols_ctrl_ops,
  493. V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1,
  494. ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu);
  495. info->saturation = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  496. V4L2_CID_SATURATION, 1, 5, 1, 3);
  497. info->zoom = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  498. V4L2_CID_ZOOM_ABSOLUTE, 1, 70, zoom_step, 1);
  499. info->colorfx = v4l2_ctrl_new_std_menu(&info->handle, &m5mols_ctrl_ops,
  500. V4L2_CID_COLORFX, 4, 0, V4L2_COLORFX_NONE);
  501. info->wdr = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  502. V4L2_CID_WIDE_DYNAMIC_RANGE, 0, 1, 1, 0);
  503. info->stabilization = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  504. V4L2_CID_IMAGE_STABILIZATION, 0, 1, 1, 0);
  505. info->jpeg_quality = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  506. V4L2_CID_JPEG_COMPRESSION_QUALITY, 1, 100, 1, 80);
  507. info->lock_3a = v4l2_ctrl_new_std(&info->handle, &m5mols_ctrl_ops,
  508. V4L2_CID_3A_LOCK, 0, 0x7, 0, 0);
  509. if (info->handle.error) {
  510. int ret = info->handle.error;
  511. v4l2_err(sd, "Failed to initialize controls: %d\n", ret);
  512. v4l2_ctrl_handler_free(&info->handle);
  513. return ret;
  514. }
  515. v4l2_ctrl_auto_cluster(4, &info->auto_exposure, 1, false);
  516. info->auto_iso->flags |= V4L2_CTRL_FLAG_VOLATILE |
  517. V4L2_CTRL_FLAG_UPDATE;
  518. v4l2_ctrl_auto_cluster(2, &info->auto_iso, 0, false);
  519. info->lock_3a->flags |= V4L2_CTRL_FLAG_VOLATILE;
  520. m5mols_set_ctrl_mode(info->auto_exposure, REG_PARAMETER);
  521. m5mols_set_ctrl_mode(info->auto_wb, REG_PARAMETER);
  522. m5mols_set_ctrl_mode(info->colorfx, REG_MONITOR);
  523. sd->ctrl_handler = &info->handle;
  524. return 0;
  525. }