hi846.c 53 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. // Copyright (c) 2021 Purism SPC
  3. #include <asm/unaligned.h>
  4. #include <linux/clk.h>
  5. #include <linux/delay.h>
  6. #include <linux/gpio/consumer.h>
  7. #include <linux/i2c.h>
  8. #include <linux/module.h>
  9. #include <linux/pm_runtime.h>
  10. #include <linux/pm.h>
  11. #include <linux/property.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <media/v4l2-ctrls.h>
  14. #include <media/v4l2-device.h>
  15. #include <media/v4l2-fwnode.h>
  16. #define HI846_MEDIA_BUS_FORMAT MEDIA_BUS_FMT_SGBRG10_1X10
  17. #define HI846_RGB_DEPTH 10
  18. /* Frame length lines / vertical timings */
  19. #define HI846_REG_FLL 0x0006
  20. #define HI846_FLL_MAX 0xffff
  21. /* Horizontal timing */
  22. #define HI846_REG_LLP 0x0008
  23. #define HI846_LINE_LENGTH 3800
  24. #define HI846_REG_BINNING_MODE 0x000c
  25. #define HI846_REG_IMAGE_ORIENTATION 0x000e
  26. #define HI846_REG_UNKNOWN_0022 0x0022
  27. #define HI846_REG_Y_ADDR_START_VACT_H 0x0026
  28. #define HI846_REG_Y_ADDR_START_VACT_L 0x0027
  29. #define HI846_REG_UNKNOWN_0028 0x0028
  30. #define HI846_REG_Y_ADDR_END_VACT_H 0x002c
  31. #define HI846_REG_Y_ADDR_END_VACT_L 0x002d
  32. #define HI846_REG_Y_ODD_INC_FOBP 0x002e
  33. #define HI846_REG_Y_EVEN_INC_FOBP 0x002f
  34. #define HI846_REG_Y_ODD_INC_VACT 0x0032
  35. #define HI846_REG_Y_EVEN_INC_VACT 0x0033
  36. #define HI846_REG_GROUPED_PARA_HOLD 0x0046
  37. #define HI846_REG_TG_ENABLE 0x004c
  38. #define HI846_REG_UNKNOWN_005C 0x005c
  39. #define HI846_REG_UNKNOWN_006A 0x006a
  40. /*
  41. * Long exposure time. Actually, exposure is a 20 bit value that
  42. * includes the lower 4 bits of 0x0073 too. Only 16 bits are used
  43. * right now
  44. */
  45. #define HI846_REG_EXPOSURE 0x0074
  46. #define HI846_EXPOSURE_MIN 6
  47. #define HI846_EXPOSURE_MAX_MARGIN 2
  48. #define HI846_EXPOSURE_STEP 1
  49. /* Analog gain controls from sensor */
  50. #define HI846_REG_ANALOG_GAIN 0x0077
  51. #define HI846_ANAL_GAIN_MIN 0
  52. #define HI846_ANAL_GAIN_MAX 240
  53. #define HI846_ANAL_GAIN_STEP 8
  54. /* Digital gain controls from sensor */
  55. #define HI846_REG_MWB_GR_GAIN_H 0x0078
  56. #define HI846_REG_MWB_GR_GAIN_L 0x0079
  57. #define HI846_REG_MWB_GB_GAIN_H 0x007a
  58. #define HI846_REG_MWB_GB_GAIN_L 0x007b
  59. #define HI846_REG_MWB_R_GAIN_H 0x007c
  60. #define HI846_REG_MWB_R_GAIN_L 0x007d
  61. #define HI846_REG_MWB_B_GAIN_H 0x007e
  62. #define HI846_REG_MWB_B_GAIN_L 0x007f
  63. #define HI846_DGTL_GAIN_MIN 512
  64. #define HI846_DGTL_GAIN_MAX 8191
  65. #define HI846_DGTL_GAIN_STEP 1
  66. #define HI846_DGTL_GAIN_DEFAULT 512
  67. #define HI846_REG_X_ADDR_START_HACT_H 0x0120
  68. #define HI846_REG_X_ADDR_END_HACT_H 0x0122
  69. #define HI846_REG_UNKNOWN_012A 0x012a
  70. #define HI846_REG_UNKNOWN_0200 0x0200
  71. #define HI846_REG_UNKNOWN_021C 0x021c
  72. #define HI846_REG_UNKNOWN_021E 0x021e
  73. #define HI846_REG_UNKNOWN_0402 0x0402
  74. #define HI846_REG_UNKNOWN_0404 0x0404
  75. #define HI846_REG_UNKNOWN_0408 0x0408
  76. #define HI846_REG_UNKNOWN_0410 0x0410
  77. #define HI846_REG_UNKNOWN_0412 0x0412
  78. #define HI846_REG_UNKNOWN_0414 0x0414
  79. #define HI846_REG_UNKNOWN_0418 0x0418
  80. #define HI846_REG_UNKNOWN_051E 0x051e
  81. /* Formatter */
  82. #define HI846_REG_X_START_H 0x0804
  83. #define HI846_REG_X_START_L 0x0805
  84. /* MIPI */
  85. #define HI846_REG_UNKNOWN_0900 0x0900
  86. #define HI846_REG_MIPI_TX_OP_EN 0x0901
  87. #define HI846_REG_MIPI_TX_OP_MODE 0x0902
  88. #define HI846_RAW8 BIT(5)
  89. #define HI846_REG_UNKNOWN_090C 0x090c
  90. #define HI846_REG_UNKNOWN_090E 0x090e
  91. #define HI846_REG_UNKNOWN_0914 0x0914
  92. #define HI846_REG_TLPX 0x0915
  93. #define HI846_REG_TCLK_PREPARE 0x0916
  94. #define HI846_REG_TCLK_ZERO 0x0917
  95. #define HI846_REG_UNKNOWN_0918 0x0918
  96. #define HI846_REG_THS_PREPARE 0x0919
  97. #define HI846_REG_THS_ZERO 0x091a
  98. #define HI846_REG_THS_TRAIL 0x091b
  99. #define HI846_REG_TCLK_POST 0x091c
  100. #define HI846_REG_TCLK_TRAIL_MIN 0x091d
  101. #define HI846_REG_UNKNOWN_091E 0x091e
  102. #define HI846_REG_UNKNOWN_0954 0x0954
  103. #define HI846_REG_UNKNOWN_0956 0x0956
  104. #define HI846_REG_UNKNOWN_0958 0x0958
  105. #define HI846_REG_UNKNOWN_095A 0x095a
  106. /* ISP Common */
  107. #define HI846_REG_MODE_SELECT 0x0a00
  108. #define HI846_MODE_STANDBY 0x00
  109. #define HI846_MODE_STREAMING 0x01
  110. #define HI846_REG_FAST_STANDBY_MODE 0x0a02
  111. #define HI846_REG_ISP_EN_H 0x0a04
  112. /* Test Pattern Control */
  113. #define HI846_REG_ISP 0x0a05
  114. #define HI846_REG_ISP_TPG_EN 0x01
  115. #define HI846_REG_TEST_PATTERN 0x020a /* 1-9 */
  116. #define HI846_REG_UNKNOWN_0A0C 0x0a0c
  117. /* Windowing */
  118. #define HI846_REG_X_OUTPUT_SIZE_H 0x0a12
  119. #define HI846_REG_X_OUTPUT_SIZE_L 0x0a13
  120. #define HI846_REG_Y_OUTPUT_SIZE_H 0x0a14
  121. #define HI846_REG_Y_OUTPUT_SIZE_L 0x0a15
  122. /* ISP Common */
  123. #define HI846_REG_PEDESTAL_EN 0x0a1a
  124. #define HI846_REG_UNKNOWN_0A1E 0x0a1e
  125. /* Horizontal Binning Mode */
  126. #define HI846_REG_HBIN_MODE 0x0a22
  127. #define HI846_REG_UNKNOWN_0A24 0x0a24
  128. #define HI846_REG_UNKNOWN_0B02 0x0b02
  129. #define HI846_REG_UNKNOWN_0B10 0x0b10
  130. #define HI846_REG_UNKNOWN_0B12 0x0b12
  131. #define HI846_REG_UNKNOWN_0B14 0x0b14
  132. /* BLC (Black Level Calibration) */
  133. #define HI846_REG_BLC_CTL0 0x0c00
  134. #define HI846_REG_UNKNOWN_0C06 0x0c06
  135. #define HI846_REG_UNKNOWN_0C10 0x0c10
  136. #define HI846_REG_UNKNOWN_0C12 0x0c12
  137. #define HI846_REG_UNKNOWN_0C14 0x0c14
  138. #define HI846_REG_UNKNOWN_0C16 0x0c16
  139. #define HI846_REG_UNKNOWN_0E04 0x0e04
  140. #define HI846_REG_CHIP_ID_L 0x0f16
  141. #define HI846_REG_CHIP_ID_H 0x0f17
  142. #define HI846_CHIP_ID_L 0x46
  143. #define HI846_CHIP_ID_H 0x08
  144. #define HI846_REG_UNKNOWN_0F04 0x0f04
  145. #define HI846_REG_UNKNOWN_0F08 0x0f08
  146. /* PLL */
  147. #define HI846_REG_PLL_CFG_MIPI2_H 0x0f2a
  148. #define HI846_REG_PLL_CFG_MIPI2_L 0x0f2b
  149. #define HI846_REG_UNKNOWN_0F30 0x0f30
  150. #define HI846_REG_PLL_CFG_RAMP1_H 0x0f32
  151. #define HI846_REG_UNKNOWN_0F36 0x0f36
  152. #define HI846_REG_PLL_CFG_MIPI1_H 0x0f38
  153. #define HI846_REG_UNKNOWN_2008 0x2008
  154. #define HI846_REG_UNKNOWN_326E 0x326e
  155. struct hi846_reg {
  156. u16 address;
  157. u16 val;
  158. };
  159. struct hi846_reg_list {
  160. u32 num_of_regs;
  161. const struct hi846_reg *regs;
  162. };
  163. struct hi846_mode {
  164. /* Frame width in pixels */
  165. u32 width;
  166. /* Frame height in pixels */
  167. u32 height;
  168. /* Horizontal timing size */
  169. u32 llp;
  170. /* Link frequency needed for this resolution */
  171. u8 link_freq_index;
  172. u16 fps;
  173. /* Vertical timining size */
  174. u16 frame_len;
  175. const struct hi846_reg_list reg_list_config;
  176. const struct hi846_reg_list reg_list_2lane;
  177. const struct hi846_reg_list reg_list_4lane;
  178. /* Position inside of the 3264x2448 pixel array */
  179. struct v4l2_rect crop;
  180. };
  181. static const struct hi846_reg hi846_init_2lane[] = {
  182. {HI846_REG_MODE_SELECT, 0x0000},
  183. /* regs below are unknown */
  184. {0x2000, 0x100a},
  185. {0x2002, 0x00ff},
  186. {0x2004, 0x0007},
  187. {0x2006, 0x3fff},
  188. {0x2008, 0x3fff},
  189. {0x200a, 0xc216},
  190. {0x200c, 0x1292},
  191. {0x200e, 0xc01a},
  192. {0x2010, 0x403d},
  193. {0x2012, 0x000e},
  194. {0x2014, 0x403e},
  195. {0x2016, 0x0b80},
  196. {0x2018, 0x403f},
  197. {0x201a, 0x82ae},
  198. {0x201c, 0x1292},
  199. {0x201e, 0xc00c},
  200. {0x2020, 0x4130},
  201. {0x2022, 0x43e2},
  202. {0x2024, 0x0180},
  203. {0x2026, 0x4130},
  204. {0x2028, 0x7400},
  205. {0x202a, 0x5000},
  206. {0x202c, 0x0253},
  207. {0x202e, 0x0ad1},
  208. {0x2030, 0x2360},
  209. {0x2032, 0x0009},
  210. {0x2034, 0x5020},
  211. {0x2036, 0x000b},
  212. {0x2038, 0x0002},
  213. {0x203a, 0x0044},
  214. {0x203c, 0x0016},
  215. {0x203e, 0x1792},
  216. {0x2040, 0x7002},
  217. {0x2042, 0x154f},
  218. {0x2044, 0x00d5},
  219. {0x2046, 0x000b},
  220. {0x2048, 0x0019},
  221. {0x204a, 0x1698},
  222. {0x204c, 0x000e},
  223. {0x204e, 0x099a},
  224. {0x2050, 0x0058},
  225. {0x2052, 0x7000},
  226. {0x2054, 0x1799},
  227. {0x2056, 0x0310},
  228. {0x2058, 0x03c3},
  229. {0x205a, 0x004c},
  230. {0x205c, 0x064a},
  231. {0x205e, 0x0001},
  232. {0x2060, 0x0007},
  233. {0x2062, 0x0bc7},
  234. {0x2064, 0x0055},
  235. {0x2066, 0x7000},
  236. {0x2068, 0x1550},
  237. {0x206a, 0x158a},
  238. {0x206c, 0x0004},
  239. {0x206e, 0x1488},
  240. {0x2070, 0x7010},
  241. {0x2072, 0x1508},
  242. {0x2074, 0x0004},
  243. {0x2076, 0x0016},
  244. {0x2078, 0x03d5},
  245. {0x207a, 0x0055},
  246. {0x207c, 0x08ca},
  247. {0x207e, 0x2019},
  248. {0x2080, 0x0007},
  249. {0x2082, 0x7057},
  250. {0x2084, 0x0fc7},
  251. {0x2086, 0x5041},
  252. {0x2088, 0x12c8},
  253. {0x208a, 0x5060},
  254. {0x208c, 0x5080},
  255. {0x208e, 0x2084},
  256. {0x2090, 0x12c8},
  257. {0x2092, 0x7800},
  258. {0x2094, 0x0802},
  259. {0x2096, 0x040f},
  260. {0x2098, 0x1007},
  261. {0x209a, 0x0803},
  262. {0x209c, 0x080b},
  263. {0x209e, 0x3803},
  264. {0x20a0, 0x0807},
  265. {0x20a2, 0x0404},
  266. {0x20a4, 0x0400},
  267. {0x20a6, 0xffff},
  268. {0x20a8, 0xf0b2},
  269. {0x20aa, 0xffef},
  270. {0x20ac, 0x0a84},
  271. {0x20ae, 0x1292},
  272. {0x20b0, 0xc02e},
  273. {0x20b2, 0x4130},
  274. {0x23fe, 0xc056},
  275. {0x3232, 0xfc0c},
  276. {0x3236, 0xfc22},
  277. {0x3248, 0xfca8},
  278. {0x326a, 0x8302},
  279. {0x326c, 0x830a},
  280. {0x326e, 0x0000},
  281. {0x32ca, 0xfc28},
  282. {0x32cc, 0xc3bc},
  283. {0x32ce, 0xc34c},
  284. {0x32d0, 0xc35a},
  285. {0x32d2, 0xc368},
  286. {0x32d4, 0xc376},
  287. {0x32d6, 0xc3c2},
  288. {0x32d8, 0xc3e6},
  289. {0x32da, 0x0003},
  290. {0x32dc, 0x0003},
  291. {0x32de, 0x00c7},
  292. {0x32e0, 0x0031},
  293. {0x32e2, 0x0031},
  294. {0x32e4, 0x0031},
  295. {0x32e6, 0xfc28},
  296. {0x32e8, 0xc3bc},
  297. {0x32ea, 0xc384},
  298. {0x32ec, 0xc392},
  299. {0x32ee, 0xc3a0},
  300. {0x32f0, 0xc3ae},
  301. {0x32f2, 0xc3c4},
  302. {0x32f4, 0xc3e6},
  303. {0x32f6, 0x0003},
  304. {0x32f8, 0x0003},
  305. {0x32fa, 0x00c7},
  306. {0x32fc, 0x0031},
  307. {0x32fe, 0x0031},
  308. {0x3300, 0x0031},
  309. {0x3302, 0x82ca},
  310. {0x3304, 0xc164},
  311. {0x3306, 0x82e6},
  312. {0x3308, 0xc19c},
  313. {0x330a, 0x001f},
  314. {0x330c, 0x001a},
  315. {0x330e, 0x0034},
  316. {0x3310, 0x0000},
  317. {0x3312, 0x0000},
  318. {0x3314, 0xfc94},
  319. {0x3316, 0xc3d8},
  320. /* regs above are unknown */
  321. {HI846_REG_MODE_SELECT, 0x0000},
  322. {HI846_REG_UNKNOWN_0E04, 0x0012},
  323. {HI846_REG_Y_ODD_INC_FOBP, 0x1111},
  324. {HI846_REG_Y_ODD_INC_VACT, 0x1111},
  325. {HI846_REG_UNKNOWN_0022, 0x0008},
  326. {HI846_REG_Y_ADDR_START_VACT_H, 0x0040},
  327. {HI846_REG_UNKNOWN_0028, 0x0017},
  328. {HI846_REG_Y_ADDR_END_VACT_H, 0x09cf},
  329. {HI846_REG_UNKNOWN_005C, 0x2101},
  330. {HI846_REG_FLL, 0x09de},
  331. {HI846_REG_LLP, 0x0ed8},
  332. {HI846_REG_IMAGE_ORIENTATION, 0x0100},
  333. {HI846_REG_BINNING_MODE, 0x0022},
  334. {HI846_REG_HBIN_MODE, 0x0000},
  335. {HI846_REG_UNKNOWN_0A24, 0x0000},
  336. {HI846_REG_X_START_H, 0x0000},
  337. {HI846_REG_X_OUTPUT_SIZE_H, 0x0cc0},
  338. {HI846_REG_Y_OUTPUT_SIZE_H, 0x0990},
  339. {HI846_REG_EXPOSURE, 0x09d8},
  340. {HI846_REG_ANALOG_GAIN, 0x0000},
  341. {HI846_REG_GROUPED_PARA_HOLD, 0x0000},
  342. {HI846_REG_UNKNOWN_051E, 0x0000},
  343. {HI846_REG_UNKNOWN_0200, 0x0400},
  344. {HI846_REG_PEDESTAL_EN, 0x0c00},
  345. {HI846_REG_UNKNOWN_0A0C, 0x0010},
  346. {HI846_REG_UNKNOWN_0A1E, 0x0ccf},
  347. {HI846_REG_UNKNOWN_0402, 0x0110},
  348. {HI846_REG_UNKNOWN_0404, 0x00f4},
  349. {HI846_REG_UNKNOWN_0408, 0x0000},
  350. {HI846_REG_UNKNOWN_0410, 0x008d},
  351. {HI846_REG_UNKNOWN_0412, 0x011a},
  352. {HI846_REG_UNKNOWN_0414, 0x864c},
  353. {HI846_REG_UNKNOWN_021C, 0x0003},
  354. {HI846_REG_UNKNOWN_021E, 0x0235},
  355. {HI846_REG_BLC_CTL0, 0x9150},
  356. {HI846_REG_UNKNOWN_0C06, 0x0021},
  357. {HI846_REG_UNKNOWN_0C10, 0x0040},
  358. {HI846_REG_UNKNOWN_0C12, 0x0040},
  359. {HI846_REG_UNKNOWN_0C14, 0x0040},
  360. {HI846_REG_UNKNOWN_0C16, 0x0040},
  361. {HI846_REG_FAST_STANDBY_MODE, 0x0100},
  362. {HI846_REG_ISP_EN_H, 0x014a},
  363. {HI846_REG_UNKNOWN_0418, 0x0000},
  364. {HI846_REG_UNKNOWN_012A, 0x03b4},
  365. {HI846_REG_X_ADDR_START_HACT_H, 0x0046},
  366. {HI846_REG_X_ADDR_END_HACT_H, 0x0376},
  367. {HI846_REG_UNKNOWN_0B02, 0xe04d},
  368. {HI846_REG_UNKNOWN_0B10, 0x6821},
  369. {HI846_REG_UNKNOWN_0B12, 0x0120},
  370. {HI846_REG_UNKNOWN_0B14, 0x0001},
  371. {HI846_REG_UNKNOWN_2008, 0x38fd},
  372. {HI846_REG_UNKNOWN_326E, 0x0000},
  373. {HI846_REG_UNKNOWN_0900, 0x0320},
  374. {HI846_REG_MIPI_TX_OP_MODE, 0xc31a},
  375. {HI846_REG_UNKNOWN_0914, 0xc109},
  376. {HI846_REG_TCLK_PREPARE, 0x061a},
  377. {HI846_REG_UNKNOWN_0918, 0x0306},
  378. {HI846_REG_THS_ZERO, 0x0b09},
  379. {HI846_REG_TCLK_POST, 0x0c07},
  380. {HI846_REG_UNKNOWN_091E, 0x0a00},
  381. {HI846_REG_UNKNOWN_090C, 0x042a},
  382. {HI846_REG_UNKNOWN_090E, 0x006b},
  383. {HI846_REG_UNKNOWN_0954, 0x0089},
  384. {HI846_REG_UNKNOWN_0956, 0x0000},
  385. {HI846_REG_UNKNOWN_0958, 0xca00},
  386. {HI846_REG_UNKNOWN_095A, 0x9240},
  387. {HI846_REG_UNKNOWN_0F08, 0x2f04},
  388. {HI846_REG_UNKNOWN_0F30, 0x001f},
  389. {HI846_REG_UNKNOWN_0F36, 0x001f},
  390. {HI846_REG_UNKNOWN_0F04, 0x3a00},
  391. {HI846_REG_PLL_CFG_RAMP1_H, 0x025a},
  392. {HI846_REG_PLL_CFG_MIPI1_H, 0x025a},
  393. {HI846_REG_PLL_CFG_MIPI2_H, 0x0024},
  394. {HI846_REG_UNKNOWN_006A, 0x0100},
  395. {HI846_REG_TG_ENABLE, 0x0100},
  396. };
  397. static const struct hi846_reg hi846_init_4lane[] = {
  398. {0x2000, 0x987a},
  399. {0x2002, 0x00ff},
  400. {0x2004, 0x0047},
  401. {0x2006, 0x3fff},
  402. {0x2008, 0x3fff},
  403. {0x200a, 0xc216},
  404. {0x200c, 0x1292},
  405. {0x200e, 0xc01a},
  406. {0x2010, 0x403d},
  407. {0x2012, 0x000e},
  408. {0x2014, 0x403e},
  409. {0x2016, 0x0b80},
  410. {0x2018, 0x403f},
  411. {0x201a, 0x82ae},
  412. {0x201c, 0x1292},
  413. {0x201e, 0xc00c},
  414. {0x2020, 0x4130},
  415. {0x2022, 0x43e2},
  416. {0x2024, 0x0180},
  417. {0x2026, 0x4130},
  418. {0x2028, 0x7400},
  419. {0x202a, 0x5000},
  420. {0x202c, 0x0253},
  421. {0x202e, 0x0ad1},
  422. {0x2030, 0x2360},
  423. {0x2032, 0x0009},
  424. {0x2034, 0x5020},
  425. {0x2036, 0x000b},
  426. {0x2038, 0x0002},
  427. {0x203a, 0x0044},
  428. {0x203c, 0x0016},
  429. {0x203e, 0x1792},
  430. {0x2040, 0x7002},
  431. {0x2042, 0x154f},
  432. {0x2044, 0x00d5},
  433. {0x2046, 0x000b},
  434. {0x2048, 0x0019},
  435. {0x204a, 0x1698},
  436. {0x204c, 0x000e},
  437. {0x204e, 0x099a},
  438. {0x2050, 0x0058},
  439. {0x2052, 0x7000},
  440. {0x2054, 0x1799},
  441. {0x2056, 0x0310},
  442. {0x2058, 0x03c3},
  443. {0x205a, 0x004c},
  444. {0x205c, 0x064a},
  445. {0x205e, 0x0001},
  446. {0x2060, 0x0007},
  447. {0x2062, 0x0bc7},
  448. {0x2064, 0x0055},
  449. {0x2066, 0x7000},
  450. {0x2068, 0x1550},
  451. {0x206a, 0x158a},
  452. {0x206c, 0x0004},
  453. {0x206e, 0x1488},
  454. {0x2070, 0x7010},
  455. {0x2072, 0x1508},
  456. {0x2074, 0x0004},
  457. {0x2076, 0x0016},
  458. {0x2078, 0x03d5},
  459. {0x207a, 0x0055},
  460. {0x207c, 0x08ca},
  461. {0x207e, 0x2019},
  462. {0x2080, 0x0007},
  463. {0x2082, 0x7057},
  464. {0x2084, 0x0fc7},
  465. {0x2086, 0x5041},
  466. {0x2088, 0x12c8},
  467. {0x208a, 0x5060},
  468. {0x208c, 0x5080},
  469. {0x208e, 0x2084},
  470. {0x2090, 0x12c8},
  471. {0x2092, 0x7800},
  472. {0x2094, 0x0802},
  473. {0x2096, 0x040f},
  474. {0x2098, 0x1007},
  475. {0x209a, 0x0803},
  476. {0x209c, 0x080b},
  477. {0x209e, 0x3803},
  478. {0x20a0, 0x0807},
  479. {0x20a2, 0x0404},
  480. {0x20a4, 0x0400},
  481. {0x20a6, 0xffff},
  482. {0x20a8, 0xf0b2},
  483. {0x20aa, 0xffef},
  484. {0x20ac, 0x0a84},
  485. {0x20ae, 0x1292},
  486. {0x20b0, 0xc02e},
  487. {0x20b2, 0x4130},
  488. {0x20b4, 0xf0b2},
  489. {0x20b6, 0xffbf},
  490. {0x20b8, 0x2004},
  491. {0x20ba, 0x403f},
  492. {0x20bc, 0x00c3},
  493. {0x20be, 0x4fe2},
  494. {0x20c0, 0x8318},
  495. {0x20c2, 0x43cf},
  496. {0x20c4, 0x0000},
  497. {0x20c6, 0x9382},
  498. {0x20c8, 0xc314},
  499. {0x20ca, 0x2003},
  500. {0x20cc, 0x12b0},
  501. {0x20ce, 0xcab0},
  502. {0x20d0, 0x4130},
  503. {0x20d2, 0x12b0},
  504. {0x20d4, 0xc90a},
  505. {0x20d6, 0x4130},
  506. {0x20d8, 0x42d2},
  507. {0x20da, 0x8318},
  508. {0x20dc, 0x00c3},
  509. {0x20de, 0x9382},
  510. {0x20e0, 0xc314},
  511. {0x20e2, 0x2009},
  512. {0x20e4, 0x120b},
  513. {0x20e6, 0x120a},
  514. {0x20e8, 0x1209},
  515. {0x20ea, 0x1208},
  516. {0x20ec, 0x1207},
  517. {0x20ee, 0x1206},
  518. {0x20f0, 0x4030},
  519. {0x20f2, 0xc15e},
  520. {0x20f4, 0x4130},
  521. {0x20f6, 0x1292},
  522. {0x20f8, 0xc008},
  523. {0x20fa, 0x4130},
  524. {0x20fc, 0x42d2},
  525. {0x20fe, 0x82a1},
  526. {0x2100, 0x00c2},
  527. {0x2102, 0x1292},
  528. {0x2104, 0xc040},
  529. {0x2106, 0x4130},
  530. {0x2108, 0x1292},
  531. {0x210a, 0xc006},
  532. {0x210c, 0x42a2},
  533. {0x210e, 0x7324},
  534. {0x2110, 0x9382},
  535. {0x2112, 0xc314},
  536. {0x2114, 0x2011},
  537. {0x2116, 0x425f},
  538. {0x2118, 0x82a1},
  539. {0x211a, 0xf25f},
  540. {0x211c, 0x00c1},
  541. {0x211e, 0xf35f},
  542. {0x2120, 0x2406},
  543. {0x2122, 0x425f},
  544. {0x2124, 0x00c0},
  545. {0x2126, 0xf37f},
  546. {0x2128, 0x522f},
  547. {0x212a, 0x4f82},
  548. {0x212c, 0x7324},
  549. {0x212e, 0x425f},
  550. {0x2130, 0x82d4},
  551. {0x2132, 0xf35f},
  552. {0x2134, 0x4fc2},
  553. {0x2136, 0x01b3},
  554. {0x2138, 0x93c2},
  555. {0x213a, 0x829f},
  556. {0x213c, 0x2421},
  557. {0x213e, 0x403e},
  558. {0x2140, 0xfffe},
  559. {0x2142, 0x40b2},
  560. {0x2144, 0xec78},
  561. {0x2146, 0x831c},
  562. {0x2148, 0x40b2},
  563. {0x214a, 0xec78},
  564. {0x214c, 0x831e},
  565. {0x214e, 0x40b2},
  566. {0x2150, 0xec78},
  567. {0x2152, 0x8320},
  568. {0x2154, 0xb3d2},
  569. {0x2156, 0x008c},
  570. {0x2158, 0x2405},
  571. {0x215a, 0x4e0f},
  572. {0x215c, 0x503f},
  573. {0x215e, 0xffd8},
  574. {0x2160, 0x4f82},
  575. {0x2162, 0x831c},
  576. {0x2164, 0x90f2},
  577. {0x2166, 0x0003},
  578. {0x2168, 0x008c},
  579. {0x216a, 0x2401},
  580. {0x216c, 0x4130},
  581. {0x216e, 0x421f},
  582. {0x2170, 0x831c},
  583. {0x2172, 0x5e0f},
  584. {0x2174, 0x4f82},
  585. {0x2176, 0x831e},
  586. {0x2178, 0x5e0f},
  587. {0x217a, 0x4f82},
  588. {0x217c, 0x8320},
  589. {0x217e, 0x3ff6},
  590. {0x2180, 0x432e},
  591. {0x2182, 0x3fdf},
  592. {0x2184, 0x421f},
  593. {0x2186, 0x7100},
  594. {0x2188, 0x4f0e},
  595. {0x218a, 0x503e},
  596. {0x218c, 0xffd8},
  597. {0x218e, 0x4e82},
  598. {0x2190, 0x7a04},
  599. {0x2192, 0x421e},
  600. {0x2194, 0x831c},
  601. {0x2196, 0x5f0e},
  602. {0x2198, 0x4e82},
  603. {0x219a, 0x7a06},
  604. {0x219c, 0x0b00},
  605. {0x219e, 0x7304},
  606. {0x21a0, 0x0050},
  607. {0x21a2, 0x40b2},
  608. {0x21a4, 0xd081},
  609. {0x21a6, 0x0b88},
  610. {0x21a8, 0x421e},
  611. {0x21aa, 0x831e},
  612. {0x21ac, 0x5f0e},
  613. {0x21ae, 0x4e82},
  614. {0x21b0, 0x7a0e},
  615. {0x21b2, 0x521f},
  616. {0x21b4, 0x8320},
  617. {0x21b6, 0x4f82},
  618. {0x21b8, 0x7a10},
  619. {0x21ba, 0x0b00},
  620. {0x21bc, 0x7304},
  621. {0x21be, 0x007a},
  622. {0x21c0, 0x40b2},
  623. {0x21c2, 0x0081},
  624. {0x21c4, 0x0b88},
  625. {0x21c6, 0x4392},
  626. {0x21c8, 0x7a0a},
  627. {0x21ca, 0x0800},
  628. {0x21cc, 0x7a0c},
  629. {0x21ce, 0x0b00},
  630. {0x21d0, 0x7304},
  631. {0x21d2, 0x022b},
  632. {0x21d4, 0x40b2},
  633. {0x21d6, 0xd081},
  634. {0x21d8, 0x0b88},
  635. {0x21da, 0x0b00},
  636. {0x21dc, 0x7304},
  637. {0x21de, 0x0255},
  638. {0x21e0, 0x40b2},
  639. {0x21e2, 0x0081},
  640. {0x21e4, 0x0b88},
  641. {0x21e6, 0x4130},
  642. {0x23fe, 0xc056},
  643. {0x3232, 0xfc0c},
  644. {0x3236, 0xfc22},
  645. {0x3238, 0xfcfc},
  646. {0x323a, 0xfd84},
  647. {0x323c, 0xfd08},
  648. {0x3246, 0xfcd8},
  649. {0x3248, 0xfca8},
  650. {0x324e, 0xfcb4},
  651. {0x326a, 0x8302},
  652. {0x326c, 0x830a},
  653. {0x326e, 0x0000},
  654. {0x32ca, 0xfc28},
  655. {0x32cc, 0xc3bc},
  656. {0x32ce, 0xc34c},
  657. {0x32d0, 0xc35a},
  658. {0x32d2, 0xc368},
  659. {0x32d4, 0xc376},
  660. {0x32d6, 0xc3c2},
  661. {0x32d8, 0xc3e6},
  662. {0x32da, 0x0003},
  663. {0x32dc, 0x0003},
  664. {0x32de, 0x00c7},
  665. {0x32e0, 0x0031},
  666. {0x32e2, 0x0031},
  667. {0x32e4, 0x0031},
  668. {0x32e6, 0xfc28},
  669. {0x32e8, 0xc3bc},
  670. {0x32ea, 0xc384},
  671. {0x32ec, 0xc392},
  672. {0x32ee, 0xc3a0},
  673. {0x32f0, 0xc3ae},
  674. {0x32f2, 0xc3c4},
  675. {0x32f4, 0xc3e6},
  676. {0x32f6, 0x0003},
  677. {0x32f8, 0x0003},
  678. {0x32fa, 0x00c7},
  679. {0x32fc, 0x0031},
  680. {0x32fe, 0x0031},
  681. {0x3300, 0x0031},
  682. {0x3302, 0x82ca},
  683. {0x3304, 0xc164},
  684. {0x3306, 0x82e6},
  685. {0x3308, 0xc19c},
  686. {0x330a, 0x001f},
  687. {0x330c, 0x001a},
  688. {0x330e, 0x0034},
  689. {0x3310, 0x0000},
  690. {0x3312, 0x0000},
  691. {0x3314, 0xfc94},
  692. {0x3316, 0xc3d8},
  693. {0x0a00, 0x0000},
  694. {0x0e04, 0x0012},
  695. {0x002e, 0x1111},
  696. {0x0032, 0x1111},
  697. {0x0022, 0x0008},
  698. {0x0026, 0x0040},
  699. {0x0028, 0x0017},
  700. {0x002c, 0x09cf},
  701. {0x005c, 0x2101},
  702. {0x0006, 0x09de},
  703. {0x0008, 0x0ed8},
  704. {0x000e, 0x0100},
  705. {0x000c, 0x0022},
  706. {0x0a22, 0x0000},
  707. {0x0a24, 0x0000},
  708. {0x0804, 0x0000},
  709. {0x0a12, 0x0cc0},
  710. {0x0a14, 0x0990},
  711. {0x0074, 0x09d8},
  712. {0x0076, 0x0000},
  713. {0x051e, 0x0000},
  714. {0x0200, 0x0400},
  715. {0x0a1a, 0x0c00},
  716. {0x0a0c, 0x0010},
  717. {0x0a1e, 0x0ccf},
  718. {0x0402, 0x0110},
  719. {0x0404, 0x00f4},
  720. {0x0408, 0x0000},
  721. {0x0410, 0x008d},
  722. {0x0412, 0x011a},
  723. {0x0414, 0x864c},
  724. /* for OTP */
  725. {0x021c, 0x0003},
  726. {0x021e, 0x0235},
  727. /* for OTP */
  728. {0x0c00, 0x9950},
  729. {0x0c06, 0x0021},
  730. {0x0c10, 0x0040},
  731. {0x0c12, 0x0040},
  732. {0x0c14, 0x0040},
  733. {0x0c16, 0x0040},
  734. {0x0a02, 0x0100},
  735. {0x0a04, 0x015a},
  736. {0x0418, 0x0000},
  737. {0x0128, 0x0028},
  738. {0x012a, 0xffff},
  739. {0x0120, 0x0046},
  740. {0x0122, 0x0376},
  741. {0x012c, 0x0020},
  742. {0x012e, 0xffff},
  743. {0x0124, 0x0040},
  744. {0x0126, 0x0378},
  745. {0x0746, 0x0050},
  746. {0x0748, 0x01d5},
  747. {0x074a, 0x022b},
  748. {0x074c, 0x03b0},
  749. {0x0756, 0x043f},
  750. {0x0758, 0x3f1d},
  751. {0x0b02, 0xe04d},
  752. {0x0b10, 0x6821},
  753. {0x0b12, 0x0120},
  754. {0x0b14, 0x0001},
  755. {0x2008, 0x38fd},
  756. {0x326e, 0x0000},
  757. {0x0900, 0x0300},
  758. {0x0902, 0xc319},
  759. {0x0914, 0xc109},
  760. {0x0916, 0x061a},
  761. {0x0918, 0x0407},
  762. {0x091a, 0x0a0b},
  763. {0x091c, 0x0e08},
  764. {0x091e, 0x0a00},
  765. {0x090c, 0x0427},
  766. {0x090e, 0x0059},
  767. {0x0954, 0x0089},
  768. {0x0956, 0x0000},
  769. {0x0958, 0xca80},
  770. {0x095a, 0x9240},
  771. {0x0f08, 0x2f04},
  772. {0x0f30, 0x001f},
  773. {0x0f36, 0x001f},
  774. {0x0f04, 0x3a00},
  775. {0x0f32, 0x025a},
  776. {0x0f38, 0x025a},
  777. {0x0f2a, 0x4124},
  778. {0x006a, 0x0100},
  779. {0x004c, 0x0100},
  780. {0x0044, 0x0001},
  781. };
  782. static const struct hi846_reg mode_640x480_config[] = {
  783. {HI846_REG_MODE_SELECT, 0x0000},
  784. {HI846_REG_Y_ODD_INC_FOBP, 0x7711},
  785. {HI846_REG_Y_ODD_INC_VACT, 0x7711},
  786. {HI846_REG_Y_ADDR_START_VACT_H, 0x0148},
  787. {HI846_REG_Y_ADDR_END_VACT_H, 0x08c7},
  788. {HI846_REG_UNKNOWN_005C, 0x4404},
  789. {HI846_REG_FLL, 0x0277},
  790. {HI846_REG_LLP, 0x0ed8},
  791. {HI846_REG_BINNING_MODE, 0x0322},
  792. {HI846_REG_HBIN_MODE, 0x0200},
  793. {HI846_REG_UNKNOWN_0A24, 0x0000},
  794. {HI846_REG_X_START_H, 0x0058},
  795. {HI846_REG_X_OUTPUT_SIZE_H, 0x0280},
  796. {HI846_REG_Y_OUTPUT_SIZE_H, 0x01e0},
  797. /* For OTP */
  798. {HI846_REG_UNKNOWN_021C, 0x0003},
  799. {HI846_REG_UNKNOWN_021E, 0x0235},
  800. {HI846_REG_ISP_EN_H, 0x016a},
  801. {HI846_REG_UNKNOWN_0418, 0x0210},
  802. {HI846_REG_UNKNOWN_0B02, 0xe04d},
  803. {HI846_REG_UNKNOWN_0B10, 0x7021},
  804. {HI846_REG_UNKNOWN_0B12, 0x0120},
  805. {HI846_REG_UNKNOWN_0B14, 0x0001},
  806. {HI846_REG_UNKNOWN_2008, 0x38fd},
  807. {HI846_REG_UNKNOWN_326E, 0x0000},
  808. };
  809. static const struct hi846_reg mode_640x480_mipi_2lane[] = {
  810. {HI846_REG_UNKNOWN_0900, 0x0300},
  811. {HI846_REG_MIPI_TX_OP_MODE, 0x4319},
  812. {HI846_REG_UNKNOWN_0914, 0xc105},
  813. {HI846_REG_TCLK_PREPARE, 0x030c},
  814. {HI846_REG_UNKNOWN_0918, 0x0304},
  815. {HI846_REG_THS_ZERO, 0x0708},
  816. {HI846_REG_TCLK_POST, 0x0b04},
  817. {HI846_REG_UNKNOWN_091E, 0x0500},
  818. {HI846_REG_UNKNOWN_090C, 0x0208},
  819. {HI846_REG_UNKNOWN_090E, 0x009a},
  820. {HI846_REG_UNKNOWN_0954, 0x0089},
  821. {HI846_REG_UNKNOWN_0956, 0x0000},
  822. {HI846_REG_UNKNOWN_0958, 0xca80},
  823. {HI846_REG_UNKNOWN_095A, 0x9240},
  824. {HI846_REG_PLL_CFG_MIPI2_H, 0x4924},
  825. {HI846_REG_TG_ENABLE, 0x0100},
  826. };
  827. static const struct hi846_reg mode_1280x720_config[] = {
  828. {HI846_REG_MODE_SELECT, 0x0000},
  829. {HI846_REG_Y_ODD_INC_FOBP, 0x3311},
  830. {HI846_REG_Y_ODD_INC_VACT, 0x3311},
  831. {HI846_REG_Y_ADDR_START_VACT_H, 0x0238},
  832. {HI846_REG_Y_ADDR_END_VACT_H, 0x07d7},
  833. {HI846_REG_UNKNOWN_005C, 0x4202},
  834. {HI846_REG_FLL, 0x034a},
  835. {HI846_REG_LLP, 0x0ed8},
  836. {HI846_REG_BINNING_MODE, 0x0122},
  837. {HI846_REG_HBIN_MODE, 0x0100},
  838. {HI846_REG_UNKNOWN_0A24, 0x0000},
  839. {HI846_REG_X_START_H, 0x00b0},
  840. {HI846_REG_X_OUTPUT_SIZE_H, 0x0500},
  841. {HI846_REG_Y_OUTPUT_SIZE_H, 0x02d0},
  842. {HI846_REG_EXPOSURE, 0x0344},
  843. /* For OTP */
  844. {HI846_REG_UNKNOWN_021C, 0x0003},
  845. {HI846_REG_UNKNOWN_021E, 0x0235},
  846. {HI846_REG_ISP_EN_H, 0x016a},
  847. {HI846_REG_UNKNOWN_0418, 0x0410},
  848. {HI846_REG_UNKNOWN_0B02, 0xe04d},
  849. {HI846_REG_UNKNOWN_0B10, 0x6c21},
  850. {HI846_REG_UNKNOWN_0B12, 0x0120},
  851. {HI846_REG_UNKNOWN_0B14, 0x0005},
  852. {HI846_REG_UNKNOWN_2008, 0x38fd},
  853. {HI846_REG_UNKNOWN_326E, 0x0000},
  854. };
  855. static const struct hi846_reg mode_1280x720_mipi_2lane[] = {
  856. {HI846_REG_UNKNOWN_0900, 0x0300},
  857. {HI846_REG_MIPI_TX_OP_MODE, 0x4319},
  858. {HI846_REG_UNKNOWN_0914, 0xc109},
  859. {HI846_REG_TCLK_PREPARE, 0x061a},
  860. {HI846_REG_UNKNOWN_0918, 0x0407},
  861. {HI846_REG_THS_ZERO, 0x0a0b},
  862. {HI846_REG_TCLK_POST, 0x0e08},
  863. {HI846_REG_UNKNOWN_091E, 0x0a00},
  864. {HI846_REG_UNKNOWN_090C, 0x0427},
  865. {HI846_REG_UNKNOWN_090E, 0x0145},
  866. {HI846_REG_UNKNOWN_0954, 0x0089},
  867. {HI846_REG_UNKNOWN_0956, 0x0000},
  868. {HI846_REG_UNKNOWN_0958, 0xca80},
  869. {HI846_REG_UNKNOWN_095A, 0x9240},
  870. {HI846_REG_PLL_CFG_MIPI2_H, 0x4124},
  871. {HI846_REG_TG_ENABLE, 0x0100},
  872. };
  873. static const struct hi846_reg mode_1280x720_mipi_4lane[] = {
  874. /* 360Mbps */
  875. {HI846_REG_UNKNOWN_0900, 0x0300},
  876. {HI846_REG_MIPI_TX_OP_MODE, 0xc319},
  877. {HI846_REG_UNKNOWN_0914, 0xc105},
  878. {HI846_REG_TCLK_PREPARE, 0x030c},
  879. {HI846_REG_UNKNOWN_0918, 0x0304},
  880. {HI846_REG_THS_ZERO, 0x0708},
  881. {HI846_REG_TCLK_POST, 0x0b04},
  882. {HI846_REG_UNKNOWN_091E, 0x0500},
  883. {HI846_REG_UNKNOWN_090C, 0x0208},
  884. {HI846_REG_UNKNOWN_090E, 0x008a},
  885. {HI846_REG_UNKNOWN_0954, 0x0089},
  886. {HI846_REG_UNKNOWN_0956, 0x0000},
  887. {HI846_REG_UNKNOWN_0958, 0xca80},
  888. {HI846_REG_UNKNOWN_095A, 0x9240},
  889. {HI846_REG_PLL_CFG_MIPI2_H, 0x4924},
  890. {HI846_REG_TG_ENABLE, 0x0100},
  891. };
  892. static const struct hi846_reg mode_1632x1224_config[] = {
  893. {HI846_REG_MODE_SELECT, 0x0000},
  894. {HI846_REG_Y_ODD_INC_FOBP, 0x3311},
  895. {HI846_REG_Y_ODD_INC_VACT, 0x3311},
  896. {HI846_REG_Y_ADDR_START_VACT_H, 0x0040},
  897. {HI846_REG_Y_ADDR_END_VACT_H, 0x09cf},
  898. {HI846_REG_UNKNOWN_005C, 0x4202},
  899. {HI846_REG_FLL, 0x09de},
  900. {HI846_REG_LLP, 0x0ed8},
  901. {HI846_REG_BINNING_MODE, 0x0122},
  902. {HI846_REG_HBIN_MODE, 0x0100},
  903. {HI846_REG_UNKNOWN_0A24, 0x0000},
  904. {HI846_REG_X_START_H, 0x0000},
  905. {HI846_REG_X_OUTPUT_SIZE_H, 0x0660},
  906. {HI846_REG_Y_OUTPUT_SIZE_H, 0x04c8},
  907. {HI846_REG_EXPOSURE, 0x09d8},
  908. /* For OTP */
  909. {HI846_REG_UNKNOWN_021C, 0x0003},
  910. {HI846_REG_UNKNOWN_021E, 0x0235},
  911. {HI846_REG_ISP_EN_H, 0x016a},
  912. {HI846_REG_UNKNOWN_0418, 0x0000},
  913. {HI846_REG_UNKNOWN_0B02, 0xe04d},
  914. {HI846_REG_UNKNOWN_0B10, 0x6c21},
  915. {HI846_REG_UNKNOWN_0B12, 0x0120},
  916. {HI846_REG_UNKNOWN_0B14, 0x0005},
  917. {HI846_REG_UNKNOWN_2008, 0x38fd},
  918. {HI846_REG_UNKNOWN_326E, 0x0000},
  919. };
  920. static const struct hi846_reg mode_1632x1224_mipi_2lane[] = {
  921. {HI846_REG_UNKNOWN_0900, 0x0300},
  922. {HI846_REG_MIPI_TX_OP_MODE, 0x4319},
  923. {HI846_REG_UNKNOWN_0914, 0xc109},
  924. {HI846_REG_TCLK_PREPARE, 0x061a},
  925. {HI846_REG_UNKNOWN_0918, 0x0407},
  926. {HI846_REG_THS_ZERO, 0x0a0b},
  927. {HI846_REG_TCLK_POST, 0x0e08},
  928. {HI846_REG_UNKNOWN_091E, 0x0a00},
  929. {HI846_REG_UNKNOWN_090C, 0x0427},
  930. {HI846_REG_UNKNOWN_090E, 0x0069},
  931. {HI846_REG_UNKNOWN_0954, 0x0089},
  932. {HI846_REG_UNKNOWN_0956, 0x0000},
  933. {HI846_REG_UNKNOWN_0958, 0xca80},
  934. {HI846_REG_UNKNOWN_095A, 0x9240},
  935. {HI846_REG_PLL_CFG_MIPI2_H, 0x4124},
  936. {HI846_REG_TG_ENABLE, 0x0100},
  937. };
  938. static const struct hi846_reg mode_1632x1224_mipi_4lane[] = {
  939. {HI846_REG_UNKNOWN_0900, 0x0300},
  940. {HI846_REG_MIPI_TX_OP_MODE, 0xc319},
  941. {HI846_REG_UNKNOWN_0914, 0xc105},
  942. {HI846_REG_TCLK_PREPARE, 0x030c},
  943. {HI846_REG_UNKNOWN_0918, 0x0304},
  944. {HI846_REG_THS_ZERO, 0x0708},
  945. {HI846_REG_TCLK_POST, 0x0b04},
  946. {HI846_REG_UNKNOWN_091E, 0x0500},
  947. {HI846_REG_UNKNOWN_090C, 0x0208},
  948. {HI846_REG_UNKNOWN_090E, 0x001c},
  949. {HI846_REG_UNKNOWN_0954, 0x0089},
  950. {HI846_REG_UNKNOWN_0956, 0x0000},
  951. {HI846_REG_UNKNOWN_0958, 0xca80},
  952. {HI846_REG_UNKNOWN_095A, 0x9240},
  953. {HI846_REG_PLL_CFG_MIPI2_H, 0x4924},
  954. {HI846_REG_TG_ENABLE, 0x0100},
  955. };
  956. static const char * const hi846_test_pattern_menu[] = {
  957. "Disabled",
  958. "Solid Colour",
  959. "100% Colour Bars",
  960. "Fade To Grey Colour Bars",
  961. "PN9",
  962. "Gradient Horizontal",
  963. "Gradient Vertical",
  964. "Check Board",
  965. "Slant Pattern",
  966. "Resolution Pattern",
  967. };
  968. #define FREQ_INDEX_640 0
  969. #define FREQ_INDEX_1280 1
  970. static const s64 hi846_link_freqs[] = {
  971. [FREQ_INDEX_640] = 80000000,
  972. [FREQ_INDEX_1280] = 200000000,
  973. };
  974. static const struct hi846_reg_list hi846_init_regs_list_2lane = {
  975. .num_of_regs = ARRAY_SIZE(hi846_init_2lane),
  976. .regs = hi846_init_2lane,
  977. };
  978. static const struct hi846_reg_list hi846_init_regs_list_4lane = {
  979. .num_of_regs = ARRAY_SIZE(hi846_init_4lane),
  980. .regs = hi846_init_4lane,
  981. };
  982. static const struct hi846_mode supported_modes[] = {
  983. {
  984. .width = 640,
  985. .height = 480,
  986. .link_freq_index = FREQ_INDEX_640,
  987. .fps = 120,
  988. .frame_len = 631,
  989. .llp = HI846_LINE_LENGTH,
  990. .reg_list_config = {
  991. .num_of_regs = ARRAY_SIZE(mode_640x480_config),
  992. .regs = mode_640x480_config,
  993. },
  994. .reg_list_2lane = {
  995. .num_of_regs = ARRAY_SIZE(mode_640x480_mipi_2lane),
  996. .regs = mode_640x480_mipi_2lane,
  997. },
  998. .reg_list_4lane = {
  999. .num_of_regs = 0,
  1000. },
  1001. .crop = {
  1002. .left = 0x58,
  1003. .top = 0x148,
  1004. .width = 640 * 4,
  1005. .height = 480 * 4,
  1006. },
  1007. },
  1008. {
  1009. .width = 1280,
  1010. .height = 720,
  1011. .link_freq_index = FREQ_INDEX_1280,
  1012. .fps = 90,
  1013. .frame_len = 842,
  1014. .llp = HI846_LINE_LENGTH,
  1015. .reg_list_config = {
  1016. .num_of_regs = ARRAY_SIZE(mode_1280x720_config),
  1017. .regs = mode_1280x720_config,
  1018. },
  1019. .reg_list_2lane = {
  1020. .num_of_regs = ARRAY_SIZE(mode_1280x720_mipi_2lane),
  1021. .regs = mode_1280x720_mipi_2lane,
  1022. },
  1023. .reg_list_4lane = {
  1024. .num_of_regs = ARRAY_SIZE(mode_1280x720_mipi_4lane),
  1025. .regs = mode_1280x720_mipi_4lane,
  1026. },
  1027. .crop = {
  1028. .left = 0xb0,
  1029. .top = 0x238,
  1030. .width = 1280 * 2,
  1031. .height = 720 * 2,
  1032. },
  1033. },
  1034. {
  1035. .width = 1632,
  1036. .height = 1224,
  1037. .link_freq_index = FREQ_INDEX_1280,
  1038. .fps = 30,
  1039. .frame_len = 2526,
  1040. .llp = HI846_LINE_LENGTH,
  1041. .reg_list_config = {
  1042. .num_of_regs = ARRAY_SIZE(mode_1632x1224_config),
  1043. .regs = mode_1632x1224_config,
  1044. },
  1045. .reg_list_2lane = {
  1046. .num_of_regs = ARRAY_SIZE(mode_1632x1224_mipi_2lane),
  1047. .regs = mode_1632x1224_mipi_2lane,
  1048. },
  1049. .reg_list_4lane = {
  1050. .num_of_regs = ARRAY_SIZE(mode_1632x1224_mipi_4lane),
  1051. .regs = mode_1632x1224_mipi_4lane,
  1052. },
  1053. .crop = {
  1054. .left = 0x0,
  1055. .top = 0x0,
  1056. .width = 1632 * 2,
  1057. .height = 1224 * 2,
  1058. },
  1059. }
  1060. };
  1061. struct hi846_datafmt {
  1062. u32 code;
  1063. enum v4l2_colorspace colorspace;
  1064. };
  1065. static const char * const hi846_supply_names[] = {
  1066. "vddio", /* Digital I/O (1.8V or 2.8V) */
  1067. "vdda", /* Analog (2.8V) */
  1068. "vddd", /* Digital Core (1.2V) */
  1069. };
  1070. #define HI846_NUM_SUPPLIES ARRAY_SIZE(hi846_supply_names)
  1071. struct hi846 {
  1072. struct gpio_desc *rst_gpio;
  1073. struct gpio_desc *shutdown_gpio;
  1074. struct regulator_bulk_data supplies[HI846_NUM_SUPPLIES];
  1075. struct clk *clock;
  1076. const struct hi846_datafmt *fmt;
  1077. struct v4l2_subdev sd;
  1078. struct media_pad pad;
  1079. struct v4l2_ctrl_handler ctrl_handler;
  1080. u8 nr_lanes;
  1081. struct v4l2_ctrl *link_freq;
  1082. struct v4l2_ctrl *pixel_rate;
  1083. struct v4l2_ctrl *vblank;
  1084. struct v4l2_ctrl *hblank;
  1085. struct v4l2_ctrl *exposure;
  1086. struct mutex mutex; /* protect cur_mode, streaming and chip access */
  1087. const struct hi846_mode *cur_mode;
  1088. bool streaming;
  1089. };
  1090. static inline struct hi846 *to_hi846(struct v4l2_subdev *sd)
  1091. {
  1092. return container_of(sd, struct hi846, sd);
  1093. }
  1094. static const struct hi846_datafmt hi846_colour_fmts[] = {
  1095. { HI846_MEDIA_BUS_FORMAT, V4L2_COLORSPACE_RAW },
  1096. };
  1097. static const struct hi846_datafmt *hi846_find_datafmt(u32 code)
  1098. {
  1099. unsigned int i;
  1100. for (i = 0; i < ARRAY_SIZE(hi846_colour_fmts); i++)
  1101. if (hi846_colour_fmts[i].code == code)
  1102. return &hi846_colour_fmts[i];
  1103. return NULL;
  1104. }
  1105. static inline u8 hi846_get_link_freq_index(struct hi846 *hi846)
  1106. {
  1107. return hi846->cur_mode->link_freq_index;
  1108. }
  1109. static u64 hi846_get_link_freq(struct hi846 *hi846)
  1110. {
  1111. u8 index = hi846_get_link_freq_index(hi846);
  1112. return hi846_link_freqs[index];
  1113. }
  1114. static u64 hi846_calc_pixel_rate(struct hi846 *hi846)
  1115. {
  1116. u64 link_freq = hi846_get_link_freq(hi846);
  1117. u64 pixel_rate = link_freq * 2 * hi846->nr_lanes;
  1118. do_div(pixel_rate, HI846_RGB_DEPTH);
  1119. return pixel_rate;
  1120. }
  1121. static int hi846_read_reg(struct hi846 *hi846, u16 reg, u8 *val)
  1122. {
  1123. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1124. struct i2c_msg msgs[2];
  1125. u8 addr_buf[2];
  1126. u8 data_buf[1] = {0};
  1127. int ret;
  1128. put_unaligned_be16(reg, addr_buf);
  1129. msgs[0].addr = client->addr;
  1130. msgs[0].flags = 0;
  1131. msgs[0].len = sizeof(addr_buf);
  1132. msgs[0].buf = addr_buf;
  1133. msgs[1].addr = client->addr;
  1134. msgs[1].flags = I2C_M_RD;
  1135. msgs[1].len = 1;
  1136. msgs[1].buf = data_buf;
  1137. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  1138. if (ret != ARRAY_SIZE(msgs)) {
  1139. dev_err(&client->dev, "i2c read error: %d\n", ret);
  1140. return -EIO;
  1141. }
  1142. *val = data_buf[0];
  1143. return 0;
  1144. }
  1145. static int hi846_write_reg(struct hi846 *hi846, u16 reg, u8 val)
  1146. {
  1147. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1148. u8 buf[3] = { reg >> 8, reg & 0xff, val };
  1149. struct i2c_msg msg[] = {
  1150. { .addr = client->addr, .flags = 0,
  1151. .len = ARRAY_SIZE(buf), .buf = buf },
  1152. };
  1153. int ret;
  1154. ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
  1155. if (ret != ARRAY_SIZE(msg)) {
  1156. dev_err(&client->dev, "i2c write error\n");
  1157. return -EIO;
  1158. }
  1159. return 0;
  1160. }
  1161. static void hi846_write_reg_16(struct hi846 *hi846, u16 reg, u16 val, int *err)
  1162. {
  1163. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1164. u8 buf[4];
  1165. int ret;
  1166. if (*err < 0)
  1167. return;
  1168. put_unaligned_be16(reg, buf);
  1169. put_unaligned_be16(val, buf + 2);
  1170. ret = i2c_master_send(client, buf, sizeof(buf));
  1171. if (ret != sizeof(buf)) {
  1172. dev_err(&client->dev, "i2c_master_send != %zu: %d\n",
  1173. sizeof(buf), ret);
  1174. *err = -EIO;
  1175. }
  1176. }
  1177. static int hi846_write_reg_list(struct hi846 *hi846,
  1178. const struct hi846_reg_list *r_list)
  1179. {
  1180. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1181. unsigned int i;
  1182. int ret = 0;
  1183. for (i = 0; i < r_list->num_of_regs; i++) {
  1184. hi846_write_reg_16(hi846, r_list->regs[i].address,
  1185. r_list->regs[i].val, &ret);
  1186. if (ret) {
  1187. dev_err_ratelimited(&client->dev,
  1188. "failed to write reg 0x%4.4x: %d",
  1189. r_list->regs[i].address, ret);
  1190. return ret;
  1191. }
  1192. }
  1193. return 0;
  1194. }
  1195. static int hi846_update_digital_gain(struct hi846 *hi846, u16 d_gain)
  1196. {
  1197. int ret = 0;
  1198. hi846_write_reg_16(hi846, HI846_REG_MWB_GR_GAIN_H, d_gain, &ret);
  1199. hi846_write_reg_16(hi846, HI846_REG_MWB_GB_GAIN_H, d_gain, &ret);
  1200. hi846_write_reg_16(hi846, HI846_REG_MWB_R_GAIN_H, d_gain, &ret);
  1201. hi846_write_reg_16(hi846, HI846_REG_MWB_B_GAIN_H, d_gain, &ret);
  1202. return ret;
  1203. }
  1204. static int hi846_test_pattern(struct hi846 *hi846, u32 pattern)
  1205. {
  1206. int ret;
  1207. u8 val;
  1208. if (pattern) {
  1209. ret = hi846_read_reg(hi846, HI846_REG_ISP, &val);
  1210. if (ret)
  1211. return ret;
  1212. ret = hi846_write_reg(hi846, HI846_REG_ISP,
  1213. val | HI846_REG_ISP_TPG_EN);
  1214. if (ret)
  1215. return ret;
  1216. }
  1217. return hi846_write_reg(hi846, HI846_REG_TEST_PATTERN, pattern);
  1218. }
  1219. static int hi846_set_ctrl(struct v4l2_ctrl *ctrl)
  1220. {
  1221. struct hi846 *hi846 = container_of(ctrl->handler,
  1222. struct hi846, ctrl_handler);
  1223. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1224. s64 exposure_max;
  1225. int ret = 0;
  1226. u32 shutter, frame_len;
  1227. /* Propagate change of current control to all related controls */
  1228. if (ctrl->id == V4L2_CID_VBLANK) {
  1229. /* Update max exposure while meeting expected vblanking */
  1230. exposure_max = hi846->cur_mode->height + ctrl->val -
  1231. HI846_EXPOSURE_MAX_MARGIN;
  1232. __v4l2_ctrl_modify_range(hi846->exposure,
  1233. hi846->exposure->minimum,
  1234. exposure_max, hi846->exposure->step,
  1235. exposure_max);
  1236. }
  1237. ret = pm_runtime_get_if_in_use(&client->dev);
  1238. if (!ret || ret == -EAGAIN)
  1239. return 0;
  1240. switch (ctrl->id) {
  1241. case V4L2_CID_ANALOGUE_GAIN:
  1242. ret = hi846_write_reg(hi846, HI846_REG_ANALOG_GAIN, ctrl->val);
  1243. break;
  1244. case V4L2_CID_DIGITAL_GAIN:
  1245. ret = hi846_update_digital_gain(hi846, ctrl->val);
  1246. break;
  1247. case V4L2_CID_EXPOSURE:
  1248. shutter = ctrl->val;
  1249. frame_len = hi846->cur_mode->frame_len;
  1250. if (shutter > frame_len - 6) { /* margin */
  1251. frame_len = shutter + 6;
  1252. if (frame_len > 0xffff) { /* max frame len */
  1253. frame_len = 0xffff;
  1254. }
  1255. }
  1256. if (shutter < 6)
  1257. shutter = 6;
  1258. if (shutter > (0xffff - 6))
  1259. shutter = 0xffff - 6;
  1260. hi846_write_reg_16(hi846, HI846_REG_FLL, frame_len, &ret);
  1261. hi846_write_reg_16(hi846, HI846_REG_EXPOSURE, shutter, &ret);
  1262. break;
  1263. case V4L2_CID_VBLANK:
  1264. /* Update FLL that meets expected vertical blanking */
  1265. hi846_write_reg_16(hi846, HI846_REG_FLL,
  1266. hi846->cur_mode->height + ctrl->val, &ret);
  1267. break;
  1268. case V4L2_CID_TEST_PATTERN:
  1269. ret = hi846_test_pattern(hi846, ctrl->val);
  1270. break;
  1271. default:
  1272. ret = -EINVAL;
  1273. break;
  1274. }
  1275. pm_runtime_put(&client->dev);
  1276. return ret;
  1277. }
  1278. static const struct v4l2_ctrl_ops hi846_ctrl_ops = {
  1279. .s_ctrl = hi846_set_ctrl,
  1280. };
  1281. static int hi846_init_controls(struct hi846 *hi846)
  1282. {
  1283. struct v4l2_ctrl_handler *ctrl_hdlr;
  1284. s64 exposure_max, h_blank;
  1285. int ret;
  1286. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1287. struct v4l2_fwnode_device_properties props;
  1288. ctrl_hdlr = &hi846->ctrl_handler;
  1289. ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
  1290. if (ret)
  1291. return ret;
  1292. ctrl_hdlr->lock = &hi846->mutex;
  1293. hi846->link_freq =
  1294. v4l2_ctrl_new_int_menu(ctrl_hdlr, &hi846_ctrl_ops,
  1295. V4L2_CID_LINK_FREQ,
  1296. ARRAY_SIZE(hi846_link_freqs) - 1,
  1297. 0, hi846_link_freqs);
  1298. if (hi846->link_freq)
  1299. hi846->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  1300. hi846->pixel_rate =
  1301. v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
  1302. V4L2_CID_PIXEL_RATE, 0,
  1303. hi846_calc_pixel_rate(hi846), 1,
  1304. hi846_calc_pixel_rate(hi846));
  1305. hi846->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
  1306. V4L2_CID_VBLANK,
  1307. hi846->cur_mode->frame_len -
  1308. hi846->cur_mode->height,
  1309. HI846_FLL_MAX -
  1310. hi846->cur_mode->height, 1,
  1311. hi846->cur_mode->frame_len -
  1312. hi846->cur_mode->height);
  1313. h_blank = hi846->cur_mode->llp - hi846->cur_mode->width;
  1314. hi846->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
  1315. V4L2_CID_HBLANK, h_blank, h_blank, 1,
  1316. h_blank);
  1317. if (hi846->hblank)
  1318. hi846->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
  1319. v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
  1320. HI846_ANAL_GAIN_MIN, HI846_ANAL_GAIN_MAX,
  1321. HI846_ANAL_GAIN_STEP, HI846_ANAL_GAIN_MIN);
  1322. v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
  1323. HI846_DGTL_GAIN_MIN, HI846_DGTL_GAIN_MAX,
  1324. HI846_DGTL_GAIN_STEP, HI846_DGTL_GAIN_DEFAULT);
  1325. exposure_max = hi846->cur_mode->frame_len - HI846_EXPOSURE_MAX_MARGIN;
  1326. hi846->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &hi846_ctrl_ops,
  1327. V4L2_CID_EXPOSURE,
  1328. HI846_EXPOSURE_MIN, exposure_max,
  1329. HI846_EXPOSURE_STEP,
  1330. exposure_max);
  1331. v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &hi846_ctrl_ops,
  1332. V4L2_CID_TEST_PATTERN,
  1333. ARRAY_SIZE(hi846_test_pattern_menu) - 1,
  1334. 0, 0, hi846_test_pattern_menu);
  1335. if (ctrl_hdlr->error) {
  1336. dev_err(&client->dev, "v4l ctrl handler error: %d\n",
  1337. ctrl_hdlr->error);
  1338. ret = ctrl_hdlr->error;
  1339. goto error;
  1340. }
  1341. ret = v4l2_fwnode_device_parse(&client->dev, &props);
  1342. if (ret)
  1343. goto error;
  1344. ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &hi846_ctrl_ops,
  1345. &props);
  1346. if (ret)
  1347. goto error;
  1348. hi846->sd.ctrl_handler = ctrl_hdlr;
  1349. return 0;
  1350. error:
  1351. v4l2_ctrl_handler_free(ctrl_hdlr);
  1352. return ret;
  1353. }
  1354. static int hi846_set_video_mode(struct hi846 *hi846, int fps)
  1355. {
  1356. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1357. u64 frame_length;
  1358. int ret = 0;
  1359. int dummy_lines;
  1360. u64 link_freq = hi846_get_link_freq(hi846);
  1361. dev_dbg(&client->dev, "%s: link freq: %llu\n", __func__,
  1362. hi846_get_link_freq(hi846));
  1363. do_div(link_freq, fps);
  1364. frame_length = link_freq;
  1365. do_div(frame_length, HI846_LINE_LENGTH);
  1366. dummy_lines = (frame_length > hi846->cur_mode->frame_len) ?
  1367. (frame_length - hi846->cur_mode->frame_len) : 0;
  1368. frame_length = hi846->cur_mode->frame_len + dummy_lines;
  1369. dev_dbg(&client->dev, "%s: frame length calculated: %llu\n", __func__,
  1370. frame_length);
  1371. hi846_write_reg_16(hi846, HI846_REG_FLL, frame_length & 0xFFFF, &ret);
  1372. hi846_write_reg_16(hi846, HI846_REG_LLP,
  1373. HI846_LINE_LENGTH & 0xFFFF, &ret);
  1374. return ret;
  1375. }
  1376. static int hi846_start_streaming(struct hi846 *hi846)
  1377. {
  1378. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1379. int ret = 0;
  1380. u8 val;
  1381. if (hi846->nr_lanes == 2)
  1382. ret = hi846_write_reg_list(hi846, &hi846_init_regs_list_2lane);
  1383. else
  1384. ret = hi846_write_reg_list(hi846, &hi846_init_regs_list_4lane);
  1385. if (ret) {
  1386. dev_err(&client->dev, "failed to set plls: %d\n", ret);
  1387. return ret;
  1388. }
  1389. ret = hi846_write_reg_list(hi846, &hi846->cur_mode->reg_list_config);
  1390. if (ret) {
  1391. dev_err(&client->dev, "failed to set mode: %d\n", ret);
  1392. return ret;
  1393. }
  1394. if (hi846->nr_lanes == 2)
  1395. ret = hi846_write_reg_list(hi846,
  1396. &hi846->cur_mode->reg_list_2lane);
  1397. else
  1398. ret = hi846_write_reg_list(hi846,
  1399. &hi846->cur_mode->reg_list_4lane);
  1400. if (ret) {
  1401. dev_err(&client->dev, "failed to set mipi mode: %d\n", ret);
  1402. return ret;
  1403. }
  1404. hi846_set_video_mode(hi846, hi846->cur_mode->fps);
  1405. ret = __v4l2_ctrl_handler_setup(hi846->sd.ctrl_handler);
  1406. if (ret)
  1407. return ret;
  1408. /*
  1409. * Reading 0x0034 is purely done for debugging reasons: It is not
  1410. * documented in the DS but only mentioned once:
  1411. * "If 0x0034[2] bit is disabled , Visible pixel width and height is 0."
  1412. * So even though that sounds like we won't see anything, we don't
  1413. * know more about this, so in that case only inform the user but do
  1414. * nothing more.
  1415. */
  1416. ret = hi846_read_reg(hi846, 0x0034, &val);
  1417. if (ret)
  1418. return ret;
  1419. if (!(val & BIT(2)))
  1420. dev_info(&client->dev, "visible pixel width and height is 0\n");
  1421. ret = hi846_write_reg(hi846, HI846_REG_MODE_SELECT,
  1422. HI846_MODE_STREAMING);
  1423. if (ret) {
  1424. dev_err(&client->dev, "failed to start stream");
  1425. return ret;
  1426. }
  1427. hi846->streaming = 1;
  1428. dev_dbg(&client->dev, "%s: started streaming successfully\n", __func__);
  1429. return ret;
  1430. }
  1431. static void hi846_stop_streaming(struct hi846 *hi846)
  1432. {
  1433. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1434. if (hi846_write_reg(hi846, HI846_REG_MODE_SELECT, HI846_MODE_STANDBY))
  1435. dev_err(&client->dev, "failed to stop stream");
  1436. hi846->streaming = 0;
  1437. }
  1438. static int hi846_set_stream(struct v4l2_subdev *sd, int enable)
  1439. {
  1440. struct hi846 *hi846 = to_hi846(sd);
  1441. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1442. int ret = 0;
  1443. if (hi846->streaming == enable)
  1444. return 0;
  1445. mutex_lock(&hi846->mutex);
  1446. if (enable) {
  1447. ret = pm_runtime_get_sync(&client->dev);
  1448. if (ret < 0) {
  1449. pm_runtime_put_noidle(&client->dev);
  1450. goto out;
  1451. }
  1452. ret = hi846_start_streaming(hi846);
  1453. }
  1454. if (!enable || ret) {
  1455. hi846_stop_streaming(hi846);
  1456. pm_runtime_put(&client->dev);
  1457. }
  1458. out:
  1459. mutex_unlock(&hi846->mutex);
  1460. return ret;
  1461. }
  1462. static int hi846_power_on(struct hi846 *hi846)
  1463. {
  1464. int ret;
  1465. ret = regulator_bulk_enable(HI846_NUM_SUPPLIES, hi846->supplies);
  1466. if (ret < 0)
  1467. return ret;
  1468. ret = clk_prepare_enable(hi846->clock);
  1469. if (ret < 0)
  1470. goto err_reg;
  1471. if (hi846->shutdown_gpio)
  1472. gpiod_set_value_cansleep(hi846->shutdown_gpio, 0);
  1473. /* 30us = 2400 cycles at 80Mhz */
  1474. usleep_range(30, 60);
  1475. if (hi846->rst_gpio)
  1476. gpiod_set_value_cansleep(hi846->rst_gpio, 0);
  1477. usleep_range(30, 60);
  1478. return 0;
  1479. err_reg:
  1480. regulator_bulk_disable(HI846_NUM_SUPPLIES, hi846->supplies);
  1481. return ret;
  1482. }
  1483. static int hi846_power_off(struct hi846 *hi846)
  1484. {
  1485. if (hi846->rst_gpio)
  1486. gpiod_set_value_cansleep(hi846->rst_gpio, 1);
  1487. if (hi846->shutdown_gpio)
  1488. gpiod_set_value_cansleep(hi846->shutdown_gpio, 1);
  1489. clk_disable_unprepare(hi846->clock);
  1490. return regulator_bulk_disable(HI846_NUM_SUPPLIES, hi846->supplies);
  1491. }
  1492. static int __maybe_unused hi846_suspend(struct device *dev)
  1493. {
  1494. struct i2c_client *client = to_i2c_client(dev);
  1495. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1496. struct hi846 *hi846 = to_hi846(sd);
  1497. if (hi846->streaming)
  1498. hi846_stop_streaming(hi846);
  1499. return hi846_power_off(hi846);
  1500. }
  1501. static int __maybe_unused hi846_resume(struct device *dev)
  1502. {
  1503. struct i2c_client *client = to_i2c_client(dev);
  1504. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1505. struct hi846 *hi846 = to_hi846(sd);
  1506. int ret;
  1507. ret = hi846_power_on(hi846);
  1508. if (ret)
  1509. return ret;
  1510. if (hi846->streaming) {
  1511. ret = hi846_start_streaming(hi846);
  1512. if (ret) {
  1513. dev_err(dev, "%s: start streaming failed: %d\n",
  1514. __func__, ret);
  1515. goto error;
  1516. }
  1517. }
  1518. return 0;
  1519. error:
  1520. hi846_power_off(hi846);
  1521. return ret;
  1522. }
  1523. static int hi846_set_format(struct v4l2_subdev *sd,
  1524. struct v4l2_subdev_state *sd_state,
  1525. struct v4l2_subdev_format *format)
  1526. {
  1527. struct hi846 *hi846 = to_hi846(sd);
  1528. struct v4l2_mbus_framefmt *mf = &format->format;
  1529. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1530. const struct hi846_datafmt *fmt = hi846_find_datafmt(mf->code);
  1531. u32 tgt_fps;
  1532. s32 vblank_def, h_blank;
  1533. if (!fmt) {
  1534. mf->code = hi846_colour_fmts[0].code;
  1535. mf->colorspace = hi846_colour_fmts[0].colorspace;
  1536. fmt = &hi846_colour_fmts[0];
  1537. }
  1538. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1539. *v4l2_subdev_get_try_format(sd, sd_state, format->pad) = *mf;
  1540. return 0;
  1541. }
  1542. if (hi846->nr_lanes == 2) {
  1543. if (!hi846->cur_mode->reg_list_2lane.num_of_regs) {
  1544. dev_err(&client->dev,
  1545. "this mode is not supported for 2 lanes\n");
  1546. return -EINVAL;
  1547. }
  1548. } else {
  1549. if (!hi846->cur_mode->reg_list_4lane.num_of_regs) {
  1550. dev_err(&client->dev,
  1551. "this mode is not supported for 4 lanes\n");
  1552. return -EINVAL;
  1553. }
  1554. }
  1555. mutex_lock(&hi846->mutex);
  1556. if (hi846->streaming) {
  1557. mutex_unlock(&hi846->mutex);
  1558. return -EBUSY;
  1559. }
  1560. hi846->fmt = fmt;
  1561. hi846->cur_mode =
  1562. v4l2_find_nearest_size(supported_modes,
  1563. ARRAY_SIZE(supported_modes),
  1564. width, height, mf->width, mf->height);
  1565. dev_dbg(&client->dev, "%s: found mode: %dx%d\n", __func__,
  1566. hi846->cur_mode->width, hi846->cur_mode->height);
  1567. tgt_fps = hi846->cur_mode->fps;
  1568. dev_dbg(&client->dev, "%s: target fps: %d\n", __func__, tgt_fps);
  1569. mf->width = hi846->cur_mode->width;
  1570. mf->height = hi846->cur_mode->height;
  1571. mf->code = HI846_MEDIA_BUS_FORMAT;
  1572. mf->field = V4L2_FIELD_NONE;
  1573. __v4l2_ctrl_s_ctrl(hi846->link_freq, hi846_get_link_freq_index(hi846));
  1574. __v4l2_ctrl_s_ctrl_int64(hi846->pixel_rate,
  1575. hi846_calc_pixel_rate(hi846));
  1576. /* Update limits and set FPS to default */
  1577. vblank_def = hi846->cur_mode->frame_len - hi846->cur_mode->height;
  1578. __v4l2_ctrl_modify_range(hi846->vblank,
  1579. hi846->cur_mode->frame_len -
  1580. hi846->cur_mode->height,
  1581. HI846_FLL_MAX - hi846->cur_mode->height, 1,
  1582. vblank_def);
  1583. __v4l2_ctrl_s_ctrl(hi846->vblank, vblank_def);
  1584. h_blank = hi846->cur_mode->llp - hi846->cur_mode->width;
  1585. __v4l2_ctrl_modify_range(hi846->hblank, h_blank, h_blank, 1,
  1586. h_blank);
  1587. dev_dbg(&client->dev, "Set fmt w=%d h=%d code=0x%x colorspace=0x%x\n",
  1588. mf->width, mf->height,
  1589. fmt->code, fmt->colorspace);
  1590. mutex_unlock(&hi846->mutex);
  1591. return 0;
  1592. }
  1593. static int hi846_get_format(struct v4l2_subdev *sd,
  1594. struct v4l2_subdev_state *sd_state,
  1595. struct v4l2_subdev_format *format)
  1596. {
  1597. struct hi846 *hi846 = to_hi846(sd);
  1598. struct v4l2_mbus_framefmt *mf = &format->format;
  1599. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1600. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  1601. format->format = *v4l2_subdev_get_try_format(&hi846->sd,
  1602. sd_state,
  1603. format->pad);
  1604. return 0;
  1605. }
  1606. mutex_lock(&hi846->mutex);
  1607. mf->code = HI846_MEDIA_BUS_FORMAT;
  1608. mf->colorspace = V4L2_COLORSPACE_RAW;
  1609. mf->field = V4L2_FIELD_NONE;
  1610. mf->width = hi846->cur_mode->width;
  1611. mf->height = hi846->cur_mode->height;
  1612. mutex_unlock(&hi846->mutex);
  1613. dev_dbg(&client->dev,
  1614. "Get format w=%d h=%d code=0x%x colorspace=0x%x\n",
  1615. mf->width, mf->height, mf->code, mf->colorspace);
  1616. return 0;
  1617. }
  1618. static int hi846_enum_mbus_code(struct v4l2_subdev *sd,
  1619. struct v4l2_subdev_state *sd_state,
  1620. struct v4l2_subdev_mbus_code_enum *code)
  1621. {
  1622. if (code->pad || code->index > 0)
  1623. return -EINVAL;
  1624. code->code = HI846_MEDIA_BUS_FORMAT;
  1625. return 0;
  1626. }
  1627. static int hi846_enum_frame_size(struct v4l2_subdev *sd,
  1628. struct v4l2_subdev_state *sd_state,
  1629. struct v4l2_subdev_frame_size_enum *fse)
  1630. {
  1631. struct i2c_client *client = v4l2_get_subdevdata(sd);
  1632. if (fse->pad || fse->index >= ARRAY_SIZE(supported_modes))
  1633. return -EINVAL;
  1634. if (fse->code != HI846_MEDIA_BUS_FORMAT) {
  1635. dev_err(&client->dev, "frame size enum not matching\n");
  1636. return -EINVAL;
  1637. }
  1638. fse->min_width = supported_modes[fse->index].width;
  1639. fse->max_width = supported_modes[fse->index].width;
  1640. fse->min_height = supported_modes[fse->index].height;
  1641. fse->max_height = supported_modes[fse->index].height;
  1642. dev_dbg(&client->dev, "%s: max width: %d max height: %d\n", __func__,
  1643. fse->max_width, fse->max_height);
  1644. return 0;
  1645. }
  1646. static int hi846_get_selection(struct v4l2_subdev *sd,
  1647. struct v4l2_subdev_state *sd_state,
  1648. struct v4l2_subdev_selection *sel)
  1649. {
  1650. struct hi846 *hi846 = to_hi846(sd);
  1651. switch (sel->target) {
  1652. case V4L2_SEL_TGT_CROP:
  1653. case V4L2_SEL_TGT_CROP_DEFAULT:
  1654. mutex_lock(&hi846->mutex);
  1655. switch (sel->which) {
  1656. case V4L2_SUBDEV_FORMAT_TRY:
  1657. v4l2_subdev_get_try_crop(sd, sd_state, sel->pad);
  1658. break;
  1659. case V4L2_SUBDEV_FORMAT_ACTIVE:
  1660. sel->r = hi846->cur_mode->crop;
  1661. break;
  1662. }
  1663. mutex_unlock(&hi846->mutex);
  1664. return 0;
  1665. case V4L2_SEL_TGT_CROP_BOUNDS:
  1666. case V4L2_SEL_TGT_NATIVE_SIZE:
  1667. sel->r.top = 0;
  1668. sel->r.left = 0;
  1669. sel->r.width = 3264;
  1670. sel->r.height = 2448;
  1671. return 0;
  1672. default:
  1673. return -EINVAL;
  1674. }
  1675. }
  1676. static int hi846_init_cfg(struct v4l2_subdev *sd,
  1677. struct v4l2_subdev_state *sd_state)
  1678. {
  1679. struct hi846 *hi846 = to_hi846(sd);
  1680. struct v4l2_mbus_framefmt *mf;
  1681. mf = v4l2_subdev_get_try_format(sd, sd_state, 0);
  1682. mutex_lock(&hi846->mutex);
  1683. mf->code = HI846_MEDIA_BUS_FORMAT;
  1684. mf->colorspace = V4L2_COLORSPACE_RAW;
  1685. mf->field = V4L2_FIELD_NONE;
  1686. mf->width = hi846->cur_mode->width;
  1687. mf->height = hi846->cur_mode->height;
  1688. mutex_unlock(&hi846->mutex);
  1689. return 0;
  1690. }
  1691. static const struct v4l2_subdev_video_ops hi846_video_ops = {
  1692. .s_stream = hi846_set_stream,
  1693. };
  1694. static const struct v4l2_subdev_pad_ops hi846_pad_ops = {
  1695. .init_cfg = hi846_init_cfg,
  1696. .enum_frame_size = hi846_enum_frame_size,
  1697. .enum_mbus_code = hi846_enum_mbus_code,
  1698. .set_fmt = hi846_set_format,
  1699. .get_fmt = hi846_get_format,
  1700. .get_selection = hi846_get_selection,
  1701. };
  1702. static const struct v4l2_subdev_ops hi846_subdev_ops = {
  1703. .video = &hi846_video_ops,
  1704. .pad = &hi846_pad_ops,
  1705. };
  1706. static const struct media_entity_operations hi846_subdev_entity_ops = {
  1707. .link_validate = v4l2_subdev_link_validate,
  1708. };
  1709. static int hi846_identify_module(struct hi846 *hi846)
  1710. {
  1711. struct i2c_client *client = v4l2_get_subdevdata(&hi846->sd);
  1712. int ret;
  1713. u8 hi, lo;
  1714. ret = hi846_read_reg(hi846, HI846_REG_CHIP_ID_L, &lo);
  1715. if (ret)
  1716. return ret;
  1717. if (lo != HI846_CHIP_ID_L) {
  1718. dev_err(&client->dev, "wrong chip id low byte: %x", lo);
  1719. return -ENXIO;
  1720. }
  1721. ret = hi846_read_reg(hi846, HI846_REG_CHIP_ID_H, &hi);
  1722. if (ret)
  1723. return ret;
  1724. if (hi != HI846_CHIP_ID_H) {
  1725. dev_err(&client->dev, "wrong chip id high byte: %x", hi);
  1726. return -ENXIO;
  1727. }
  1728. dev_info(&client->dev, "chip id %02X %02X using %d mipi lanes\n",
  1729. hi, lo, hi846->nr_lanes);
  1730. return 0;
  1731. }
  1732. static s64 hi846_check_link_freqs(struct hi846 *hi846,
  1733. struct v4l2_fwnode_endpoint *ep)
  1734. {
  1735. const s64 *freqs = hi846_link_freqs;
  1736. int freqs_count = ARRAY_SIZE(hi846_link_freqs);
  1737. int i, j;
  1738. for (i = 0; i < freqs_count; i++) {
  1739. for (j = 0; j < ep->nr_of_link_frequencies; j++)
  1740. if (freqs[i] == ep->link_frequencies[j])
  1741. break;
  1742. if (j == ep->nr_of_link_frequencies)
  1743. return freqs[i];
  1744. }
  1745. return 0;
  1746. }
  1747. static int hi846_parse_dt(struct hi846 *hi846, struct device *dev)
  1748. {
  1749. struct fwnode_handle *ep;
  1750. struct fwnode_handle *fwnode = dev_fwnode(dev);
  1751. struct v4l2_fwnode_endpoint bus_cfg = {
  1752. .bus_type = V4L2_MBUS_CSI2_DPHY
  1753. };
  1754. int ret;
  1755. s64 fq;
  1756. ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
  1757. if (!ep) {
  1758. dev_err(dev, "unable to find endpoint node\n");
  1759. return -ENXIO;
  1760. }
  1761. ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
  1762. fwnode_handle_put(ep);
  1763. if (ret) {
  1764. dev_err(dev, "failed to parse endpoint node: %d\n", ret);
  1765. return ret;
  1766. }
  1767. if (bus_cfg.bus.mipi_csi2.num_data_lanes != 2 &&
  1768. bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
  1769. dev_err(dev, "number of CSI2 data lanes %d is not supported",
  1770. bus_cfg.bus.mipi_csi2.num_data_lanes);
  1771. ret = -EINVAL;
  1772. goto check_hwcfg_error;
  1773. }
  1774. hi846->nr_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
  1775. if (!bus_cfg.nr_of_link_frequencies) {
  1776. dev_err(dev, "link-frequency property not found in DT\n");
  1777. ret = -EINVAL;
  1778. goto check_hwcfg_error;
  1779. }
  1780. /* Check that link frequences for all the modes are in device tree */
  1781. fq = hi846_check_link_freqs(hi846, &bus_cfg);
  1782. if (fq) {
  1783. dev_err(dev, "Link frequency of %lld is not supported\n", fq);
  1784. ret = -EINVAL;
  1785. goto check_hwcfg_error;
  1786. }
  1787. v4l2_fwnode_endpoint_free(&bus_cfg);
  1788. hi846->rst_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
  1789. if (IS_ERR(hi846->rst_gpio)) {
  1790. dev_err(dev, "failed to get reset gpio: %pe\n",
  1791. hi846->rst_gpio);
  1792. return PTR_ERR(hi846->rst_gpio);
  1793. }
  1794. hi846->shutdown_gpio = devm_gpiod_get_optional(dev, "shutdown",
  1795. GPIOD_OUT_LOW);
  1796. if (IS_ERR(hi846->shutdown_gpio)) {
  1797. dev_err(dev, "failed to get shutdown gpio: %pe\n",
  1798. hi846->shutdown_gpio);
  1799. return PTR_ERR(hi846->shutdown_gpio);
  1800. }
  1801. return 0;
  1802. check_hwcfg_error:
  1803. v4l2_fwnode_endpoint_free(&bus_cfg);
  1804. return ret;
  1805. }
  1806. static int hi846_probe(struct i2c_client *client)
  1807. {
  1808. struct hi846 *hi846;
  1809. int ret;
  1810. int i;
  1811. u32 mclk_freq;
  1812. hi846 = devm_kzalloc(&client->dev, sizeof(*hi846), GFP_KERNEL);
  1813. if (!hi846)
  1814. return -ENOMEM;
  1815. ret = hi846_parse_dt(hi846, &client->dev);
  1816. if (ret) {
  1817. dev_err(&client->dev, "failed to check HW configuration: %d",
  1818. ret);
  1819. return ret;
  1820. }
  1821. hi846->clock = devm_clk_get(&client->dev, NULL);
  1822. if (IS_ERR(hi846->clock)) {
  1823. dev_err(&client->dev, "failed to get clock: %pe\n",
  1824. hi846->clock);
  1825. return PTR_ERR(hi846->clock);
  1826. }
  1827. mclk_freq = clk_get_rate(hi846->clock);
  1828. if (mclk_freq != 25000000)
  1829. dev_warn(&client->dev,
  1830. "External clock freq should be 25000000, not %u.\n",
  1831. mclk_freq);
  1832. for (i = 0; i < HI846_NUM_SUPPLIES; i++)
  1833. hi846->supplies[i].supply = hi846_supply_names[i];
  1834. ret = devm_regulator_bulk_get(&client->dev, HI846_NUM_SUPPLIES,
  1835. hi846->supplies);
  1836. if (ret < 0)
  1837. return ret;
  1838. v4l2_i2c_subdev_init(&hi846->sd, client, &hi846_subdev_ops);
  1839. mutex_init(&hi846->mutex);
  1840. ret = hi846_power_on(hi846);
  1841. if (ret)
  1842. goto err_mutex;
  1843. ret = hi846_identify_module(hi846);
  1844. if (ret)
  1845. goto err_power_off;
  1846. hi846->cur_mode = &supported_modes[0];
  1847. ret = hi846_init_controls(hi846);
  1848. if (ret) {
  1849. dev_err(&client->dev, "failed to init controls: %d", ret);
  1850. goto err_power_off;
  1851. }
  1852. hi846->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1853. hi846->sd.entity.ops = &hi846_subdev_entity_ops;
  1854. hi846->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
  1855. hi846->pad.flags = MEDIA_PAD_FL_SOURCE;
  1856. ret = media_entity_pads_init(&hi846->sd.entity, 1, &hi846->pad);
  1857. if (ret) {
  1858. dev_err(&client->dev, "failed to init entity pads: %d", ret);
  1859. goto err_v4l2_ctrl_handler_free;
  1860. }
  1861. ret = v4l2_async_register_subdev_sensor(&hi846->sd);
  1862. if (ret < 0) {
  1863. dev_err(&client->dev, "failed to register V4L2 subdev: %d",
  1864. ret);
  1865. goto err_media_entity_cleanup;
  1866. }
  1867. pm_runtime_set_active(&client->dev);
  1868. pm_runtime_enable(&client->dev);
  1869. pm_runtime_idle(&client->dev);
  1870. return 0;
  1871. err_media_entity_cleanup:
  1872. media_entity_cleanup(&hi846->sd.entity);
  1873. err_v4l2_ctrl_handler_free:
  1874. v4l2_ctrl_handler_free(hi846->sd.ctrl_handler);
  1875. err_power_off:
  1876. hi846_power_off(hi846);
  1877. err_mutex:
  1878. mutex_destroy(&hi846->mutex);
  1879. return ret;
  1880. }
  1881. static void hi846_remove(struct i2c_client *client)
  1882. {
  1883. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1884. struct hi846 *hi846 = to_hi846(sd);
  1885. v4l2_async_unregister_subdev(sd);
  1886. media_entity_cleanup(&sd->entity);
  1887. v4l2_ctrl_handler_free(sd->ctrl_handler);
  1888. pm_runtime_disable(&client->dev);
  1889. if (!pm_runtime_status_suspended(&client->dev))
  1890. hi846_suspend(&client->dev);
  1891. pm_runtime_set_suspended(&client->dev);
  1892. mutex_destroy(&hi846->mutex);
  1893. }
  1894. static const struct dev_pm_ops hi846_pm_ops = {
  1895. SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
  1896. pm_runtime_force_resume)
  1897. SET_RUNTIME_PM_OPS(hi846_suspend, hi846_resume, NULL)
  1898. };
  1899. static const struct of_device_id hi846_of_match[] = {
  1900. { .compatible = "hynix,hi846", },
  1901. {},
  1902. };
  1903. MODULE_DEVICE_TABLE(of, hi846_of_match);
  1904. static struct i2c_driver hi846_i2c_driver = {
  1905. .driver = {
  1906. .name = "hi846",
  1907. .pm = &hi846_pm_ops,
  1908. .of_match_table = hi846_of_match,
  1909. },
  1910. .probe_new = hi846_probe,
  1911. .remove = hi846_remove,
  1912. };
  1913. module_i2c_driver(hi846_i2c_driver);
  1914. MODULE_AUTHOR("Angus Ainslie <[email protected]>");
  1915. MODULE_AUTHOR("Martin Kepplinger <[email protected]>");
  1916. MODULE_DESCRIPTION("Hynix HI846 sensor driver");
  1917. MODULE_LICENSE("GPL v2");