et8ek8_mode.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * et8ek8_mode.c
  4. *
  5. * Copyright (C) 2008 Nokia Corporation
  6. *
  7. * Contact: Sakari Ailus <[email protected]>
  8. * Tuukka Toivonen <[email protected]>
  9. */
  10. #include "et8ek8_reg.h"
  11. /*
  12. * Stingray sensor mode settings for Scooby
  13. */
  14. /* Mode1_poweron_Mode2_16VGA_2592x1968_12.07fps */
  15. static struct et8ek8_reglist mode1_poweron_mode2_16vga_2592x1968_12_07fps = {
  16. /* (without the +1)
  17. * SPCK = 80 MHz
  18. * CCP2 = 640 MHz
  19. * VCO = 640 MHz
  20. * VCOUNT = 84 (2016)
  21. * HCOUNT = 137 (3288)
  22. * CKREF_DIV = 2
  23. * CKVAR_DIV = 200
  24. * VCO_DIV = 0
  25. * SPCK_DIV = 7
  26. * MRCK_DIV = 7
  27. * LVDSCK_DIV = 0
  28. */
  29. .type = ET8EK8_REGLIST_POWERON,
  30. .mode = {
  31. .sensor_width = 2592,
  32. .sensor_height = 1968,
  33. .sensor_window_origin_x = 0,
  34. .sensor_window_origin_y = 0,
  35. .sensor_window_width = 2592,
  36. .sensor_window_height = 1968,
  37. .width = 3288,
  38. .height = 2016,
  39. .window_origin_x = 0,
  40. .window_origin_y = 0,
  41. .window_width = 2592,
  42. .window_height = 1968,
  43. .pixel_clock = 80000000,
  44. .ext_clock = 9600000,
  45. .timeperframe = {
  46. .numerator = 100,
  47. .denominator = 1207
  48. },
  49. .max_exp = 2012,
  50. /* .max_gain = 0, */
  51. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  52. .sensitivity = 65536
  53. },
  54. .regs = {
  55. /* Need to set firstly */
  56. { ET8EK8_REG_8BIT, 0x126C, 0xCC },
  57. /* Strobe and Data of CCP2 delay are minimized. */
  58. { ET8EK8_REG_8BIT, 0x1269, 0x00 },
  59. /* Refined value of Min H_COUNT */
  60. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  61. /* Frequency of SPCK setting (SPCK=MRCK) */
  62. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  63. { ET8EK8_REG_8BIT, 0x1241, 0x94 },
  64. { ET8EK8_REG_8BIT, 0x1242, 0x02 },
  65. { ET8EK8_REG_8BIT, 0x124B, 0x00 },
  66. { ET8EK8_REG_8BIT, 0x1255, 0xFF },
  67. { ET8EK8_REG_8BIT, 0x1256, 0x9F },
  68. { ET8EK8_REG_8BIT, 0x1258, 0x00 },
  69. /* From parallel out to serial out */
  70. { ET8EK8_REG_8BIT, 0x125D, 0x88 },
  71. /* From w/ embedded data to w/o embedded data */
  72. { ET8EK8_REG_8BIT, 0x125E, 0xC0 },
  73. /* CCP2 out is from STOP to ACTIVE */
  74. { ET8EK8_REG_8BIT, 0x1263, 0x98 },
  75. { ET8EK8_REG_8BIT, 0x1268, 0xC6 },
  76. { ET8EK8_REG_8BIT, 0x1434, 0x00 },
  77. { ET8EK8_REG_8BIT, 0x1163, 0x44 },
  78. { ET8EK8_REG_8BIT, 0x1166, 0x29 },
  79. { ET8EK8_REG_8BIT, 0x1140, 0x02 },
  80. { ET8EK8_REG_8BIT, 0x1011, 0x24 },
  81. { ET8EK8_REG_8BIT, 0x1151, 0x80 },
  82. { ET8EK8_REG_8BIT, 0x1152, 0x23 },
  83. /* Initial setting for improvement2 of lower frequency noise */
  84. { ET8EK8_REG_8BIT, 0x1014, 0x05 },
  85. { ET8EK8_REG_8BIT, 0x1033, 0x06 },
  86. { ET8EK8_REG_8BIT, 0x1034, 0x79 },
  87. { ET8EK8_REG_8BIT, 0x1423, 0x3F },
  88. { ET8EK8_REG_8BIT, 0x1424, 0x3F },
  89. { ET8EK8_REG_8BIT, 0x1426, 0x00 },
  90. /* Switch of Preset-White-balance (0d:disable / 1d:enable) */
  91. { ET8EK8_REG_8BIT, 0x1439, 0x00 },
  92. /* Switch of blemish correction (0d:disable / 1d:enable) */
  93. { ET8EK8_REG_8BIT, 0x161F, 0x60 },
  94. /* Switch of auto noise correction (0d:disable / 1d:enable) */
  95. { ET8EK8_REG_8BIT, 0x1634, 0x00 },
  96. { ET8EK8_REG_8BIT, 0x1646, 0x00 },
  97. { ET8EK8_REG_8BIT, 0x1648, 0x00 },
  98. { ET8EK8_REG_8BIT, 0x113E, 0x01 },
  99. { ET8EK8_REG_8BIT, 0x113F, 0x22 },
  100. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  101. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  102. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  103. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  104. { ET8EK8_REG_8BIT, 0x121B, 0x64 },
  105. { ET8EK8_REG_8BIT, 0x121D, 0x64 },
  106. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  107. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  108. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  109. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  110. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  111. { ET8EK8_REG_TERM, 0, 0}
  112. }
  113. };
  114. /* Mode1_16VGA_2592x1968_13.12fps_DPCM10-8 */
  115. static struct et8ek8_reglist mode1_16vga_2592x1968_13_12fps_dpcm10_8 = {
  116. /* (without the +1)
  117. * SPCK = 80 MHz
  118. * CCP2 = 560 MHz
  119. * VCO = 560 MHz
  120. * VCOUNT = 84 (2016)
  121. * HCOUNT = 128 (3072)
  122. * CKREF_DIV = 2
  123. * CKVAR_DIV = 175
  124. * VCO_DIV = 0
  125. * SPCK_DIV = 6
  126. * MRCK_DIV = 7
  127. * LVDSCK_DIV = 0
  128. */
  129. .type = ET8EK8_REGLIST_MODE,
  130. .mode = {
  131. .sensor_width = 2592,
  132. .sensor_height = 1968,
  133. .sensor_window_origin_x = 0,
  134. .sensor_window_origin_y = 0,
  135. .sensor_window_width = 2592,
  136. .sensor_window_height = 1968,
  137. .width = 3072,
  138. .height = 2016,
  139. .window_origin_x = 0,
  140. .window_origin_y = 0,
  141. .window_width = 2592,
  142. .window_height = 1968,
  143. .pixel_clock = 80000000,
  144. .ext_clock = 9600000,
  145. .timeperframe = {
  146. .numerator = 100,
  147. .denominator = 1292
  148. },
  149. .max_exp = 2012,
  150. /* .max_gain = 0, */
  151. .bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  152. .sensitivity = 65536
  153. },
  154. .regs = {
  155. { ET8EK8_REG_8BIT, 0x1239, 0x57 },
  156. { ET8EK8_REG_8BIT, 0x1238, 0x82 },
  157. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  158. { ET8EK8_REG_8BIT, 0x123A, 0x06 },
  159. { ET8EK8_REG_8BIT, 0x121B, 0x64 },
  160. { ET8EK8_REG_8BIT, 0x121D, 0x64 },
  161. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  162. { ET8EK8_REG_8BIT, 0x1220, 0x80 }, /* <-changed to v14 7E->80 */
  163. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  164. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  165. { ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/ */
  166. { ET8EK8_REG_TERM, 0, 0}
  167. }
  168. };
  169. /* Mode3_4VGA_1296x984_29.99fps_DPCM10-8 */
  170. static struct et8ek8_reglist mode3_4vga_1296x984_29_99fps_dpcm10_8 = {
  171. /* (without the +1)
  172. * SPCK = 96.5333333333333 MHz
  173. * CCP2 = 579.2 MHz
  174. * VCO = 579.2 MHz
  175. * VCOUNT = 84 (2016)
  176. * HCOUNT = 133 (3192)
  177. * CKREF_DIV = 2
  178. * CKVAR_DIV = 181
  179. * VCO_DIV = 0
  180. * SPCK_DIV = 5
  181. * MRCK_DIV = 7
  182. * LVDSCK_DIV = 0
  183. */
  184. .type = ET8EK8_REGLIST_MODE,
  185. .mode = {
  186. .sensor_width = 2592,
  187. .sensor_height = 1968,
  188. .sensor_window_origin_x = 0,
  189. .sensor_window_origin_y = 0,
  190. .sensor_window_width = 2592,
  191. .sensor_window_height = 1968,
  192. .width = 3192,
  193. .height = 1008,
  194. .window_origin_x = 0,
  195. .window_origin_y = 0,
  196. .window_width = 1296,
  197. .window_height = 984,
  198. .pixel_clock = 96533333,
  199. .ext_clock = 9600000,
  200. .timeperframe = {
  201. .numerator = 100,
  202. .denominator = 3000
  203. },
  204. .max_exp = 1004,
  205. /* .max_gain = 0, */
  206. .bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  207. .sensitivity = 65536
  208. },
  209. .regs = {
  210. { ET8EK8_REG_8BIT, 0x1239, 0x5A },
  211. { ET8EK8_REG_8BIT, 0x1238, 0x82 },
  212. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  213. { ET8EK8_REG_8BIT, 0x123A, 0x05 },
  214. { ET8EK8_REG_8BIT, 0x121B, 0x63 },
  215. { ET8EK8_REG_8BIT, 0x1220, 0x85 },
  216. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  217. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  218. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  219. { ET8EK8_REG_8BIT, 0x121D, 0x63 },
  220. { ET8EK8_REG_8BIT, 0x125D, 0x83 }, /* CCP_LVDS_MODE/ */
  221. { ET8EK8_REG_TERM, 0, 0}
  222. }
  223. };
  224. /* Mode4_SVGA_864x656_29.88fps */
  225. static struct et8ek8_reglist mode4_svga_864x656_29_88fps = {
  226. /* (without the +1)
  227. * SPCK = 80 MHz
  228. * CCP2 = 320 MHz
  229. * VCO = 640 MHz
  230. * VCOUNT = 84 (2016)
  231. * HCOUNT = 166 (3984)
  232. * CKREF_DIV = 2
  233. * CKVAR_DIV = 200
  234. * VCO_DIV = 0
  235. * SPCK_DIV = 7
  236. * MRCK_DIV = 7
  237. * LVDSCK_DIV = 1
  238. */
  239. .type = ET8EK8_REGLIST_MODE,
  240. .mode = {
  241. .sensor_width = 2592,
  242. .sensor_height = 1968,
  243. .sensor_window_origin_x = 0,
  244. .sensor_window_origin_y = 0,
  245. .sensor_window_width = 2592,
  246. .sensor_window_height = 1968,
  247. .width = 3984,
  248. .height = 672,
  249. .window_origin_x = 0,
  250. .window_origin_y = 0,
  251. .window_width = 864,
  252. .window_height = 656,
  253. .pixel_clock = 80000000,
  254. .ext_clock = 9600000,
  255. .timeperframe = {
  256. .numerator = 100,
  257. .denominator = 2988
  258. },
  259. .max_exp = 668,
  260. /* .max_gain = 0, */
  261. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  262. .sensitivity = 65536
  263. },
  264. .regs = {
  265. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  266. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  267. { ET8EK8_REG_8BIT, 0x123B, 0x71 },
  268. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  269. { ET8EK8_REG_8BIT, 0x121B, 0x62 },
  270. { ET8EK8_REG_8BIT, 0x121D, 0x62 },
  271. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  272. { ET8EK8_REG_8BIT, 0x1220, 0xA6 },
  273. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  274. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  275. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  276. { ET8EK8_REG_TERM, 0, 0}
  277. }
  278. };
  279. /* Mode5_VGA_648x492_29.93fps */
  280. static struct et8ek8_reglist mode5_vga_648x492_29_93fps = {
  281. /* (without the +1)
  282. * SPCK = 80 MHz
  283. * CCP2 = 320 MHz
  284. * VCO = 640 MHz
  285. * VCOUNT = 84 (2016)
  286. * HCOUNT = 221 (5304)
  287. * CKREF_DIV = 2
  288. * CKVAR_DIV = 200
  289. * VCO_DIV = 0
  290. * SPCK_DIV = 7
  291. * MRCK_DIV = 7
  292. * LVDSCK_DIV = 1
  293. */
  294. .type = ET8EK8_REGLIST_MODE,
  295. .mode = {
  296. .sensor_width = 2592,
  297. .sensor_height = 1968,
  298. .sensor_window_origin_x = 0,
  299. .sensor_window_origin_y = 0,
  300. .sensor_window_width = 2592,
  301. .sensor_window_height = 1968,
  302. .width = 5304,
  303. .height = 504,
  304. .window_origin_x = 0,
  305. .window_origin_y = 0,
  306. .window_width = 648,
  307. .window_height = 492,
  308. .pixel_clock = 80000000,
  309. .ext_clock = 9600000,
  310. .timeperframe = {
  311. .numerator = 100,
  312. .denominator = 2993
  313. },
  314. .max_exp = 500,
  315. /* .max_gain = 0, */
  316. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  317. .sensitivity = 65536
  318. },
  319. .regs = {
  320. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  321. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  322. { ET8EK8_REG_8BIT, 0x123B, 0x71 },
  323. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  324. { ET8EK8_REG_8BIT, 0x121B, 0x61 },
  325. { ET8EK8_REG_8BIT, 0x121D, 0x61 },
  326. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  327. { ET8EK8_REG_8BIT, 0x1220, 0xDD },
  328. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  329. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  330. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  331. { ET8EK8_REG_TERM, 0, 0}
  332. }
  333. };
  334. /* Mode2_16VGA_2592x1968_3.99fps */
  335. static struct et8ek8_reglist mode2_16vga_2592x1968_3_99fps = {
  336. /* (without the +1)
  337. * SPCK = 80 MHz
  338. * CCP2 = 640 MHz
  339. * VCO = 640 MHz
  340. * VCOUNT = 254 (6096)
  341. * HCOUNT = 137 (3288)
  342. * CKREF_DIV = 2
  343. * CKVAR_DIV = 200
  344. * VCO_DIV = 0
  345. * SPCK_DIV = 7
  346. * MRCK_DIV = 7
  347. * LVDSCK_DIV = 0
  348. */
  349. .type = ET8EK8_REGLIST_MODE,
  350. .mode = {
  351. .sensor_width = 2592,
  352. .sensor_height = 1968,
  353. .sensor_window_origin_x = 0,
  354. .sensor_window_origin_y = 0,
  355. .sensor_window_width = 2592,
  356. .sensor_window_height = 1968,
  357. .width = 3288,
  358. .height = 6096,
  359. .window_origin_x = 0,
  360. .window_origin_y = 0,
  361. .window_width = 2592,
  362. .window_height = 1968,
  363. .pixel_clock = 80000000,
  364. .ext_clock = 9600000,
  365. .timeperframe = {
  366. .numerator = 100,
  367. .denominator = 399
  368. },
  369. .max_exp = 6092,
  370. /* .max_gain = 0, */
  371. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  372. .sensitivity = 65536
  373. },
  374. .regs = {
  375. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  376. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  377. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  378. { ET8EK8_REG_8BIT, 0x123A, 0x07 },
  379. { ET8EK8_REG_8BIT, 0x121B, 0x64 },
  380. { ET8EK8_REG_8BIT, 0x121D, 0x64 },
  381. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  382. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  383. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  384. { ET8EK8_REG_8BIT, 0x1222, 0xFE },
  385. { ET8EK8_REG_TERM, 0, 0}
  386. }
  387. };
  388. /* Mode_648x492_5fps */
  389. static struct et8ek8_reglist mode_648x492_5fps = {
  390. /* (without the +1)
  391. * SPCK = 13.3333333333333 MHz
  392. * CCP2 = 53.3333333333333 MHz
  393. * VCO = 640 MHz
  394. * VCOUNT = 84 (2016)
  395. * HCOUNT = 221 (5304)
  396. * CKREF_DIV = 2
  397. * CKVAR_DIV = 200
  398. * VCO_DIV = 5
  399. * SPCK_DIV = 7
  400. * MRCK_DIV = 7
  401. * LVDSCK_DIV = 1
  402. */
  403. .type = ET8EK8_REGLIST_MODE,
  404. .mode = {
  405. .sensor_width = 2592,
  406. .sensor_height = 1968,
  407. .sensor_window_origin_x = 0,
  408. .sensor_window_origin_y = 0,
  409. .sensor_window_width = 2592,
  410. .sensor_window_height = 1968,
  411. .width = 5304,
  412. .height = 504,
  413. .window_origin_x = 0,
  414. .window_origin_y = 0,
  415. .window_width = 648,
  416. .window_height = 492,
  417. .pixel_clock = 13333333,
  418. .ext_clock = 9600000,
  419. .timeperframe = {
  420. .numerator = 100,
  421. .denominator = 499
  422. },
  423. .max_exp = 500,
  424. /* .max_gain = 0, */
  425. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  426. .sensitivity = 65536
  427. },
  428. .regs = {
  429. { ET8EK8_REG_8BIT, 0x1239, 0x64 },
  430. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  431. { ET8EK8_REG_8BIT, 0x123B, 0x71 },
  432. { ET8EK8_REG_8BIT, 0x123A, 0x57 },
  433. { ET8EK8_REG_8BIT, 0x121B, 0x61 },
  434. { ET8EK8_REG_8BIT, 0x121D, 0x61 },
  435. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  436. { ET8EK8_REG_8BIT, 0x1220, 0xDD },
  437. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  438. { ET8EK8_REG_8BIT, 0x1222, 0x54 },
  439. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  440. { ET8EK8_REG_TERM, 0, 0}
  441. }
  442. };
  443. /* Mode3_4VGA_1296x984_5fps */
  444. static struct et8ek8_reglist mode3_4vga_1296x984_5fps = {
  445. /* (without the +1)
  446. * SPCK = 49.4 MHz
  447. * CCP2 = 395.2 MHz
  448. * VCO = 790.4 MHz
  449. * VCOUNT = 250 (6000)
  450. * HCOUNT = 137 (3288)
  451. * CKREF_DIV = 2
  452. * CKVAR_DIV = 247
  453. * VCO_DIV = 1
  454. * SPCK_DIV = 7
  455. * MRCK_DIV = 7
  456. * LVDSCK_DIV = 0
  457. */
  458. .type = ET8EK8_REGLIST_MODE,
  459. .mode = {
  460. .sensor_width = 2592,
  461. .sensor_height = 1968,
  462. .sensor_window_origin_x = 0,
  463. .sensor_window_origin_y = 0,
  464. .sensor_window_width = 2592,
  465. .sensor_window_height = 1968,
  466. .width = 3288,
  467. .height = 3000,
  468. .window_origin_x = 0,
  469. .window_origin_y = 0,
  470. .window_width = 1296,
  471. .window_height = 984,
  472. .pixel_clock = 49400000,
  473. .ext_clock = 9600000,
  474. .timeperframe = {
  475. .numerator = 100,
  476. .denominator = 501
  477. },
  478. .max_exp = 2996,
  479. /* .max_gain = 0, */
  480. .bus_format = MEDIA_BUS_FMT_SGRBG10_1X10,
  481. .sensitivity = 65536
  482. },
  483. .regs = {
  484. { ET8EK8_REG_8BIT, 0x1239, 0x7B },
  485. { ET8EK8_REG_8BIT, 0x1238, 0x82 },
  486. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  487. { ET8EK8_REG_8BIT, 0x123A, 0x17 },
  488. { ET8EK8_REG_8BIT, 0x121B, 0x63 },
  489. { ET8EK8_REG_8BIT, 0x121D, 0x63 },
  490. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  491. { ET8EK8_REG_8BIT, 0x1220, 0x89 },
  492. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  493. { ET8EK8_REG_8BIT, 0x1222, 0xFA },
  494. { ET8EK8_REG_8BIT, 0x125D, 0x88 }, /* CCP_LVDS_MODE/ */
  495. { ET8EK8_REG_TERM, 0, 0}
  496. }
  497. };
  498. /* Mode_4VGA_1296x984_25fps_DPCM10-8 */
  499. static struct et8ek8_reglist mode_4vga_1296x984_25fps_dpcm10_8 = {
  500. /* (without the +1)
  501. * SPCK = 84.2666666666667 MHz
  502. * CCP2 = 505.6 MHz
  503. * VCO = 505.6 MHz
  504. * VCOUNT = 88 (2112)
  505. * HCOUNT = 133 (3192)
  506. * CKREF_DIV = 2
  507. * CKVAR_DIV = 158
  508. * VCO_DIV = 0
  509. * SPCK_DIV = 5
  510. * MRCK_DIV = 7
  511. * LVDSCK_DIV = 0
  512. */
  513. .type = ET8EK8_REGLIST_MODE,
  514. .mode = {
  515. .sensor_width = 2592,
  516. .sensor_height = 1968,
  517. .sensor_window_origin_x = 0,
  518. .sensor_window_origin_y = 0,
  519. .sensor_window_width = 2592,
  520. .sensor_window_height = 1968,
  521. .width = 3192,
  522. .height = 1056,
  523. .window_origin_x = 0,
  524. .window_origin_y = 0,
  525. .window_width = 1296,
  526. .window_height = 984,
  527. .pixel_clock = 84266667,
  528. .ext_clock = 9600000,
  529. .timeperframe = {
  530. .numerator = 100,
  531. .denominator = 2500
  532. },
  533. .max_exp = 1052,
  534. /* .max_gain = 0, */
  535. .bus_format = MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  536. .sensitivity = 65536
  537. },
  538. .regs = {
  539. { ET8EK8_REG_8BIT, 0x1239, 0x4F },
  540. { ET8EK8_REG_8BIT, 0x1238, 0x02 },
  541. { ET8EK8_REG_8BIT, 0x123B, 0x70 },
  542. { ET8EK8_REG_8BIT, 0x123A, 0x05 },
  543. { ET8EK8_REG_8BIT, 0x121B, 0x63 },
  544. { ET8EK8_REG_8BIT, 0x1220, 0x85 },
  545. { ET8EK8_REG_8BIT, 0x1221, 0x00 },
  546. { ET8EK8_REG_8BIT, 0x1222, 0x58 },
  547. { ET8EK8_REG_8BIT, 0x1223, 0x00 },
  548. { ET8EK8_REG_8BIT, 0x121D, 0x63 },
  549. { ET8EK8_REG_8BIT, 0x125D, 0x83 },
  550. { ET8EK8_REG_TERM, 0, 0}
  551. }
  552. };
  553. struct et8ek8_meta_reglist meta_reglist = {
  554. .version = "V14 03-June-2008",
  555. .reglist = {
  556. { .ptr = &mode1_poweron_mode2_16vga_2592x1968_12_07fps },
  557. { .ptr = &mode1_16vga_2592x1968_13_12fps_dpcm10_8 },
  558. { .ptr = &mode3_4vga_1296x984_29_99fps_dpcm10_8 },
  559. { .ptr = &mode4_svga_864x656_29_88fps },
  560. { .ptr = &mode5_vga_648x492_29_93fps },
  561. { .ptr = &mode2_16vga_2592x1968_3_99fps },
  562. { .ptr = &mode_648x492_5fps },
  563. { .ptr = &mode3_4vga_1296x984_5fps },
  564. { .ptr = &mode_4vga_1296x984_25fps_dpcm10_8 },
  565. { .ptr = NULL }
  566. }
  567. };