ccs-quirk.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * drivers/media/i2c/ccs/ccs-quirk.c
  4. *
  5. * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
  6. *
  7. * Copyright (C) 2020 Intel Corporation
  8. * Copyright (C) 2011--2012 Nokia Corporation
  9. * Contact: Sakari Ailus <[email protected]>
  10. */
  11. #include <linux/delay.h>
  12. #include "ccs.h"
  13. #include "ccs-limits.h"
  14. static int ccs_write_addr_8s(struct ccs_sensor *sensor,
  15. const struct ccs_reg_8 *regs, int len)
  16. {
  17. struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
  18. int rval;
  19. for (; len > 0; len--, regs++) {
  20. rval = ccs_write_addr(sensor, regs->reg, regs->val);
  21. if (rval < 0) {
  22. dev_err(&client->dev,
  23. "error %d writing reg 0x%4.4x, val 0x%2.2x",
  24. rval, regs->reg, regs->val);
  25. return rval;
  26. }
  27. }
  28. return 0;
  29. }
  30. static int jt8ew9_limits(struct ccs_sensor *sensor)
  31. {
  32. if (sensor->minfo.revision_number < 0x0300)
  33. sensor->frame_skip = 1;
  34. /* Below 24 gain doesn't have effect at all, */
  35. /* but ~59 is needed for full dynamic range */
  36. ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
  37. ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
  38. return 0;
  39. }
  40. static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
  41. {
  42. static const struct ccs_reg_8 regs[] = {
  43. { 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
  44. { 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
  45. { 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
  46. { 0x322d, 0x04 }, /* Adjusting Processing Image Size to Scaler Toshiba Recommendation Setting */
  47. { 0x3255, 0x0f }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
  48. { 0x3256, 0x15 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
  49. { 0x3258, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
  50. { 0x3259, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
  51. { 0x325f, 0x7c }, /* Analog Gain Control Toshiba Recommendation Setting */
  52. { 0x3302, 0x06 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
  53. { 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
  54. { 0x3307, 0x22 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
  55. { 0x3308, 0x8d }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
  56. { 0x331e, 0x0f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
  57. { 0x3320, 0x30 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
  58. { 0x3321, 0x11 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
  59. { 0x3322, 0x98 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
  60. { 0x3323, 0x64 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
  61. { 0x3325, 0x83 }, /* Read Out Timing Control Toshiba Recommendation Setting */
  62. { 0x3330, 0x18 }, /* Read Out Timing Control Toshiba Recommendation Setting */
  63. { 0x333c, 0x01 }, /* Read Out Timing Control Toshiba Recommendation Setting */
  64. { 0x3345, 0x2f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
  65. { 0x33de, 0x38 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
  66. /* Taken from v03. No idea what the rest are. */
  67. { 0x32e0, 0x05 },
  68. { 0x32e1, 0x05 },
  69. { 0x32e2, 0x04 },
  70. { 0x32e5, 0x04 },
  71. { 0x32e6, 0x04 },
  72. };
  73. return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
  74. }
  75. const struct ccs_quirk smiapp_jt8ew9_quirk = {
  76. .limits = jt8ew9_limits,
  77. .post_poweron = jt8ew9_post_poweron,
  78. };
  79. static int imx125es_post_poweron(struct ccs_sensor *sensor)
  80. {
  81. /* Taken from v02. No idea what the other two are. */
  82. static const struct ccs_reg_8 regs[] = {
  83. /*
  84. * 0x3302: clk during frame blanking:
  85. * 0x00 - HS mode, 0x01 - LP11
  86. */
  87. { 0x3302, 0x01 },
  88. { 0x302d, 0x00 },
  89. { 0x3b08, 0x8c },
  90. };
  91. return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
  92. }
  93. const struct ccs_quirk smiapp_imx125es_quirk = {
  94. .post_poweron = imx125es_post_poweron,
  95. };
  96. static int jt8ev1_limits(struct ccs_sensor *sensor)
  97. {
  98. ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
  99. ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
  100. return 0;
  101. }
  102. static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
  103. {
  104. struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
  105. int rval;
  106. static const struct ccs_reg_8 regs[] = {
  107. { 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
  108. { 0x30a3, 0xd0 }, /* FLASH STROBE enable */
  109. { 0x3237, 0x00 }, /* For control of pulse timing for ADC */
  110. { 0x3238, 0x43 },
  111. { 0x3301, 0x06 }, /* For analog bias for sensor */
  112. { 0x3302, 0x06 },
  113. { 0x3304, 0x00 },
  114. { 0x3305, 0x88 },
  115. { 0x332a, 0x14 },
  116. { 0x332c, 0x6b },
  117. { 0x3336, 0x01 },
  118. { 0x333f, 0x1f },
  119. { 0x3355, 0x00 },
  120. { 0x3356, 0x20 },
  121. { 0x33bf, 0x20 }, /* Adjust the FBC speed */
  122. { 0x33c9, 0x20 },
  123. { 0x33ce, 0x30 }, /* Adjust the parameter for logic function */
  124. { 0x33cf, 0xec }, /* For Black sun */
  125. { 0x3328, 0x80 }, /* Ugh. No idea what's this. */
  126. };
  127. static const struct ccs_reg_8 regs_96[] = {
  128. { 0x30ae, 0x00 }, /* For control of ADC clock */
  129. { 0x30af, 0xd0 },
  130. { 0x30b0, 0x01 },
  131. };
  132. rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
  133. if (rval < 0)
  134. return rval;
  135. switch (sensor->hwcfg.ext_clk) {
  136. case 9600000:
  137. return ccs_write_addr_8s(sensor, regs_96,
  138. ARRAY_SIZE(regs_96));
  139. default:
  140. dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
  141. sensor->hwcfg.ext_clk);
  142. return 0;
  143. }
  144. }
  145. static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
  146. {
  147. return ccs_write_addr(sensor, 0x3328, 0x00);
  148. }
  149. static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
  150. {
  151. int rval;
  152. /* Workaround: allows fast standby to work properly */
  153. rval = ccs_write_addr(sensor, 0x3205, 0x04);
  154. if (rval < 0)
  155. return rval;
  156. /* Wait for 1 ms + one line => 2 ms is likely enough */
  157. usleep_range(2000, 2050);
  158. /* Restore it */
  159. rval = ccs_write_addr(sensor, 0x3205, 0x00);
  160. if (rval < 0)
  161. return rval;
  162. return ccs_write_addr(sensor, 0x3328, 0x80);
  163. }
  164. static int jt8ev1_init(struct ccs_sensor *sensor)
  165. {
  166. sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
  167. CCS_PLL_FLAG_LINK_DECOUPLED;
  168. sensor->pll.vt_lanes = 1;
  169. sensor->pll.op_lanes = sensor->pll.csi2.lanes;
  170. return 0;
  171. }
  172. const struct ccs_quirk smiapp_jt8ev1_quirk = {
  173. .limits = jt8ev1_limits,
  174. .post_poweron = jt8ev1_post_poweron,
  175. .pre_streamon = jt8ev1_pre_streamon,
  176. .post_streamoff = jt8ev1_post_streamoff,
  177. .init = jt8ev1_init,
  178. };
  179. static int tcm8500md_limits(struct ccs_sensor *sensor)
  180. {
  181. ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
  182. return 0;
  183. }
  184. const struct ccs_quirk smiapp_tcm8500md_quirk = {
  185. .limits = tcm8500md_limits,
  186. };