android_kernel_samsung_sm8650_ksu/drivers/media/dvb-frontends/drx39xyj/drxj_map.h

/*
  Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
  All rights reserved.

  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions are met:

  * Redistributions of source code must retain the above copyright notice,
    this list of conditions and the following disclaimer.
  * Redistributions in binary form must reproduce the above copyright notice,
    this list of conditions and the following disclaimer in the documentation
	and/or other materials provided with the distribution.
  * Neither the name of Trident Microsystems nor Hauppauge Computer Works
    nor the names of its contributors may be used to endorse or promote
	products derived from this software without specific prior written
	permission.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  POSSIBILITY OF SUCH DAMAGE.
*/

/*
 ***********************************************************************************************************************
 * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
 *
 * Filename:        drxj_map.h
 * Generated on:    Mon Jan 18 12:09:24 2010
 * Generated by:    IDF:x 1.3.0
 * Generated from:  reg_map
 * Output start:    [entry point]
 *
 * filename         last modified               re-use
 * -----------------------------------------------------
 * reg_map.1.tmp    Mon Jan 18 12:09:24 2010    -
 *
 */

#ifndef __DRXJ_MAP__H__
#define __DRXJ_MAP__H__ INCLUDED

#ifdef _REGISTERTABLE_
#include <registertable.h>
	extern register_table_t drxj_map[];
	extern register_table_info_t drxj_map_info[];
#endif

#define ATV_COMM_EXEC__A                                                    0xC00000
#define ATV_COMM_EXEC__W                                                    2
#define ATV_COMM_EXEC__M                                                    0x3
#define ATV_COMM_EXEC__PRE                                                  0x0
#define   ATV_COMM_EXEC_STOP                                                0x0
#define   ATV_COMM_EXEC_ACTIVE                                              0x1
#define   ATV_COMM_EXEC_HOLD                                                0x2

#define ATV_COMM_STATE__A                                                   0xC00001
#define ATV_COMM_STATE__W                                                   16
#define ATV_COMM_STATE__M                                                   0xFFFF
#define ATV_COMM_STATE__PRE                                                 0x0
#define ATV_COMM_MB__A                                                      0xC00002
#define ATV_COMM_MB__W                                                      16
#define ATV_COMM_MB__M                                                      0xFFFF
#define ATV_COMM_MB__PRE                                                    0x0
#define ATV_COMM_INT_REQ__A                                                 0xC00003
#define ATV_COMM_INT_REQ__W                                                 16
#define ATV_COMM_INT_REQ__M                                                 0xFFFF
#define ATV_COMM_INT_REQ__PRE                                               0x0
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__B                                  0
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__W                                  1
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__M                                  0x1
#define   ATV_COMM_INT_REQ_COMM_INT_REQ__PRE                                0x0

#define ATV_COMM_INT_STA__A                                                 0xC00005
#define ATV_COMM_INT_STA__W                                                 16
#define ATV_COMM_INT_STA__M                                                 0xFFFF
#define ATV_COMM_INT_STA__PRE                                               0x0
#define ATV_COMM_INT_MSK__A                                                 0xC00006
#define ATV_COMM_INT_MSK__W                                                 16
#define ATV_COMM_INT_MSK__M                                                 0xFFFF
#define ATV_COMM_INT_MSK__PRE                                               0x0
#define ATV_COMM_INT_STM__A                                                 0xC00007
#define ATV_COMM_INT_STM__W                                                 16
#define ATV_COMM_INT_STM__M                                                 0xFFFF
#define ATV_COMM_INT_STM__PRE                                               0x0

#define ATV_COMM_KEY__A                                                     0xC0000F
#define ATV_COMM_KEY__W                                                     16
#define ATV_COMM_KEY__M                                                     0xFFFF
#define ATV_COMM_KEY__PRE                                                   0x0
#define   ATV_COMM_KEY_KEY                                                  0xFABA
#define   ATV_COMM_KEY_MIN                                                  0x0
#define   ATV_COMM_KEY_MAX                                                  0xFFFF

#define ATV_TOP_COMM_EXEC__A                                                0xC10000
#define ATV_TOP_COMM_EXEC__W                                                2
#define ATV_TOP_COMM_EXEC__M                                                0x3
#define ATV_TOP_COMM_EXEC__PRE                                              0x0
#define   ATV_TOP_COMM_EXEC_STOP                                            0x0
#define   ATV_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   ATV_TOP_COMM_EXEC_HOLD                                            0x2

#define ATV_TOP_COMM_STATE__A                                               0xC10001
#define ATV_TOP_COMM_STATE__W                                               16
#define ATV_TOP_COMM_STATE__M                                               0xFFFF
#define ATV_TOP_COMM_STATE__PRE                                             0x0
#define   ATV_TOP_COMM_STATE_STATE__B                                       0
#define   ATV_TOP_COMM_STATE_STATE__W                                       16
#define   ATV_TOP_COMM_STATE_STATE__M                                       0xFFFF
#define   ATV_TOP_COMM_STATE_STATE__PRE                                     0x0

#define ATV_TOP_COMM_MB__A                                                  0xC10002
#define ATV_TOP_COMM_MB__W                                                  16
#define ATV_TOP_COMM_MB__M                                                  0xFFFF
#define ATV_TOP_COMM_MB__PRE                                                0x0
#define   ATV_TOP_COMM_MB_CTL__B                                            0
#define   ATV_TOP_COMM_MB_CTL__W                                            1
#define   ATV_TOP_COMM_MB_CTL__M                                            0x1
#define   ATV_TOP_COMM_MB_CTL__PRE                                          0x0
#define   ATV_TOP_COMM_MB_OBS__B                                            1
#define   ATV_TOP_COMM_MB_OBS__W                                            1
#define   ATV_TOP_COMM_MB_OBS__M                                            0x2
#define   ATV_TOP_COMM_MB_OBS__PRE                                          0x0

#define   ATV_TOP_COMM_MB_MUX_CTRL__B                                       2
#define   ATV_TOP_COMM_MB_MUX_CTRL__W                                       4
#define   ATV_TOP_COMM_MB_MUX_CTRL__M                                       0x3C
#define   ATV_TOP_COMM_MB_MUX_CTRL__PRE                                     0x0
#define     ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S                                 0x0
#define     ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN                               0x4
#define     ATV_TOP_COMM_MB_MUX_CTRL_CORR_O                                 0x8
#define     ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O                               0xC
#define     ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ                              0x10
#define     ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O                                0x14
#define     ATV_TOP_COMM_MB_MUX_CTRL_SIF_O                                  0x18
#define     ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O                              0x1C
#define     ATV_TOP_COMM_MB_MUX_CTRL_POST_S                                 0x20

#define   ATV_TOP_COMM_MB_MUX_OBS__B                                        6
#define   ATV_TOP_COMM_MB_MUX_OBS__W                                        4
#define   ATV_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
#define   ATV_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
#define     ATV_TOP_COMM_MB_MUX_OBS_PEAK_S                                  0x0
#define     ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN                                0x40
#define     ATV_TOP_COMM_MB_MUX_OBS_CORR_O                                  0x80
#define     ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O                                0xC0
#define     ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ                               0x100
#define     ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O                                 0x140
#define     ATV_TOP_COMM_MB_MUX_OBS_SIF_O                                   0x180
#define     ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O                               0x1C0
#define     ATV_TOP_COMM_MB_MUX_OBS_POST_S                                  0x200

#define ATV_TOP_COMM_INT_REQ__A                                             0xC10003
#define ATV_TOP_COMM_INT_REQ__W                                             16
#define ATV_TOP_COMM_INT_REQ__M                                             0xFFFF
#define ATV_TOP_COMM_INT_REQ__PRE                                           0x0
#define ATV_TOP_COMM_INT_STA__A                                             0xC10005
#define ATV_TOP_COMM_INT_STA__W                                             16
#define ATV_TOP_COMM_INT_STA__M                                             0xFFFF
#define ATV_TOP_COMM_INT_STA__PRE                                           0x0

#define   ATV_TOP_COMM_INT_STA_FAGC_STA__B                                  0
#define   ATV_TOP_COMM_INT_STA_FAGC_STA__W                                  1
#define   ATV_TOP_COMM_INT_STA_FAGC_STA__M                                  0x1
#define   ATV_TOP_COMM_INT_STA_FAGC_STA__PRE                                0x0

#define   ATV_TOP_COMM_INT_STA_OVM_STA__B                                   1
#define   ATV_TOP_COMM_INT_STA_OVM_STA__W                                   1
#define   ATV_TOP_COMM_INT_STA_OVM_STA__M                                   0x2
#define   ATV_TOP_COMM_INT_STA_OVM_STA__PRE                                 0x0

#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__B                                 2
#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__W                                 1
#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__M                                 0x4
#define   ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE                               0x0

#define ATV_TOP_COMM_INT_MSK__A                                             0xC10006
#define ATV_TOP_COMM_INT_MSK__W                                             16
#define ATV_TOP_COMM_INT_MSK__M                                             0xFFFF
#define ATV_TOP_COMM_INT_MSK__PRE                                           0x0

#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__B                                  0
#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__W                                  1
#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__M                                  0x1
#define   ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE                                0x0

#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__B                                   1
#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__W                                   1
#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__M                                   0x2
#define   ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE                                 0x0

#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B                                 2
#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W                                 1
#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M                                 0x4
#define   ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE                               0x0

#define ATV_TOP_COMM_INT_STM__A                                             0xC10007
#define ATV_TOP_COMM_INT_STM__W                                             16
#define ATV_TOP_COMM_INT_STM__M                                             0xFFFF
#define ATV_TOP_COMM_INT_STM__PRE                                           0x0

#define   ATV_TOP_COMM_INT_STM_FAGC_STM__B                                  0
#define   ATV_TOP_COMM_INT_STM_FAGC_STM__W                                  1
#define   ATV_TOP_COMM_INT_STM_FAGC_STM__M                                  0x1
#define   ATV_TOP_COMM_INT_STM_FAGC_STM__PRE                                0x0

#define   ATV_TOP_COMM_INT_STM_OVM_STM__B                                   1
#define   ATV_TOP_COMM_INT_STM_OVM_STM__W                                   1
#define   ATV_TOP_COMM_INT_STM_OVM_STM__M                                   0x2
#define   ATV_TOP_COMM_INT_STM_OVM_STM__PRE                                 0x0

#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__B                                 2
#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__W                                 1
#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__M                                 0x4
#define   ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE                               0x0

#define ATV_TOP_COMM_KEY__A                                                 0xC1000F
#define ATV_TOP_COMM_KEY__W                                                 16
#define ATV_TOP_COMM_KEY__M                                                 0xFFFF
#define ATV_TOP_COMM_KEY__PRE                                               0x0

#define   ATV_TOP_COMM_KEY_KEY__B                                           0
#define   ATV_TOP_COMM_KEY_KEY__W                                           16
#define   ATV_TOP_COMM_KEY_KEY__M                                           0xFFFF
#define   ATV_TOP_COMM_KEY_KEY__PRE                                         0x0
#define     ATV_TOP_COMM_KEY_KEY_KEY                                        0xFABA
#define     ATV_TOP_COMM_KEY_KEY_MIN                                        0x0
#define     ATV_TOP_COMM_KEY_KEY_MAX                                        0xFFFF

#define ATV_TOP_CR_AMP_TH__A                                                0xC10010
#define ATV_TOP_CR_AMP_TH__W                                                8
#define ATV_TOP_CR_AMP_TH__M                                                0xFF
#define ATV_TOP_CR_AMP_TH__PRE                                              0x8
#define   ATV_TOP_CR_AMP_TH_MN                                              0x8

#define ATV_TOP_CR_CONT__A                                                  0xC10011
#define ATV_TOP_CR_CONT__W                                                  9
#define ATV_TOP_CR_CONT__M                                                  0x1FF
#define ATV_TOP_CR_CONT__PRE                                                0x9C

#define   ATV_TOP_CR_CONT_CR_P__B                                           0
#define   ATV_TOP_CR_CONT_CR_P__W                                           3
#define   ATV_TOP_CR_CONT_CR_P__M                                           0x7
#define   ATV_TOP_CR_CONT_CR_P__PRE                                         0x4
#define     ATV_TOP_CR_CONT_CR_P_MN                                         0x4
#define     ATV_TOP_CR_CONT_CR_P_FM                                         0x0

#define   ATV_TOP_CR_CONT_CR_D__B                                           3
#define   ATV_TOP_CR_CONT_CR_D__W                                           3
#define   ATV_TOP_CR_CONT_CR_D__M                                           0x38
#define   ATV_TOP_CR_CONT_CR_D__PRE                                         0x18
#define     ATV_TOP_CR_CONT_CR_D_MN                                         0x18
#define     ATV_TOP_CR_CONT_CR_D_FM                                         0x0

#define   ATV_TOP_CR_CONT_CR_I__B                                           6
#define   ATV_TOP_CR_CONT_CR_I__W                                           3
#define   ATV_TOP_CR_CONT_CR_I__M                                           0x1C0
#define   ATV_TOP_CR_CONT_CR_I__PRE                                         0x80
#define     ATV_TOP_CR_CONT_CR_I_MN                                         0x80
#define     ATV_TOP_CR_CONT_CR_I_FM                                         0x0

#define ATV_TOP_CR_OVM_TH__A                                                0xC10012
#define ATV_TOP_CR_OVM_TH__W                                                8
#define ATV_TOP_CR_OVM_TH__M                                                0xFF
#define ATV_TOP_CR_OVM_TH__PRE                                              0xA0
#define   ATV_TOP_CR_OVM_TH_MN                                              0xA0
#define   ATV_TOP_CR_OVM_TH_FM                                              0x0

#define ATV_TOP_NOISE_TH__A                                                 0xC10013
#define ATV_TOP_NOISE_TH__W                                                 4
#define ATV_TOP_NOISE_TH__M                                                 0xF
#define ATV_TOP_NOISE_TH__PRE                                               0x8
#define   ATV_TOP_NOISE_TH_MN                                               0x8

#define ATV_TOP_EQU0__A                                                     0xC10014
#define ATV_TOP_EQU0__W                                                     9
#define ATV_TOP_EQU0__M                                                     0x1FF
#define ATV_TOP_EQU0__PRE                                                   0x1FB

#define   ATV_TOP_EQU0_EQU_C0__B                                            0
#define   ATV_TOP_EQU0_EQU_C0__W                                            9
#define   ATV_TOP_EQU0_EQU_C0__M                                            0x1FF
#define   ATV_TOP_EQU0_EQU_C0__PRE                                          0x1FB
#define     ATV_TOP_EQU0_EQU_C0_MN                                          0xFB

#define ATV_TOP_EQU1__A                                                     0xC10015
#define ATV_TOP_EQU1__W                                                     9
#define ATV_TOP_EQU1__M                                                     0x1FF
#define ATV_TOP_EQU1__PRE                                                   0x1CE

#define   ATV_TOP_EQU1_EQU_C1__B                                            0
#define   ATV_TOP_EQU1_EQU_C1__W                                            9
#define   ATV_TOP_EQU1_EQU_C1__M                                            0x1FF
#define   ATV_TOP_EQU1_EQU_C1__PRE                                          0x1CE
#define     ATV_TOP_EQU1_EQU_C1_MN                                          0xCE

#define ATV_TOP_EQU2__A                                                     0xC10016
#define ATV_TOP_EQU2__W                                                     9
#define ATV_TOP_EQU2__M                                                     0x1FF
#define ATV_TOP_EQU2__PRE                                                   0xD2

#define   ATV_TOP_EQU2_EQU_C2__B                                            0
#define   ATV_TOP_EQU2_EQU_C2__W                                            9
#define   ATV_TOP_EQU2_EQU_C2__M                                            0x1FF
#define   ATV_TOP_EQU2_EQU_C2__PRE                                          0xD2
#define     ATV_TOP_EQU2_EQU_C2_MN                                          0xD2

#define ATV_TOP_EQU3__A                                                     0xC10017
#define ATV_TOP_EQU3__W                                                     9
#define ATV_TOP_EQU3__M                                                     0x1FF
#define ATV_TOP_EQU3__PRE                                                   0x160

#define   ATV_TOP_EQU3_EQU_C3__B                                            0
#define   ATV_TOP_EQU3_EQU_C3__W                                            9
#define   ATV_TOP_EQU3_EQU_C3__M                                            0x1FF
#define   ATV_TOP_EQU3_EQU_C3__PRE                                          0x160
#define     ATV_TOP_EQU3_EQU_C3_MN                                          0x60

#define ATV_TOP_ROT_MODE__A                                                 0xC10018
#define ATV_TOP_ROT_MODE__W                                                 1
#define ATV_TOP_ROT_MODE__M                                                 0x1
#define ATV_TOP_ROT_MODE__PRE                                               0x0
#define   ATV_TOP_ROT_MODE_AMPTH_DEPEND                                     0x0
#define   ATV_TOP_ROT_MODE_ALWAYS                                           0x1

#define ATV_TOP_MOD_CONTROL__A                                              0xC10019
#define ATV_TOP_MOD_CONTROL__W                                              12
#define ATV_TOP_MOD_CONTROL__M                                              0xFFF
#define ATV_TOP_MOD_CONTROL__PRE                                            0x5B1

#define   ATV_TOP_MOD_CONTROL_MOD_IR__B                                     0
#define   ATV_TOP_MOD_CONTROL_MOD_IR__W                                     3
#define   ATV_TOP_MOD_CONTROL_MOD_IR__M                                     0x7
#define   ATV_TOP_MOD_CONTROL_MOD_IR__PRE                                   0x1
#define     ATV_TOP_MOD_CONTROL_MOD_IR_MN                                   0x1
#define     ATV_TOP_MOD_CONTROL_MOD_IR_FM                                   0x0

#define   ATV_TOP_MOD_CONTROL_MOD_IF__B                                     3
#define   ATV_TOP_MOD_CONTROL_MOD_IF__W                                     4
#define   ATV_TOP_MOD_CONTROL_MOD_IF__M                                     0x78
#define   ATV_TOP_MOD_CONTROL_MOD_IF__PRE                                   0x30
#define     ATV_TOP_MOD_CONTROL_MOD_IF_MN                                   0x30
#define     ATV_TOP_MOD_CONTROL_MOD_IF_FM                                   0x0

#define   ATV_TOP_MOD_CONTROL_MOD_MODE__B                                   7
#define   ATV_TOP_MOD_CONTROL_MOD_MODE__W                                   1
#define   ATV_TOP_MOD_CONTROL_MOD_MODE__M                                   0x80
#define   ATV_TOP_MOD_CONTROL_MOD_MODE__PRE                                 0x80
#define     ATV_TOP_MOD_CONTROL_MOD_MODE_RISE                               0x0
#define     ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL                          0x80

#define   ATV_TOP_MOD_CONTROL_MOD_TH__B                                     8
#define   ATV_TOP_MOD_CONTROL_MOD_TH__W                                     4
#define   ATV_TOP_MOD_CONTROL_MOD_TH__M                                     0xF00
#define   ATV_TOP_MOD_CONTROL_MOD_TH__PRE                                   0x500
#define     ATV_TOP_MOD_CONTROL_MOD_TH_MN                                   0x500
#define     ATV_TOP_MOD_CONTROL_MOD_TH_FM                                   0x0

#define ATV_TOP_STD__A                                                      0xC1001A
#define ATV_TOP_STD__W                                                      2
#define ATV_TOP_STD__M                                                      0x3
#define ATV_TOP_STD__PRE                                                    0x0

#define   ATV_TOP_STD_MODE__B                                               0
#define   ATV_TOP_STD_MODE__W                                               1
#define   ATV_TOP_STD_MODE__M                                               0x1
#define   ATV_TOP_STD_MODE__PRE                                             0x0
#define     ATV_TOP_STD_MODE_MN                                             0x0
#define     ATV_TOP_STD_MODE_FM                                             0x1

#define   ATV_TOP_STD_VID_POL__B                                            1
#define   ATV_TOP_STD_VID_POL__W                                            1
#define   ATV_TOP_STD_VID_POL__M                                            0x2
#define   ATV_TOP_STD_VID_POL__PRE                                          0x0
#define     ATV_TOP_STD_VID_POL_NEG                                         0x0
#define     ATV_TOP_STD_VID_POL_POS                                         0x2

#define ATV_TOP_VID_AMP__A                                                  0xC1001B
#define ATV_TOP_VID_AMP__W                                                  12
#define ATV_TOP_VID_AMP__M                                                  0xFFF
#define ATV_TOP_VID_AMP__PRE                                                0x380
#define   ATV_TOP_VID_AMP_MN                                                0x380
#define   ATV_TOP_VID_AMP_FM                                                0x0

#define ATV_TOP_VID_PEAK__A                                                 0xC1001C
#define ATV_TOP_VID_PEAK__W                                                 5
#define ATV_TOP_VID_PEAK__M                                                 0x1F
#define ATV_TOP_VID_PEAK__PRE                                               0x1

#define ATV_TOP_FAGC_TH__A                                                  0xC1001D
#define ATV_TOP_FAGC_TH__W                                                  11
#define ATV_TOP_FAGC_TH__M                                                  0x7FF
#define ATV_TOP_FAGC_TH__PRE                                                0x2B2
#define   ATV_TOP_FAGC_TH_MN                                                0x2B2

#define ATV_TOP_SYNC_SLICE__A                                               0xC1001E
#define ATV_TOP_SYNC_SLICE__W                                               11
#define ATV_TOP_SYNC_SLICE__M                                               0x7FF
#define ATV_TOP_SYNC_SLICE__PRE                                             0x243
#define   ATV_TOP_SYNC_SLICE_MN                                             0x243

#define ATV_TOP_SIF_GAIN__A                                                 0xC1001F
#define ATV_TOP_SIF_GAIN__W                                                 11
#define ATV_TOP_SIF_GAIN__M                                                 0x7FF
#define ATV_TOP_SIF_GAIN__PRE                                               0x0

#define ATV_TOP_SIF_TP__A                                                   0xC10020
#define ATV_TOP_SIF_TP__W                                                   6
#define ATV_TOP_SIF_TP__M                                                   0x3F
#define ATV_TOP_SIF_TP__PRE                                                 0x0

#define ATV_TOP_MOD_ACCU__A                                                 0xC10021
#define ATV_TOP_MOD_ACCU__W                                                 10
#define ATV_TOP_MOD_ACCU__M                                                 0x3FF
#define ATV_TOP_MOD_ACCU__PRE                                               0x0

#define ATV_TOP_CR_FREQ__A                                                  0xC10022
#define ATV_TOP_CR_FREQ__W                                                  8
#define ATV_TOP_CR_FREQ__M                                                  0xFF
#define ATV_TOP_CR_FREQ__PRE                                                0x0

#define ATV_TOP_CR_PHAD__A                                                  0xC10023
#define ATV_TOP_CR_PHAD__W                                                  12
#define ATV_TOP_CR_PHAD__M                                                  0xFFF
#define ATV_TOP_CR_PHAD__PRE                                                0x0

#define ATV_TOP_AF_SIF_ATT__A                                               0xC10024
#define ATV_TOP_AF_SIF_ATT__W                                               2
#define ATV_TOP_AF_SIF_ATT__M                                               0x3
#define ATV_TOP_AF_SIF_ATT__PRE                                             0x0
#define   ATV_TOP_AF_SIF_ATT_0DB                                            0x0
#define   ATV_TOP_AF_SIF_ATT_M3DB                                           0x1
#define   ATV_TOP_AF_SIF_ATT_M6DB                                           0x2
#define   ATV_TOP_AF_SIF_ATT_M9DB                                           0x3

#define ATV_TOP_STDBY__A                                                    0xC10025
#define ATV_TOP_STDBY__W                                                    2
#define ATV_TOP_STDBY__M                                                    0x3
#define ATV_TOP_STDBY__PRE                                                  0x1

#define   ATV_TOP_STDBY_SIF_STDBY__B                                        0
#define   ATV_TOP_STDBY_SIF_STDBY__W                                        1
#define   ATV_TOP_STDBY_SIF_STDBY__M                                        0x1
#define   ATV_TOP_STDBY_SIF_STDBY__PRE                                      0x1
#define     ATV_TOP_STDBY_SIF_STDBY_ACTIVE                                  0x0
#define     ATV_TOP_STDBY_SIF_STDBY_STANDBY                                 0x1

#define   ATV_TOP_STDBY_CVBS_STDBY__B                                       1
#define   ATV_TOP_STDBY_CVBS_STDBY__W                                       1
#define   ATV_TOP_STDBY_CVBS_STDBY__M                                       0x2
#define   ATV_TOP_STDBY_CVBS_STDBY__PRE                                     0x0
#define     ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE                              0x0
#define     ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY                             0x2
#define     ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE                              0x2
#define     ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY                             0x0

#define ATV_TOP_OVERRIDE_SFR__A                                             0xC10026
#define ATV_TOP_OVERRIDE_SFR__W                                             1
#define ATV_TOP_OVERRIDE_SFR__M                                             0x1
#define ATV_TOP_OVERRIDE_SFR__PRE                                           0x0
#define   ATV_TOP_OVERRIDE_SFR_ACTIVE                                       0x0
#define   ATV_TOP_OVERRIDE_SFR_OVERRIDE                                     0x1

#define ATV_TOP_SFR_VID_GAIN__A                                             0xC10027
#define ATV_TOP_SFR_VID_GAIN__W                                             16
#define ATV_TOP_SFR_VID_GAIN__M                                             0xFFFF
#define ATV_TOP_SFR_VID_GAIN__PRE                                           0x0

#define ATV_TOP_SFR_AGC_RES__A                                              0xC10028
#define ATV_TOP_SFR_AGC_RES__W                                              5
#define ATV_TOP_SFR_AGC_RES__M                                              0x1F
#define ATV_TOP_SFR_AGC_RES__PRE                                            0x0

#define ATV_TOP_OVM_COMP__A                                                 0xC10029
#define ATV_TOP_OVM_COMP__W                                                 12
#define ATV_TOP_OVM_COMP__M                                                 0xFFF
#define ATV_TOP_OVM_COMP__PRE                                               0x0
#define ATV_TOP_OUT_CONF__A                                                 0xC1002A
#define ATV_TOP_OUT_CONF__W                                                 5
#define ATV_TOP_OUT_CONF__M                                                 0x1F
#define ATV_TOP_OUT_CONF__PRE                                               0x0

#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B                                 0
#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W                                 1
#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M                                 0x1
#define   ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE                               0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED                         0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED                           0x1

#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B                                  1
#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W                                  1
#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M                                  0x2
#define   ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE                                0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED                          0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED                            0x2

#define   ATV_TOP_OUT_CONF_SIF20_SIGN__B                                    2
#define   ATV_TOP_OUT_CONF_SIF20_SIGN__W                                    1
#define   ATV_TOP_OUT_CONF_SIF20_SIGN__M                                    0x4
#define   ATV_TOP_OUT_CONF_SIF20_SIGN__PRE                                  0x0
#define     ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED                            0x0
#define     ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED                              0x4

#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__B                                   3
#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__W                                   1
#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__M                                   0x8
#define   ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE                                 0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL                             0x0
#define     ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED                        0x8

#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__B                                    4
#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__W                                    1
#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__M                                    0x10
#define   ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE                                  0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL                              0x0
#define     ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED                         0x10

#define ATV_AFT_COMM_EXEC__A                                                0xFF0000
#define ATV_AFT_COMM_EXEC__W                                                2
#define ATV_AFT_COMM_EXEC__M                                                0x3
#define ATV_AFT_COMM_EXEC__PRE                                              0x0
#define   ATV_AFT_COMM_EXEC_STOP                                            0x0
#define   ATV_AFT_COMM_EXEC_ACTIVE                                          0x1
#define   ATV_AFT_COMM_EXEC_HOLD                                            0x2

#define ATV_AFT_TST__A                                                      0xFF0010
#define ATV_AFT_TST__W                                                      4
#define ATV_AFT_TST__M                                                      0xF
#define ATV_AFT_TST__PRE                                                    0x0

#define AUD_COMM_EXEC__A                                                    0x1000000
#define AUD_COMM_EXEC__W                                                    2
#define AUD_COMM_EXEC__M                                                    0x3
#define AUD_COMM_EXEC__PRE                                                  0x0
#define   AUD_COMM_EXEC_STOP                                                0x0
#define   AUD_COMM_EXEC_ACTIVE                                              0x1

#define AUD_COMM_MB__A                                                      0x1000002
#define AUD_COMM_MB__W                                                      16
#define AUD_COMM_MB__M                                                      0xFFFF
#define AUD_COMM_MB__PRE                                                    0x0

#define AUD_TOP_COMM_EXEC__A                                                0x1010000
#define AUD_TOP_COMM_EXEC__W                                                2
#define AUD_TOP_COMM_EXEC__M                                                0x3
#define AUD_TOP_COMM_EXEC__PRE                                              0x0
#define   AUD_TOP_COMM_EXEC_STOP                                            0x0
#define   AUD_TOP_COMM_EXEC_ACTIVE                                          0x1

#define AUD_TOP_COMM_MB__A                                                  0x1010002
#define AUD_TOP_COMM_MB__W                                                  16
#define AUD_TOP_COMM_MB__M                                                  0xFFFF
#define AUD_TOP_COMM_MB__PRE                                                0x0

#define   AUD_TOP_COMM_MB_CTL__B                                            0
#define   AUD_TOP_COMM_MB_CTL__W                                            1
#define   AUD_TOP_COMM_MB_CTL__M                                            0x1
#define   AUD_TOP_COMM_MB_CTL__PRE                                          0x0
#define     AUD_TOP_COMM_MB_CTL_CTR_OFF                                     0x0
#define     AUD_TOP_COMM_MB_CTL_CTR_ON                                      0x1

#define   AUD_TOP_COMM_MB_OBS__B                                            1
#define   AUD_TOP_COMM_MB_OBS__W                                            1
#define   AUD_TOP_COMM_MB_OBS__M                                            0x2
#define   AUD_TOP_COMM_MB_OBS__PRE                                          0x0
#define     AUD_TOP_COMM_MB_OBS_OBS_OFF                                     0x0
#define     AUD_TOP_COMM_MB_OBS_OBS_ON                                      0x2

#define   AUD_TOP_COMM_MB_MUX_CTRL__B                                       2
#define   AUD_TOP_COMM_MB_MUX_CTRL__W                                       4
#define   AUD_TOP_COMM_MB_MUX_CTRL__M                                       0x3C
#define   AUD_TOP_COMM_MB_MUX_CTRL__PRE                                     0x0
#define     AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO                              0x0
#define     AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS                              0x4
#define     AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC                              0x8
#define     AUD_TOP_COMM_MB_MUX_CTRL_SAOUT                                  0xC
#define     AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ                             0x10

#define   AUD_TOP_COMM_MB_MUX_OBS__B                                        6
#define   AUD_TOP_COMM_MB_MUX_OBS__W                                        4
#define   AUD_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
#define   AUD_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
#define     AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO                               0x0
#define     AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS                               0x40
#define     AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC                               0x80
#define     AUD_TOP_COMM_MB_MUX_OBS_SAOUT                                   0xC0
#define     AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ                              0x100

#define AUD_TOP_TR_MDE__A                                                   0x1010010
#define AUD_TOP_TR_MDE__W                                                   5
#define AUD_TOP_TR_MDE__M                                                   0x1F
#define AUD_TOP_TR_MDE__PRE                                                 0x18

#define   AUD_TOP_TR_MDE_FIFO_SIZE__B                                       0
#define   AUD_TOP_TR_MDE_FIFO_SIZE__W                                       4
#define   AUD_TOP_TR_MDE_FIFO_SIZE__M                                       0xF
#define   AUD_TOP_TR_MDE_FIFO_SIZE__PRE                                     0x8

#define   AUD_TOP_TR_MDE_RD_LOCK__B                                         4
#define   AUD_TOP_TR_MDE_RD_LOCK__W                                         1
#define   AUD_TOP_TR_MDE_RD_LOCK__M                                         0x10
#define   AUD_TOP_TR_MDE_RD_LOCK__PRE                                       0x10
#define     AUD_TOP_TR_MDE_RD_LOCK_NORMAL                                   0x0
#define     AUD_TOP_TR_MDE_RD_LOCK_LOCK                                     0x10

#define AUD_TOP_TR_CTR__A                                                   0x1010011
#define AUD_TOP_TR_CTR__W                                                   4
#define AUD_TOP_TR_CTR__M                                                   0xF
#define AUD_TOP_TR_CTR__PRE                                                 0x0

#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__B                                     0
#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__W                                     1
#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__M                                     0x1
#define   AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE                                   0x0
#define     AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY                            0x0
#define     AUD_TOP_TR_CTR_FIFO_RD_RDY_READY                                0x1

#define   AUD_TOP_TR_CTR_FIFO_EMPTY__B                                      1
#define   AUD_TOP_TR_CTR_FIFO_EMPTY__W                                      1
#define   AUD_TOP_TR_CTR_FIFO_EMPTY__M                                      0x2
#define   AUD_TOP_TR_CTR_FIFO_EMPTY__PRE                                    0x0
#define     AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY                             0x0
#define     AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY                                 0x2

#define   AUD_TOP_TR_CTR_FIFO_LOCK__B                                       2
#define   AUD_TOP_TR_CTR_FIFO_LOCK__W                                       1
#define   AUD_TOP_TR_CTR_FIFO_LOCK__M                                       0x4
#define   AUD_TOP_TR_CTR_FIFO_LOCK__PRE                                     0x0
#define     AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED                               0x0
#define     AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED                                 0x4

#define   AUD_TOP_TR_CTR_FIFO_FULL__B                                       3
#define   AUD_TOP_TR_CTR_FIFO_FULL__W                                       1
#define   AUD_TOP_TR_CTR_FIFO_FULL__M                                       0x8
#define   AUD_TOP_TR_CTR_FIFO_FULL__PRE                                     0x0
#define     AUD_TOP_TR_CTR_FIFO_FULL_EMPTY                                  0x0
#define     AUD_TOP_TR_CTR_FIFO_FULL_FULL                                   0x8

#define AUD_TOP_TR_RD_REG__A                                                0x1010012
#define AUD_TOP_TR_RD_REG__W                                                16
#define AUD_TOP_TR_RD_REG__M                                                0xFFFF
#define AUD_TOP_TR_RD_REG__PRE                                              0x0

#define   AUD_TOP_TR_RD_REG_RESULT__B                                       0
#define   AUD_TOP_TR_RD_REG_RESULT__W                                       16
#define   AUD_TOP_TR_RD_REG_RESULT__M                                       0xFFFF
#define   AUD_TOP_TR_RD_REG_RESULT__PRE                                     0x0

#define AUD_TOP_TR_TIMER__A                                                 0x1010013
#define AUD_TOP_TR_TIMER__W                                                 16
#define AUD_TOP_TR_TIMER__M                                                 0xFFFF
#define AUD_TOP_TR_TIMER__PRE                                               0x0

#define   AUD_TOP_TR_TIMER_CYCLES__B                                        0
#define   AUD_TOP_TR_TIMER_CYCLES__W                                        16
#define   AUD_TOP_TR_TIMER_CYCLES__M                                        0xFFFF
#define   AUD_TOP_TR_TIMER_CYCLES__PRE                                      0x0

#define AUD_TOP_DEMOD_TBO_SEL__A                                            0x1010014
#define AUD_TOP_DEMOD_TBO_SEL__W                                            5
#define AUD_TOP_DEMOD_TBO_SEL__M                                            0x1F
#define AUD_TOP_DEMOD_TBO_SEL__PRE                                          0x0

#define AUD_DEM_WR_MODUS__A                                                 0x1030030
#define AUD_DEM_WR_MODUS__W                                                 16
#define AUD_DEM_WR_MODUS__M                                                 0xFFFF
#define AUD_DEM_WR_MODUS__PRE                                               0x0

#define   AUD_DEM_WR_MODUS_MOD_ASS__B                                       0
#define   AUD_DEM_WR_MODUS_MOD_ASS__W                                       1
#define   AUD_DEM_WR_MODUS_MOD_ASS__M                                       0x1
#define   AUD_DEM_WR_MODUS_MOD_ASS__PRE                                     0x0
#define     AUD_DEM_WR_MODUS_MOD_ASS_OFF                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_ASS_ON                                     0x1

#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__B                                1
#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__W                                1
#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__M                                0x2
#define   AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE                              0x0
#define     AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE                         0x0
#define     AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE                          0x2

#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B                               2
#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W                               1
#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M                               0x4
#define   AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE                             0x0
#define     AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED                        0x0
#define     AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED                       0x4

#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__B                                    8
#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__W                                    1
#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__M                                    0x100
#define   AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL                              0x0
#define     AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION                      0x100

#define   AUD_DEM_WR_MODUS_MOD_CM_A__B                                      9
#define   AUD_DEM_WR_MODUS_MOD_CM_A__W                                      1
#define   AUD_DEM_WR_MODUS_MOD_CM_A__M                                      0x200
#define   AUD_DEM_WR_MODUS_MOD_CM_A__PRE                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_A_MUTE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_A_NOISE                                 0x200

#define   AUD_DEM_WR_MODUS_MOD_CM_B__B                                      10
#define   AUD_DEM_WR_MODUS_MOD_CM_B__W                                      1
#define   AUD_DEM_WR_MODUS_MOD_CM_B__M                                      0x400
#define   AUD_DEM_WR_MODUS_MOD_CM_B__PRE                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_B_MUTE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_CM_B_NOISE                                 0x400

#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__B                                   11
#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__W                                   1
#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__M                                   0x800
#define   AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE                                 0x0
#define     AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U                             0x0
#define     AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U                             0x800

#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__B                                    12
#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__W                                    1
#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__M                                    0x1000
#define   AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM                               0x0
#define     AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K                                 0x1000

#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__B                                    13
#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__W                                    2
#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__M                                    0x6000
#define   AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE                                  0x0
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA                             0x0
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC                              0x2000
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ                              0x4000
#define     AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA                              0x6000

#define   AUD_DEM_WR_MODUS_MOD_BTSC__B                                      15
#define   AUD_DEM_WR_MODUS_MOD_BTSC__W                                      1
#define   AUD_DEM_WR_MODUS_MOD_BTSC__M                                      0x8000
#define   AUD_DEM_WR_MODUS_MOD_BTSC__PRE                                    0x0
#define     AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO                           0x0
#define     AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP                              0x8000

#define AUD_DEM_WR_STANDARD_SEL__A                                          0x1030020
#define AUD_DEM_WR_STANDARD_SEL__W                                          16
#define AUD_DEM_WR_STANDARD_SEL__M                                          0xFFFF
#define AUD_DEM_WR_STANDARD_SEL__PRE                                        0x0

#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__B                                0
#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__W                                12
#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__M                                0xFFF
#define   AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE                              0x0
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO                            0x1
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA                         0x2
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM                           0x3
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1                            0x4
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2                            0x5
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3                            0x7
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM                     0x8
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM                      0x9
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM                      0xA
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM                    0xB
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO                     0x20
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP                        0x21
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J                           0x30
#define     AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO                        0x40

#define AUD_DEM_RD_STANDARD_RES__A                                          0x102007E
#define AUD_DEM_RD_STANDARD_RES__W                                          16
#define AUD_DEM_RD_STANDARD_RES__M                                          0xFFFF
#define AUD_DEM_RD_STANDARD_RES__PRE                                        0x0

#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__B                             0
#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__W                             16
#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__M                             0xFFFF
#define   AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE                           0x0
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD            0x0
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM       0x2
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM          0x3
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM         0x4
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM         0x5
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM         0x7
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM                 0x8
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM                   0x9
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM                   0xA
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM                 0xB
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO                  0x20
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP                0x21
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J                   0x30
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO                     0x40
#define     AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE       0x7FF

#define AUD_DEM_RD_STATUS__A                                                0x1020200
#define AUD_DEM_RD_STATUS__W                                                16
#define AUD_DEM_RD_STATUS__M                                                0xFFFF
#define AUD_DEM_RD_STATUS__PRE                                              0x0

#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__B                                 0
#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__W                                 1
#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__M                                 0x1
#define   AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE                               0x0
#define     AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA                      0x0
#define     AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA                     0x1

#define   AUD_DEM_RD_STATUS_STAT_CARR_A__B                                  1
#define   AUD_DEM_RD_STATUS_STAT_CARR_A__W                                  1
#define   AUD_DEM_RD_STATUS_STAT_CARR_A__M                                  0x2
#define   AUD_DEM_RD_STATUS_STAT_CARR_A__PRE                                0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED                          0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED                      0x2

#define   AUD_DEM_RD_STATUS_STAT_CARR_B__B                                  2
#define   AUD_DEM_RD_STATUS_STAT_CARR_B__W                                  1
#define   AUD_DEM_RD_STATUS_STAT_CARR_B__M                                  0x4
#define   AUD_DEM_RD_STATUS_STAT_CARR_B__PRE                                0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED                          0x0
#define     AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED                      0x4

#define   AUD_DEM_RD_STATUS_STAT_NICAM__B                                   5
#define   AUD_DEM_RD_STATUS_STAT_NICAM__W                                   1
#define   AUD_DEM_RD_STATUS_STAT_NICAM__M                                   0x20
#define   AUD_DEM_RD_STATUS_STAT_NICAM__PRE                                 0x0
#define     AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM                           0x0
#define     AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED                     0x20

#define   AUD_DEM_RD_STATUS_STAT_STEREO__B                                  6
#define   AUD_DEM_RD_STATUS_STAT_STEREO__W                                  1
#define   AUD_DEM_RD_STATUS_STAT_STEREO__M                                  0x40
#define   AUD_DEM_RD_STATUS_STAT_STEREO__PRE                                0x0
#define     AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO                         0x0
#define     AUD_DEM_RD_STATUS_STAT_STEREO_STEREO                            0x40

#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B                              7
#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W                              1
#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M                              0x80
#define   AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE                            0x0
#define     AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM     0x0
#define     AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM   0x80

#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B                              8
#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W                              1
#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M                              0x100
#define   AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE                            0x0
#define     AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP                        0x0
#define     AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP                           0x100

#define   AUD_DEM_RD_STATUS_BAD_NICAM__B                                    9
#define   AUD_DEM_RD_STATUS_BAD_NICAM__W                                    1
#define   AUD_DEM_RD_STATUS_BAD_NICAM__M                                    0x200
#define   AUD_DEM_RD_STATUS_BAD_NICAM__PRE                                  0x0
#define     AUD_DEM_RD_STATUS_BAD_NICAM_OK                                  0x0
#define     AUD_DEM_RD_STATUS_BAD_NICAM_BAD                                 0x200

#define AUD_DEM_RD_RDS_ARRAY_CNT__A                                         0x102020F
#define AUD_DEM_RD_RDS_ARRAY_CNT__W                                         12
#define AUD_DEM_RD_RDS_ARRAY_CNT__M                                         0xFFF
#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE                                       0x0

#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B                          0
#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W                          12
#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M                          0xFFF
#define   AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE                        0x0
#define     AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID        0xFFF

#define AUD_DEM_RD_RDS_DATA__A                                              0x1020210
#define AUD_DEM_RD_RDS_DATA__W                                              12
#define AUD_DEM_RD_RDS_DATA__M                                              0xFFF
#define AUD_DEM_RD_RDS_DATA__PRE                                            0x0

#define AUD_DSP_WR_FM_PRESC__A                                              0x105000E
#define AUD_DSP_WR_FM_PRESC__W                                              16
#define AUD_DSP_WR_FM_PRESC__M                                              0xFFFF
#define AUD_DSP_WR_FM_PRESC__PRE                                            0x0

#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B                                8
#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W                                8
#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M                                0xFF00
#define   AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE                              0x0
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION             0x7F00
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION             0x4800
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION             0x3000
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION            0x2400
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION            0x1800
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION            0x1300
#define     AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION            0x900

#define AUD_DSP_WR_NICAM_PRESC__A                                           0x1050010
#define AUD_DSP_WR_NICAM_PRESC__W                                           16
#define AUD_DSP_WR_NICAM_PRESC__M                                           0xFFFF
#define AUD_DSP_WR_NICAM_PRESC__PRE                                         0x0
#define AUD_DSP_WR_VOLUME__A                                                0x1050000
#define AUD_DSP_WR_VOLUME__W                                                16
#define AUD_DSP_WR_VOLUME__M                                                0xFFFF
#define AUD_DSP_WR_VOLUME__PRE                                              0x0

#define   AUD_DSP_WR_VOLUME_VOL_MAIN__B                                     8
#define   AUD_DSP_WR_VOLUME_VOL_MAIN__W                                     8
#define   AUD_DSP_WR_VOLUME_VOL_MAIN__M                                     0xFF00
#define   AUD_DSP_WR_VOLUME_VOL_MAIN__PRE                                   0x0

#define AUD_DSP_WR_SRC_I2S_MATR__A                                          0x1050038
#define AUD_DSP_WR_SRC_I2S_MATR__W                                          16
#define AUD_DSP_WR_SRC_I2S_MATR__M                                          0xFFFF
#define AUD_DSP_WR_SRC_I2S_MATR__PRE                                        0x0

#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B                                8
#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W                                8
#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M                                0xFF00
#define   AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE                              0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO                            0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB                       0x100
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A                        0x300
#define     AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B                        0x400

#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B                                0
#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W                                8
#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M                                0xFF
#define   AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE                              0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A                         0x0
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B                         0x10
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO                          0x20
#define     AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO                            0x30

#define AUD_DSP_WR_AVC__A                                                   0x1050029
#define AUD_DSP_WR_AVC__W                                                   16
#define AUD_DSP_WR_AVC__M                                                   0xFFFF
#define AUD_DSP_WR_AVC__PRE                                                 0x0

#define   AUD_DSP_WR_AVC_AVC_ON__B                                          14
#define   AUD_DSP_WR_AVC_AVC_ON__W                                          2
#define   AUD_DSP_WR_AVC_AVC_ON__M                                          0xC000
#define   AUD_DSP_WR_AVC_AVC_ON__PRE                                        0x0
#define     AUD_DSP_WR_AVC_AVC_ON_OFF                                       0x0
#define     AUD_DSP_WR_AVC_AVC_ON_ON                                        0xC000

#define   AUD_DSP_WR_AVC_AVC_DECAY__B                                       8
#define   AUD_DSP_WR_AVC_AVC_DECAY__W                                       4
#define   AUD_DSP_WR_AVC_AVC_DECAY__M                                       0xF00
#define   AUD_DSP_WR_AVC_AVC_DECAY__PRE                                     0x0
#define     AUD_DSP_WR_AVC_AVC_DECAY_8_SEC                                  0x800
#define     AUD_DSP_WR_AVC_AVC_DECAY_4_SEC                                  0x400
#define     AUD_DSP_WR_AVC_AVC_DECAY_2_SEC                                  0x200
#define     AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC                                0x100

#define   AUD_DSP_WR_AVC_AVC_REF_LEV__B                                     4
#define   AUD_DSP_WR_AVC_AVC_REF_LEV__W                                     4
#define   AUD_DSP_WR_AVC_AVC_REF_LEV__M                                     0xF0
#define   AUD_DSP_WR_AVC_AVC_REF_LEV__PRE                                   0x0

#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__B                                     2
#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__W                                     2
#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__M                                     0xC
#define   AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE                                   0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB                                 0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB                                 0x4
#define     AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB                                 0x8

#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__B                                    0
#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__W                                    2
#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__M                                    0x3
#define   AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE                                  0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB                                 0x0
#define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB                                0x1
#define     AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB                                 0x3

#define AUD_DSP_WR_QPEAK__A                                                 0x105000C
#define AUD_DSP_WR_QPEAK__W                                                 16
#define AUD_DSP_WR_QPEAK__M                                                 0xFFFF
#define AUD_DSP_WR_QPEAK__PRE                                               0x0

#define   AUD_DSP_WR_QPEAK_SRC_QP__B                                        8
#define   AUD_DSP_WR_QPEAK_SRC_QP__W                                        8
#define   AUD_DSP_WR_QPEAK_SRC_QP__M                                        0xFF00
#define   AUD_DSP_WR_QPEAK_SRC_QP__PRE                                      0x0
#define     AUD_DSP_WR_QPEAK_SRC_QP_MONO                                    0x0
#define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB                               0x100
#define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A                                0x300
#define     AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B                                0x400

#define   AUD_DSP_WR_QPEAK_MAT_QP__B                                        0
#define   AUD_DSP_WR_QPEAK_MAT_QP__W                                        8
#define   AUD_DSP_WR_QPEAK_MAT_QP__M                                        0xFF
#define   AUD_DSP_WR_QPEAK_MAT_QP__PRE                                      0x0
#define     AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A                                 0x0
#define     AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B                                 0x10
#define     AUD_DSP_WR_QPEAK_MAT_QP_STEREO                                  0x20
#define     AUD_DSP_WR_QPEAK_MAT_QP_MONO                                    0x30

#define AUD_DSP_RD_QPEAK_L__A                                               0x1040019
#define AUD_DSP_RD_QPEAK_L__W                                               16
#define AUD_DSP_RD_QPEAK_L__M                                               0xFFFF
#define AUD_DSP_RD_QPEAK_L__PRE                                             0x0

#define AUD_DSP_RD_QPEAK_R__A                                               0x104001A
#define AUD_DSP_RD_QPEAK_R__W                                               16
#define AUD_DSP_RD_QPEAK_R__M                                               0xFFFF
#define AUD_DSP_RD_QPEAK_R__PRE                                             0x0

#define AUD_DSP_WR_BEEPER__A                                                0x1050014
#define AUD_DSP_WR_BEEPER__W                                                16
#define AUD_DSP_WR_BEEPER__M                                                0xFFFF
#define AUD_DSP_WR_BEEPER__PRE                                              0x0

#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__B                                  8
#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__W                                  7
#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__M                                  0x7F00
#define   AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE                                0x0

#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B                               0
#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W                               7
#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M                               0x7F
#define   AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE                             0x0

#define AUD_DEM_WR_I2S_CONFIG2__A                                           0x1030050
#define AUD_DEM_WR_I2S_CONFIG2__W                                           16
#define AUD_DEM_WR_I2S_CONFIG2__M                                           0xFFFF
#define AUD_DEM_WR_I2S_CONFIG2__PRE                                         0x0

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B                              6
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W                              1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M                              0x40
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE                            0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL                        0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED                      0x40

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B                              4
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W                              1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M                              0x10
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE                            0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE                       0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE                        0x10

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B                             3
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W                             1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M                             0x8
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE                           0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER                       0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE                        0x8

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B                              2
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W                              1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M                              0x4
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE                            0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW                      0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH                     0x4

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B                             1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W                             1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M                             0x2
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE                           0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY                     0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY                        0x2

#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B                            0
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W                            1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M                            0x1
#define   AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE                          0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32                      0x0
#define     AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16                      0x1

#define AUD_DSP_WR_I2S_OUT_FS__A                                            0x105002A
#define AUD_DSP_WR_I2S_OUT_FS__W                                            16
#define AUD_DSP_WR_I2S_OUT_FS__M                                            0xFFFF
#define AUD_DSP_WR_I2S_OUT_FS__PRE                                          0x0

#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B                                   0
#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W                                   16
#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M                                   0xFFFF
#define   AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE                                 0x0

#define AUD_DSP_WR_AV_SYNC__A                                               0x105002B
#define AUD_DSP_WR_AV_SYNC__W                                               16
#define AUD_DSP_WR_AV_SYNC__M                                               0xFFFF
#define AUD_DSP_WR_AV_SYNC__PRE                                             0x0

#define   AUD_DSP_WR_AV_SYNC_AV_ON__B                                       15
#define   AUD_DSP_WR_AV_SYNC_AV_ON__W                                       1
#define   AUD_DSP_WR_AV_SYNC_AV_ON__M                                       0x8000
#define   AUD_DSP_WR_AV_SYNC_AV_ON__PRE                                     0x0
#define     AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE                                0x0
#define     AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE                                 0x8000

#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B                                14
#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W                                1
#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M                                0x4000
#define   AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE                              0x0
#define     AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME                      0x0
#define     AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC                            0x4000

#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B                                  0
#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W                                  2
#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M                                  0x3
#define   AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE                                0x0
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO                              0x0
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM                         0x1
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC                              0x2
#define     AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME                        0x3

#define AUD_DSP_RD_STATUS2__A                                               0x104007B
#define AUD_DSP_RD_STATUS2__W                                               16
#define AUD_DSP_RD_STATUS2__M                                               0xFFFF
#define AUD_DSP_RD_STATUS2__PRE                                             0x0

#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__B                                   15
#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__W                                   1
#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__M                                   0x8000
#define   AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE                                 0x0
#define     AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC                            0x0
#define     AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE                        0x8000

#define AUD_DSP_RD_XDFP_FW__A                                               0x104001D
#define AUD_DSP_RD_XDFP_FW__W                                               16
#define AUD_DSP_RD_XDFP_FW__M                                               0xFFFF
#define AUD_DSP_RD_XDFP_FW__PRE                                             0x344

#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B                                  0
#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W                                  16
#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M                                  0xFFFF
#define   AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE                                0x344

#define AUD_DSP_RD_XFP_FW__A                                                0x10404B8
#define AUD_DSP_RD_XFP_FW__W                                                16
#define AUD_DSP_RD_XFP_FW__M                                                0xFFFF
#define AUD_DSP_RD_XFP_FW__PRE                                              0x42

#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__B                                    0
#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__W                                    16
#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__M                                    0xFFFF
#define   AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE                                  0x42

#define AUD_DEM_WR_DCO_B_HI__A                                              0x103009B
#define AUD_DEM_WR_DCO_B_HI__W                                              16
#define AUD_DEM_WR_DCO_B_HI__M                                              0xFFFF
#define AUD_DEM_WR_DCO_B_HI__PRE                                            0x0

#define AUD_DEM_WR_DCO_B_LO__A                                              0x1030093
#define AUD_DEM_WR_DCO_B_LO__W                                              16
#define AUD_DEM_WR_DCO_B_LO__M                                              0xFFFF
#define AUD_DEM_WR_DCO_B_LO__PRE                                            0x0

#define AUD_DEM_WR_DCO_A_HI__A                                              0x10300AB
#define AUD_DEM_WR_DCO_A_HI__W                                              16
#define AUD_DEM_WR_DCO_A_HI__M                                              0xFFFF
#define AUD_DEM_WR_DCO_A_HI__PRE                                            0x0

#define AUD_DEM_WR_DCO_A_LO__A                                              0x10300A3
#define AUD_DEM_WR_DCO_A_LO__W                                              16
#define AUD_DEM_WR_DCO_A_LO__M                                              0xFFFF
#define AUD_DEM_WR_DCO_A_LO__PRE                                            0x0
#define AUD_DEM_WR_NICAM_THRSHLD__A                                         0x1030021
#define AUD_DEM_WR_NICAM_THRSHLD__W                                         16
#define AUD_DEM_WR_NICAM_THRSHLD__M                                         0xFFFF
#define AUD_DEM_WR_NICAM_THRSHLD__PRE                                       0x2BC

#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B                            0
#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W                            12
#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M                            0xFFF
#define   AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE                          0x2BC

#define AUD_DEM_WR_A2_THRSHLD__A                                            0x1030022
#define AUD_DEM_WR_A2_THRSHLD__W                                            16
#define AUD_DEM_WR_A2_THRSHLD__M                                            0xFFFF
#define AUD_DEM_WR_A2_THRSHLD__PRE                                          0x190

#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__B                                  0
#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__W                                  12
#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__M                                  0xFFF
#define   AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE                                0x190

#define AUD_DEM_WR_BTSC_THRSHLD__A                                          0x1030023
#define AUD_DEM_WR_BTSC_THRSHLD__W                                          16
#define AUD_DEM_WR_BTSC_THRSHLD__M                                          0xFFFF
#define AUD_DEM_WR_BTSC_THRSHLD__PRE                                        0xC

#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B                              0
#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W                              12
#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M                              0xFFF
#define   AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE                            0xC

#define AUD_DEM_WR_CM_A_THRSHLD__A                                          0x1030024
#define AUD_DEM_WR_CM_A_THRSHLD__W                                          16
#define AUD_DEM_WR_CM_A_THRSHLD__M                                          0xFFFF
#define AUD_DEM_WR_CM_A_THRSHLD__PRE                                        0x2A

#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B                              0
#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W                              12
#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M                              0xFFF
#define   AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE                            0x2A

#define AUD_DEM_WR_CM_B_THRSHLD__A                                          0x1030025
#define AUD_DEM_WR_CM_B_THRSHLD__W                                          16
#define AUD_DEM_WR_CM_B_THRSHLD__M                                          0xFFFF
#define AUD_DEM_WR_CM_B_THRSHLD__PRE                                        0x2A

#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B                              0
#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W                              12
#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M                              0xFFF
#define   AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE                            0x2A

#define AUD_DEM_RD_NIC_C_AD_BITS__A                                         0x1020023
#define AUD_DEM_RD_NIC_C_AD_BITS__W                                         16
#define AUD_DEM_RD_NIC_C_AD_BITS__M                                         0xFFFF
#define AUD_DEM_RD_NIC_C_AD_BITS__PRE                                       0x0

#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B                            0
#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W                            1
#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M                            0x1
#define   AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE                          0x0
#define     AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED                  0x0
#define     AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED                      0x1

#define   AUD_DEM_RD_NIC_C_AD_BITS_C__B                                     1
#define   AUD_DEM_RD_NIC_C_AD_BITS_C__W                                     4
#define   AUD_DEM_RD_NIC_C_AD_BITS_C__M                                     0x1E
#define   AUD_DEM_RD_NIC_C_AD_BITS_C__PRE                                   0x0

#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B                            5
#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W                            3
#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M                            0xE0
#define   AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE                          0x0

#define AUD_DEM_RD_NIC_ADD_BITS_HI__A                                       0x1020038
#define AUD_DEM_RD_NIC_ADD_BITS_HI__W                                       16
#define AUD_DEM_RD_NIC_ADD_BITS_HI__M                                       0xFFFF
#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE                                     0x0

#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B                          0
#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W                          8
#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M                          0xFF
#define   AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE                        0x0

#define AUD_DEM_RD_NIC_CIB__A                                               0x1020038
#define AUD_DEM_RD_NIC_CIB__W                                               16
#define AUD_DEM_RD_NIC_CIB__M                                               0xFFFF
#define AUD_DEM_RD_NIC_CIB__PRE                                             0x0

#define   AUD_DEM_RD_NIC_CIB_CIB2__B                                        0
#define   AUD_DEM_RD_NIC_CIB_CIB2__W                                        1
#define   AUD_DEM_RD_NIC_CIB_CIB2__M                                        0x1
#define   AUD_DEM_RD_NIC_CIB_CIB2__PRE                                      0x0

#define   AUD_DEM_RD_NIC_CIB_CIB1__B                                        1
#define   AUD_DEM_RD_NIC_CIB_CIB1__W                                        1
#define   AUD_DEM_RD_NIC_CIB_CIB1__M                                        0x2
#define   AUD_DEM_RD_NIC_CIB_CIB1__PRE                                      0x0

#define AUD_DEM_RD_NIC_ERROR_RATE__A                                        0x1020057
#define AUD_DEM_RD_NIC_ERROR_RATE__W                                        16
#define AUD_DEM_RD_NIC_ERROR_RATE__M                                        0xFFFF
#define AUD_DEM_RD_NIC_ERROR_RATE__PRE                                      0x0

#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B                           0
#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W                           12
#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M                           0xFFF
#define   AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE                         0x0

#define AUD_DEM_WR_FM_DEEMPH__A                                             0x103000F
#define AUD_DEM_WR_FM_DEEMPH__W                                             16
#define AUD_DEM_WR_FM_DEEMPH__M                                             0xFFFF
#define AUD_DEM_WR_FM_DEEMPH__PRE                                           0x0
#define   AUD_DEM_WR_FM_DEEMPH_50US                                         0x0
#define   AUD_DEM_WR_FM_DEEMPH_75US                                         0x1
#define   AUD_DEM_WR_FM_DEEMPH_OFF                                          0x3F

#define AUD_DEM_WR_FM_MATRIX__A                                             0x103006F
#define AUD_DEM_WR_FM_MATRIX__W                                             16
#define AUD_DEM_WR_FM_MATRIX__M                                             0xFFFF
#define AUD_DEM_WR_FM_MATRIX__PRE                                           0x0
#define   AUD_DEM_WR_FM_MATRIX_NO_MATRIX                                    0x0
#define   AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX                                0x1
#define   AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX                                0x2
#define   AUD_DEM_WR_FM_MATRIX_SOUND_A                                      0x3
#define   AUD_DEM_WR_FM_MATRIX_SOUND_B                                      0x4

#define AUD_DSP_RD_FM_IDENT_VALUE__A                                        0x1040018
#define AUD_DSP_RD_FM_IDENT_VALUE__W                                        16
#define AUD_DSP_RD_FM_IDENT_VALUE__M                                        0xFFFF
#define AUD_DSP_RD_FM_IDENT_VALUE__PRE                                      0x0

#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B                             8
#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W                             8
#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M                             0xFF00
#define   AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE                           0x0

#define AUD_DSP_RD_FM_DC_LEVEL_A__A                                         0x104001B
#define AUD_DSP_RD_FM_DC_LEVEL_A__W                                         16
#define AUD_DSP_RD_FM_DC_LEVEL_A__M                                         0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE                                       0x0

#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B                           0
#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W                           16
#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M                           0xFFFF
#define   AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE                         0x0

#define AUD_DSP_RD_FM_DC_LEVEL_B__A                                         0x104001C
#define AUD_DSP_RD_FM_DC_LEVEL_B__W                                         16
#define AUD_DSP_RD_FM_DC_LEVEL_B__M                                         0xFFFF
#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE                                       0x0

#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B                           0
#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W                           16
#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M                           0xFFFF
#define   AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE                         0x0

#define AUD_DEM_WR_FM_DC_NOTCH_SW__A                                        0x1030017
#define AUD_DEM_WR_FM_DC_NOTCH_SW__W                                        16
#define AUD_DEM_WR_FM_DC_NOTCH_SW__M                                        0xFFFF
#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE                                      0x0

#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B                          0
#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W                          16
#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M                          0xFFFF
#define   AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE                        0x0
#define     AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON                        0x0
#define     AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF                       0x3F

#define AUD_DSP_WR_SYNC_OUT__A                                              0x1050026
#define AUD_DSP_WR_SYNC_OUT__W                                              16
#define AUD_DSP_WR_SYNC_OUT__M                                              0xFFFF
#define AUD_DSP_WR_SYNC_OUT__PRE                                            0x0
#define   AUD_DSP_WR_SYNC_OUT_OFF                                           0x0
#define   AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS                                   0x1

#define AUD_XFP_DRAM_1K__A                                                  0x1060000
#define AUD_XFP_DRAM_1K__W                                                  16
#define AUD_XFP_DRAM_1K__M                                                  0xFFFF
#define AUD_XFP_DRAM_1K__PRE                                                0x0
#define   AUD_XFP_DRAM_1K_D__B                                              0
#define   AUD_XFP_DRAM_1K_D__W                                              16
#define   AUD_XFP_DRAM_1K_D__M                                              0xFFFF
#define   AUD_XFP_DRAM_1K_D__PRE                                            0x0

#define AUD_XFP_PRAM_4K__A                                                  0x1070000
#define AUD_XFP_PRAM_4K__W                                                  16
#define AUD_XFP_PRAM_4K__M                                                  0xFFFF
#define AUD_XFP_PRAM_4K__PRE                                                0x0
#define   AUD_XFP_PRAM_4K_D__B                                              0
#define   AUD_XFP_PRAM_4K_D__W                                              16
#define   AUD_XFP_PRAM_4K_D__M                                              0xFFFF
#define   AUD_XFP_PRAM_4K_D__PRE                                            0x0

#define AUD_XDFP_DRAM_1K__A                                                 0x1080000
#define AUD_XDFP_DRAM_1K__W                                                 16
#define AUD_XDFP_DRAM_1K__M                                                 0xFFFF
#define AUD_XDFP_DRAM_1K__PRE                                               0x0
#define   AUD_XDFP_DRAM_1K_D__B                                             0
#define   AUD_XDFP_DRAM_1K_D__W                                             16
#define   AUD_XDFP_DRAM_1K_D__M                                             0xFFFF
#define   AUD_XDFP_DRAM_1K_D__PRE                                           0x0

#define AUD_XDFP_PRAM_4K__A                                                 0x1090000
#define AUD_XDFP_PRAM_4K__W                                                 16
#define AUD_XDFP_PRAM_4K__M                                                 0xFFFF
#define AUD_XDFP_PRAM_4K__PRE                                               0x0
#define   AUD_XDFP_PRAM_4K_D__B                                             0
#define   AUD_XDFP_PRAM_4K_D__W                                             16
#define   AUD_XDFP_PRAM_4K_D__M                                             0xFFFF
#define   AUD_XDFP_PRAM_4K_D__PRE                                           0x0

#define FEC_COMM_EXEC__A                                                    0x2400000
#define FEC_COMM_EXEC__W                                                    2
#define FEC_COMM_EXEC__M                                                    0x3
#define FEC_COMM_EXEC__PRE                                                  0x0
#define   FEC_COMM_EXEC_STOP                                                0x0
#define   FEC_COMM_EXEC_ACTIVE                                              0x1
#define   FEC_COMM_EXEC_HOLD                                                0x2

#define FEC_COMM_MB__A                                                      0x2400002
#define FEC_COMM_MB__W                                                      16
#define FEC_COMM_MB__M                                                      0xFFFF
#define FEC_COMM_MB__PRE                                                    0x0
#define FEC_COMM_INT_REQ__A                                                 0x2400003
#define FEC_COMM_INT_REQ__W                                                 16
#define FEC_COMM_INT_REQ__M                                                 0xFFFF
#define FEC_COMM_INT_REQ__PRE                                               0x0
#define   FEC_COMM_INT_REQ_OC_REQ__B                                        0
#define   FEC_COMM_INT_REQ_OC_REQ__W                                        1
#define   FEC_COMM_INT_REQ_OC_REQ__M                                        0x1
#define   FEC_COMM_INT_REQ_OC_REQ__PRE                                      0x0
#define   FEC_COMM_INT_REQ_RS_REQ__B                                        1
#define   FEC_COMM_INT_REQ_RS_REQ__W                                        1
#define   FEC_COMM_INT_REQ_RS_REQ__M                                        0x2
#define   FEC_COMM_INT_REQ_RS_REQ__PRE                                      0x0
#define   FEC_COMM_INT_REQ_DI_REQ__B                                        2
#define   FEC_COMM_INT_REQ_DI_REQ__W                                        1
#define   FEC_COMM_INT_REQ_DI_REQ__M                                        0x4
#define   FEC_COMM_INT_REQ_DI_REQ__PRE                                      0x0

#define FEC_COMM_INT_STA__A                                                 0x2400005
#define FEC_COMM_INT_STA__W                                                 16
#define FEC_COMM_INT_STA__M                                                 0xFFFF
#define FEC_COMM_INT_STA__PRE                                               0x0
#define FEC_COMM_INT_MSK__A                                                 0x2400006
#define FEC_COMM_INT_MSK__W                                                 16
#define FEC_COMM_INT_MSK__M                                                 0xFFFF
#define FEC_COMM_INT_MSK__PRE                                               0x0
#define FEC_COMM_INT_STM__A                                                 0x2400007
#define FEC_COMM_INT_STM__W                                                 16
#define FEC_COMM_INT_STM__M                                                 0xFFFF
#define FEC_COMM_INT_STM__PRE                                               0x0

#define FEC_TOP_COMM_EXEC__A                                                0x2410000
#define FEC_TOP_COMM_EXEC__W                                                2
#define FEC_TOP_COMM_EXEC__M                                                0x3
#define FEC_TOP_COMM_EXEC__PRE                                              0x0
#define   FEC_TOP_COMM_EXEC_STOP                                            0x0
#define   FEC_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   FEC_TOP_COMM_EXEC_HOLD                                            0x2

#define FEC_TOP_ANNEX__A                                                    0x2410010
#define FEC_TOP_ANNEX__W                                                    2
#define FEC_TOP_ANNEX__M                                                    0x3
#define FEC_TOP_ANNEX__PRE                                                  0x0
#define   FEC_TOP_ANNEX_A                                                   0x0
#define   FEC_TOP_ANNEX_B                                                   0x1
#define   FEC_TOP_ANNEX_C                                                   0x2
#define   FEC_TOP_ANNEX_D                                                   0x3

#define FEC_DI_COMM_EXEC__A                                                 0x2420000
#define FEC_DI_COMM_EXEC__W                                                 2
#define FEC_DI_COMM_EXEC__M                                                 0x3
#define FEC_DI_COMM_EXEC__PRE                                               0x0
#define   FEC_DI_COMM_EXEC_STOP                                             0x0
#define   FEC_DI_COMM_EXEC_ACTIVE                                           0x1
#define   FEC_DI_COMM_EXEC_HOLD                                             0x2

#define FEC_DI_COMM_MB__A                                                   0x2420002
#define FEC_DI_COMM_MB__W                                                   2
#define FEC_DI_COMM_MB__M                                                   0x3
#define FEC_DI_COMM_MB__PRE                                                 0x0
#define   FEC_DI_COMM_MB_CTL__B                                             0
#define   FEC_DI_COMM_MB_CTL__W                                             1
#define   FEC_DI_COMM_MB_CTL__M                                             0x1
#define   FEC_DI_COMM_MB_CTL__PRE                                           0x0
#define     FEC_DI_COMM_MB_CTL_OFF                                          0x0
#define     FEC_DI_COMM_MB_CTL_ON                                           0x1
#define   FEC_DI_COMM_MB_OBS__B                                             1
#define   FEC_DI_COMM_MB_OBS__W                                             1
#define   FEC_DI_COMM_MB_OBS__M                                             0x2
#define   FEC_DI_COMM_MB_OBS__PRE                                           0x0
#define     FEC_DI_COMM_MB_OBS_OFF                                          0x0
#define     FEC_DI_COMM_MB_OBS_ON                                           0x2

#define FEC_DI_COMM_INT_REQ__A                                              0x2420003
#define FEC_DI_COMM_INT_REQ__W                                              1
#define FEC_DI_COMM_INT_REQ__M                                              0x1
#define FEC_DI_COMM_INT_REQ__PRE                                            0x0
#define FEC_DI_COMM_INT_STA__A                                              0x2420005
#define FEC_DI_COMM_INT_STA__W                                              2
#define FEC_DI_COMM_INT_STA__M                                              0x3
#define FEC_DI_COMM_INT_STA__PRE                                            0x0

#define   FEC_DI_COMM_INT_STA_STAT_INT__B                                   0
#define   FEC_DI_COMM_INT_STA_STAT_INT__W                                   1
#define   FEC_DI_COMM_INT_STA_STAT_INT__M                                   0x1
#define   FEC_DI_COMM_INT_STA_STAT_INT__PRE                                 0x0

#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__B                                1
#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__W                                1
#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__M                                0x2
#define   FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE                              0x0

#define FEC_DI_COMM_INT_MSK__A                                              0x2420006
#define FEC_DI_COMM_INT_MSK__W                                              2
#define FEC_DI_COMM_INT_MSK__M                                              0x3
#define FEC_DI_COMM_INT_MSK__PRE                                            0x0
#define   FEC_DI_COMM_INT_MSK_STAT_INT__B                                   0
#define   FEC_DI_COMM_INT_MSK_STAT_INT__W                                   1
#define   FEC_DI_COMM_INT_MSK_STAT_INT__M                                   0x1
#define   FEC_DI_COMM_INT_MSK_STAT_INT__PRE                                 0x0
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B                                1
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W                                1
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M                                0x2
#define   FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE                              0x0

#define FEC_DI_COMM_INT_STM__A                                              0x2420007
#define FEC_DI_COMM_INT_STM__W                                              2
#define FEC_DI_COMM_INT_STM__M                                              0x3
#define FEC_DI_COMM_INT_STM__PRE                                            0x0
#define   FEC_DI_COMM_INT_STM_STAT_INT__B                                   0
#define   FEC_DI_COMM_INT_STM_STAT_INT__W                                   1
#define   FEC_DI_COMM_INT_STM_STAT_INT__M                                   0x1
#define   FEC_DI_COMM_INT_STM_STAT_INT__PRE                                 0x0
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__B                                1
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__W                                1
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__M                                0x2
#define   FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE                              0x0

#define FEC_DI_STATUS__A                                                    0x2420010
#define FEC_DI_STATUS__W                                                    1
#define FEC_DI_STATUS__M                                                    0x1
#define FEC_DI_STATUS__PRE                                                  0x0
#define FEC_DI_MODE__A                                                      0x2420011
#define FEC_DI_MODE__W                                                      3
#define FEC_DI_MODE__M                                                      0x7
#define FEC_DI_MODE__PRE                                                    0x0

#define   FEC_DI_MODE_NO_SYNC__B                                            0
#define   FEC_DI_MODE_NO_SYNC__W                                            1
#define   FEC_DI_MODE_NO_SYNC__M                                            0x1
#define   FEC_DI_MODE_NO_SYNC__PRE                                          0x0

#define   FEC_DI_MODE_IGNORE_LOST_SYNC__B                                   1
#define   FEC_DI_MODE_IGNORE_LOST_SYNC__W                                   1
#define   FEC_DI_MODE_IGNORE_LOST_SYNC__M                                   0x2
#define   FEC_DI_MODE_IGNORE_LOST_SYNC__PRE                                 0x0

#define   FEC_DI_MODE_IGNORE_TIMEOUT__B                                     2
#define   FEC_DI_MODE_IGNORE_TIMEOUT__W                                     1
#define   FEC_DI_MODE_IGNORE_TIMEOUT__M                                     0x4
#define   FEC_DI_MODE_IGNORE_TIMEOUT__PRE                                   0x0

#define FEC_DI_CONTROL_WORD__A                                              0x2420012
#define FEC_DI_CONTROL_WORD__W                                              4
#define FEC_DI_CONTROL_WORD__M                                              0xF
#define FEC_DI_CONTROL_WORD__PRE                                            0x0

#define FEC_DI_RESTART__A                                                   0x2420013
#define FEC_DI_RESTART__W                                                   1
#define FEC_DI_RESTART__M                                                   0x1
#define FEC_DI_RESTART__PRE                                                 0x0

#define FEC_DI_TIMEOUT_LO__A                                                0x2420014
#define FEC_DI_TIMEOUT_LO__W                                                16
#define FEC_DI_TIMEOUT_LO__M                                                0xFFFF
#define FEC_DI_TIMEOUT_LO__PRE                                              0x0

#define FEC_DI_TIMEOUT_HI__A                                                0x2420015
#define FEC_DI_TIMEOUT_HI__W                                                8
#define FEC_DI_TIMEOUT_HI__M                                                0xFF
#define FEC_DI_TIMEOUT_HI__PRE                                              0xA

#define FEC_RS_COMM_EXEC__A                                                 0x2430000
#define FEC_RS_COMM_EXEC__W                                                 2
#define FEC_RS_COMM_EXEC__M                                                 0x3
#define FEC_RS_COMM_EXEC__PRE                                               0x0
#define   FEC_RS_COMM_EXEC_STOP                                             0x0
#define   FEC_RS_COMM_EXEC_ACTIVE                                           0x1
#define   FEC_RS_COMM_EXEC_HOLD                                             0x2

#define FEC_RS_COMM_MB__A                                                   0x2430002
#define FEC_RS_COMM_MB__W                                                   2
#define FEC_RS_COMM_MB__M                                                   0x3
#define FEC_RS_COMM_MB__PRE                                                 0x0
#define   FEC_RS_COMM_MB_CTL__B                                             0
#define   FEC_RS_COMM_MB_CTL__W                                             1
#define   FEC_RS_COMM_MB_CTL__M                                             0x1
#define   FEC_RS_COMM_MB_CTL__PRE                                           0x0
#define     FEC_RS_COMM_MB_CTL_OFF                                          0x0
#define     FEC_RS_COMM_MB_CTL_ON                                           0x1
#define   FEC_RS_COMM_MB_OBS__B                                             1
#define   FEC_RS_COMM_MB_OBS__W                                             1
#define   FEC_RS_COMM_MB_OBS__M                                             0x2
#define   FEC_RS_COMM_MB_OBS__PRE                                           0x0
#define     FEC_RS_COMM_MB_OBS_OFF                                          0x0
#define     FEC_RS_COMM_MB_OBS_ON                                           0x2

#define FEC_RS_COMM_INT_REQ__A                                              0x2430003
#define FEC_RS_COMM_INT_REQ__W                                              1
#define FEC_RS_COMM_INT_REQ__M                                              0x1
#define FEC_RS_COMM_INT_REQ__PRE                                            0x0
#define FEC_RS_COMM_INT_STA__A                                              0x2430005
#define FEC_RS_COMM_INT_STA__W                                              2
#define FEC_RS_COMM_INT_STA__M                                              0x3
#define FEC_RS_COMM_INT_STA__PRE                                            0x0

#define   FEC_RS_COMM_INT_STA_FAILURE_INT__B                                0
#define   FEC_RS_COMM_INT_STA_FAILURE_INT__W                                1
#define   FEC_RS_COMM_INT_STA_FAILURE_INT__M                                0x1
#define   FEC_RS_COMM_INT_STA_FAILURE_INT__PRE                              0x0

#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B                            1
#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W                            1
#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M                            0x2
#define   FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE                          0x0

#define FEC_RS_COMM_INT_MSK__A                                              0x2430006
#define FEC_RS_COMM_INT_MSK__W                                              2
#define FEC_RS_COMM_INT_MSK__M                                              0x3
#define FEC_RS_COMM_INT_MSK__PRE                                            0x0
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__B                                0
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__W                                1
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__M                                0x1
#define   FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE                              0x0
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B                            1
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W                            1
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M                            0x2
#define   FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE                          0x0

#define FEC_RS_COMM_INT_STM__A                                              0x2430007
#define FEC_RS_COMM_INT_STM__W                                              2
#define FEC_RS_COMM_INT_STM__M                                              0x3
#define FEC_RS_COMM_INT_STM__PRE                                            0x0
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__B                                0
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__W                                1
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__M                                0x1
#define   FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE                              0x0
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B                            1
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W                            1
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M                            0x2
#define   FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE                          0x0

#define FEC_RS_STATUS__A                                                    0x2430010
#define FEC_RS_STATUS__W                                                    1
#define FEC_RS_STATUS__M                                                    0x1
#define FEC_RS_STATUS__PRE                                                  0x0
#define FEC_RS_MODE__A                                                      0x2430011
#define FEC_RS_MODE__W                                                      1
#define FEC_RS_MODE__M                                                      0x1
#define FEC_RS_MODE__PRE                                                    0x0

#define   FEC_RS_MODE_BYPASS__B                                             0
#define   FEC_RS_MODE_BYPASS__W                                             1
#define   FEC_RS_MODE_BYPASS__M                                             0x1
#define   FEC_RS_MODE_BYPASS__PRE                                           0x0

#define FEC_RS_MEASUREMENT_PERIOD__A                                        0x2430012
#define FEC_RS_MEASUREMENT_PERIOD__W                                        16
#define FEC_RS_MEASUREMENT_PERIOD__M                                        0xFFFF
#define FEC_RS_MEASUREMENT_PERIOD__PRE                                      0x1171

#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__B                               0
#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__W                               16
#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__M                               0xFFFF
#define   FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE                             0x1171

#define FEC_RS_MEASUREMENT_PRESCALE__A                                      0x2430013
#define FEC_RS_MEASUREMENT_PRESCALE__W                                      16
#define FEC_RS_MEASUREMENT_PRESCALE__M                                      0xFFFF
#define FEC_RS_MEASUREMENT_PRESCALE__PRE                                    0x1

#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B                           0
#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W                           16
#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M                           0xFFFF
#define   FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE                         0x1

#define FEC_RS_NR_BIT_ERRORS__A                                             0x2430014
#define FEC_RS_NR_BIT_ERRORS__W                                             16
#define FEC_RS_NR_BIT_ERRORS__M                                             0xFFFF
#define FEC_RS_NR_BIT_ERRORS__PRE                                           0xFFFF

#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B                                0
#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W                                12
#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M                                0xFFF
#define   FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE                              0xFFF

#define   FEC_RS_NR_BIT_ERRORS_EXP__B                                       12
#define   FEC_RS_NR_BIT_ERRORS_EXP__W                                       4
#define   FEC_RS_NR_BIT_ERRORS_EXP__M                                       0xF000
#define   FEC_RS_NR_BIT_ERRORS_EXP__PRE                                     0xF000

#define FEC_RS_NR_SYMBOL_ERRORS__A                                          0x2430015
#define FEC_RS_NR_SYMBOL_ERRORS__W                                          16
#define FEC_RS_NR_SYMBOL_ERRORS__M                                          0xFFFF
#define FEC_RS_NR_SYMBOL_ERRORS__PRE                                        0xFFFF

#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B                             0
#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W                             12
#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M                             0xFFF
#define   FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                           0xFFF

#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__B                                    12
#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__W                                    4
#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__M                                    0xF000
#define   FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE                                  0xF000

#define FEC_RS_NR_PACKET_ERRORS__A                                          0x2430016
#define FEC_RS_NR_PACKET_ERRORS__W                                          16
#define FEC_RS_NR_PACKET_ERRORS__M                                          0xFFFF
#define FEC_RS_NR_PACKET_ERRORS__PRE                                        0xFFFF

#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B                             0
#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W                             12
#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M                             0xFFF
#define   FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE                           0xFFF

#define   FEC_RS_NR_PACKET_ERRORS_EXP__B                                    12
#define   FEC_RS_NR_PACKET_ERRORS_EXP__W                                    4
#define   FEC_RS_NR_PACKET_ERRORS_EXP__M                                    0xF000
#define   FEC_RS_NR_PACKET_ERRORS_EXP__PRE                                  0xF000

#define FEC_RS_NR_FAILURES__A                                               0x2430017
#define FEC_RS_NR_FAILURES__W                                               16
#define FEC_RS_NR_FAILURES__M                                               0xFFFF
#define FEC_RS_NR_FAILURES__PRE                                             0x0

#define   FEC_RS_NR_FAILURES_FIXED_MANT__B                                  0
#define   FEC_RS_NR_FAILURES_FIXED_MANT__W                                  12
#define   FEC_RS_NR_FAILURES_FIXED_MANT__M                                  0xFFF
#define   FEC_RS_NR_FAILURES_FIXED_MANT__PRE                                0x0

#define   FEC_RS_NR_FAILURES_EXP__B                                         12
#define   FEC_RS_NR_FAILURES_EXP__W                                         4
#define   FEC_RS_NR_FAILURES_EXP__M                                         0xF000
#define   FEC_RS_NR_FAILURES_EXP__PRE                                       0x0

#define FEC_OC_COMM_EXEC__A                                                 0x2440000
#define FEC_OC_COMM_EXEC__W                                                 2
#define FEC_OC_COMM_EXEC__M                                                 0x3
#define FEC_OC_COMM_EXEC__PRE                                               0x0
#define   FEC_OC_COMM_EXEC_STOP                                             0x0
#define   FEC_OC_COMM_EXEC_ACTIVE                                           0x1
#define   FEC_OC_COMM_EXEC_HOLD                                             0x2

#define FEC_OC_COMM_MB__A                                                   0x2440002
#define FEC_OC_COMM_MB__W                                                   2
#define FEC_OC_COMM_MB__M                                                   0x3
#define FEC_OC_COMM_MB__PRE                                                 0x0
#define   FEC_OC_COMM_MB_CTL__B                                             0
#define   FEC_OC_COMM_MB_CTL__W                                             1
#define   FEC_OC_COMM_MB_CTL__M                                             0x1
#define   FEC_OC_COMM_MB_CTL__PRE                                           0x0
#define     FEC_OC_COMM_MB_CTL_OFF                                          0x0
#define     FEC_OC_COMM_MB_CTL_ON                                           0x1
#define   FEC_OC_COMM_MB_OBS__B                                             1
#define   FEC_OC_COMM_MB_OBS__W                                             1
#define   FEC_OC_COMM_MB_OBS__M                                             0x2
#define   FEC_OC_COMM_MB_OBS__PRE                                           0x0
#define     FEC_OC_COMM_MB_OBS_OFF                                          0x0
#define     FEC_OC_COMM_MB_OBS_ON                                           0x2

#define FEC_OC_COMM_INT_REQ__A                                              0x2440003
#define FEC_OC_COMM_INT_REQ__W                                              1
#define FEC_OC_COMM_INT_REQ__M                                              0x1
#define FEC_OC_COMM_INT_REQ__PRE                                            0x0
#define FEC_OC_COMM_INT_STA__A                                              0x2440005
#define FEC_OC_COMM_INT_STA__W                                              8
#define FEC_OC_COMM_INT_STA__M                                              0xFF
#define FEC_OC_COMM_INT_STA__PRE                                            0x0

#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B                               0
#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W                               1
#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M                               0x1
#define   FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE                             0x0

#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B                               1
#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W                               1
#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M                               0x2
#define   FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE                             0x0

#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__B                               2
#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__W                               1
#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__M                               0x4
#define   FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE                             0x0

#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__B                                3
#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__W                                1
#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__M                                0x8
#define   FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE                              0x0

#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B                              4
#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W                              1
#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M                              0x10
#define   FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE                            0x0

#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B                             5
#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W                             1
#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M                             0x20
#define   FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE                           0x0

#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B                                6
#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W                                1
#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M                                0x40
#define   FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE                              0x0

#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__B                               7
#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__W                               1
#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__M                               0x80
#define   FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE                             0x0

#define FEC_OC_COMM_INT_MSK__A                                              0x2440006
#define FEC_OC_COMM_INT_MSK__W                                              8
#define FEC_OC_COMM_INT_MSK__M                                              0xFF
#define FEC_OC_COMM_INT_MSK__PRE                                            0x0
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B                               0
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M                               0x1
#define   FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B                               1
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M                               0x2
#define   FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B                               2
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M                               0x4
#define   FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B                                3
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W                                1
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M                                0x8
#define   FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B                              4
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W                              1
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M                              0x10
#define   FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE                            0x0
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B                             5
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W                             1
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M                             0x20
#define   FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE                           0x0
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B                                6
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W                                1
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M                                0x40
#define   FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B                               7
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W                               1
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M                               0x80
#define   FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE                             0x0

#define FEC_OC_COMM_INT_STM__A                                              0x2440007
#define FEC_OC_COMM_INT_STM__W                                              8
#define FEC_OC_COMM_INT_STM__M                                              0xFF
#define FEC_OC_COMM_INT_STM__PRE                                            0x0
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B                               0
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M                               0x1
#define   FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B                               1
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M                               0x2
#define   FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B                               2
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M                               0x4
#define   FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE                             0x0
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B                                3
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W                                1
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M                                0x8
#define   FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B                              4
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W                              1
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M                              0x10
#define   FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE                            0x0
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B                             5
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W                             1
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M                             0x20
#define   FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE                           0x0
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B                                6
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W                                1
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M                                0x40
#define   FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE                              0x0
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B                               7
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W                               1
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M                               0x80
#define   FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE                             0x0

#define FEC_OC_STATUS__A                                                    0x2440010
#define FEC_OC_STATUS__W                                                    5
#define FEC_OC_STATUS__M                                                    0x1F
#define FEC_OC_STATUS__PRE                                                  0x0

#define   FEC_OC_STATUS_DPR_STATUS__B                                       0
#define   FEC_OC_STATUS_DPR_STATUS__W                                       1
#define   FEC_OC_STATUS_DPR_STATUS__M                                       0x1
#define   FEC_OC_STATUS_DPR_STATUS__PRE                                     0x0

#define   FEC_OC_STATUS_SNC_STATUS__B                                       1
#define   FEC_OC_STATUS_SNC_STATUS__W                                       2
#define   FEC_OC_STATUS_SNC_STATUS__M                                       0x6
#define   FEC_OC_STATUS_SNC_STATUS__PRE                                     0x0

#define   FEC_OC_STATUS_FIFO_FULL__B                                        3
#define   FEC_OC_STATUS_FIFO_FULL__W                                        1
#define   FEC_OC_STATUS_FIFO_FULL__M                                        0x8
#define   FEC_OC_STATUS_FIFO_FULL__PRE                                      0x0

#define   FEC_OC_STATUS_FIFO_EMPTY__B                                       4
#define   FEC_OC_STATUS_FIFO_EMPTY__W                                       1
#define   FEC_OC_STATUS_FIFO_EMPTY__M                                       0x10
#define   FEC_OC_STATUS_FIFO_EMPTY__PRE                                     0x0

#define FEC_OC_MODE__A                                                      0x2440011
#define FEC_OC_MODE__W                                                      4
#define FEC_OC_MODE__M                                                      0xF
#define FEC_OC_MODE__PRE                                                    0x0

#define   FEC_OC_MODE_PARITY__B                                             0
#define   FEC_OC_MODE_PARITY__W                                             1
#define   FEC_OC_MODE_PARITY__M                                             0x1
#define   FEC_OC_MODE_PARITY__PRE                                           0x0

#define   FEC_OC_MODE_TRANSPARENT__B                                        1
#define   FEC_OC_MODE_TRANSPARENT__W                                        1
#define   FEC_OC_MODE_TRANSPARENT__M                                        0x2
#define   FEC_OC_MODE_TRANSPARENT__PRE                                      0x0

#define   FEC_OC_MODE_CLEAR__B                                              2
#define   FEC_OC_MODE_CLEAR__W                                              1
#define   FEC_OC_MODE_CLEAR__M                                              0x4
#define   FEC_OC_MODE_CLEAR__PRE                                            0x0

#define   FEC_OC_MODE_RETAIN_FRAMING__B                                     3
#define   FEC_OC_MODE_RETAIN_FRAMING__W                                     1
#define   FEC_OC_MODE_RETAIN_FRAMING__M                                     0x8
#define   FEC_OC_MODE_RETAIN_FRAMING__PRE                                   0x0

#define FEC_OC_DPR_MODE__A                                                  0x2440012
#define FEC_OC_DPR_MODE__W                                                  2
#define FEC_OC_DPR_MODE__M                                                  0x3
#define FEC_OC_DPR_MODE__PRE                                                0x0

#define   FEC_OC_DPR_MODE_ERR_DISABLE__B                                    0
#define   FEC_OC_DPR_MODE_ERR_DISABLE__W                                    1
#define   FEC_OC_DPR_MODE_ERR_DISABLE__M                                    0x1
#define   FEC_OC_DPR_MODE_ERR_DISABLE__PRE                                  0x0

#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__B                                  1
#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__W                                  1
#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__M                                  0x2
#define   FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE                                0x0

#define FEC_OC_DPR_UNLOCK__A                                                0x2440013
#define FEC_OC_DPR_UNLOCK__W                                                1
#define FEC_OC_DPR_UNLOCK__M                                                0x1
#define FEC_OC_DPR_UNLOCK__PRE                                              0x0
#define FEC_OC_DTO_MODE__A                                                  0x2440014
#define FEC_OC_DTO_MODE__W                                                  3
#define FEC_OC_DTO_MODE__M                                                  0x7
#define FEC_OC_DTO_MODE__PRE                                                0x0

#define   FEC_OC_DTO_MODE_DYNAMIC__B                                        0
#define   FEC_OC_DTO_MODE_DYNAMIC__W                                        1
#define   FEC_OC_DTO_MODE_DYNAMIC__M                                        0x1
#define   FEC_OC_DTO_MODE_DYNAMIC__PRE                                      0x0

#define   FEC_OC_DTO_MODE_DUTY_CYCLE__B                                     1
#define   FEC_OC_DTO_MODE_DUTY_CYCLE__W                                     1
#define   FEC_OC_DTO_MODE_DUTY_CYCLE__M                                     0x2
#define   FEC_OC_DTO_MODE_DUTY_CYCLE__PRE                                   0x0

#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__B                                  2
#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__W                                  1
#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__M                                  0x4
#define   FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE                                0x0

#define FEC_OC_DTO_PERIOD__A                                                0x2440015
#define FEC_OC_DTO_PERIOD__W                                                8
#define FEC_OC_DTO_PERIOD__M                                                0xFF
#define FEC_OC_DTO_PERIOD__PRE                                              0x0
#define FEC_OC_DTO_RATE_LO__A                                               0x2440016
#define FEC_OC_DTO_RATE_LO__W                                               16
#define FEC_OC_DTO_RATE_LO__M                                               0xFFFF
#define FEC_OC_DTO_RATE_LO__PRE                                             0x0

#define   FEC_OC_DTO_RATE_LO_RATE_LO__B                                     0
#define   FEC_OC_DTO_RATE_LO_RATE_LO__W                                     16
#define   FEC_OC_DTO_RATE_LO_RATE_LO__M                                     0xFFFF
#define   FEC_OC_DTO_RATE_LO_RATE_LO__PRE                                   0x0

#define FEC_OC_DTO_RATE_HI__A                                               0x2440017
#define FEC_OC_DTO_RATE_HI__W                                               10
#define FEC_OC_DTO_RATE_HI__M                                               0x3FF
#define FEC_OC_DTO_RATE_HI__PRE                                             0xC0

#define   FEC_OC_DTO_RATE_HI_RATE_HI__B                                     0
#define   FEC_OC_DTO_RATE_HI_RATE_HI__W                                     10
#define   FEC_OC_DTO_RATE_HI_RATE_HI__M                                     0x3FF
#define   FEC_OC_DTO_RATE_HI_RATE_HI__PRE                                   0xC0

#define FEC_OC_DTO_BURST_LEN__A                                             0x2440018
#define FEC_OC_DTO_BURST_LEN__W                                             8
#define FEC_OC_DTO_BURST_LEN__M                                             0xFF
#define FEC_OC_DTO_BURST_LEN__PRE                                           0xBC

#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__B                                 0
#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__W                                 8
#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__M                                 0xFF
#define   FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE                               0xBC

#define FEC_OC_FCT_MODE__A                                                  0x244001A
#define FEC_OC_FCT_MODE__W                                                  2
#define FEC_OC_FCT_MODE__M                                                  0x3
#define FEC_OC_FCT_MODE__PRE                                                0x0

#define   FEC_OC_FCT_MODE_RAT_ENA__B                                        0
#define   FEC_OC_FCT_MODE_RAT_ENA__W                                        1
#define   FEC_OC_FCT_MODE_RAT_ENA__M                                        0x1
#define   FEC_OC_FCT_MODE_RAT_ENA__PRE                                      0x0

#define   FEC_OC_FCT_MODE_VIRT_ENA__B                                       1
#define   FEC_OC_FCT_MODE_VIRT_ENA__W                                       1
#define   FEC_OC_FCT_MODE_VIRT_ENA__M                                       0x2
#define   FEC_OC_FCT_MODE_VIRT_ENA__PRE                                     0x0

#define FEC_OC_FCT_USAGE__A                                                 0x244001B
#define FEC_OC_FCT_USAGE__W                                                 3
#define FEC_OC_FCT_USAGE__M                                                 0x7
#define FEC_OC_FCT_USAGE__PRE                                               0x2

#define   FEC_OC_FCT_USAGE_USAGE__B                                         0
#define   FEC_OC_FCT_USAGE_USAGE__W                                         3
#define   FEC_OC_FCT_USAGE_USAGE__M                                         0x7
#define   FEC_OC_FCT_USAGE_USAGE__PRE                                       0x2

#define FEC_OC_FCT_OCCUPATION__A                                            0x244001C
#define FEC_OC_FCT_OCCUPATION__W                                            12
#define FEC_OC_FCT_OCCUPATION__M                                            0xFFF
#define FEC_OC_FCT_OCCUPATION__PRE                                          0x0

#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__B                               0
#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__W                               12
#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__M                               0xFFF
#define   FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE                             0x0

#define FEC_OC_TMD_MODE__A                                                  0x244001E
#define FEC_OC_TMD_MODE__W                                                  3
#define FEC_OC_TMD_MODE__M                                                  0x7
#define FEC_OC_TMD_MODE__PRE                                                0x4

#define   FEC_OC_TMD_MODE_MODE__B                                           0
#define   FEC_OC_TMD_MODE_MODE__W                                           3
#define   FEC_OC_TMD_MODE_MODE__M                                           0x7
#define   FEC_OC_TMD_MODE_MODE__PRE                                         0x4

#define FEC_OC_TMD_COUNT__A                                                 0x244001F
#define FEC_OC_TMD_COUNT__W                                                 10
#define FEC_OC_TMD_COUNT__M                                                 0x3FF
#define FEC_OC_TMD_COUNT__PRE                                               0x1F4

#define   FEC_OC_TMD_COUNT_COUNT__B                                         0
#define   FEC_OC_TMD_COUNT_COUNT__W                                         10
#define   FEC_OC_TMD_COUNT_COUNT__M                                         0x3FF
#define   FEC_OC_TMD_COUNT_COUNT__PRE                                       0x1F4

#define FEC_OC_TMD_HI_MARGIN__A                                             0x2440020
#define FEC_OC_TMD_HI_MARGIN__W                                             11
#define FEC_OC_TMD_HI_MARGIN__M                                             0x7FF
#define FEC_OC_TMD_HI_MARGIN__PRE                                           0x200

#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B                                 0
#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W                                 11
#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M                                 0x7FF
#define   FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE                               0x200

#define FEC_OC_TMD_LO_MARGIN__A                                             0x2440021
#define FEC_OC_TMD_LO_MARGIN__W                                             11
#define FEC_OC_TMD_LO_MARGIN__M                                             0x7FF
#define FEC_OC_TMD_LO_MARGIN__PRE                                           0x100

#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B                                 0
#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W                                 11
#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M                                 0x7FF
#define   FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE                               0x100

#define FEC_OC_TMD_CTL_UPD_RATE__A                                          0x2440022
#define FEC_OC_TMD_CTL_UPD_RATE__W                                          4
#define FEC_OC_TMD_CTL_UPD_RATE__M                                          0xF
#define FEC_OC_TMD_CTL_UPD_RATE__PRE                                        0x1

#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__B                                   0
#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__W                                   4
#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__M                                   0xF
#define   FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE                                 0x1

#define FEC_OC_TMD_INT_UPD_RATE__A                                          0x2440023
#define FEC_OC_TMD_INT_UPD_RATE__W                                          4
#define FEC_OC_TMD_INT_UPD_RATE__M                                          0xF
#define FEC_OC_TMD_INT_UPD_RATE__PRE                                        0x4

#define   FEC_OC_TMD_INT_UPD_RATE_RATE__B                                   0
#define   FEC_OC_TMD_INT_UPD_RATE_RATE__W                                   4
#define   FEC_OC_TMD_INT_UPD_RATE_RATE__M                                   0xF
#define   FEC_OC_TMD_INT_UPD_RATE_RATE__PRE                                 0x4

#define FEC_OC_AVR_PARM_A__A                                                0x2440026
#define FEC_OC_AVR_PARM_A__W                                                4
#define FEC_OC_AVR_PARM_A__M                                                0xF
#define FEC_OC_AVR_PARM_A__PRE                                              0x6

#define   FEC_OC_AVR_PARM_A_PARM__B                                         0
#define   FEC_OC_AVR_PARM_A_PARM__W                                         4
#define   FEC_OC_AVR_PARM_A_PARM__M                                         0xF
#define   FEC_OC_AVR_PARM_A_PARM__PRE                                       0x6

#define FEC_OC_AVR_PARM_B__A                                                0x2440027
#define FEC_OC_AVR_PARM_B__W                                                4
#define FEC_OC_AVR_PARM_B__M                                                0xF
#define FEC_OC_AVR_PARM_B__PRE                                              0x4

#define   FEC_OC_AVR_PARM_B_PARM__B                                         0
#define   FEC_OC_AVR_PARM_B_PARM__W                                         4
#define   FEC_OC_AVR_PARM_B_PARM__M                                         0xF
#define   FEC_OC_AVR_PARM_B_PARM__PRE                                       0x4

#define FEC_OC_AVR_AVG_LO__A                                                0x2440028
#define FEC_OC_AVR_AVG_LO__W                                                16
#define FEC_OC_AVR_AVG_LO__M                                                0xFFFF
#define FEC_OC_AVR_AVG_LO__PRE                                              0x0

#define   FEC_OC_AVR_AVG_LO_AVG_LO__B                                       0
#define   FEC_OC_AVR_AVG_LO_AVG_LO__W                                       16
#define   FEC_OC_AVR_AVG_LO_AVG_LO__M                                       0xFFFF
#define   FEC_OC_AVR_AVG_LO_AVG_LO__PRE                                     0x0

#define FEC_OC_AVR_AVG_HI__A                                                0x2440029
#define FEC_OC_AVR_AVG_HI__W                                                6
#define FEC_OC_AVR_AVG_HI__M                                                0x3F
#define FEC_OC_AVR_AVG_HI__PRE                                              0x0

#define   FEC_OC_AVR_AVG_HI_AVG_HI__B                                       0
#define   FEC_OC_AVR_AVG_HI_AVG_HI__W                                       6
#define   FEC_OC_AVR_AVG_HI_AVG_HI__M                                       0x3F
#define   FEC_OC_AVR_AVG_HI_AVG_HI__PRE                                     0x0

#define FEC_OC_RCN_MODE__A                                                  0x244002C
#define FEC_OC_RCN_MODE__W                                                  5
#define FEC_OC_RCN_MODE__M                                                  0x1F
#define FEC_OC_RCN_MODE__PRE                                                0x1F

#define   FEC_OC_RCN_MODE_MODE__B                                           0
#define   FEC_OC_RCN_MODE_MODE__W                                           5
#define   FEC_OC_RCN_MODE_MODE__M                                           0x1F
#define   FEC_OC_RCN_MODE_MODE__PRE                                         0x1F

#define FEC_OC_RCN_OCC_SETTLE__A                                            0x244002D
#define FEC_OC_RCN_OCC_SETTLE__W                                            11
#define FEC_OC_RCN_OCC_SETTLE__M                                            0x7FF
#define FEC_OC_RCN_OCC_SETTLE__PRE                                          0x180

#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__B                                    0
#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__W                                    11
#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__M                                    0x7FF
#define   FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE                                  0x180

#define FEC_OC_RCN_GAIN__A                                                  0x244002E
#define FEC_OC_RCN_GAIN__W                                                  4
#define FEC_OC_RCN_GAIN__M                                                  0xF
#define FEC_OC_RCN_GAIN__PRE                                                0xC

#define   FEC_OC_RCN_GAIN_GAIN__B                                           0
#define   FEC_OC_RCN_GAIN_GAIN__W                                           4
#define   FEC_OC_RCN_GAIN_GAIN__M                                           0xF
#define   FEC_OC_RCN_GAIN_GAIN__PRE                                         0xC

#define FEC_OC_RCN_CTL_RATE_LO__A                                           0x2440030
#define FEC_OC_RCN_CTL_RATE_LO__W                                           16
#define FEC_OC_RCN_CTL_RATE_LO__M                                           0xFFFF
#define FEC_OC_RCN_CTL_RATE_LO__PRE                                         0x0

#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B                                  0
#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W                                  16
#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M                                  0xFFFF
#define   FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE                                0x0

#define FEC_OC_RCN_CTL_RATE_HI__A                                           0x2440031
#define FEC_OC_RCN_CTL_RATE_HI__W                                           8
#define FEC_OC_RCN_CTL_RATE_HI__M                                           0xFF
#define FEC_OC_RCN_CTL_RATE_HI__PRE                                         0xC0

#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B                                  0
#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W                                  8
#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M                                  0xFF
#define   FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE                                0xC0

#define FEC_OC_RCN_CTL_STEP_LO__A                                           0x2440032
#define FEC_OC_RCN_CTL_STEP_LO__W                                           16
#define FEC_OC_RCN_CTL_STEP_LO__M                                           0xFFFF
#define FEC_OC_RCN_CTL_STEP_LO__PRE                                         0x0

#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B                                  0
#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W                                  16
#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M                                  0xFFFF
#define   FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE                                0x0

#define FEC_OC_RCN_CTL_STEP_HI__A                                           0x2440033
#define FEC_OC_RCN_CTL_STEP_HI__W                                           8
#define FEC_OC_RCN_CTL_STEP_HI__M                                           0xFF
#define FEC_OC_RCN_CTL_STEP_HI__PRE                                         0x8

#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B                                  0
#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W                                  8
#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M                                  0xFF
#define   FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE                                0x8

#define FEC_OC_RCN_DTO_OFS_LO__A                                            0x2440034
#define FEC_OC_RCN_DTO_OFS_LO__W                                            16
#define FEC_OC_RCN_DTO_OFS_LO__M                                            0xFFFF
#define FEC_OC_RCN_DTO_OFS_LO__PRE                                          0x0

#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B                                   0
#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W                                   16
#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M                                   0xFFFF
#define   FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE                                 0x0

#define FEC_OC_RCN_DTO_OFS_HI__A                                            0x2440035
#define FEC_OC_RCN_DTO_OFS_HI__W                                            8
#define FEC_OC_RCN_DTO_OFS_HI__M                                            0xFF
#define FEC_OC_RCN_DTO_OFS_HI__PRE                                          0x0

#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B                                   0
#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W                                   8
#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M                                   0xFF
#define   FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE                                 0x0

#define FEC_OC_RCN_DTO_RATE_LO__A                                           0x2440036
#define FEC_OC_RCN_DTO_RATE_LO__W                                           16
#define FEC_OC_RCN_DTO_RATE_LO__M                                           0xFFFF
#define FEC_OC_RCN_DTO_RATE_LO__PRE                                         0x0

#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B                                  0
#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W                                  16
#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M                                  0xFFFF
#define   FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE                                0x0

#define FEC_OC_RCN_DTO_RATE_HI__A                                           0x2440037
#define FEC_OC_RCN_DTO_RATE_HI__W                                           8
#define FEC_OC_RCN_DTO_RATE_HI__M                                           0xFF
#define FEC_OC_RCN_DTO_RATE_HI__PRE                                         0x0

#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B                                  0
#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W                                  8
#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M                                  0xFF
#define   FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE                                0x0

#define FEC_OC_RCN_RATE_CLIP_LO__A                                          0x2440038
#define FEC_OC_RCN_RATE_CLIP_LO__W                                          16
#define FEC_OC_RCN_RATE_CLIP_LO__M                                          0xFFFF
#define FEC_OC_RCN_RATE_CLIP_LO__PRE                                        0x0

#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B                                0
#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W                                16
#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M                                0xFFFF
#define   FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE                              0x0

#define FEC_OC_RCN_RATE_CLIP_HI__A                                          0x2440039
#define FEC_OC_RCN_RATE_CLIP_HI__W                                          8
#define FEC_OC_RCN_RATE_CLIP_HI__M                                          0xFF
#define FEC_OC_RCN_RATE_CLIP_HI__PRE                                        0xF0

#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B                                0
#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W                                8
#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M                                0xFF
#define   FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE                              0xF0

#define FEC_OC_RCN_DYN_RATE_LO__A                                           0x244003A
#define FEC_OC_RCN_DYN_RATE_LO__W                                           16
#define FEC_OC_RCN_DYN_RATE_LO__M                                           0xFFFF
#define FEC_OC_RCN_DYN_RATE_LO__PRE                                         0x0

#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B                                 0
#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W                                 16
#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M                                 0xFFFF
#define   FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE                               0x0

#define FEC_OC_RCN_DYN_RATE_HI__A                                           0x244003B
#define FEC_OC_RCN_DYN_RATE_HI__W                                           8
#define FEC_OC_RCN_DYN_RATE_HI__M                                           0xFF
#define FEC_OC_RCN_DYN_RATE_HI__PRE                                         0x0

#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B                                 0
#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W                                 8
#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M                                 0xFF
#define   FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE                               0x0

#define FEC_OC_SNC_MODE__A                                                  0x2440040
#define FEC_OC_SNC_MODE__W                                                  4
#define FEC_OC_SNC_MODE__M                                                  0xF
#define FEC_OC_SNC_MODE__PRE                                                0x0

#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__B                                  0
#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__W                                  1
#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__M                                  0x1
#define   FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE                                0x0

#define   FEC_OC_SNC_MODE_ERROR_CTL__B                                      1
#define   FEC_OC_SNC_MODE_ERROR_CTL__W                                      2
#define   FEC_OC_SNC_MODE_ERROR_CTL__M                                      0x6
#define   FEC_OC_SNC_MODE_ERROR_CTL__PRE                                    0x0

#define   FEC_OC_SNC_MODE_CORR_DISABLE__B                                   3
#define   FEC_OC_SNC_MODE_CORR_DISABLE__W                                   1
#define   FEC_OC_SNC_MODE_CORR_DISABLE__M                                   0x8
#define   FEC_OC_SNC_MODE_CORR_DISABLE__PRE                                 0x0

#define FEC_OC_SNC_LWM__A                                                   0x2440041
#define FEC_OC_SNC_LWM__W                                                   4
#define FEC_OC_SNC_LWM__M                                                   0xF
#define FEC_OC_SNC_LWM__PRE                                                 0x3

#define   FEC_OC_SNC_LWM_MARK__B                                            0
#define   FEC_OC_SNC_LWM_MARK__W                                            4
#define   FEC_OC_SNC_LWM_MARK__M                                            0xF
#define   FEC_OC_SNC_LWM_MARK__PRE                                          0x3

#define FEC_OC_SNC_HWM__A                                                   0x2440042
#define FEC_OC_SNC_HWM__W                                                   4
#define FEC_OC_SNC_HWM__M                                                   0xF
#define FEC_OC_SNC_HWM__PRE                                                 0x5

#define   FEC_OC_SNC_HWM_MARK__B                                            0
#define   FEC_OC_SNC_HWM_MARK__W                                            4
#define   FEC_OC_SNC_HWM_MARK__M                                            0xF
#define   FEC_OC_SNC_HWM_MARK__PRE                                          0x5

#define FEC_OC_SNC_UNLOCK__A                                                0x2440043
#define FEC_OC_SNC_UNLOCK__W                                                1
#define FEC_OC_SNC_UNLOCK__M                                                0x1
#define FEC_OC_SNC_UNLOCK__PRE                                              0x0

#define   FEC_OC_SNC_UNLOCK_RESTART__B                                      0
#define   FEC_OC_SNC_UNLOCK_RESTART__W                                      1
#define   FEC_OC_SNC_UNLOCK_RESTART__M                                      0x1
#define   FEC_OC_SNC_UNLOCK_RESTART__PRE                                    0x0

#define FEC_OC_SNC_LOCK_COUNT__A                                            0x2440044
#define FEC_OC_SNC_LOCK_COUNT__W                                            12
#define FEC_OC_SNC_LOCK_COUNT__M                                            0xFFF
#define FEC_OC_SNC_LOCK_COUNT__PRE                                          0x0

#define   FEC_OC_SNC_LOCK_COUNT_COUNT__B                                    0
#define   FEC_OC_SNC_LOCK_COUNT_COUNT__W                                    12
#define   FEC_OC_SNC_LOCK_COUNT_COUNT__M                                    0xFFF
#define   FEC_OC_SNC_LOCK_COUNT_COUNT__PRE                                  0x0

#define FEC_OC_SNC_FAIL_COUNT__A                                            0x2440045
#define FEC_OC_SNC_FAIL_COUNT__W                                            12
#define FEC_OC_SNC_FAIL_COUNT__M                                            0xFFF
#define FEC_OC_SNC_FAIL_COUNT__PRE                                          0x0

#define   FEC_OC_SNC_FAIL_COUNT_COUNT__B                                    0
#define   FEC_OC_SNC_FAIL_COUNT_COUNT__W                                    12
#define   FEC_OC_SNC_FAIL_COUNT_COUNT__M                                    0xFFF
#define   FEC_OC_SNC_FAIL_COUNT_COUNT__PRE                                  0x0

#define FEC_OC_SNC_FAIL_PERIOD__A                                           0x2440046
#define FEC_OC_SNC_FAIL_PERIOD__W                                           16
#define FEC_OC_SNC_FAIL_PERIOD__M                                           0xFFFF
#define FEC_OC_SNC_FAIL_PERIOD__PRE                                         0x1171

#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__B                                  0
#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__W                                  16
#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__M                                  0xFFFF
#define   FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE                                0x1171

#define FEC_OC_EMS_MODE__A                                                  0x2440047
#define FEC_OC_EMS_MODE__W                                                  2
#define FEC_OC_EMS_MODE__M                                                  0x3
#define FEC_OC_EMS_MODE__PRE                                                0x0

#define   FEC_OC_EMS_MODE_MODE__B                                           0
#define   FEC_OC_EMS_MODE_MODE__W                                           2
#define   FEC_OC_EMS_MODE_MODE__M                                           0x3
#define   FEC_OC_EMS_MODE_MODE__PRE                                         0x0

#define FEC_OC_IPR_MODE__A                                                  0x2440048
#define FEC_OC_IPR_MODE__W                                                  12
#define FEC_OC_IPR_MODE__M                                                  0xFFF
#define FEC_OC_IPR_MODE__PRE                                                0x0

#define   FEC_OC_IPR_MODE_SERIAL__B                                         0
#define   FEC_OC_IPR_MODE_SERIAL__W                                         1
#define   FEC_OC_IPR_MODE_SERIAL__M                                         0x1
#define   FEC_OC_IPR_MODE_SERIAL__PRE                                       0x0

#define   FEC_OC_IPR_MODE_REVERSE_ORDER__B                                  1
#define   FEC_OC_IPR_MODE_REVERSE_ORDER__W                                  1
#define   FEC_OC_IPR_MODE_REVERSE_ORDER__M                                  0x2
#define   FEC_OC_IPR_MODE_REVERSE_ORDER__PRE                                0x0

#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B                               2
#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W                               1
#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M                               0x4
#define   FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE                             0x0

#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__B                                   3
#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__W                                   1
#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__M                                   0x8
#define   FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__B                                   4
#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__W                                   1
#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__M                                   0x10
#define   FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__B                                   5
#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__W                                   1
#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__M                                   0x20
#define   FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MD_DIS_PAR__B                                     6
#define   FEC_OC_IPR_MODE_MD_DIS_PAR__W                                     1
#define   FEC_OC_IPR_MODE_MD_DIS_PAR__M                                     0x40
#define   FEC_OC_IPR_MODE_MD_DIS_PAR__PRE                                   0x0

#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__B                                   7
#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__W                                   1
#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__M                                   0x80
#define   FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__B                                   8
#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__W                                   1
#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__M                                   0x100
#define   FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__B                                   9
#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__W                                   1
#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__M                                   0x200
#define   FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE                                 0x0

#define   FEC_OC_IPR_MODE_MD_DIS_ERR__B                                     10
#define   FEC_OC_IPR_MODE_MD_DIS_ERR__W                                     1
#define   FEC_OC_IPR_MODE_MD_DIS_ERR__M                                     0x400
#define   FEC_OC_IPR_MODE_MD_DIS_ERR__PRE                                   0x0

#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B                                  11
#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W                                  1
#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M                                  0x800
#define   FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE                                0x0

#define FEC_OC_IPR_INVERT__A                                                0x2440049
#define FEC_OC_IPR_INVERT__W                                                12
#define FEC_OC_IPR_INVERT__M                                                0xFFF
#define FEC_OC_IPR_INVERT__PRE                                              0x0

#define   FEC_OC_IPR_INVERT_MD0__B                                          0
#define   FEC_OC_IPR_INVERT_MD0__W                                          1
#define   FEC_OC_IPR_INVERT_MD0__M                                          0x1
#define   FEC_OC_IPR_INVERT_MD0__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD1__B                                          1
#define   FEC_OC_IPR_INVERT_MD1__W                                          1
#define   FEC_OC_IPR_INVERT_MD1__M                                          0x2
#define   FEC_OC_IPR_INVERT_MD1__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD2__B                                          2
#define   FEC_OC_IPR_INVERT_MD2__W                                          1
#define   FEC_OC_IPR_INVERT_MD2__M                                          0x4
#define   FEC_OC_IPR_INVERT_MD2__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD3__B                                          3
#define   FEC_OC_IPR_INVERT_MD3__W                                          1
#define   FEC_OC_IPR_INVERT_MD3__M                                          0x8
#define   FEC_OC_IPR_INVERT_MD3__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD4__B                                          4
#define   FEC_OC_IPR_INVERT_MD4__W                                          1
#define   FEC_OC_IPR_INVERT_MD4__M                                          0x10
#define   FEC_OC_IPR_INVERT_MD4__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD5__B                                          5
#define   FEC_OC_IPR_INVERT_MD5__W                                          1
#define   FEC_OC_IPR_INVERT_MD5__M                                          0x20
#define   FEC_OC_IPR_INVERT_MD5__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD6__B                                          6
#define   FEC_OC_IPR_INVERT_MD6__W                                          1
#define   FEC_OC_IPR_INVERT_MD6__M                                          0x40
#define   FEC_OC_IPR_INVERT_MD6__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MD7__B                                          7
#define   FEC_OC_IPR_INVERT_MD7__W                                          1
#define   FEC_OC_IPR_INVERT_MD7__M                                          0x80
#define   FEC_OC_IPR_INVERT_MD7__PRE                                        0x0

#define   FEC_OC_IPR_INVERT_MERR__B                                         8
#define   FEC_OC_IPR_INVERT_MERR__W                                         1
#define   FEC_OC_IPR_INVERT_MERR__M                                         0x100
#define   FEC_OC_IPR_INVERT_MERR__PRE                                       0x0

#define   FEC_OC_IPR_INVERT_MSTRT__B                                        9
#define   FEC_OC_IPR_INVERT_MSTRT__W                                        1
#define   FEC_OC_IPR_INVERT_MSTRT__M                                        0x200
#define   FEC_OC_IPR_INVERT_MSTRT__PRE                                      0x0

#define   FEC_OC_IPR_INVERT_MVAL__B                                         10
#define   FEC_OC_IPR_INVERT_MVAL__W                                         1
#define   FEC_OC_IPR_INVERT_MVAL__M                                         0x400
#define   FEC_OC_IPR_INVERT_MVAL__PRE                                       0x0

#define   FEC_OC_IPR_INVERT_MCLK__B                                         11
#define   FEC_OC_IPR_INVERT_MCLK__W                                         1
#define   FEC_OC_IPR_INVERT_MCLK__M                                         0x800
#define   FEC_OC_IPR_INVERT_MCLK__PRE                                       0x0

#define FEC_OC_OCR_MODE__A                                                  0x2440050
#define FEC_OC_OCR_MODE__W                                                  4
#define FEC_OC_OCR_MODE__M                                                  0xF
#define FEC_OC_OCR_MODE__PRE                                                0x0

#define   FEC_OC_OCR_MODE_MB_SELECT__B                                      0
#define   FEC_OC_OCR_MODE_MB_SELECT__W                                      1
#define   FEC_OC_OCR_MODE_MB_SELECT__M                                      0x1
#define   FEC_OC_OCR_MODE_MB_SELECT__PRE                                    0x0

#define   FEC_OC_OCR_MODE_GRAB_ENABLE__B                                    1
#define   FEC_OC_OCR_MODE_GRAB_ENABLE__W                                    1
#define   FEC_OC_OCR_MODE_GRAB_ENABLE__M                                    0x2
#define   FEC_OC_OCR_MODE_GRAB_ENABLE__PRE                                  0x0

#define   FEC_OC_OCR_MODE_GRAB_SELECT__B                                    2
#define   FEC_OC_OCR_MODE_GRAB_SELECT__W                                    1
#define   FEC_OC_OCR_MODE_GRAB_SELECT__M                                    0x4
#define   FEC_OC_OCR_MODE_GRAB_SELECT__PRE                                  0x0

#define   FEC_OC_OCR_MODE_GRAB_COUNTED__B                                   3
#define   FEC_OC_OCR_MODE_GRAB_COUNTED__W                                   1
#define   FEC_OC_OCR_MODE_GRAB_COUNTED__M                                   0x8
#define   FEC_OC_OCR_MODE_GRAB_COUNTED__PRE                                 0x0

#define FEC_OC_OCR_RATE__A                                                  0x2440051
#define FEC_OC_OCR_RATE__W                                                  4
#define FEC_OC_OCR_RATE__M                                                  0xF
#define FEC_OC_OCR_RATE__PRE                                                0x0

#define   FEC_OC_OCR_RATE_RATE__B                                           0
#define   FEC_OC_OCR_RATE_RATE__W                                           4
#define   FEC_OC_OCR_RATE_RATE__M                                           0xF
#define   FEC_OC_OCR_RATE_RATE__PRE                                         0x0

#define FEC_OC_OCR_INVERT__A                                                0x2440052
#define FEC_OC_OCR_INVERT__W                                                12
#define FEC_OC_OCR_INVERT__M                                                0xFFF
#define FEC_OC_OCR_INVERT__PRE                                              0x800

#define   FEC_OC_OCR_INVERT_INVERT__B                                       0
#define   FEC_OC_OCR_INVERT_INVERT__W                                       12
#define   FEC_OC_OCR_INVERT_INVERT__M                                       0xFFF
#define   FEC_OC_OCR_INVERT_INVERT__PRE                                     0x800

#define FEC_OC_OCR_GRAB_COUNT__A                                            0x2440053
#define FEC_OC_OCR_GRAB_COUNT__W                                            16
#define FEC_OC_OCR_GRAB_COUNT__M                                            0xFFFF
#define FEC_OC_OCR_GRAB_COUNT__PRE                                          0x0

#define   FEC_OC_OCR_GRAB_COUNT_COUNT__B                                    0
#define   FEC_OC_OCR_GRAB_COUNT_COUNT__W                                    16
#define   FEC_OC_OCR_GRAB_COUNT_COUNT__M                                    0xFFFF
#define   FEC_OC_OCR_GRAB_COUNT_COUNT__PRE                                  0x0

#define FEC_OC_OCR_GRAB_SYNC__A                                             0x2440054
#define FEC_OC_OCR_GRAB_SYNC__W                                             8
#define FEC_OC_OCR_GRAB_SYNC__M                                             0xFF
#define FEC_OC_OCR_GRAB_SYNC__PRE                                           0x0

#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B                                  0
#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W                                  3
#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M                                  0x7
#define   FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE                                0x0

#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B                                   3
#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W                                   4
#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M                                   0x78
#define   FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE                                 0x0

#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B                                 7
#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W                                 1
#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M                                 0x80
#define   FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE                               0x0

#define FEC_OC_OCR_GRAB_RD0__A                                              0x2440055
#define FEC_OC_OCR_GRAB_RD0__W                                              10
#define FEC_OC_OCR_GRAB_RD0__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD0__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD0_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD0_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD0_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD0_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD1__A                                              0x2440056
#define FEC_OC_OCR_GRAB_RD1__W                                              10
#define FEC_OC_OCR_GRAB_RD1__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD1__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD1_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD1_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD1_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD1_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD2__A                                              0x2440057
#define FEC_OC_OCR_GRAB_RD2__W                                              10
#define FEC_OC_OCR_GRAB_RD2__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD2__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD2_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD2_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD2_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD2_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD3__A                                              0x2440058
#define FEC_OC_OCR_GRAB_RD3__W                                              10
#define FEC_OC_OCR_GRAB_RD3__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD3__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD3_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD3_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD3_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD3_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD4__A                                              0x2440059
#define FEC_OC_OCR_GRAB_RD4__W                                              10
#define FEC_OC_OCR_GRAB_RD4__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD4__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD4_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD4_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD4_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD4_DATA__PRE                                     0x0

#define FEC_OC_OCR_GRAB_RD5__A                                              0x244005A
#define FEC_OC_OCR_GRAB_RD5__W                                              10
#define FEC_OC_OCR_GRAB_RD5__M                                              0x3FF
#define FEC_OC_OCR_GRAB_RD5__PRE                                            0x0

#define   FEC_OC_OCR_GRAB_RD5_DATA__B                                       0
#define   FEC_OC_OCR_GRAB_RD5_DATA__W                                       10
#define   FEC_OC_OCR_GRAB_RD5_DATA__M                                       0x3FF
#define   FEC_OC_OCR_GRAB_RD5_DATA__PRE                                     0x0

#define FEC_DI_RAM__A                                                       0x2450000

#define FEC_RS_RAM__A                                                       0x2460000

#define FEC_OC_RAM__A                                                       0x2470000

#define IQM_COMM_EXEC__A                                                    0x1800000
#define IQM_COMM_EXEC__W                                                    2
#define IQM_COMM_EXEC__M                                                    0x3
#define IQM_COMM_EXEC__PRE                                                  0x0
#define   IQM_COMM_EXEC_STOP                                                0x0
#define   IQM_COMM_EXEC_ACTIVE                                              0x1
#define   IQM_COMM_EXEC_HOLD                                                0x2

#define IQM_COMM_MB__A                                                      0x1800002
#define IQM_COMM_MB__W                                                      16
#define IQM_COMM_MB__M                                                      0xFFFF
#define IQM_COMM_MB__PRE                                                    0x0
#define IQM_COMM_INT_REQ__A                                                 0x1800003
#define IQM_COMM_INT_REQ__W                                                 2
#define IQM_COMM_INT_REQ__M                                                 0x3
#define IQM_COMM_INT_REQ__PRE                                               0x0

#define   IQM_COMM_INT_REQ_AF_REQ__B                                        0
#define   IQM_COMM_INT_REQ_AF_REQ__W                                        1
#define   IQM_COMM_INT_REQ_AF_REQ__M                                        0x1
#define   IQM_COMM_INT_REQ_AF_REQ__PRE                                      0x0

#define   IQM_COMM_INT_REQ_CF_REQ__B                                        1
#define   IQM_COMM_INT_REQ_CF_REQ__W                                        1
#define   IQM_COMM_INT_REQ_CF_REQ__M                                        0x2
#define   IQM_COMM_INT_REQ_CF_REQ__PRE                                      0x0

#define IQM_COMM_INT_STA__A                                                 0x1800005
#define IQM_COMM_INT_STA__W                                                 16
#define IQM_COMM_INT_STA__M                                                 0xFFFF
#define IQM_COMM_INT_STA__PRE                                               0x0
#define IQM_COMM_INT_MSK__A                                                 0x1800006
#define IQM_COMM_INT_MSK__W                                                 16
#define IQM_COMM_INT_MSK__M                                                 0xFFFF
#define IQM_COMM_INT_MSK__PRE                                               0x0
#define IQM_COMM_INT_STM__A                                                 0x1800007
#define IQM_COMM_INT_STM__W                                                 16
#define IQM_COMM_INT_STM__M                                                 0xFFFF
#define IQM_COMM_INT_STM__PRE                                               0x0

#define IQM_FS_COMM_EXEC__A                                                 0x1820000
#define IQM_FS_COMM_EXEC__W                                                 2
#define IQM_FS_COMM_EXEC__M                                                 0x3
#define IQM_FS_COMM_EXEC__PRE                                               0x0
#define   IQM_FS_COMM_EXEC_STOP                                             0x0
#define   IQM_FS_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_FS_COMM_EXEC_HOLD                                             0x2

#define IQM_FS_COMM_MB__A                                                   0x1820002
#define IQM_FS_COMM_MB__W                                                   2
#define IQM_FS_COMM_MB__M                                                   0x3
#define IQM_FS_COMM_MB__PRE                                                 0x0
#define   IQM_FS_COMM_MB_CTL__B                                             0
#define   IQM_FS_COMM_MB_CTL__W                                             1
#define   IQM_FS_COMM_MB_CTL__M                                             0x1
#define   IQM_FS_COMM_MB_CTL__PRE                                           0x0
#define     IQM_FS_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_FS_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_FS_COMM_MB_OBS__B                                             1
#define   IQM_FS_COMM_MB_OBS__W                                             1
#define   IQM_FS_COMM_MB_OBS__M                                             0x2
#define   IQM_FS_COMM_MB_OBS__PRE                                           0x0
#define     IQM_FS_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_FS_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_FS_RATE_OFS_LO__A                                               0x1820010
#define IQM_FS_RATE_OFS_LO__W                                               16
#define IQM_FS_RATE_OFS_LO__M                                               0xFFFF
#define IQM_FS_RATE_OFS_LO__PRE                                             0x0
#define IQM_FS_RATE_OFS_HI__A                                               0x1820011
#define IQM_FS_RATE_OFS_HI__W                                               12
#define IQM_FS_RATE_OFS_HI__M                                               0xFFF
#define IQM_FS_RATE_OFS_HI__PRE                                             0x0
#define IQM_FS_RATE_LO__A                                                   0x1820012
#define IQM_FS_RATE_LO__W                                                   16
#define IQM_FS_RATE_LO__M                                                   0xFFFF
#define IQM_FS_RATE_LO__PRE                                                 0x0
#define IQM_FS_RATE_HI__A                                                   0x1820013
#define IQM_FS_RATE_HI__W                                                   12
#define IQM_FS_RATE_HI__M                                                   0xFFF
#define IQM_FS_RATE_HI__PRE                                                 0x0

#define IQM_FS_ADJ_SEL__A                                                   0x1820014
#define IQM_FS_ADJ_SEL__W                                                   2
#define IQM_FS_ADJ_SEL__M                                                   0x3
#define IQM_FS_ADJ_SEL__PRE                                                 0x0
#define   IQM_FS_ADJ_SEL_OFF                                                0x0
#define   IQM_FS_ADJ_SEL_QAM                                                0x1
#define   IQM_FS_ADJ_SEL_VSB                                                0x2

#define IQM_FD_COMM_EXEC__A                                                 0x1830000
#define IQM_FD_COMM_EXEC__W                                                 2
#define IQM_FD_COMM_EXEC__M                                                 0x3
#define IQM_FD_COMM_EXEC__PRE                                               0x0
#define   IQM_FD_COMM_EXEC_STOP                                             0x0
#define   IQM_FD_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_FD_COMM_EXEC_HOLD                                             0x2

#define IQM_FD_COMM_MB__A                                                   0x1830002
#define IQM_FD_COMM_MB__W                                                   2
#define IQM_FD_COMM_MB__M                                                   0x3
#define IQM_FD_COMM_MB__PRE                                                 0x0
#define   IQM_FD_COMM_MB_CTL__B                                             0
#define   IQM_FD_COMM_MB_CTL__W                                             1
#define   IQM_FD_COMM_MB_CTL__M                                             0x1
#define   IQM_FD_COMM_MB_CTL__PRE                                           0x0
#define     IQM_FD_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_FD_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_FD_COMM_MB_OBS__B                                             1
#define   IQM_FD_COMM_MB_OBS__W                                             1
#define   IQM_FD_COMM_MB_OBS__M                                             0x2
#define   IQM_FD_COMM_MB_OBS__PRE                                           0x0
#define     IQM_FD_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_FD_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_RC_COMM_EXEC__A                                                 0x1840000
#define IQM_RC_COMM_EXEC__W                                                 2
#define IQM_RC_COMM_EXEC__M                                                 0x3
#define IQM_RC_COMM_EXEC__PRE                                               0x0
#define   IQM_RC_COMM_EXEC_STOP                                             0x0
#define   IQM_RC_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_RC_COMM_EXEC_HOLD                                             0x2

#define IQM_RC_COMM_MB__A                                                   0x1840002
#define IQM_RC_COMM_MB__W                                                   2
#define IQM_RC_COMM_MB__M                                                   0x3
#define IQM_RC_COMM_MB__PRE                                                 0x0
#define   IQM_RC_COMM_MB_CTL__B                                             0
#define   IQM_RC_COMM_MB_CTL__W                                             1
#define   IQM_RC_COMM_MB_CTL__M                                             0x1
#define   IQM_RC_COMM_MB_CTL__PRE                                           0x0
#define     IQM_RC_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_RC_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_RC_COMM_MB_OBS__B                                             1
#define   IQM_RC_COMM_MB_OBS__W                                             1
#define   IQM_RC_COMM_MB_OBS__M                                             0x2
#define   IQM_RC_COMM_MB_OBS__PRE                                           0x0
#define     IQM_RC_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_RC_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_RC_RATE_OFS_LO__A                                               0x1840010
#define IQM_RC_RATE_OFS_LO__W                                               16
#define IQM_RC_RATE_OFS_LO__M                                               0xFFFF
#define IQM_RC_RATE_OFS_LO__PRE                                             0x0
#define IQM_RC_RATE_OFS_HI__A                                               0x1840011
#define IQM_RC_RATE_OFS_HI__W                                               8
#define IQM_RC_RATE_OFS_HI__M                                               0xFF
#define IQM_RC_RATE_OFS_HI__PRE                                             0x0
#define IQM_RC_RATE_LO__A                                                   0x1840012
#define IQM_RC_RATE_LO__W                                                   16
#define IQM_RC_RATE_LO__M                                                   0xFFFF
#define IQM_RC_RATE_LO__PRE                                                 0x0
#define IQM_RC_RATE_HI__A                                                   0x1840013
#define IQM_RC_RATE_HI__W                                                   8
#define IQM_RC_RATE_HI__M                                                   0xFF
#define IQM_RC_RATE_HI__PRE                                                 0x0

#define IQM_RC_ADJ_SEL__A                                                   0x1840014
#define IQM_RC_ADJ_SEL__W                                                   2
#define IQM_RC_ADJ_SEL__M                                                   0x3
#define IQM_RC_ADJ_SEL__PRE                                                 0x0
#define   IQM_RC_ADJ_SEL_OFF                                                0x0
#define   IQM_RC_ADJ_SEL_QAM                                                0x1
#define   IQM_RC_ADJ_SEL_VSB                                                0x2

#define IQM_RC_CROUT_ENA__A                                                 0x1840015
#define IQM_RC_CROUT_ENA__W                                                 1
#define IQM_RC_CROUT_ENA__M                                                 0x1
#define IQM_RC_CROUT_ENA__PRE                                               0x0

#define   IQM_RC_CROUT_ENA_ENA__B                                           0
#define   IQM_RC_CROUT_ENA_ENA__W                                           1
#define   IQM_RC_CROUT_ENA_ENA__M                                           0x1
#define   IQM_RC_CROUT_ENA_ENA__PRE                                         0x0

#define IQM_RC_STRETCH__A                                                   0x1840016
#define IQM_RC_STRETCH__W                                                   5
#define IQM_RC_STRETCH__M                                                   0x1F
#define IQM_RC_STRETCH__PRE                                                 0x0
#define   IQM_RC_STRETCH_QAM_B_64                                           0x1E
#define   IQM_RC_STRETCH_QAM_B_256                                          0x1C
#define   IQM_RC_STRETCH_ATV                                                0xF

#define IQM_RT_COMM_EXEC__A                                                 0x1850000
#define IQM_RT_COMM_EXEC__W                                                 2
#define IQM_RT_COMM_EXEC__M                                                 0x3
#define IQM_RT_COMM_EXEC__PRE                                               0x0
#define   IQM_RT_COMM_EXEC_STOP                                             0x0
#define   IQM_RT_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_RT_COMM_EXEC_HOLD                                             0x2

#define IQM_RT_COMM_MB__A                                                   0x1850002
#define IQM_RT_COMM_MB__W                                                   2
#define IQM_RT_COMM_MB__M                                                   0x3
#define IQM_RT_COMM_MB__PRE                                                 0x0
#define   IQM_RT_COMM_MB_CTL__B                                             0
#define   IQM_RT_COMM_MB_CTL__W                                             1
#define   IQM_RT_COMM_MB_CTL__M                                             0x1
#define   IQM_RT_COMM_MB_CTL__PRE                                           0x0
#define     IQM_RT_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_RT_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_RT_COMM_MB_OBS__B                                             1
#define   IQM_RT_COMM_MB_OBS__W                                             1
#define   IQM_RT_COMM_MB_OBS__M                                             0x2
#define   IQM_RT_COMM_MB_OBS__PRE                                           0x0
#define     IQM_RT_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_RT_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_RT_ACTIVE__A                                                    0x1850010
#define IQM_RT_ACTIVE__W                                                    2
#define IQM_RT_ACTIVE__M                                                    0x3
#define IQM_RT_ACTIVE__PRE                                                  0x0

#define   IQM_RT_ACTIVE_ACTIVE_RT__B                                        0
#define   IQM_RT_ACTIVE_ACTIVE_RT__W                                        1
#define   IQM_RT_ACTIVE_ACTIVE_RT__M                                        0x1
#define   IQM_RT_ACTIVE_ACTIVE_RT__PRE                                      0x0
#define     IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF                             0x0
#define     IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON                              0x1

#define   IQM_RT_ACTIVE_ACTIVE_CR__B                                        1
#define   IQM_RT_ACTIVE_ACTIVE_CR__W                                        1
#define   IQM_RT_ACTIVE_ACTIVE_CR__M                                        0x2
#define   IQM_RT_ACTIVE_ACTIVE_CR__PRE                                      0x0
#define     IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF                              0x0
#define     IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON                               0x2

#define IQM_RT_LO_INCR__A                                                   0x1850011
#define IQM_RT_LO_INCR__W                                                   12
#define IQM_RT_LO_INCR__M                                                   0xFFF
#define IQM_RT_LO_INCR__PRE                                                 0x588
#define   IQM_RT_LO_INCR_FM                                                 0x0
#define   IQM_RT_LO_INCR_MN                                                 0x588

#define IQM_RT_ROT_BP__A                                                    0x1850012
#define IQM_RT_ROT_BP__W                                                    2
#define IQM_RT_ROT_BP__M                                                    0x3
#define IQM_RT_ROT_BP__PRE                                                  0x0

#define   IQM_RT_ROT_BP_ROT_OFF__B                                          0
#define   IQM_RT_ROT_BP_ROT_OFF__W                                          1
#define   IQM_RT_ROT_BP_ROT_OFF__M                                          0x1
#define   IQM_RT_ROT_BP_ROT_OFF__PRE                                        0x0
#define     IQM_RT_ROT_BP_ROT_OFF_ACTIVE                                    0x0
#define     IQM_RT_ROT_BP_ROT_OFF_OFF                                       0x1

#define   IQM_RT_ROT_BP_ROT_BPF__B                                          1
#define   IQM_RT_ROT_BP_ROT_BPF__W                                          1
#define   IQM_RT_ROT_BP_ROT_BPF__M                                          0x2
#define   IQM_RT_ROT_BP_ROT_BPF__PRE                                        0x0

#define IQM_RT_LP_BP__A                                                     0x1850013
#define IQM_RT_LP_BP__W                                                     1
#define IQM_RT_LP_BP__M                                                     0x1
#define IQM_RT_LP_BP__PRE                                                   0x0

#define IQM_RT_DELAY__A                                                     0x1850014
#define IQM_RT_DELAY__W                                                     7
#define IQM_RT_DELAY__M                                                     0x7F
#define IQM_RT_DELAY__PRE                                                   0x45

#define IQM_CF_COMM_EXEC__A                                                 0x1860000
#define IQM_CF_COMM_EXEC__W                                                 2
#define IQM_CF_COMM_EXEC__M                                                 0x3
#define IQM_CF_COMM_EXEC__PRE                                               0x0
#define   IQM_CF_COMM_EXEC_STOP                                             0x0
#define   IQM_CF_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_CF_COMM_EXEC_HOLD                                             0x2

#define IQM_CF_COMM_MB__A                                                   0x1860002
#define IQM_CF_COMM_MB__W                                                   2
#define IQM_CF_COMM_MB__M                                                   0x3
#define IQM_CF_COMM_MB__PRE                                                 0x0
#define   IQM_CF_COMM_MB_CTL__B                                             0
#define   IQM_CF_COMM_MB_CTL__W                                             1
#define   IQM_CF_COMM_MB_CTL__M                                             0x1
#define   IQM_CF_COMM_MB_CTL__PRE                                           0x0
#define     IQM_CF_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_CF_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_CF_COMM_MB_OBS__B                                             1
#define   IQM_CF_COMM_MB_OBS__W                                             1
#define   IQM_CF_COMM_MB_OBS__M                                             0x2
#define   IQM_CF_COMM_MB_OBS__PRE                                           0x0
#define     IQM_CF_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_CF_COMM_MB_OBS_OBS_ON                                       0x2

#define IQM_CF_COMM_INT_REQ__A                                              0x1860003
#define IQM_CF_COMM_INT_REQ__W                                              1
#define IQM_CF_COMM_INT_REQ__M                                              0x1
#define IQM_CF_COMM_INT_REQ__PRE                                            0x0
#define IQM_CF_COMM_INT_STA__A                                              0x1860005
#define IQM_CF_COMM_INT_STA__W                                              1
#define IQM_CF_COMM_INT_STA__M                                              0x1
#define IQM_CF_COMM_INT_STA__PRE                                            0x0
#define   IQM_CF_COMM_INT_STA_PM__B                                         0
#define   IQM_CF_COMM_INT_STA_PM__W                                         1
#define   IQM_CF_COMM_INT_STA_PM__M                                         0x1
#define   IQM_CF_COMM_INT_STA_PM__PRE                                       0x0

#define IQM_CF_COMM_INT_MSK__A                                              0x1860006
#define IQM_CF_COMM_INT_MSK__W                                              1
#define IQM_CF_COMM_INT_MSK__M                                              0x1
#define IQM_CF_COMM_INT_MSK__PRE                                            0x0
#define   IQM_CF_COMM_INT_MSK_PM__B                                         0
#define   IQM_CF_COMM_INT_MSK_PM__W                                         1
#define   IQM_CF_COMM_INT_MSK_PM__M                                         0x1
#define   IQM_CF_COMM_INT_MSK_PM__PRE                                       0x0

#define IQM_CF_COMM_INT_STM__A                                              0x1860007
#define IQM_CF_COMM_INT_STM__W                                              1
#define IQM_CF_COMM_INT_STM__M                                              0x1
#define IQM_CF_COMM_INT_STM__PRE                                            0x0
#define   IQM_CF_COMM_INT_STM_PM__B                                         0
#define   IQM_CF_COMM_INT_STM_PM__W                                         1
#define   IQM_CF_COMM_INT_STM_PM__M                                         0x1
#define   IQM_CF_COMM_INT_STM_PM__PRE                                       0x0

#define IQM_CF_SYMMETRIC__A                                                 0x1860010
#define IQM_CF_SYMMETRIC__W                                                 2
#define IQM_CF_SYMMETRIC__M                                                 0x3
#define IQM_CF_SYMMETRIC__PRE                                               0x0

#define   IQM_CF_SYMMETRIC_RE__B                                            0
#define   IQM_CF_SYMMETRIC_RE__W                                            1
#define   IQM_CF_SYMMETRIC_RE__M                                            0x1
#define   IQM_CF_SYMMETRIC_RE__PRE                                          0x0

#define   IQM_CF_SYMMETRIC_IM__B                                            1
#define   IQM_CF_SYMMETRIC_IM__W                                            1
#define   IQM_CF_SYMMETRIC_IM__M                                            0x2
#define   IQM_CF_SYMMETRIC_IM__PRE                                          0x0

#define IQM_CF_MIDTAP__A                                                    0x1860011
#define IQM_CF_MIDTAP__W                                                    2
#define IQM_CF_MIDTAP__M                                                    0x3
#define IQM_CF_MIDTAP__PRE                                                  0x3

#define   IQM_CF_MIDTAP_RE__B                                               0
#define   IQM_CF_MIDTAP_RE__W                                               1
#define   IQM_CF_MIDTAP_RE__M                                               0x1
#define   IQM_CF_MIDTAP_RE__PRE                                             0x1

#define   IQM_CF_MIDTAP_IM__B                                               1
#define   IQM_CF_MIDTAP_IM__W                                               1
#define   IQM_CF_MIDTAP_IM__M                                               0x2
#define   IQM_CF_MIDTAP_IM__PRE                                             0x2

#define IQM_CF_OUT_ENA__A                                                   0x1860012
#define IQM_CF_OUT_ENA__W                                                   3
#define IQM_CF_OUT_ENA__M                                                   0x7
#define IQM_CF_OUT_ENA__PRE                                                 0x0

#define   IQM_CF_OUT_ENA_ATV__B                                             0
#define   IQM_CF_OUT_ENA_ATV__W                                             1
#define   IQM_CF_OUT_ENA_ATV__M                                             0x1
#define   IQM_CF_OUT_ENA_ATV__PRE                                           0x0

#define   IQM_CF_OUT_ENA_QAM__B                                             1
#define   IQM_CF_OUT_ENA_QAM__W                                             1
#define   IQM_CF_OUT_ENA_QAM__M                                             0x2
#define   IQM_CF_OUT_ENA_QAM__PRE                                           0x0

#define   IQM_CF_OUT_ENA_VSB__B                                             2
#define   IQM_CF_OUT_ENA_VSB__W                                             1
#define   IQM_CF_OUT_ENA_VSB__M                                             0x4
#define   IQM_CF_OUT_ENA_VSB__PRE                                           0x0

#define IQM_CF_ADJ_SEL__A                                                   0x1860013
#define IQM_CF_ADJ_SEL__W                                                   2
#define IQM_CF_ADJ_SEL__M                                                   0x3
#define IQM_CF_ADJ_SEL__PRE                                                 0x0
#define IQM_CF_SCALE__A                                                     0x1860014
#define IQM_CF_SCALE__W                                                     14
#define IQM_CF_SCALE__M                                                     0x3FFF
#define IQM_CF_SCALE__PRE                                                   0x400

#define IQM_CF_SCALE_SH__A                                                  0x1860015
#define IQM_CF_SCALE_SH__W                                                  2
#define IQM_CF_SCALE_SH__M                                                  0x3
#define IQM_CF_SCALE_SH__PRE                                                0x0

#define IQM_CF_AMP__A                                                       0x1860016
#define IQM_CF_AMP__W                                                       14
#define IQM_CF_AMP__M                                                       0x3FFF
#define IQM_CF_AMP__PRE                                                     0x0

#define IQM_CF_POW_MEAS_LEN__A                                              0x1860017
#define IQM_CF_POW_MEAS_LEN__W                                              3
#define IQM_CF_POW_MEAS_LEN__M                                              0x7
#define IQM_CF_POW_MEAS_LEN__PRE                                            0x2
#define   IQM_CF_POW_MEAS_LEN_QAM_B_64                                      0x1
#define   IQM_CF_POW_MEAS_LEN_QAM_B_256                                     0x1

#define IQM_CF_POW__A                                                       0x1860018
#define IQM_CF_POW__W                                                       16
#define IQM_CF_POW__M                                                       0xFFFF
#define IQM_CF_POW__PRE                                                     0x2
#define IQM_CF_TAP_RE0__A                                                   0x1860020
#define IQM_CF_TAP_RE0__W                                                   7
#define IQM_CF_TAP_RE0__M                                                   0x7F
#define IQM_CF_TAP_RE0__PRE                                                 0x2
#define IQM_CF_TAP_RE1__A                                                   0x1860021
#define IQM_CF_TAP_RE1__W                                                   7
#define IQM_CF_TAP_RE1__M                                                   0x7F
#define IQM_CF_TAP_RE1__PRE                                                 0x2
#define IQM_CF_TAP_RE2__A                                                   0x1860022
#define IQM_CF_TAP_RE2__W                                                   7
#define IQM_CF_TAP_RE2__M                                                   0x7F
#define IQM_CF_TAP_RE2__PRE                                                 0x2
#define IQM_CF_TAP_RE3__A                                                   0x1860023
#define IQM_CF_TAP_RE3__W                                                   7
#define IQM_CF_TAP_RE3__M                                                   0x7F
#define IQM_CF_TAP_RE3__PRE                                                 0x2
#define IQM_CF_TAP_RE4__A                                                   0x1860024
#define IQM_CF_TAP_RE4__W                                                   7
#define IQM_CF_TAP_RE4__M                                                   0x7F
#define IQM_CF_TAP_RE4__PRE                                                 0x2
#define IQM_CF_TAP_RE5__A                                                   0x1860025
#define IQM_CF_TAP_RE5__W                                                   7
#define IQM_CF_TAP_RE5__M                                                   0x7F
#define IQM_CF_TAP_RE5__PRE                                                 0x2
#define IQM_CF_TAP_RE6__A                                                   0x1860026
#define IQM_CF_TAP_RE6__W                                                   7
#define IQM_CF_TAP_RE6__M                                                   0x7F
#define IQM_CF_TAP_RE6__PRE                                                 0x2
#define IQM_CF_TAP_RE7__A                                                   0x1860027
#define IQM_CF_TAP_RE7__W                                                   9
#define IQM_CF_TAP_RE7__M                                                   0x1FF
#define IQM_CF_TAP_RE7__PRE                                                 0x2
#define IQM_CF_TAP_RE8__A                                                   0x1860028
#define IQM_CF_TAP_RE8__W                                                   9
#define IQM_CF_TAP_RE8__M                                                   0x1FF
#define IQM_CF_TAP_RE8__PRE                                                 0x2
#define IQM_CF_TAP_RE9__A                                                   0x1860029
#define IQM_CF_TAP_RE9__W                                                   9
#define IQM_CF_TAP_RE9__M                                                   0x1FF
#define IQM_CF_TAP_RE9__PRE                                                 0x2
#define IQM_CF_TAP_RE10__A                                                  0x186002A
#define IQM_CF_TAP_RE10__W                                                  9
#define IQM_CF_TAP_RE10__M                                                  0x1FF
#define IQM_CF_TAP_RE10__PRE                                                0x2
#define IQM_CF_TAP_RE11__A                                                  0x186002B
#define IQM_CF_TAP_RE11__W                                                  9
#define IQM_CF_TAP_RE11__M                                                  0x1FF
#define IQM_CF_TAP_RE11__PRE                                                0x2
#define IQM_CF_TAP_RE12__A                                                  0x186002C
#define IQM_CF_TAP_RE12__W                                                  9
#define IQM_CF_TAP_RE12__M                                                  0x1FF
#define IQM_CF_TAP_RE12__PRE                                                0x2
#define IQM_CF_TAP_RE13__A                                                  0x186002D
#define IQM_CF_TAP_RE13__W                                                  9
#define IQM_CF_TAP_RE13__M                                                  0x1FF
#define IQM_CF_TAP_RE13__PRE                                                0x2
#define IQM_CF_TAP_RE14__A                                                  0x186002E
#define IQM_CF_TAP_RE14__W                                                  9
#define IQM_CF_TAP_RE14__M                                                  0x1FF
#define IQM_CF_TAP_RE14__PRE                                                0x2
#define IQM_CF_TAP_RE15__A                                                  0x186002F
#define IQM_CF_TAP_RE15__W                                                  9
#define IQM_CF_TAP_RE15__M                                                  0x1FF
#define IQM_CF_TAP_RE15__PRE                                                0x2
#define IQM_CF_TAP_RE16__A                                                  0x1860030
#define IQM_CF_TAP_RE16__W                                                  9
#define IQM_CF_TAP_RE16__M                                                  0x1FF
#define IQM_CF_TAP_RE16__PRE                                                0x2
#define IQM_CF_TAP_RE17__A                                                  0x1860031
#define IQM_CF_TAP_RE17__W                                                  9
#define IQM_CF_TAP_RE17__M                                                  0x1FF
#define IQM_CF_TAP_RE17__PRE                                                0x2
#define IQM_CF_TAP_RE18__A                                                  0x1860032
#define IQM_CF_TAP_RE18__W                                                  9
#define IQM_CF_TAP_RE18__M                                                  0x1FF
#define IQM_CF_TAP_RE18__PRE                                                0x2
#define IQM_CF_TAP_RE19__A                                                  0x1860033
#define IQM_CF_TAP_RE19__W                                                  9
#define IQM_CF_TAP_RE19__M                                                  0x1FF
#define IQM_CF_TAP_RE19__PRE                                                0x2
#define IQM_CF_TAP_RE20__A                                                  0x1860034
#define IQM_CF_TAP_RE20__W                                                  9
#define IQM_CF_TAP_RE20__M                                                  0x1FF
#define IQM_CF_TAP_RE20__PRE                                                0x2
#define IQM_CF_TAP_RE21__A                                                  0x1860035
#define IQM_CF_TAP_RE21__W                                                  11
#define IQM_CF_TAP_RE21__M                                                  0x7FF
#define IQM_CF_TAP_RE21__PRE                                                0x2
#define IQM_CF_TAP_RE22__A                                                  0x1860036
#define IQM_CF_TAP_RE22__W                                                  11
#define IQM_CF_TAP_RE22__M                                                  0x7FF
#define IQM_CF_TAP_RE22__PRE                                                0x2
#define IQM_CF_TAP_RE23__A                                                  0x1860037
#define IQM_CF_TAP_RE23__W                                                  11
#define IQM_CF_TAP_RE23__M                                                  0x7FF
#define IQM_CF_TAP_RE23__PRE                                                0x2
#define IQM_CF_TAP_RE24__A                                                  0x1860038
#define IQM_CF_TAP_RE24__W                                                  11
#define IQM_CF_TAP_RE24__M                                                  0x7FF
#define IQM_CF_TAP_RE24__PRE                                                0x2
#define IQM_CF_TAP_RE25__A                                                  0x1860039
#define IQM_CF_TAP_RE25__W                                                  11
#define IQM_CF_TAP_RE25__M                                                  0x7FF
#define IQM_CF_TAP_RE25__PRE                                                0x2
#define IQM_CF_TAP_RE26__A                                                  0x186003A
#define IQM_CF_TAP_RE26__W                                                  11
#define IQM_CF_TAP_RE26__M                                                  0x7FF
#define IQM_CF_TAP_RE26__PRE                                                0x2
#define IQM_CF_TAP_RE27__A                                                  0x186003B
#define IQM_CF_TAP_RE27__W                                                  11
#define IQM_CF_TAP_RE27__M                                                  0x7FF
#define IQM_CF_TAP_RE27__PRE                                                0x2
#define IQM_CF_TAP_IM0__A                                                   0x1860040
#define IQM_CF_TAP_IM0__W                                                   7
#define IQM_CF_TAP_IM0__M                                                   0x7F
#define IQM_CF_TAP_IM0__PRE                                                 0x2
#define IQM_CF_TAP_IM1__A                                                   0x1860041
#define IQM_CF_TAP_IM1__W                                                   7
#define IQM_CF_TAP_IM1__M                                                   0x7F
#define IQM_CF_TAP_IM1__PRE                                                 0x2
#define IQM_CF_TAP_IM2__A                                                   0x1860042
#define IQM_CF_TAP_IM2__W                                                   7
#define IQM_CF_TAP_IM2__M                                                   0x7F
#define IQM_CF_TAP_IM2__PRE                                                 0x2
#define IQM_CF_TAP_IM3__A                                                   0x1860043
#define IQM_CF_TAP_IM3__W                                                   7
#define IQM_CF_TAP_IM3__M                                                   0x7F
#define IQM_CF_TAP_IM3__PRE                                                 0x2
#define IQM_CF_TAP_IM4__A                                                   0x1860044
#define IQM_CF_TAP_IM4__W                                                   7
#define IQM_CF_TAP_IM4__M                                                   0x7F
#define IQM_CF_TAP_IM4__PRE                                                 0x2
#define IQM_CF_TAP_IM5__A                                                   0x1860045
#define IQM_CF_TAP_IM5__W                                                   7
#define IQM_CF_TAP_IM5__M                                                   0x7F
#define IQM_CF_TAP_IM5__PRE                                                 0x2
#define IQM_CF_TAP_IM6__A                                                   0x1860046
#define IQM_CF_TAP_IM6__W                                                   7
#define IQM_CF_TAP_IM6__M                                                   0x7F
#define IQM_CF_TAP_IM6__PRE                                                 0x2
#define IQM_CF_TAP_IM7__A                                                   0x1860047
#define IQM_CF_TAP_IM7__W                                                   9
#define IQM_CF_TAP_IM7__M                                                   0x1FF
#define IQM_CF_TAP_IM7__PRE                                                 0x2
#define IQM_CF_TAP_IM8__A                                                   0x1860048
#define IQM_CF_TAP_IM8__W                                                   9
#define IQM_CF_TAP_IM8__M                                                   0x1FF
#define IQM_CF_TAP_IM8__PRE                                                 0x2
#define IQM_CF_TAP_IM9__A                                                   0x1860049
#define IQM_CF_TAP_IM9__W                                                   9
#define IQM_CF_TAP_IM9__M                                                   0x1FF
#define IQM_CF_TAP_IM9__PRE                                                 0x2
#define IQM_CF_TAP_IM10__A                                                  0x186004A
#define IQM_CF_TAP_IM10__W                                                  9
#define IQM_CF_TAP_IM10__M                                                  0x1FF
#define IQM_CF_TAP_IM10__PRE                                                0x2
#define IQM_CF_TAP_IM11__A                                                  0x186004B
#define IQM_CF_TAP_IM11__W                                                  9
#define IQM_CF_TAP_IM11__M                                                  0x1FF
#define IQM_CF_TAP_IM11__PRE                                                0x2
#define IQM_CF_TAP_IM12__A                                                  0x186004C
#define IQM_CF_TAP_IM12__W                                                  9
#define IQM_CF_TAP_IM12__M                                                  0x1FF
#define IQM_CF_TAP_IM12__PRE                                                0x2
#define IQM_CF_TAP_IM13__A                                                  0x186004D
#define IQM_CF_TAP_IM13__W                                                  9
#define IQM_CF_TAP_IM13__M                                                  0x1FF
#define IQM_CF_TAP_IM13__PRE                                                0x2
#define IQM_CF_TAP_IM14__A                                                  0x186004E
#define IQM_CF_TAP_IM14__W                                                  9
#define IQM_CF_TAP_IM14__M                                                  0x1FF
#define IQM_CF_TAP_IM14__PRE                                                0x2
#define IQM_CF_TAP_IM15__A                                                  0x186004F
#define IQM_CF_TAP_IM15__W                                                  9
#define IQM_CF_TAP_IM15__M                                                  0x1FF
#define IQM_CF_TAP_IM15__PRE                                                0x2
#define IQM_CF_TAP_IM16__A                                                  0x1860050
#define IQM_CF_TAP_IM16__W                                                  9
#define IQM_CF_TAP_IM16__M                                                  0x1FF
#define IQM_CF_TAP_IM16__PRE                                                0x2
#define IQM_CF_TAP_IM17__A                                                  0x1860051
#define IQM_CF_TAP_IM17__W                                                  9
#define IQM_CF_TAP_IM17__M                                                  0x1FF
#define IQM_CF_TAP_IM17__PRE                                                0x2
#define IQM_CF_TAP_IM18__A                                                  0x1860052
#define IQM_CF_TAP_IM18__W                                                  9
#define IQM_CF_TAP_IM18__M                                                  0x1FF
#define IQM_CF_TAP_IM18__PRE                                                0x2
#define IQM_CF_TAP_IM19__A                                                  0x1860053
#define IQM_CF_TAP_IM19__W                                                  9
#define IQM_CF_TAP_IM19__M                                                  0x1FF
#define IQM_CF_TAP_IM19__PRE                                                0x2
#define IQM_CF_TAP_IM20__A                                                  0x1860054
#define IQM_CF_TAP_IM20__W                                                  9
#define IQM_CF_TAP_IM20__M                                                  0x1FF
#define IQM_CF_TAP_IM20__PRE                                                0x2
#define IQM_CF_TAP_IM21__A                                                  0x1860055
#define IQM_CF_TAP_IM21__W                                                  11
#define IQM_CF_TAP_IM21__M                                                  0x7FF
#define IQM_CF_TAP_IM21__PRE                                                0x2
#define IQM_CF_TAP_IM22__A                                                  0x1860056
#define IQM_CF_TAP_IM22__W                                                  11
#define IQM_CF_TAP_IM22__M                                                  0x7FF
#define IQM_CF_TAP_IM22__PRE                                                0x2
#define IQM_CF_TAP_IM23__A                                                  0x1860057
#define IQM_CF_TAP_IM23__W                                                  11
#define IQM_CF_TAP_IM23__M                                                  0x7FF
#define IQM_CF_TAP_IM23__PRE                                                0x2
#define IQM_CF_TAP_IM24__A                                                  0x1860058
#define IQM_CF_TAP_IM24__W                                                  11
#define IQM_CF_TAP_IM24__M                                                  0x7FF
#define IQM_CF_TAP_IM24__PRE                                                0x2
#define IQM_CF_TAP_IM25__A                                                  0x1860059
#define IQM_CF_TAP_IM25__W                                                  11
#define IQM_CF_TAP_IM25__M                                                  0x7FF
#define IQM_CF_TAP_IM25__PRE                                                0x2
#define IQM_CF_TAP_IM26__A                                                  0x186005A
#define IQM_CF_TAP_IM26__W                                                  11
#define IQM_CF_TAP_IM26__M                                                  0x7FF
#define IQM_CF_TAP_IM26__PRE                                                0x2
#define IQM_CF_TAP_IM27__A                                                  0x186005B
#define IQM_CF_TAP_IM27__W                                                  11
#define IQM_CF_TAP_IM27__M                                                  0x7FF
#define IQM_CF_TAP_IM27__PRE                                                0x2

#define IQM_AF_COMM_EXEC__A                                                 0x1870000
#define IQM_AF_COMM_EXEC__W                                                 2
#define IQM_AF_COMM_EXEC__M                                                 0x3
#define IQM_AF_COMM_EXEC__PRE                                               0x0
#define   IQM_AF_COMM_EXEC_STOP                                             0x0
#define   IQM_AF_COMM_EXEC_ACTIVE                                           0x1
#define   IQM_AF_COMM_EXEC_HOLD                                             0x2

#define IQM_AF_COMM_MB__A                                                   0x1870002
#define IQM_AF_COMM_MB__W                                                   8
#define IQM_AF_COMM_MB__M                                                   0xFF
#define IQM_AF_COMM_MB__PRE                                                 0x0
#define   IQM_AF_COMM_MB_CTL__B                                             0
#define   IQM_AF_COMM_MB_CTL__W                                             1
#define   IQM_AF_COMM_MB_CTL__M                                             0x1
#define   IQM_AF_COMM_MB_CTL__PRE                                           0x0
#define     IQM_AF_COMM_MB_CTL_CTL_OFF                                      0x0
#define     IQM_AF_COMM_MB_CTL_CTL_ON                                       0x1
#define   IQM_AF_COMM_MB_OBS__B                                             1
#define   IQM_AF_COMM_MB_OBS__W                                             1
#define   IQM_AF_COMM_MB_OBS__M                                             0x2
#define   IQM_AF_COMM_MB_OBS__PRE                                           0x0
#define     IQM_AF_COMM_MB_OBS_OBS_OFF                                      0x0
#define     IQM_AF_COMM_MB_OBS_OBS_ON                                       0x2
#define   IQM_AF_COMM_MB_MUX_CTRL__B                                        2
#define   IQM_AF_COMM_MB_MUX_CTRL__W                                        3
#define   IQM_AF_COMM_MB_MUX_CTRL__M                                        0x1C
#define   IQM_AF_COMM_MB_MUX_CTRL__PRE                                      0x0
#define     IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT                           0x0
#define     IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT                             0x4
#define     IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT                          0x8
#define     IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT                           0xC
#define     IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT                           0x10
#define   IQM_AF_COMM_MB_MUX_OBS__B                                         5
#define   IQM_AF_COMM_MB_MUX_OBS__W                                         3
#define   IQM_AF_COMM_MB_MUX_OBS__M                                         0xE0
#define   IQM_AF_COMM_MB_MUX_OBS__PRE                                       0x0
#define     IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT                            0x0
#define     IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT                              0x20
#define     IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT                           0x40
#define     IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT                            0x60
#define     IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT                            0x80

#define IQM_AF_COMM_INT_REQ__A                                              0x1870003
#define IQM_AF_COMM_INT_REQ__W                                              1
#define IQM_AF_COMM_INT_REQ__M                                              0x1
#define IQM_AF_COMM_INT_REQ__PRE                                            0x0
#define IQM_AF_COMM_INT_STA__A                                              0x1870005
#define IQM_AF_COMM_INT_STA__W                                              2
#define IQM_AF_COMM_INT_STA__M                                              0x3
#define IQM_AF_COMM_INT_STA__PRE                                            0x0
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__B                                0
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__M                                0x1
#define   IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE                              0x0
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__B                                1
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__M                                0x2
#define   IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE                              0x0

#define IQM_AF_COMM_INT_MSK__A                                              0x1870006
#define IQM_AF_COMM_INT_MSK__W                                              2
#define IQM_AF_COMM_INT_MSK__M                                              0x3
#define IQM_AF_COMM_INT_MSK__PRE                                            0x0
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B                                0
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W                                1
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M                                0x1
#define   IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE                              0x0
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B                                1
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W                                1
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M                                0x2
#define   IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE                              0x0

#define IQM_AF_COMM_INT_STM__A                                              0x1870007
#define IQM_AF_COMM_INT_STM__W                                              2
#define IQM_AF_COMM_INT_STM__M                                              0x3
#define IQM_AF_COMM_INT_STM__PRE                                            0x0
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__B                                0
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__M                                0x1
#define   IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE                              0x0
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__B                                1
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__W                                1
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__M                                0x2
#define   IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE                              0x0

#define IQM_AF_FDB_SEL__A                                                   0x1870010
#define IQM_AF_FDB_SEL__W                                                   1
#define IQM_AF_FDB_SEL__M                                                   0x1
#define IQM_AF_FDB_SEL__PRE                                                 0x0

#define IQM_AF_INVEXT__A                                                    0x1870011
#define IQM_AF_INVEXT__W                                                    1
#define IQM_AF_INVEXT__M                                                    0x1
#define IQM_AF_INVEXT__PRE                                                  0x0
#define IQM_AF_CLKNEG__A                                                    0x1870012
#define IQM_AF_CLKNEG__W                                                    2
#define IQM_AF_CLKNEG__M                                                    0x3
#define IQM_AF_CLKNEG__PRE                                                  0x0

#define   IQM_AF_CLKNEG_CLKNEGPEAK__B                                       0
#define   IQM_AF_CLKNEG_CLKNEGPEAK__W                                       1
#define   IQM_AF_CLKNEG_CLKNEGPEAK__M                                       0x1
#define   IQM_AF_CLKNEG_CLKNEGPEAK__PRE                                     0x0
#define     IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS                       0x0
#define     IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG                       0x1

#define   IQM_AF_CLKNEG_CLKNEGDATA__B                                       1
#define   IQM_AF_CLKNEG_CLKNEGDATA__W                                       1
#define   IQM_AF_CLKNEG_CLKNEGDATA__M                                       0x2
#define   IQM_AF_CLKNEG_CLKNEGDATA__PRE                                     0x0
#define     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS                       0x0
#define     IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG                       0x2

#define IQM_AF_MON_IN_MUX__A                                                0x1870013
#define IQM_AF_MON_IN_MUX__W                                                2
#define IQM_AF_MON_IN_MUX__M                                                0x3
#define IQM_AF_MON_IN_MUX__PRE                                              0x0

#define IQM_AF_MON_IN5__A                                                   0x1870014
#define IQM_AF_MON_IN5__W                                                   10
#define IQM_AF_MON_IN5__M                                                   0x3FF
#define IQM_AF_MON_IN5__PRE                                                 0x0

#define IQM_AF_MON_IN4__A                                                   0x1870015
#define IQM_AF_MON_IN4__W                                                   10
#define IQM_AF_MON_IN4__M                                                   0x3FF
#define IQM_AF_MON_IN4__PRE                                                 0x0

#define IQM_AF_MON_IN3__A                                                   0x1870016
#define IQM_AF_MON_IN3__W                                                   10
#define IQM_AF_MON_IN3__M                                                   0x3FF
#define IQM_AF_MON_IN3__PRE                                                 0x0

#define IQM_AF_MON_IN2__A                                                   0x1870017
#define IQM_AF_MON_IN2__W                                                   10
#define IQM_AF_MON_IN2__M                                                   0x3FF
#define IQM_AF_MON_IN2__PRE                                                 0x0

#define IQM_AF_MON_IN1__A                                                   0x1870018
#define IQM_AF_MON_IN1__W                                                   10
#define IQM_AF_MON_IN1__M                                                   0x3FF
#define IQM_AF_MON_IN1__PRE                                                 0x0

#define IQM_AF_MON_IN0__A                                                   0x1870019
#define IQM_AF_MON_IN0__W                                                   10
#define IQM_AF_MON_IN0__M                                                   0x3FF
#define IQM_AF_MON_IN0__PRE                                                 0x0

#define IQM_AF_MON_IN_VAL__A                                                0x187001A
#define IQM_AF_MON_IN_VAL__W                                                1
#define IQM_AF_MON_IN_VAL__M                                                0x1
#define IQM_AF_MON_IN_VAL__PRE                                              0x0

#define IQM_AF_START_LOCK__A                                                0x187001B
#define IQM_AF_START_LOCK__W                                                1
#define IQM_AF_START_LOCK__M                                                0x1
#define IQM_AF_START_LOCK__PRE                                              0x0

#define IQM_AF_PHASE0__A                                                    0x187001C
#define IQM_AF_PHASE0__W                                                    7
#define IQM_AF_PHASE0__M                                                    0x7F
#define IQM_AF_PHASE0__PRE                                                  0x0

#define IQM_AF_PHASE1__A                                                    0x187001D
#define IQM_AF_PHASE1__W                                                    7
#define IQM_AF_PHASE1__M                                                    0x7F
#define IQM_AF_PHASE1__PRE                                                  0x0

#define IQM_AF_PHASE2__A                                                    0x187001E
#define IQM_AF_PHASE2__W                                                    7
#define IQM_AF_PHASE2__M                                                    0x7F
#define IQM_AF_PHASE2__PRE                                                  0x0

#define IQM_AF_SCU_PHASE__A                                                 0x187001F
#define IQM_AF_SCU_PHASE__W                                                 2
#define IQM_AF_SCU_PHASE__M                                                 0x3
#define IQM_AF_SCU_PHASE__PRE                                               0x0

#define IQM_AF_SYNC_SEL__A                                                  0x1870020
#define IQM_AF_SYNC_SEL__W                                                  2
#define IQM_AF_SYNC_SEL__M                                                  0x3
#define IQM_AF_SYNC_SEL__PRE                                                0x0
#define IQM_AF_ADC_CONF__A                                                  0x1870021
#define IQM_AF_ADC_CONF__W                                                  4
#define IQM_AF_ADC_CONF__M                                                  0xF
#define IQM_AF_ADC_CONF__PRE                                                0x0

#define   IQM_AF_ADC_CONF_ADC_SIGN__B                                       0
#define   IQM_AF_ADC_CONF_ADC_SIGN__W                                       1
#define   IQM_AF_ADC_CONF_ADC_SIGN__M                                       0x1
#define   IQM_AF_ADC_CONF_ADC_SIGN__PRE                                     0x0
#define     IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED                             0x0
#define     IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED                           0x1

#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__B                                 1
#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__W                                 1
#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__M                                 0x2
#define   IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE                               0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL                       0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED                  0x2

#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__B                                2
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__W                                1
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__M                                0x4
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE                              0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL                0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED           0x4

#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__B                                3
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__W                                1
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__M                                0x8
#define   IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE                              0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL                0x0
#define     IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED           0x8

#define IQM_AF_CLP_CLIP__A                                                  0x1870022
#define IQM_AF_CLP_CLIP__W                                                  16
#define IQM_AF_CLP_CLIP__M                                                  0xFFFF
#define IQM_AF_CLP_CLIP__PRE                                                0x0

#define IQM_AF_CLP_LEN__A                                                   0x1870023
#define IQM_AF_CLP_LEN__W                                                   16
#define IQM_AF_CLP_LEN__M                                                   0xFFFF
#define IQM_AF_CLP_LEN__PRE                                                 0x0
#define   IQM_AF_CLP_LEN_QAM_B_64                                           0x400
#define   IQM_AF_CLP_LEN_QAM_B_256                                          0x400
#define   IQM_AF_CLP_LEN_ATV                                                0x0

#define IQM_AF_CLP_TH__A                                                    0x1870024
#define IQM_AF_CLP_TH__W                                                    9
#define IQM_AF_CLP_TH__M                                                    0x1FF
#define IQM_AF_CLP_TH__PRE                                                  0x0
#define   IQM_AF_CLP_TH_QAM_B_64                                            0x80
#define   IQM_AF_CLP_TH_QAM_B_256                                           0x80
#define   IQM_AF_CLP_TH_ATV                                                 0x1C0

#define IQM_AF_DCF_BYPASS__A                                                0x1870025
#define IQM_AF_DCF_BYPASS__W                                                1
#define IQM_AF_DCF_BYPASS__M                                                0x1
#define IQM_AF_DCF_BYPASS__PRE                                              0x0
#define   IQM_AF_DCF_BYPASS_ACTIVE                                          0x0
#define   IQM_AF_DCF_BYPASS_BYPASS                                          0x1

#define IQM_AF_SNS_LEN__A                                                   0x1870026
#define IQM_AF_SNS_LEN__W                                                   16
#define IQM_AF_SNS_LEN__M                                                   0xFFFF
#define IQM_AF_SNS_LEN__PRE                                                 0x0
#define   IQM_AF_SNS_LEN_QAM_B_64                                           0x400
#define   IQM_AF_SNS_LEN_QAM_B_256                                          0x400
#define   IQM_AF_SNS_LEN_ATV                                                0x0

#define IQM_AF_SNS_SENSE__A                                                 0x1870027
#define IQM_AF_SNS_SENSE__W                                                 16
#define IQM_AF_SNS_SENSE__M                                                 0xFFFF
#define IQM_AF_SNS_SENSE__PRE                                               0x0

#define IQM_AF_AGC_IF__A                                                    0x1870028
#define IQM_AF_AGC_IF__W                                                    15
#define IQM_AF_AGC_IF__M                                                    0x7FFF
#define IQM_AF_AGC_IF__PRE                                                  0x0

#define IQM_AF_AGC_RF__A                                                    0x1870029
#define IQM_AF_AGC_RF__W                                                    15
#define IQM_AF_AGC_RF__M                                                    0x7FFF
#define IQM_AF_AGC_RF__PRE                                                  0x0

#define IQM_AF_PGA_GAIN__A                                                  0x187002A
#define IQM_AF_PGA_GAIN__W                                                  4
#define IQM_AF_PGA_GAIN__M                                                  0xF
#define IQM_AF_PGA_GAIN__PRE                                                0x0

#define IQM_AF_PDREF__A                                                     0x187002B
#define IQM_AF_PDREF__W                                                     5
#define IQM_AF_PDREF__M                                                     0x1F
#define IQM_AF_PDREF__PRE                                                   0x0
#define   IQM_AF_PDREF_QAM_B_64                                             0xF
#define   IQM_AF_PDREF_QAM_B_256                                            0xF
#define   IQM_AF_PDREF_ATV                                                  0xF

#define IQM_AF_STDBY__A                                                     0x187002C
#define IQM_AF_STDBY__W                                                     6
#define IQM_AF_STDBY__M                                                     0x3F
#define IQM_AF_STDBY__PRE                                                   0x0

#define   IQM_AF_STDBY_STDBY_BIAS__B                                        0
#define   IQM_AF_STDBY_STDBY_BIAS__W                                        1
#define   IQM_AF_STDBY_STDBY_BIAS__M                                        0x1
#define   IQM_AF_STDBY_STDBY_BIAS__PRE                                      0x0
#define     IQM_AF_STDBY_STDBY_BIAS_ACTIVE                                  0x0
#define     IQM_AF_STDBY_STDBY_BIAS_STANDBY                                 0x1

#define   IQM_AF_STDBY_STDBY_ADC__B                                         1
#define   IQM_AF_STDBY_STDBY_ADC__W                                         1
#define   IQM_AF_STDBY_STDBY_ADC__M                                         0x2
#define   IQM_AF_STDBY_STDBY_ADC__PRE                                       0x0
#define     IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE                                0x0
#define     IQM_AF_STDBY_STDBY_ADC_A1_STANDBY                               0x2
#define     IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE                                0x2
#define     IQM_AF_STDBY_STDBY_ADC_A2_STANDBY                               0x0

#define   IQM_AF_STDBY_STDBY_AMP__B                                         2
#define   IQM_AF_STDBY_STDBY_AMP__W                                         1
#define   IQM_AF_STDBY_STDBY_AMP__M                                         0x4
#define   IQM_AF_STDBY_STDBY_AMP__PRE                                       0x0
#define     IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE                                0x0
#define     IQM_AF_STDBY_STDBY_AMP_A1_STANDBY                               0x4
#define     IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE                                0x4
#define     IQM_AF_STDBY_STDBY_AMP_A2_STANDBY                               0x0

#define   IQM_AF_STDBY_STDBY_PD__B                                          3
#define   IQM_AF_STDBY_STDBY_PD__W                                          1
#define   IQM_AF_STDBY_STDBY_PD__M                                          0x8
#define   IQM_AF_STDBY_STDBY_PD__PRE                                        0x0
#define     IQM_AF_STDBY_STDBY_PD_A1_ACTIVE                                 0x0
#define     IQM_AF_STDBY_STDBY_PD_A1_STANDBY                                0x8
#define     IQM_AF_STDBY_STDBY_PD_A2_ACTIVE                                 0x8
#define     IQM_AF_STDBY_STDBY_PD_A2_STANDBY                                0x0

#define   IQM_AF_STDBY_STDBY_TAGC_IF__B                                     4
#define   IQM_AF_STDBY_STDBY_TAGC_IF__W                                     1
#define   IQM_AF_STDBY_STDBY_TAGC_IF__M                                     0x10
#define   IQM_AF_STDBY_STDBY_TAGC_IF__PRE                                   0x0
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE                            0x0
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY                           0x10
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE                            0x10
#define     IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY                           0x0

#define   IQM_AF_STDBY_STDBY_TAGC_RF__B                                     5
#define   IQM_AF_STDBY_STDBY_TAGC_RF__W                                     1
#define   IQM_AF_STDBY_STDBY_TAGC_RF__M                                     0x20
#define   IQM_AF_STDBY_STDBY_TAGC_RF__PRE                                   0x0
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE                            0x0
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY                           0x20
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE                            0x20
#define     IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY                           0x0

#define IQM_AF_AMUX__A                                                      0x187002D
#define IQM_AF_AMUX__W                                                      2
#define IQM_AF_AMUX__M                                                      0x3
#define IQM_AF_AMUX__PRE                                                    0x0

#define IQM_AF_TST_AFEMAIN__A                                               0x187002E
#define IQM_AF_TST_AFEMAIN__W                                               8
#define IQM_AF_TST_AFEMAIN__M                                               0xFF
#define IQM_AF_TST_AFEMAIN__PRE                                             0x0

#define IQM_RT_RAM__A                                                       0x1880000

#define   IQM_RT_RAM_DLY__B                                                 0
#define   IQM_RT_RAM_DLY__W                                                 13
#define   IQM_RT_RAM_DLY__M                                                 0x1FFF
#define   IQM_RT_RAM_DLY__PRE                                               0x0

#define ORX_COMM_EXEC__A                                                    0x2000000
#define ORX_COMM_EXEC__W                                                    2
#define ORX_COMM_EXEC__M                                                    0x3
#define ORX_COMM_EXEC__PRE                                                  0x0
#define   ORX_COMM_EXEC_STOP                                                0x0
#define   ORX_COMM_EXEC_ACTIVE                                              0x1
#define   ORX_COMM_EXEC_HOLD                                                0x2

#define ORX_COMM_STATE__A                                                   0x2000001
#define ORX_COMM_STATE__W                                                   16
#define ORX_COMM_STATE__M                                                   0xFFFF
#define ORX_COMM_STATE__PRE                                                 0x0
#define ORX_COMM_MB__A                                                      0x2000002
#define ORX_COMM_MB__W                                                      16
#define ORX_COMM_MB__M                                                      0xFFFF
#define ORX_COMM_MB__PRE                                                    0x0
#define ORX_COMM_INT_REQ__A                                                 0x2000003
#define ORX_COMM_INT_REQ__W                                                 16
#define ORX_COMM_INT_REQ__M                                                 0xFFFF
#define ORX_COMM_INT_REQ__PRE                                               0x0
#define   ORX_COMM_INT_REQ_EQU_REQ__B                                       0
#define   ORX_COMM_INT_REQ_EQU_REQ__W                                       1
#define   ORX_COMM_INT_REQ_EQU_REQ__M                                       0x1
#define   ORX_COMM_INT_REQ_EQU_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_DDC_REQ__B                                       1
#define   ORX_COMM_INT_REQ_DDC_REQ__W                                       1
#define   ORX_COMM_INT_REQ_DDC_REQ__M                                       0x2
#define   ORX_COMM_INT_REQ_DDC_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_FWP_REQ__B                                       2
#define   ORX_COMM_INT_REQ_FWP_REQ__W                                       1
#define   ORX_COMM_INT_REQ_FWP_REQ__M                                       0x4
#define   ORX_COMM_INT_REQ_FWP_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_CON_REQ__B                                       3
#define   ORX_COMM_INT_REQ_CON_REQ__W                                       1
#define   ORX_COMM_INT_REQ_CON_REQ__M                                       0x8
#define   ORX_COMM_INT_REQ_CON_REQ__PRE                                     0x0
#define   ORX_COMM_INT_REQ_NSU_REQ__B                                       4
#define   ORX_COMM_INT_REQ_NSU_REQ__W                                       1
#define   ORX_COMM_INT_REQ_NSU_REQ__M                                       0x10
#define   ORX_COMM_INT_REQ_NSU_REQ__PRE                                     0x0

#define ORX_COMM_INT_STA__A                                                 0x2000005
#define ORX_COMM_INT_STA__W                                                 16
#define ORX_COMM_INT_STA__M                                                 0xFFFF
#define ORX_COMM_INT_STA__PRE                                               0x0
#define ORX_COMM_INT_MSK__A                                                 0x2000006
#define ORX_COMM_INT_MSK__W                                                 16
#define ORX_COMM_INT_MSK__M                                                 0xFFFF
#define ORX_COMM_INT_MSK__PRE                                               0x0
#define ORX_COMM_INT_STM__A                                                 0x2000007
#define ORX_COMM_INT_STM__W                                                 16
#define ORX_COMM_INT_STM__M                                                 0xFFFF
#define ORX_COMM_INT_STM__PRE                                               0x0

#define ORX_TOP_COMM_EXEC__A                                                0x2010000
#define ORX_TOP_COMM_EXEC__W                                                2
#define ORX_TOP_COMM_EXEC__M                                                0x3
#define ORX_TOP_COMM_EXEC__PRE                                              0x0
#define   ORX_TOP_COMM_EXEC_STOP                                            0x0
#define   ORX_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_TOP_COMM_EXEC_HOLD                                            0x2

#define ORX_TOP_COMM_KEY__A                                                 0x201000F
#define ORX_TOP_COMM_KEY__W                                                 16
#define ORX_TOP_COMM_KEY__M                                                 0xFFFF
#define ORX_TOP_COMM_KEY__PRE                                               0x0
#define   ORX_TOP_COMM_KEY_KEY                                              0xFABA

#define ORX_TOP_MDE_W__A                                                    0x2010010
#define ORX_TOP_MDE_W__W                                                    2
#define ORX_TOP_MDE_W__M                                                    0x3
#define ORX_TOP_MDE_W__PRE                                                  0x2
#define   ORX_TOP_MDE_W_RATE_1544KBPS                                       0x0
#define   ORX_TOP_MDE_W_RATE_3088KBPS                                       0x1
#define   ORX_TOP_MDE_W_RATE_2048KBPS_SQRT                                  0x2
#define   ORX_TOP_MDE_W_RATE_2048KBPS_RO                                    0x3

#define ORX_TOP_AIF_CTRL_W__A                                               0x2010011
#define ORX_TOP_AIF_CTRL_W__W                                               3
#define ORX_TOP_AIF_CTRL_W__M                                               0x7
#define ORX_TOP_AIF_CTRL_W__PRE                                             0x0
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B                                0
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W                                1
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M                                0x1
#define   ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE                              0x0
#define     ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE       0x0
#define     ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE       0x1
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B                                 1
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W                                 1
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M                                 0x2
#define   ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE                               0x0
#define     ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC            0x0
#define     ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC           0x2
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__B                                     2
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__W                                     1
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__M                                     0x4
#define   ORX_TOP_AIF_CTRL_W_INV_MSB__PRE                                   0x0
#define     ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC                 0x0
#define     ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC                    0x4

#define ORX_FWP_COMM_EXEC__A                                                0x2020000
#define ORX_FWP_COMM_EXEC__W                                                2
#define ORX_FWP_COMM_EXEC__M                                                0x3
#define ORX_FWP_COMM_EXEC__PRE                                              0x0
#define   ORX_FWP_COMM_EXEC_STOP                                            0x0
#define   ORX_FWP_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_FWP_COMM_EXEC_HOLD                                            0x2

#define ORX_FWP_COMM_MB__A                                                  0x2020002
#define ORX_FWP_COMM_MB__W                                                  8
#define ORX_FWP_COMM_MB__M                                                  0xFF
#define ORX_FWP_COMM_MB__PRE                                                0x0
#define   ORX_FWP_COMM_MB_CTL__B                                            0
#define   ORX_FWP_COMM_MB_CTL__W                                            1
#define   ORX_FWP_COMM_MB_CTL__M                                            0x1
#define   ORX_FWP_COMM_MB_CTL__PRE                                          0x0
#define     ORX_FWP_COMM_MB_CTL_OFF                                         0x0
#define     ORX_FWP_COMM_MB_CTL_ON                                          0x1
#define   ORX_FWP_COMM_MB_OBS__B                                            1
#define   ORX_FWP_COMM_MB_OBS__W                                            1
#define   ORX_FWP_COMM_MB_OBS__M                                            0x2
#define   ORX_FWP_COMM_MB_OBS__PRE                                          0x0
#define     ORX_FWP_COMM_MB_OBS_OFF                                         0x0
#define     ORX_FWP_COMM_MB_OBS_ON                                          0x2

#define   ORX_FWP_COMM_MB_CTL_MUX__B                                        2
#define   ORX_FWP_COMM_MB_CTL_MUX__W                                        3
#define   ORX_FWP_COMM_MB_CTL_MUX__M                                        0x1C
#define   ORX_FWP_COMM_MB_CTL_MUX__PRE                                      0x0

#define   ORX_FWP_COMM_MB_OBS_MUX__B                                        5
#define   ORX_FWP_COMM_MB_OBS_MUX__W                                        3
#define   ORX_FWP_COMM_MB_OBS_MUX__M                                        0xE0
#define   ORX_FWP_COMM_MB_OBS_MUX__PRE                                      0x0

#define ORX_FWP_AAG_LEN_W__A                                                0x2020010
#define ORX_FWP_AAG_LEN_W__W                                                16
#define ORX_FWP_AAG_LEN_W__M                                                0xFFFF
#define ORX_FWP_AAG_LEN_W__PRE                                              0x800

#define ORX_FWP_AAG_THR_W__A                                                0x2020011
#define ORX_FWP_AAG_THR_W__W                                                8
#define ORX_FWP_AAG_THR_W__M                                                0xFF
#define ORX_FWP_AAG_THR_W__PRE                                              0x50

#define ORX_FWP_AAG_THR_CNT_R__A                                            0x2020012
#define ORX_FWP_AAG_THR_CNT_R__W                                            16
#define ORX_FWP_AAG_THR_CNT_R__M                                            0xFFFF
#define ORX_FWP_AAG_THR_CNT_R__PRE                                          0x0

#define ORX_FWP_AAG_SNS_CNT_R__A                                            0x2020013
#define ORX_FWP_AAG_SNS_CNT_R__W                                            16
#define ORX_FWP_AAG_SNS_CNT_R__M                                            0xFFFF
#define ORX_FWP_AAG_SNS_CNT_R__PRE                                          0x0

#define ORX_FWP_PFI_A_W__A                                                  0x2020014
#define ORX_FWP_PFI_A_W__W                                                  8
#define ORX_FWP_PFI_A_W__M                                                  0xFF
#define ORX_FWP_PFI_A_W__PRE                                                0xB0
#define   ORX_FWP_PFI_A_W_RATE_2048KBPS                                     0xB0
#define   ORX_FWP_PFI_A_W_RATE_1544KBPS                                     0xA4
#define   ORX_FWP_PFI_A_W_RATE_3088KBPS                                     0xC0

#define ORX_FWP_PFI_B_W__A                                                  0x2020015
#define ORX_FWP_PFI_B_W__W                                                  8
#define ORX_FWP_PFI_B_W__M                                                  0xFF
#define ORX_FWP_PFI_B_W__PRE                                                0x9E
#define   ORX_FWP_PFI_B_W_RATE_2048KBPS                                     0x9E
#define   ORX_FWP_PFI_B_W_RATE_1544KBPS                                     0x94
#define   ORX_FWP_PFI_B_W_RATE_3088KBPS                                     0xB0

#define ORX_FWP_PFI_C_W__A                                                  0x2020016
#define ORX_FWP_PFI_C_W__W                                                  8
#define ORX_FWP_PFI_C_W__M                                                  0xFF
#define ORX_FWP_PFI_C_W__PRE                                                0x5C
#define   ORX_FWP_PFI_C_W_RATE_2048KBPS                                     0x5C
#define   ORX_FWP_PFI_C_W_RATE_1544KBPS                                     0x64
#define   ORX_FWP_PFI_C_W_RATE_3088KBPS                                     0x50

#define ORX_FWP_KR1_AMP_R__A                                                0x2020017
#define ORX_FWP_KR1_AMP_R__W                                                9
#define ORX_FWP_KR1_AMP_R__M                                                0x1FF
#define ORX_FWP_KR1_AMP_R__PRE                                              0x0

#define ORX_FWP_KR1_LDT_W__A                                                0x2020018
#define ORX_FWP_KR1_LDT_W__W                                                3
#define ORX_FWP_KR1_LDT_W__M                                                0x7
#define ORX_FWP_KR1_LDT_W__PRE                                              0x2
#define ORX_FWP_SRC_DGN_W__A                                                0x2020019
#define ORX_FWP_SRC_DGN_W__W                                                16
#define ORX_FWP_SRC_DGN_W__M                                                0xFFFF
#define ORX_FWP_SRC_DGN_W__PRE                                              0x1FF

#define   ORX_FWP_SRC_DGN_W_MANT__B                                         0
#define   ORX_FWP_SRC_DGN_W_MANT__W                                         9
#define   ORX_FWP_SRC_DGN_W_MANT__M                                         0x1FF
#define   ORX_FWP_SRC_DGN_W_MANT__PRE                                       0x1FF

#define   ORX_FWP_SRC_DGN_W_EXP__B                                          12
#define   ORX_FWP_SRC_DGN_W_EXP__W                                          4
#define   ORX_FWP_SRC_DGN_W_EXP__M                                          0xF000
#define   ORX_FWP_SRC_DGN_W_EXP__PRE                                        0x0

#define ORX_FWP_NYQ_ADR_W__A                                                0x202001A
#define ORX_FWP_NYQ_ADR_W__W                                                5
#define ORX_FWP_NYQ_ADR_W__M                                                0x1F
#define ORX_FWP_NYQ_ADR_W__PRE                                              0x1F

#define ORX_FWP_NYQ_COF_RW__A                                               0x202001B
#define ORX_FWP_NYQ_COF_RW__W                                               10
#define ORX_FWP_NYQ_COF_RW__M                                               0x3FF
#define ORX_FWP_NYQ_COF_RW__PRE                                             0x0

#define ORX_FWP_IQM_FRQ_W__A                                                0x202001C
#define ORX_FWP_IQM_FRQ_W__W                                                16
#define ORX_FWP_IQM_FRQ_W__M                                                0xFFFF
#define ORX_FWP_IQM_FRQ_W__PRE                                              0x4301

#define ORX_EQU_COMM_EXEC__A                                                0x2030000
#define ORX_EQU_COMM_EXEC__W                                                2
#define ORX_EQU_COMM_EXEC__M                                                0x3
#define ORX_EQU_COMM_EXEC__PRE                                              0x0
#define   ORX_EQU_COMM_EXEC_STOP                                            0x0
#define   ORX_EQU_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_EQU_COMM_EXEC_HOLD                                            0x2

#define ORX_EQU_COMM_MB__A                                                  0x2030002
#define ORX_EQU_COMM_MB__W                                                  8
#define ORX_EQU_COMM_MB__M                                                  0xFF
#define ORX_EQU_COMM_MB__PRE                                                0x0
#define   ORX_EQU_COMM_MB_CTL__B                                            0
#define   ORX_EQU_COMM_MB_CTL__W                                            1
#define   ORX_EQU_COMM_MB_CTL__M                                            0x1
#define   ORX_EQU_COMM_MB_CTL__PRE                                          0x0
#define     ORX_EQU_COMM_MB_CTL_OFF                                         0x0
#define     ORX_EQU_COMM_MB_CTL_ON                                          0x1
#define   ORX_EQU_COMM_MB_OBS__B                                            1
#define   ORX_EQU_COMM_MB_OBS__W                                            1
#define   ORX_EQU_COMM_MB_OBS__M                                            0x2
#define   ORX_EQU_COMM_MB_OBS__PRE                                          0x0
#define     ORX_EQU_COMM_MB_OBS_OFF                                         0x0
#define     ORX_EQU_COMM_MB_OBS_ON                                          0x2

#define   ORX_EQU_COMM_MB_CTL_MUX__B                                        2
#define   ORX_EQU_COMM_MB_CTL_MUX__W                                        3
#define   ORX_EQU_COMM_MB_CTL_MUX__M                                        0x1C
#define   ORX_EQU_COMM_MB_CTL_MUX__PRE                                      0x0

#define   ORX_EQU_COMM_MB_OBS_MUX__B                                        5
#define   ORX_EQU_COMM_MB_OBS_MUX__W                                        3
#define   ORX_EQU_COMM_MB_OBS_MUX__M                                        0xE0
#define   ORX_EQU_COMM_MB_OBS_MUX__PRE                                      0x0

#define ORX_EQU_COMM_INT_REQ__A                                             0x2030003
#define ORX_EQU_COMM_INT_REQ__W                                             1
#define ORX_EQU_COMM_INT_REQ__M                                             0x1
#define ORX_EQU_COMM_INT_REQ__PRE                                           0x0
#define ORX_EQU_COMM_INT_STA__A                                             0x2030005
#define ORX_EQU_COMM_INT_STA__W                                             2
#define ORX_EQU_COMM_INT_STA__M                                             0x3
#define ORX_EQU_COMM_INT_STA__PRE                                           0x0

#define   ORX_EQU_COMM_INT_STA_FFF_READ__B                                  0
#define   ORX_EQU_COMM_INT_STA_FFF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STA_FFF_READ__M                                  0x1
#define   ORX_EQU_COMM_INT_STA_FFF_READ__PRE                                0x0

#define   ORX_EQU_COMM_INT_STA_FBF_READ__B                                  1
#define   ORX_EQU_COMM_INT_STA_FBF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STA_FBF_READ__M                                  0x2
#define   ORX_EQU_COMM_INT_STA_FBF_READ__PRE                                0x0

#define ORX_EQU_COMM_INT_MSK__A                                             0x2030006
#define ORX_EQU_COMM_INT_MSK__W                                             2
#define ORX_EQU_COMM_INT_MSK__M                                             0x3
#define ORX_EQU_COMM_INT_MSK__PRE                                           0x0
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__B                                  0
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__W                                  1
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__M                                  0x1
#define   ORX_EQU_COMM_INT_MSK_FFF_READ__PRE                                0x0
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__B                                  1
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__W                                  1
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__M                                  0x2
#define   ORX_EQU_COMM_INT_MSK_FBF_READ__PRE                                0x0

#define ORX_EQU_COMM_INT_STM__A                                             0x2030007
#define ORX_EQU_COMM_INT_STM__W                                             2
#define ORX_EQU_COMM_INT_STM__M                                             0x3
#define ORX_EQU_COMM_INT_STM__PRE                                           0x0
#define   ORX_EQU_COMM_INT_STM_FFF_READ__B                                  0
#define   ORX_EQU_COMM_INT_STM_FFF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STM_FFF_READ__M                                  0x1
#define   ORX_EQU_COMM_INT_STM_FFF_READ__PRE                                0x0
#define   ORX_EQU_COMM_INT_STM_FBF_READ__B                                  1
#define   ORX_EQU_COMM_INT_STM_FBF_READ__W                                  1
#define   ORX_EQU_COMM_INT_STM_FBF_READ__M                                  0x2
#define   ORX_EQU_COMM_INT_STM_FBF_READ__PRE                                0x0

#define ORX_EQU_FFF_SCL_W__A                                                0x2030010
#define ORX_EQU_FFF_SCL_W__W                                                1
#define ORX_EQU_FFF_SCL_W__M                                                0x1
#define ORX_EQU_FFF_SCL_W__PRE                                              0x0
#define   ORX_EQU_FFF_SCL_W_SCALE_GAIN_1                                    0x0
#define   ORX_EQU_FFF_SCL_W_SCALE_GAIN_2                                    0x1

#define ORX_EQU_FFF_UPD_W__A                                                0x2030011
#define ORX_EQU_FFF_UPD_W__W                                                1
#define ORX_EQU_FFF_UPD_W__M                                                0x1
#define ORX_EQU_FFF_UPD_W__PRE                                              0x0
#define   ORX_EQU_FFF_UPD_W_NO_UPDATE                                       0x0
#define   ORX_EQU_FFF_UPD_W_LMS_UPDATE                                      0x1

#define ORX_EQU_FFF_STP_W__A                                                0x2030012
#define ORX_EQU_FFF_STP_W__W                                                3
#define ORX_EQU_FFF_STP_W__M                                                0x7
#define ORX_EQU_FFF_STP_W__PRE                                              0x2

#define ORX_EQU_FFF_LEA_W__A                                                0x2030013
#define ORX_EQU_FFF_LEA_W__W                                                4
#define ORX_EQU_FFF_LEA_W__M                                                0xF
#define ORX_EQU_FFF_LEA_W__PRE                                              0x4

#define ORX_EQU_FFF_RWT_W__A                                                0x2030014
#define ORX_EQU_FFF_RWT_W__W                                                2
#define ORX_EQU_FFF_RWT_W__M                                                0x3
#define ORX_EQU_FFF_RWT_W__PRE                                              0x0

#define ORX_EQU_FFF_C0RE_RW__A                                              0x2030015
#define ORX_EQU_FFF_C0RE_RW__W                                              12
#define ORX_EQU_FFF_C0RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C0RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C0IM_RW__A                                              0x2030016
#define ORX_EQU_FFF_C0IM_RW__W                                              12
#define ORX_EQU_FFF_C0IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C0IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C1RE_RW__A                                              0x2030017
#define ORX_EQU_FFF_C1RE_RW__W                                              12
#define ORX_EQU_FFF_C1RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C1RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C1IM_RW__A                                              0x2030018
#define ORX_EQU_FFF_C1IM_RW__W                                              12
#define ORX_EQU_FFF_C1IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C1IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C2RE_RW__A                                              0x2030019
#define ORX_EQU_FFF_C2RE_RW__W                                              12
#define ORX_EQU_FFF_C2RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C2RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C2IM_RW__A                                              0x203001A
#define ORX_EQU_FFF_C2IM_RW__W                                              12
#define ORX_EQU_FFF_C2IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C2IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C3RE_RW__A                                              0x203001B
#define ORX_EQU_FFF_C3RE_RW__W                                              12
#define ORX_EQU_FFF_C3RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C3RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C3IM_RW__A                                              0x203001C
#define ORX_EQU_FFF_C3IM_RW__W                                              12
#define ORX_EQU_FFF_C3IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C3IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C4RE_RW__A                                              0x203001D
#define ORX_EQU_FFF_C4RE_RW__W                                              12
#define ORX_EQU_FFF_C4RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C4RE_RW__PRE                                            0x400

#define ORX_EQU_FFF_C4IM_RW__A                                              0x203001E
#define ORX_EQU_FFF_C4IM_RW__W                                              12
#define ORX_EQU_FFF_C4IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C4IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C5RE_RW__A                                              0x203001F
#define ORX_EQU_FFF_C5RE_RW__W                                              12
#define ORX_EQU_FFF_C5RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C5RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C5IM_RW__A                                              0x2030020
#define ORX_EQU_FFF_C5IM_RW__W                                              12
#define ORX_EQU_FFF_C5IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C5IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C6RE_RW__A                                              0x2030021
#define ORX_EQU_FFF_C6RE_RW__W                                              12
#define ORX_EQU_FFF_C6RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C6RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C6IM_RW__A                                              0x2030022
#define ORX_EQU_FFF_C6IM_RW__W                                              12
#define ORX_EQU_FFF_C6IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C6IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C7RE_RW__A                                              0x2030023
#define ORX_EQU_FFF_C7RE_RW__W                                              12
#define ORX_EQU_FFF_C7RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C7RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C7IM_RW__A                                              0x2030024
#define ORX_EQU_FFF_C7IM_RW__W                                              12
#define ORX_EQU_FFF_C7IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C7IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C8RE_RW__A                                              0x2030025
#define ORX_EQU_FFF_C8RE_RW__W                                              12
#define ORX_EQU_FFF_C8RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C8RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C8IM_RW__A                                              0x2030026
#define ORX_EQU_FFF_C8IM_RW__W                                              12
#define ORX_EQU_FFF_C8IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C8IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C9RE_RW__A                                              0x2030027
#define ORX_EQU_FFF_C9RE_RW__W                                              12
#define ORX_EQU_FFF_C9RE_RW__M                                              0xFFF
#define ORX_EQU_FFF_C9RE_RW__PRE                                            0x0

#define ORX_EQU_FFF_C9IM_RW__A                                              0x2030028
#define ORX_EQU_FFF_C9IM_RW__W                                              12
#define ORX_EQU_FFF_C9IM_RW__M                                              0xFFF
#define ORX_EQU_FFF_C9IM_RW__PRE                                            0x0

#define ORX_EQU_FFF_C10RE_RW__A                                             0x2030029
#define ORX_EQU_FFF_C10RE_RW__W                                             12
#define ORX_EQU_FFF_C10RE_RW__M                                             0xFFF
#define ORX_EQU_FFF_C10RE_RW__PRE                                           0x0

#define ORX_EQU_FFF_C10IM_RW__A                                             0x203002A
#define ORX_EQU_FFF_C10IM_RW__W                                             12
#define ORX_EQU_FFF_C10IM_RW__M                                             0xFFF
#define ORX_EQU_FFF_C10IM_RW__PRE                                           0x0

#define ORX_EQU_MXB_SEL_W__A                                                0x203002B
#define ORX_EQU_MXB_SEL_W__W                                                1
#define ORX_EQU_MXB_SEL_W__M                                                0x1
#define ORX_EQU_MXB_SEL_W__PRE                                              0x0
#define   ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS                               0x0
#define   ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS                                 0x1

#define ORX_EQU_FBF_UPD_W__A                                                0x203002C
#define ORX_EQU_FBF_UPD_W__W                                                1
#define ORX_EQU_FBF_UPD_W__M                                                0x1
#define ORX_EQU_FBF_UPD_W__PRE                                              0x0
#define   ORX_EQU_FBF_UPD_W_NO_UPDATE                                       0x0
#define   ORX_EQU_FBF_UPD_W_LMS_UPDATE                                      0x1

#define ORX_EQU_FBF_STP_W__A                                                0x203002D
#define ORX_EQU_FBF_STP_W__W                                                3
#define ORX_EQU_FBF_STP_W__M                                                0x7
#define ORX_EQU_FBF_STP_W__PRE                                              0x2

#define ORX_EQU_FBF_LEA_W__A                                                0x203002E
#define ORX_EQU_FBF_LEA_W__W                                                4
#define ORX_EQU_FBF_LEA_W__M                                                0xF
#define ORX_EQU_FBF_LEA_W__PRE                                              0x4

#define ORX_EQU_FBF_RWT_W__A                                                0x203002F
#define ORX_EQU_FBF_RWT_W__W                                                2
#define ORX_EQU_FBF_RWT_W__M                                                0x3
#define ORX_EQU_FBF_RWT_W__PRE                                              0x0

#define ORX_EQU_FBF_C0RE_RW__A                                              0x2030030
#define ORX_EQU_FBF_C0RE_RW__W                                              12
#define ORX_EQU_FBF_C0RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C0RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C0IM_RW__A                                              0x2030031
#define ORX_EQU_FBF_C0IM_RW__W                                              12
#define ORX_EQU_FBF_C0IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C0IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C1RE_RW__A                                              0x2030032
#define ORX_EQU_FBF_C1RE_RW__W                                              12
#define ORX_EQU_FBF_C1RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C1RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C1IM_RW__A                                              0x2030033
#define ORX_EQU_FBF_C1IM_RW__W                                              12
#define ORX_EQU_FBF_C1IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C1IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C2RE_RW__A                                              0x2030034
#define ORX_EQU_FBF_C2RE_RW__W                                              12
#define ORX_EQU_FBF_C2RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C2RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C2IM_RW__A                                              0x2030035
#define ORX_EQU_FBF_C2IM_RW__W                                              12
#define ORX_EQU_FBF_C2IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C2IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C3RE_RW__A                                              0x2030036
#define ORX_EQU_FBF_C3RE_RW__W                                              12
#define ORX_EQU_FBF_C3RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C3RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C3IM_RW__A                                              0x2030037
#define ORX_EQU_FBF_C3IM_RW__W                                              12
#define ORX_EQU_FBF_C3IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C3IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C4RE_RW__A                                              0x2030038
#define ORX_EQU_FBF_C4RE_RW__W                                              12
#define ORX_EQU_FBF_C4RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C4RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C4IM_RW__A                                              0x2030039
#define ORX_EQU_FBF_C4IM_RW__W                                              12
#define ORX_EQU_FBF_C4IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C4IM_RW__PRE                                            0x0

#define ORX_EQU_FBF_C5RE_RW__A                                              0x203003A
#define ORX_EQU_FBF_C5RE_RW__W                                              12
#define ORX_EQU_FBF_C5RE_RW__M                                              0xFFF
#define ORX_EQU_FBF_C5RE_RW__PRE                                            0x0

#define ORX_EQU_FBF_C5IM_RW__A                                              0x203003B
#define ORX_EQU_FBF_C5IM_RW__W                                              12
#define ORX_EQU_FBF_C5IM_RW__M                                              0xFFF
#define ORX_EQU_FBF_C5IM_RW__PRE                                            0x0

#define ORX_EQU_ERR_SEL_W__A                                                0x203003C
#define ORX_EQU_ERR_SEL_W__W                                                1
#define ORX_EQU_ERR_SEL_W__M                                                0x1
#define ORX_EQU_ERR_SEL_W__PRE                                              0x0
#define   ORX_EQU_ERR_SEL_W_CMA_ERROR                                       0x0
#define   ORX_EQU_ERR_SEL_W_DDA_ERROR                                       0x1

#define ORX_EQU_ERR_TIS_W__A                                                0x203003D
#define ORX_EQU_ERR_TIS_W__W                                                1
#define ORX_EQU_ERR_TIS_W__M                                                0x1
#define ORX_EQU_ERR_TIS_W__PRE                                              0x0
#define   ORX_EQU_ERR_TIS_W_CMA_SIGNALS                                     0x0
#define   ORX_EQU_ERR_TIS_W_DDA_SIGNALS                                     0x1

#define ORX_EQU_ERR_EDI_R__A                                                0x203003E
#define ORX_EQU_ERR_EDI_R__W                                                5
#define ORX_EQU_ERR_EDI_R__M                                                0x1F
#define ORX_EQU_ERR_EDI_R__PRE                                              0xF

#define ORX_EQU_ERR_EDQ_R__A                                                0x203003F
#define ORX_EQU_ERR_EDQ_R__W                                                5
#define ORX_EQU_ERR_EDQ_R__M                                                0x1F
#define ORX_EQU_ERR_EDQ_R__PRE                                              0xF

#define ORX_EQU_ERR_ECI_R__A                                                0x2030040
#define ORX_EQU_ERR_ECI_R__W                                                5
#define ORX_EQU_ERR_ECI_R__M                                                0x1F
#define ORX_EQU_ERR_ECI_R__PRE                                              0xF

#define ORX_EQU_ERR_ECQ_R__A                                                0x2030041
#define ORX_EQU_ERR_ECQ_R__W                                                5
#define ORX_EQU_ERR_ECQ_R__M                                                0x1F
#define ORX_EQU_ERR_ECQ_R__PRE                                              0xF

#define ORX_EQU_MER_MER_R__A                                                0x2030042
#define ORX_EQU_MER_MER_R__W                                                6
#define ORX_EQU_MER_MER_R__M                                                0x3F
#define ORX_EQU_MER_MER_R__PRE                                              0x3F

#define ORX_EQU_MER_LDT_W__A                                                0x2030043
#define ORX_EQU_MER_LDT_W__W                                                3
#define ORX_EQU_MER_LDT_W__M                                                0x7
#define ORX_EQU_MER_LDT_W__PRE                                              0x4

#define ORX_EQU_SYN_LEN_W__A                                                0x2030044
#define ORX_EQU_SYN_LEN_W__W                                                16
#define ORX_EQU_SYN_LEN_W__M                                                0xFFFF
#define ORX_EQU_SYN_LEN_W__PRE                                              0x0

#define ORX_DDC_COMM_EXEC__A                                                0x2040000
#define ORX_DDC_COMM_EXEC__W                                                2
#define ORX_DDC_COMM_EXEC__M                                                0x3
#define ORX_DDC_COMM_EXEC__PRE                                              0x0
#define   ORX_DDC_COMM_EXEC_STOP                                            0x0
#define   ORX_DDC_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_DDC_COMM_EXEC_HOLD                                            0x2

#define ORX_DDC_COMM_MB__A                                                  0x2040002
#define ORX_DDC_COMM_MB__W                                                  6
#define ORX_DDC_COMM_MB__M                                                  0x3F
#define ORX_DDC_COMM_MB__PRE                                                0x0
#define   ORX_DDC_COMM_MB_CTL__B                                            0
#define   ORX_DDC_COMM_MB_CTL__W                                            1
#define   ORX_DDC_COMM_MB_CTL__M                                            0x1
#define   ORX_DDC_COMM_MB_CTL__PRE                                          0x0
#define     ORX_DDC_COMM_MB_CTL_OFF                                         0x0
#define     ORX_DDC_COMM_MB_CTL_ON                                          0x1
#define   ORX_DDC_COMM_MB_OBS__B                                            1
#define   ORX_DDC_COMM_MB_OBS__W                                            1
#define   ORX_DDC_COMM_MB_OBS__M                                            0x2
#define   ORX_DDC_COMM_MB_OBS__PRE                                          0x0
#define     ORX_DDC_COMM_MB_OBS_OFF                                         0x0
#define     ORX_DDC_COMM_MB_OBS_ON                                          0x2

#define   ORX_DDC_COMM_MB_CTL_MUX__B                                        2
#define   ORX_DDC_COMM_MB_CTL_MUX__W                                        2
#define   ORX_DDC_COMM_MB_CTL_MUX__M                                        0xC
#define   ORX_DDC_COMM_MB_CTL_MUX__PRE                                      0x0

#define   ORX_DDC_COMM_MB_OBS_MUX__B                                        4
#define   ORX_DDC_COMM_MB_OBS_MUX__W                                        2
#define   ORX_DDC_COMM_MB_OBS_MUX__M                                        0x30
#define   ORX_DDC_COMM_MB_OBS_MUX__PRE                                      0x0

#define ORX_DDC_COMM_INT_REQ__A                                             0x2040003
#define ORX_DDC_COMM_INT_REQ__W                                             1
#define ORX_DDC_COMM_INT_REQ__M                                             0x1
#define ORX_DDC_COMM_INT_REQ__PRE                                           0x0
#define ORX_DDC_COMM_INT_STA__A                                             0x2040005
#define ORX_DDC_COMM_INT_STA__W                                             1
#define ORX_DDC_COMM_INT_STA__M                                             0x1
#define ORX_DDC_COMM_INT_STA__PRE                                           0x0
#define ORX_DDC_COMM_INT_MSK__A                                             0x2040006
#define ORX_DDC_COMM_INT_MSK__W                                             1
#define ORX_DDC_COMM_INT_MSK__M                                             0x1
#define ORX_DDC_COMM_INT_MSK__PRE                                           0x0
#define ORX_DDC_COMM_INT_STM__A                                             0x2040007
#define ORX_DDC_COMM_INT_STM__W                                             1
#define ORX_DDC_COMM_INT_STM__M                                             0x1
#define ORX_DDC_COMM_INT_STM__PRE                                           0x0
#define ORX_DDC_DEC_MAP_W__A                                                0x2040010
#define ORX_DDC_DEC_MAP_W__W                                                9
#define ORX_DDC_DEC_MAP_W__M                                                0x1FF
#define ORX_DDC_DEC_MAP_W__PRE                                              0x178

#define   ORX_DDC_DEC_MAP_W_QUADR0__B                                       0
#define   ORX_DDC_DEC_MAP_W_QUADR0__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR0__M                                       0x3
#define   ORX_DDC_DEC_MAP_W_QUADR0__PRE                                     0x0
#define     ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT                         0x0
#define     ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE                       0x0

#define   ORX_DDC_DEC_MAP_W_QUADR1__B                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR1__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR1__M                                       0xC
#define   ORX_DDC_DEC_MAP_W_QUADR1__PRE                                     0x8
#define     ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT                         0x8
#define     ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE                       0x4

#define   ORX_DDC_DEC_MAP_W_QUADR2__B                                       4
#define   ORX_DDC_DEC_MAP_W_QUADR2__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR2__M                                       0x30
#define   ORX_DDC_DEC_MAP_W_QUADR2__PRE                                     0x30
#define     ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT                         0x30
#define     ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE                       0x30

#define   ORX_DDC_DEC_MAP_W_QUADR3__B                                       6
#define   ORX_DDC_DEC_MAP_W_QUADR3__W                                       2
#define   ORX_DDC_DEC_MAP_W_QUADR3__M                                       0xC0
#define   ORX_DDC_DEC_MAP_W_QUADR3__PRE                                     0x40
#define     ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT                         0x40
#define     ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE                       0x80
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__B                                   8
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__W                                   1
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__M                                   0x100
#define   ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE                                 0x100
#define     ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING                  0x0
#define     ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING                      0x100

#define ORX_DDC_OFO_SET_W__A                                                0x2040011
#define ORX_DDC_OFO_SET_W__W                                                16
#define ORX_DDC_OFO_SET_W__M                                                0xFFFF
#define ORX_DDC_OFO_SET_W__PRE                                              0x1402

#define   ORX_DDC_OFO_SET_W_PHASE__B                                        0
#define   ORX_DDC_OFO_SET_W_PHASE__W                                        7
#define   ORX_DDC_OFO_SET_W_PHASE__M                                        0x7F
#define   ORX_DDC_OFO_SET_W_PHASE__PRE                                      0x2

#define   ORX_DDC_OFO_SET_W_CRXHITIME__B                                    7
#define   ORX_DDC_OFO_SET_W_CRXHITIME__W                                    7
#define   ORX_DDC_OFO_SET_W_CRXHITIME__M                                    0x3F80
#define   ORX_DDC_OFO_SET_W_CRXHITIME__PRE                                  0x1400

#define   ORX_DDC_OFO_SET_W_CRXINV__B                                       14
#define   ORX_DDC_OFO_SET_W_CRXINV__W                                       1
#define   ORX_DDC_OFO_SET_W_CRXINV__M                                       0x4000
#define   ORX_DDC_OFO_SET_W_CRXINV__PRE                                     0x0

#define   ORX_DDC_OFO_SET_W_DISABLE__B                                      15
#define   ORX_DDC_OFO_SET_W_DISABLE__W                                      1
#define   ORX_DDC_OFO_SET_W_DISABLE__M                                      0x8000
#define   ORX_DDC_OFO_SET_W_DISABLE__PRE                                    0x0

#define ORX_CON_COMM_EXEC__A                                                0x2050000
#define ORX_CON_COMM_EXEC__W                                                2
#define ORX_CON_COMM_EXEC__M                                                0x3
#define ORX_CON_COMM_EXEC__PRE                                              0x0
#define   ORX_CON_COMM_EXEC_STOP                                            0x0
#define   ORX_CON_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_CON_COMM_EXEC_HOLD                                            0x2

#define ORX_CON_LDT_W__A                                                    0x2050010
#define ORX_CON_LDT_W__W                                                    3
#define ORX_CON_LDT_W__M                                                    0x7
#define ORX_CON_LDT_W__PRE                                                  0x3

#define   ORX_CON_LDT_W_CON_LDT_W__B                                        0
#define   ORX_CON_LDT_W_CON_LDT_W__W                                        3
#define   ORX_CON_LDT_W_CON_LDT_W__M                                        0x7
#define   ORX_CON_LDT_W_CON_LDT_W__PRE                                      0x3

#define ORX_CON_RST_W__A                                                    0x2050011
#define ORX_CON_RST_W__W                                                    4
#define ORX_CON_RST_W__M                                                    0xF
#define ORX_CON_RST_W__PRE                                                  0x0

#define   ORX_CON_RST_W_CPH__B                                              0
#define   ORX_CON_RST_W_CPH__W                                              1
#define   ORX_CON_RST_W_CPH__M                                              0x1
#define   ORX_CON_RST_W_CPH__PRE                                            0x0

#define   ORX_CON_RST_W_CTI__B                                              1
#define   ORX_CON_RST_W_CTI__W                                              1
#define   ORX_CON_RST_W_CTI__M                                              0x2
#define   ORX_CON_RST_W_CTI__PRE                                            0x0

#define   ORX_CON_RST_W_KRN__B                                              2
#define   ORX_CON_RST_W_KRN__W                                              1
#define   ORX_CON_RST_W_KRN__M                                              0x4
#define   ORX_CON_RST_W_KRN__PRE                                            0x0

#define   ORX_CON_RST_W_KRP__B                                              3
#define   ORX_CON_RST_W_KRP__W                                              1
#define   ORX_CON_RST_W_KRP__M                                              0x8
#define   ORX_CON_RST_W_KRP__PRE                                            0x0

#define ORX_CON_CPH_PHI_R__A                                                0x2050012
#define ORX_CON_CPH_PHI_R__W                                                16
#define ORX_CON_CPH_PHI_R__M                                                0xFFFF
#define ORX_CON_CPH_PHI_R__PRE                                              0x0

#define ORX_CON_CPH_FRQ_R__A                                                0x2050013
#define ORX_CON_CPH_FRQ_R__W                                                16
#define ORX_CON_CPH_FRQ_R__M                                                0xFFFF
#define ORX_CON_CPH_FRQ_R__PRE                                              0x0

#define ORX_CON_CPH_AMP_R__A                                                0x2050014
#define ORX_CON_CPH_AMP_R__W                                                16
#define ORX_CON_CPH_AMP_R__M                                                0xFFFF
#define ORX_CON_CPH_AMP_R__PRE                                              0x0

#define ORX_CON_CPH_KDF_W__A                                                0x2050015
#define ORX_CON_CPH_KDF_W__W                                                4
#define ORX_CON_CPH_KDF_W__M                                                0xF
#define ORX_CON_CPH_KDF_W__PRE                                              0x0

#define ORX_CON_CPH_KPF_W__A                                                0x2050016
#define ORX_CON_CPH_KPF_W__W                                                4
#define ORX_CON_CPH_KPF_W__M                                                0xF
#define ORX_CON_CPH_KPF_W__PRE                                              0x0

#define ORX_CON_CPH_KIF_W__A                                                0x2050017
#define ORX_CON_CPH_KIF_W__W                                                4
#define ORX_CON_CPH_KIF_W__M                                                0xF
#define ORX_CON_CPH_KIF_W__PRE                                              0x0
#define ORX_CON_CPH_APT_W__A                                                0x2050018
#define ORX_CON_CPH_APT_W__W                                                16
#define ORX_CON_CPH_APT_W__M                                                0xFFFF
#define ORX_CON_CPH_APT_W__PRE                                              0x804

#define   ORX_CON_CPH_APT_W_PTH__B                                          0
#define   ORX_CON_CPH_APT_W_PTH__W                                          8
#define   ORX_CON_CPH_APT_W_PTH__M                                          0xFF
#define   ORX_CON_CPH_APT_W_PTH__PRE                                        0x4

#define   ORX_CON_CPH_APT_W_ATH__B                                          8
#define   ORX_CON_CPH_APT_W_ATH__W                                          8
#define   ORX_CON_CPH_APT_W_ATH__M                                          0xFF00
#define   ORX_CON_CPH_APT_W_ATH__PRE                                        0x800

#define ORX_CON_CPH_WLC_W__A                                                0x2050019
#define ORX_CON_CPH_WLC_W__W                                                8
#define ORX_CON_CPH_WLC_W__M                                                0xFF
#define ORX_CON_CPH_WLC_W__PRE                                              0x81

#define   ORX_CON_CPH_WLC_W_LATC__B                                         0
#define   ORX_CON_CPH_WLC_W_LATC__W                                         4
#define   ORX_CON_CPH_WLC_W_LATC__M                                         0xF
#define   ORX_CON_CPH_WLC_W_LATC__PRE                                       0x1

#define   ORX_CON_CPH_WLC_W_WLIM__B                                         4
#define   ORX_CON_CPH_WLC_W_WLIM__W                                         4
#define   ORX_CON_CPH_WLC_W_WLIM__M                                         0xF0
#define   ORX_CON_CPH_WLC_W_WLIM__PRE                                       0x80

#define ORX_CON_CPH_DLY_W__A                                                0x205001A
#define ORX_CON_CPH_DLY_W__W                                                3
#define ORX_CON_CPH_DLY_W__M                                                0x7
#define ORX_CON_CPH_DLY_W__PRE                                              0x4

#define ORX_CON_CPH_TCL_W__A                                                0x205001B
#define ORX_CON_CPH_TCL_W__W                                                3
#define ORX_CON_CPH_TCL_W__M                                                0x7
#define ORX_CON_CPH_TCL_W__PRE                                              0x3

#define ORX_CON_KRP_AMP_R__A                                                0x205001C
#define ORX_CON_KRP_AMP_R__W                                                9
#define ORX_CON_KRP_AMP_R__M                                                0x1FF
#define ORX_CON_KRP_AMP_R__PRE                                              0x0

#define ORX_CON_KRN_AMP_R__A                                                0x205001D
#define ORX_CON_KRN_AMP_R__W                                                9
#define ORX_CON_KRN_AMP_R__M                                                0x1FF
#define ORX_CON_KRN_AMP_R__PRE                                              0x0

#define ORX_CON_CTI_DTI_R__A                                                0x205001E
#define ORX_CON_CTI_DTI_R__W                                                16
#define ORX_CON_CTI_DTI_R__M                                                0xFFFF
#define ORX_CON_CTI_DTI_R__PRE                                              0x0

#define ORX_CON_CTI_KDT_W__A                                                0x205001F
#define ORX_CON_CTI_KDT_W__W                                                4
#define ORX_CON_CTI_KDT_W__M                                                0xF
#define ORX_CON_CTI_KDT_W__PRE                                              0x4

#define ORX_CON_CTI_KPT_W__A                                                0x2050020
#define ORX_CON_CTI_KPT_W__W                                                4
#define ORX_CON_CTI_KPT_W__M                                                0xF
#define ORX_CON_CTI_KPT_W__PRE                                              0x3

#define ORX_CON_CTI_KIT_W__A                                                0x2050021
#define ORX_CON_CTI_KIT_W__W                                                4
#define ORX_CON_CTI_KIT_W__M                                                0xF
#define ORX_CON_CTI_KIT_W__PRE                                              0xB

#define ORX_CON_CTI_TAT_W__A                                                0x2050022
#define ORX_CON_CTI_TAT_W__W                                                4
#define ORX_CON_CTI_TAT_W__M                                                0xF
#define ORX_CON_CTI_TAT_W__PRE                                              0x3

#define ORX_NSU_COMM_EXEC__A                                                0x2060000
#define ORX_NSU_COMM_EXEC__W                                                2
#define ORX_NSU_COMM_EXEC__M                                                0x3
#define ORX_NSU_COMM_EXEC__PRE                                              0x0
#define   ORX_NSU_COMM_EXEC_STOP                                            0x0
#define   ORX_NSU_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_NSU_COMM_EXEC_HOLD                                            0x2

#define ORX_NSU_AOX_STDBY_W__A                                              0x2060010
#define ORX_NSU_AOX_STDBY_W__W                                              8
#define ORX_NSU_AOX_STDBY_W__M                                              0xFF
#define ORX_NSU_AOX_STDBY_W__PRE                                            0x0

#define   ORX_NSU_AOX_STDBY_W_STDBYADC__B                                   0
#define   ORX_NSU_AOX_STDBY_W_STDBYADC__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYADC__M                                   0x1
#define   ORX_NSU_AOX_STDBY_W_STDBYADC__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF                             0x1
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON                              0x1

#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__B                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__M                                   0x2
#define   ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF                             0x2
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON                              0x2

#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__B                                  2
#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__W                                  1
#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__M                                  0x4
#define   ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE                                0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF                            0x4
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF                            0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON                             0x4

#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__B                                   3
#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__M                                   0x8
#define   ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF                             0x8
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON                              0x8

#define   ORX_NSU_AOX_STDBY_W_STDBYPD__B                                    4
#define   ORX_NSU_AOX_STDBY_W_STDBYPD__W                                    1
#define   ORX_NSU_AOX_STDBY_W_STDBYPD__M                                    0x10
#define   ORX_NSU_AOX_STDBY_W_STDBYPD__PRE                                  0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON                               0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF                              0x10
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON                               0x10

#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B                               5
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W                               1
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M                               0x20
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON                          0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF                         0x20
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF                         0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON                          0x20

#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B                               6
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W                               1
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M                               0x40
#define   ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON                          0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF                         0x40
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF                         0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON                          0x40

#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__B                                   7
#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__W                                   1
#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__M                                   0x80
#define   ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE                                 0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON                              0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF                             0x80
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF                             0x0
#define     ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON                              0x80

#define ORX_NSU_AOX_LOFRQ_W__A                                              0x2060011
#define ORX_NSU_AOX_LOFRQ_W__W                                              16
#define ORX_NSU_AOX_LOFRQ_W__M                                              0xFFFF
#define ORX_NSU_AOX_LOFRQ_W__PRE                                            0x0
#define ORX_NSU_AOX_LOMDE_W__A                                              0x2060012
#define ORX_NSU_AOX_LOMDE_W__W                                              16
#define ORX_NSU_AOX_LOMDE_W__M                                              0xFFFF
#define ORX_NSU_AOX_LOMDE_W__PRE                                            0x0

#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B                              0
#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W                              8
#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M                              0xFF
#define   ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE                            0x0

#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__B                                  13
#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__W                                  1
#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__M                                  0x2000
#define   ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE                                0x0

#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__B                                    14
#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__W                                    2
#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__M                                    0xC000
#define   ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE                                  0x0

#define ORX_NSU_AOX_LOPOW_W__A                                              0x2060013
#define ORX_NSU_AOX_LOPOW_W__W                                              2
#define ORX_NSU_AOX_LOPOW_W__M                                              0x3
#define ORX_NSU_AOX_LOPOW_W__PRE                                            0x0
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB                                0x0
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB                                0x1
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB                               0x2
#define   ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB                               0x3

#define ORX_NSU_AOX_STHR_W__A                                               0x2060014
#define ORX_NSU_AOX_STHR_W__W                                               5
#define ORX_NSU_AOX_STHR_W__M                                               0x1F
#define ORX_NSU_AOX_STHR_W__PRE                                             0x0

#define ORX_NSU_TUN_RFGAIN_W__A                                             0x2060015
#define ORX_NSU_TUN_RFGAIN_W__W                                             15
#define ORX_NSU_TUN_RFGAIN_W__M                                             0x7FFF
#define ORX_NSU_TUN_RFGAIN_W__PRE                                           0x0

#define ORX_NSU_TUN_IFGAIN_W__A                                             0x2060016
#define ORX_NSU_TUN_IFGAIN_W__W                                             15
#define ORX_NSU_TUN_IFGAIN_W__M                                             0x7FFF
#define ORX_NSU_TUN_IFGAIN_W__PRE                                           0x0

#define ORX_NSU_TUN_BPF_W__A                                                0x2060017
#define ORX_NSU_TUN_BPF_W__W                                                15
#define ORX_NSU_TUN_BPF_W__M                                                0x7FFF
#define ORX_NSU_TUN_BPF_W__PRE                                              0x1F9
#define ORX_NSU_NSS_BITSWAP_W__A                                            0x2060018
#define ORX_NSU_NSS_BITSWAP_W__W                                            3
#define ORX_NSU_NSS_BITSWAP_W__M                                            0x7
#define ORX_NSU_NSS_BITSWAP_W__PRE                                          0x0

#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B                           0
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M                           0x1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE                         0x0

#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M                           0x2
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE                         0x0

#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B                           2
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W                           1
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M                           0x4
#define   ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE                         0x0

#define ORX_TST_COMM_EXEC__A                                                0x23F0000
#define ORX_TST_COMM_EXEC__W                                                2
#define ORX_TST_COMM_EXEC__M                                                0x3
#define ORX_TST_COMM_EXEC__PRE                                              0x0
#define   ORX_TST_COMM_EXEC_STOP                                            0x0
#define   ORX_TST_COMM_EXEC_ACTIVE                                          0x1
#define   ORX_TST_COMM_EXEC_HOLD                                            0x2

#define ORX_TST_AOX_TST_W__A                                                0x23F0010
#define ORX_TST_AOX_TST_W__W                                                8
#define ORX_TST_AOX_TST_W__M                                                0xFF
#define ORX_TST_AOX_TST_W__PRE                                              0x0

#define QAM_COMM_EXEC__A                                                    0x1400000
#define QAM_COMM_EXEC__W                                                    2
#define QAM_COMM_EXEC__M                                                    0x3
#define QAM_COMM_EXEC__PRE                                                  0x0
#define   QAM_COMM_EXEC_STOP                                                0x0
#define   QAM_COMM_EXEC_ACTIVE                                              0x1
#define   QAM_COMM_EXEC_HOLD                                                0x2

#define QAM_COMM_MB__A                                                      0x1400002
#define QAM_COMM_MB__W                                                      16
#define QAM_COMM_MB__M                                                      0xFFFF
#define QAM_COMM_MB__PRE                                                    0x0
#define QAM_COMM_INT_REQ__A                                                 0x1400003
#define QAM_COMM_INT_REQ__W                                                 16
#define QAM_COMM_INT_REQ__M                                                 0xFFFF
#define QAM_COMM_INT_REQ__PRE                                               0x0

#define   QAM_COMM_INT_REQ_SL_REQ__B                                        0
#define   QAM_COMM_INT_REQ_SL_REQ__W                                        1
#define   QAM_COMM_INT_REQ_SL_REQ__M                                        0x1
#define   QAM_COMM_INT_REQ_SL_REQ__PRE                                      0x0

#define   QAM_COMM_INT_REQ_LC_REQ__B                                        1
#define   QAM_COMM_INT_REQ_LC_REQ__W                                        1
#define   QAM_COMM_INT_REQ_LC_REQ__M                                        0x2
#define   QAM_COMM_INT_REQ_LC_REQ__PRE                                      0x0

#define   QAM_COMM_INT_REQ_VD_REQ__B                                        2
#define   QAM_COMM_INT_REQ_VD_REQ__W                                        1
#define   QAM_COMM_INT_REQ_VD_REQ__M                                        0x4
#define   QAM_COMM_INT_REQ_VD_REQ__PRE                                      0x0

#define   QAM_COMM_INT_REQ_SY_REQ__B                                        3
#define   QAM_COMM_INT_REQ_SY_REQ__W                                        1
#define   QAM_COMM_INT_REQ_SY_REQ__M                                        0x8
#define   QAM_COMM_INT_REQ_SY_REQ__PRE                                      0x0

#define QAM_COMM_INT_STA__A                                                 0x1400005
#define QAM_COMM_INT_STA__W                                                 16
#define QAM_COMM_INT_STA__M                                                 0xFFFF
#define QAM_COMM_INT_STA__PRE                                               0x0
#define QAM_COMM_INT_MSK__A                                                 0x1400006
#define QAM_COMM_INT_MSK__W                                                 16
#define QAM_COMM_INT_MSK__M                                                 0xFFFF
#define QAM_COMM_INT_MSK__PRE                                               0x0
#define QAM_COMM_INT_STM__A                                                 0x1400007
#define QAM_COMM_INT_STM__W                                                 16
#define QAM_COMM_INT_STM__M                                                 0xFFFF
#define QAM_COMM_INT_STM__PRE                                               0x0

#define QAM_TOP_COMM_EXEC__A                                                0x1410000
#define QAM_TOP_COMM_EXEC__W                                                2
#define QAM_TOP_COMM_EXEC__M                                                0x3
#define QAM_TOP_COMM_EXEC__PRE                                              0x0
#define   QAM_TOP_COMM_EXEC_STOP                                            0x0
#define   QAM_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   QAM_TOP_COMM_EXEC_HOLD                                            0x2

#define QAM_TOP_ANNEX__A                                                    0x1410010
#define QAM_TOP_ANNEX__W                                                    2
#define QAM_TOP_ANNEX__M                                                    0x3
#define QAM_TOP_ANNEX__PRE                                                  0x1
#define   QAM_TOP_ANNEX_A                                                   0x0
#define   QAM_TOP_ANNEX_B                                                   0x1
#define   QAM_TOP_ANNEX_C                                                   0x2
#define   QAM_TOP_ANNEX_D                                                   0x3

#define QAM_TOP_CONSTELLATION__A                                            0x1410011
#define QAM_TOP_CONSTELLATION__W                                            3
#define QAM_TOP_CONSTELLATION__M                                            0x7
#define QAM_TOP_CONSTELLATION__PRE                                          0x5
#define   QAM_TOP_CONSTELLATION_NONE                                        0x0
#define   QAM_TOP_CONSTELLATION_QPSK                                        0x1
#define   QAM_TOP_CONSTELLATION_QAM8                                        0x2
#define   QAM_TOP_CONSTELLATION_QAM16                                       0x3
#define   QAM_TOP_CONSTELLATION_QAM32                                       0x4
#define   QAM_TOP_CONSTELLATION_QAM64                                       0x5
#define   QAM_TOP_CONSTELLATION_QAM128                                      0x6
#define   QAM_TOP_CONSTELLATION_QAM256                                      0x7

#define QAM_FQ_COMM_EXEC__A                                                 0x1420000
#define QAM_FQ_COMM_EXEC__W                                                 2
#define QAM_FQ_COMM_EXEC__M                                                 0x3
#define QAM_FQ_COMM_EXEC__PRE                                               0x0
#define   QAM_FQ_COMM_EXEC_STOP                                             0x0
#define   QAM_FQ_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_FQ_COMM_EXEC_HOLD                                             0x2

#define QAM_FQ_MODE__A                                                      0x1420010
#define QAM_FQ_MODE__W                                                      3
#define QAM_FQ_MODE__M                                                      0x7
#define QAM_FQ_MODE__PRE                                                    0x0

#define   QAM_FQ_MODE_TAPRESET__B                                           0
#define   QAM_FQ_MODE_TAPRESET__W                                           1
#define   QAM_FQ_MODE_TAPRESET__M                                           0x1
#define   QAM_FQ_MODE_TAPRESET__PRE                                         0x0
#define     QAM_FQ_MODE_TAPRESET_RST                                        0x1

#define   QAM_FQ_MODE_TAPLMS__B                                             1
#define   QAM_FQ_MODE_TAPLMS__W                                             1
#define   QAM_FQ_MODE_TAPLMS__M                                             0x2
#define   QAM_FQ_MODE_TAPLMS__PRE                                           0x0
#define     QAM_FQ_MODE_TAPLMS_UPD                                          0x2

#define   QAM_FQ_MODE_TAPDRAIN__B                                           2
#define   QAM_FQ_MODE_TAPDRAIN__W                                           1
#define   QAM_FQ_MODE_TAPDRAIN__M                                           0x4
#define   QAM_FQ_MODE_TAPDRAIN__PRE                                         0x0
#define     QAM_FQ_MODE_TAPDRAIN_DRAIN                                      0x4

#define QAM_FQ_MU_FACTOR__A                                                 0x1420011
#define QAM_FQ_MU_FACTOR__W                                                 3
#define QAM_FQ_MU_FACTOR__M                                                 0x7
#define QAM_FQ_MU_FACTOR__PRE                                               0x0

#define QAM_FQ_LA_FACTOR__A                                                 0x1420012
#define QAM_FQ_LA_FACTOR__W                                                 4
#define QAM_FQ_LA_FACTOR__M                                                 0xF
#define QAM_FQ_LA_FACTOR__PRE                                               0xC
#define QAM_FQ_CENTTAP_IDX__A                                               0x1420016
#define QAM_FQ_CENTTAP_IDX__W                                               5
#define QAM_FQ_CENTTAP_IDX__M                                               0x1F
#define QAM_FQ_CENTTAP_IDX__PRE                                             0x13

#define   QAM_FQ_CENTTAP_IDX_IDX__B                                         0
#define   QAM_FQ_CENTTAP_IDX_IDX__W                                         5
#define   QAM_FQ_CENTTAP_IDX_IDX__M                                         0x1F
#define   QAM_FQ_CENTTAP_IDX_IDX__PRE                                       0x13

#define QAM_FQ_CENTTAP_VALUE__A                                             0x1420017
#define QAM_FQ_CENTTAP_VALUE__W                                             12
#define QAM_FQ_CENTTAP_VALUE__M                                             0xFFF
#define QAM_FQ_CENTTAP_VALUE__PRE                                           0x600

#define   QAM_FQ_CENTTAP_VALUE_TAP__B                                       0
#define   QAM_FQ_CENTTAP_VALUE_TAP__W                                       12
#define   QAM_FQ_CENTTAP_VALUE_TAP__M                                       0xFFF
#define   QAM_FQ_CENTTAP_VALUE_TAP__PRE                                     0x600

#define QAM_FQ_TAP_RE_EL0__A                                                0x1420020
#define QAM_FQ_TAP_RE_EL0__W                                                12
#define QAM_FQ_TAP_RE_EL0__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL0__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL0_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL0_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL0_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL0_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL0__A                                                0x1420021
#define QAM_FQ_TAP_IM_EL0__W                                                12
#define QAM_FQ_TAP_IM_EL0__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL0__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL0_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL0_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL0_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL0_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL1__A                                                0x1420022
#define QAM_FQ_TAP_RE_EL1__W                                                12
#define QAM_FQ_TAP_RE_EL1__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL1__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL1_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL1_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL1_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL1_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL1__A                                                0x1420023
#define QAM_FQ_TAP_IM_EL1__W                                                12
#define QAM_FQ_TAP_IM_EL1__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL1__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL1_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL1_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL1_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL1_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL2__A                                                0x1420024
#define QAM_FQ_TAP_RE_EL2__W                                                12
#define QAM_FQ_TAP_RE_EL2__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL2__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL2_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL2_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL2_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL2_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL2__A                                                0x1420025
#define QAM_FQ_TAP_IM_EL2__W                                                12
#define QAM_FQ_TAP_IM_EL2__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL2__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL2_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL2_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL2_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL2_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL3__A                                                0x1420026
#define QAM_FQ_TAP_RE_EL3__W                                                12
#define QAM_FQ_TAP_RE_EL3__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL3__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL3_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL3_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL3_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL3_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL3__A                                                0x1420027
#define QAM_FQ_TAP_IM_EL3__W                                                12
#define QAM_FQ_TAP_IM_EL3__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL3__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL3_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL3_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL3_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL3_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL4__A                                                0x1420028
#define QAM_FQ_TAP_RE_EL4__W                                                12
#define QAM_FQ_TAP_RE_EL4__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL4__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL4_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL4_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL4_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL4_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL4__A                                                0x1420029
#define QAM_FQ_TAP_IM_EL4__W                                                12
#define QAM_FQ_TAP_IM_EL4__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL4__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL4_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL4_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL4_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL4_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL5__A                                                0x142002A
#define QAM_FQ_TAP_RE_EL5__W                                                12
#define QAM_FQ_TAP_RE_EL5__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL5__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL5_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL5_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL5_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL5_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL5__A                                                0x142002B
#define QAM_FQ_TAP_IM_EL5__W                                                12
#define QAM_FQ_TAP_IM_EL5__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL5__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL5_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL5_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL5_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL5_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL6__A                                                0x142002C
#define QAM_FQ_TAP_RE_EL6__W                                                12
#define QAM_FQ_TAP_RE_EL6__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL6__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL6_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL6_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL6_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL6_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL6__A                                                0x142002D
#define QAM_FQ_TAP_IM_EL6__W                                                12
#define QAM_FQ_TAP_IM_EL6__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL6__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL6_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL6_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL6_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL6_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL7__A                                                0x142002E
#define QAM_FQ_TAP_RE_EL7__W                                                12
#define QAM_FQ_TAP_RE_EL7__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL7__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL7_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL7_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL7_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL7_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL7__A                                                0x142002F
#define QAM_FQ_TAP_IM_EL7__W                                                12
#define QAM_FQ_TAP_IM_EL7__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL7__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL7_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL7_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL7_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL7_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL8__A                                                0x1420030
#define QAM_FQ_TAP_RE_EL8__W                                                12
#define QAM_FQ_TAP_RE_EL8__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL8__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL8_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL8_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL8_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL8_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL8__A                                                0x1420031
#define QAM_FQ_TAP_IM_EL8__W                                                12
#define QAM_FQ_TAP_IM_EL8__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL8__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL8_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL8_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL8_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL8_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL9__A                                                0x1420032
#define QAM_FQ_TAP_RE_EL9__W                                                12
#define QAM_FQ_TAP_RE_EL9__M                                                0xFFF
#define QAM_FQ_TAP_RE_EL9__PRE                                              0x2

#define   QAM_FQ_TAP_RE_EL9_TAP__B                                          0
#define   QAM_FQ_TAP_RE_EL9_TAP__W                                          12
#define   QAM_FQ_TAP_RE_EL9_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_RE_EL9_TAP__PRE                                        0x2

#define QAM_FQ_TAP_IM_EL9__A                                                0x1420033
#define QAM_FQ_TAP_IM_EL9__W                                                12
#define QAM_FQ_TAP_IM_EL9__M                                                0xFFF
#define QAM_FQ_TAP_IM_EL9__PRE                                              0x2

#define   QAM_FQ_TAP_IM_EL9_TAP__B                                          0
#define   QAM_FQ_TAP_IM_EL9_TAP__W                                          12
#define   QAM_FQ_TAP_IM_EL9_TAP__M                                          0xFFF
#define   QAM_FQ_TAP_IM_EL9_TAP__PRE                                        0x2

#define QAM_FQ_TAP_RE_EL10__A                                               0x1420034
#define QAM_FQ_TAP_RE_EL10__W                                               12
#define QAM_FQ_TAP_RE_EL10__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL10__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL10_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL10_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL10_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL10_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL10__A                                               0x1420035
#define QAM_FQ_TAP_IM_EL10__W                                               12
#define QAM_FQ_TAP_IM_EL10__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL10__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL10_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL10_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL10_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL10_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL11__A                                               0x1420036
#define QAM_FQ_TAP_RE_EL11__W                                               12
#define QAM_FQ_TAP_RE_EL11__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL11__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL11_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL11_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL11_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL11_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL11__A                                               0x1420037
#define QAM_FQ_TAP_IM_EL11__W                                               12
#define QAM_FQ_TAP_IM_EL11__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL11__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL11_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL11_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL11_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL11_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL12__A                                               0x1420038
#define QAM_FQ_TAP_RE_EL12__W                                               12
#define QAM_FQ_TAP_RE_EL12__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL12__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL12_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL12_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL12_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL12_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL12__A                                               0x1420039
#define QAM_FQ_TAP_IM_EL12__W                                               12
#define QAM_FQ_TAP_IM_EL12__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL12__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL12_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL12_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL12_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL12_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL13__A                                               0x142003A
#define QAM_FQ_TAP_RE_EL13__W                                               12
#define QAM_FQ_TAP_RE_EL13__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL13__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL13_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL13_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL13_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL13_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL13__A                                               0x142003B
#define QAM_FQ_TAP_IM_EL13__W                                               12
#define QAM_FQ_TAP_IM_EL13__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL13__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL13_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL13_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL13_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL13_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL14__A                                               0x142003C
#define QAM_FQ_TAP_RE_EL14__W                                               12
#define QAM_FQ_TAP_RE_EL14__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL14__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL14_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL14_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL14_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL14_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL14__A                                               0x142003D
#define QAM_FQ_TAP_IM_EL14__W                                               12
#define QAM_FQ_TAP_IM_EL14__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL14__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL14_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL14_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL14_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL14_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL15__A                                               0x142003E
#define QAM_FQ_TAP_RE_EL15__W                                               12
#define QAM_FQ_TAP_RE_EL15__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL15__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL15_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL15_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL15_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL15_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL15__A                                               0x142003F
#define QAM_FQ_TAP_IM_EL15__W                                               12
#define QAM_FQ_TAP_IM_EL15__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL15__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL15_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL15_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL15_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL15_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL16__A                                               0x1420040
#define QAM_FQ_TAP_RE_EL16__W                                               12
#define QAM_FQ_TAP_RE_EL16__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL16__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL16_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL16_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL16_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL16_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL16__A                                               0x1420041
#define QAM_FQ_TAP_IM_EL16__W                                               12
#define QAM_FQ_TAP_IM_EL16__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL16__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL16_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL16_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL16_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL16_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL17__A                                               0x1420042
#define QAM_FQ_TAP_RE_EL17__W                                               12
#define QAM_FQ_TAP_RE_EL17__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL17__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL17_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL17_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL17_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL17_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL17__A                                               0x1420043
#define QAM_FQ_TAP_IM_EL17__W                                               12
#define QAM_FQ_TAP_IM_EL17__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL17__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL17_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL17_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL17_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL17_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL18__A                                               0x1420044
#define QAM_FQ_TAP_RE_EL18__W                                               12
#define QAM_FQ_TAP_RE_EL18__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL18__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL18_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL18_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL18_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL18_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL18__A                                               0x1420045
#define QAM_FQ_TAP_IM_EL18__W                                               12
#define QAM_FQ_TAP_IM_EL18__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL18__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL18_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL18_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL18_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL18_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL19__A                                               0x1420046
#define QAM_FQ_TAP_RE_EL19__W                                               12
#define QAM_FQ_TAP_RE_EL19__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL19__PRE                                             0x600

#define   QAM_FQ_TAP_RE_EL19_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL19_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL19_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL19_TAP__PRE                                       0x600

#define QAM_FQ_TAP_IM_EL19__A                                               0x1420047
#define QAM_FQ_TAP_IM_EL19__W                                               12
#define QAM_FQ_TAP_IM_EL19__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL19__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL19_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL19_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL19_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL19_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL20__A                                               0x1420048
#define QAM_FQ_TAP_RE_EL20__W                                               12
#define QAM_FQ_TAP_RE_EL20__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL20__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL20_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL20_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL20_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL20_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL20__A                                               0x1420049
#define QAM_FQ_TAP_IM_EL20__W                                               12
#define QAM_FQ_TAP_IM_EL20__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL20__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL20_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL20_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL20_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL20_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL21__A                                               0x142004A
#define QAM_FQ_TAP_RE_EL21__W                                               12
#define QAM_FQ_TAP_RE_EL21__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL21__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL21_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL21_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL21_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL21_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL21__A                                               0x142004B
#define QAM_FQ_TAP_IM_EL21__W                                               12
#define QAM_FQ_TAP_IM_EL21__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL21__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL21_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL21_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL21_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL21_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL22__A                                               0x142004C
#define QAM_FQ_TAP_RE_EL22__W                                               12
#define QAM_FQ_TAP_RE_EL22__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL22__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL22_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL22_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL22_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL22_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL22__A                                               0x142004D
#define QAM_FQ_TAP_IM_EL22__W                                               12
#define QAM_FQ_TAP_IM_EL22__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL22__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL22_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL22_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL22_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL22_TAP__PRE                                       0x2

#define QAM_FQ_TAP_RE_EL23__A                                               0x142004E
#define QAM_FQ_TAP_RE_EL23__W                                               12
#define QAM_FQ_TAP_RE_EL23__M                                               0xFFF
#define QAM_FQ_TAP_RE_EL23__PRE                                             0x2

#define   QAM_FQ_TAP_RE_EL23_TAP__B                                         0
#define   QAM_FQ_TAP_RE_EL23_TAP__W                                         12
#define   QAM_FQ_TAP_RE_EL23_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_RE_EL23_TAP__PRE                                       0x2

#define QAM_FQ_TAP_IM_EL23__A                                               0x142004F
#define QAM_FQ_TAP_IM_EL23__W                                               12
#define QAM_FQ_TAP_IM_EL23__M                                               0xFFF
#define QAM_FQ_TAP_IM_EL23__PRE                                             0x2

#define   QAM_FQ_TAP_IM_EL23_TAP__B                                         0
#define   QAM_FQ_TAP_IM_EL23_TAP__W                                         12
#define   QAM_FQ_TAP_IM_EL23_TAP__M                                         0xFFF
#define   QAM_FQ_TAP_IM_EL23_TAP__PRE                                       0x2

#define QAM_SL_COMM_EXEC__A                                                 0x1430000
#define QAM_SL_COMM_EXEC__W                                                 2
#define QAM_SL_COMM_EXEC__M                                                 0x3
#define QAM_SL_COMM_EXEC__PRE                                               0x0
#define   QAM_SL_COMM_EXEC_STOP                                             0x0
#define   QAM_SL_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_SL_COMM_EXEC_HOLD                                             0x2

#define QAM_SL_COMM_MB__A                                                   0x1430002
#define QAM_SL_COMM_MB__W                                                   4
#define QAM_SL_COMM_MB__M                                                   0xF
#define QAM_SL_COMM_MB__PRE                                                 0x0
#define   QAM_SL_COMM_MB_CTL__B                                             0
#define   QAM_SL_COMM_MB_CTL__W                                             1
#define   QAM_SL_COMM_MB_CTL__M                                             0x1
#define   QAM_SL_COMM_MB_CTL__PRE                                           0x0
#define     QAM_SL_COMM_MB_CTL_OFF                                          0x0
#define     QAM_SL_COMM_MB_CTL_ON                                           0x1
#define   QAM_SL_COMM_MB_OBS__B                                             1
#define   QAM_SL_COMM_MB_OBS__W                                             1
#define   QAM_SL_COMM_MB_OBS__M                                             0x2
#define   QAM_SL_COMM_MB_OBS__PRE                                           0x0
#define     QAM_SL_COMM_MB_OBS_OFF                                          0x0
#define     QAM_SL_COMM_MB_OBS_ON                                           0x2
#define   QAM_SL_COMM_MB_MUX_OBS__B                                         2
#define   QAM_SL_COMM_MB_MUX_OBS__W                                         2
#define   QAM_SL_COMM_MB_MUX_OBS__M                                         0xC
#define   QAM_SL_COMM_MB_MUX_OBS__PRE                                       0x0
#define     QAM_SL_COMM_MB_MUX_OBS_CONST_CORR                               0x0
#define     QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O                               0x4
#define     QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O                               0x8
#define     QAM_SL_COMM_MB_MUX_OBS_VDEC_O                                   0xC

#define QAM_SL_COMM_INT_REQ__A                                              0x1430003
#define QAM_SL_COMM_INT_REQ__W                                              1
#define QAM_SL_COMM_INT_REQ__M                                              0x1
#define QAM_SL_COMM_INT_REQ__PRE                                            0x0
#define QAM_SL_COMM_INT_STA__A                                              0x1430005
#define QAM_SL_COMM_INT_STA__W                                              2
#define QAM_SL_COMM_INT_STA__M                                              0x3
#define QAM_SL_COMM_INT_STA__PRE                                            0x0

#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__B                                0
#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__W                                1
#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__M                                0x1
#define   QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE                              0x0

#define   QAM_SL_COMM_INT_STA_MER_INT__B                                    1
#define   QAM_SL_COMM_INT_STA_MER_INT__W                                    1
#define   QAM_SL_COMM_INT_STA_MER_INT__M                                    0x2
#define   QAM_SL_COMM_INT_STA_MER_INT__PRE                                  0x0

#define QAM_SL_COMM_INT_MSK__A                                              0x1430006
#define QAM_SL_COMM_INT_MSK__W                                              2
#define QAM_SL_COMM_INT_MSK__M                                              0x3
#define QAM_SL_COMM_INT_MSK__PRE                                            0x0
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B                                0
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W                                1
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M                                0x1
#define   QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE                              0x0
#define   QAM_SL_COMM_INT_MSK_MER_MSK__B                                    1
#define   QAM_SL_COMM_INT_MSK_MER_MSK__W                                    1
#define   QAM_SL_COMM_INT_MSK_MER_MSK__M                                    0x2
#define   QAM_SL_COMM_INT_MSK_MER_MSK__PRE                                  0x0

#define QAM_SL_COMM_INT_STM__A                                              0x1430007
#define QAM_SL_COMM_INT_STM__W                                              2
#define QAM_SL_COMM_INT_STM__M                                              0x3
#define QAM_SL_COMM_INT_STM__PRE                                            0x0
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__B                                0
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__W                                1
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__M                                0x1
#define   QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE                              0x0
#define   QAM_SL_COMM_INT_STM_MER_STM__B                                    1
#define   QAM_SL_COMM_INT_STM_MER_STM__W                                    1
#define   QAM_SL_COMM_INT_STM_MER_STM__M                                    0x2
#define   QAM_SL_COMM_INT_STM_MER_STM__PRE                                  0x0

#define QAM_SL_MODE__A                                                      0x1430010
#define QAM_SL_MODE__W                                                      11
#define QAM_SL_MODE__M                                                      0x7FF
#define QAM_SL_MODE__PRE                                                    0x0

#define   QAM_SL_MODE_SLICER4LC__B                                          0
#define   QAM_SL_MODE_SLICER4LC__W                                          2
#define   QAM_SL_MODE_SLICER4LC__M                                          0x3
#define   QAM_SL_MODE_SLICER4LC__PRE                                        0x0
#define     QAM_SL_MODE_SLICER4LC_RECT                                      0x0
#define     QAM_SL_MODE_SLICER4LC_ONET                                      0x1
#define     QAM_SL_MODE_SLICER4LC_RAD                                       0x2

#define   QAM_SL_MODE_SLICER4DQ__B                                          2
#define   QAM_SL_MODE_SLICER4DQ__W                                          2
#define   QAM_SL_MODE_SLICER4DQ__M                                          0xC
#define   QAM_SL_MODE_SLICER4DQ__PRE                                        0x0
#define     QAM_SL_MODE_SLICER4DQ_RECT                                      0x0
#define     QAM_SL_MODE_SLICER4DQ_ONET                                      0x4
#define     QAM_SL_MODE_SLICER4DQ_RAD                                       0x8

#define   QAM_SL_MODE_SLICER4VD__B                                          4
#define   QAM_SL_MODE_SLICER4VD__W                                          2
#define   QAM_SL_MODE_SLICER4VD__M                                          0x30
#define   QAM_SL_MODE_SLICER4VD__PRE                                        0x0
#define     QAM_SL_MODE_SLICER4VD_RECT                                      0x0
#define     QAM_SL_MODE_SLICER4VD_ONET                                      0x10
#define     QAM_SL_MODE_SLICER4VD_RAD                                       0x20

#define   QAM_SL_MODE_ROT_DIS__B                                            6
#define   QAM_SL_MODE_ROT_DIS__W                                            1
#define   QAM_SL_MODE_ROT_DIS__M                                            0x40
#define   QAM_SL_MODE_ROT_DIS__PRE                                          0x0

#define   QAM_SL_MODE_DQROT_DIS__B                                          7
#define   QAM_SL_MODE_DQROT_DIS__W                                          1
#define   QAM_SL_MODE_DQROT_DIS__M                                          0x80
#define   QAM_SL_MODE_DQROT_DIS__PRE                                        0x0

#define   QAM_SL_MODE_DFE_DIS__B                                            8
#define   QAM_SL_MODE_DFE_DIS__W                                            1
#define   QAM_SL_MODE_DFE_DIS__M                                            0x100
#define   QAM_SL_MODE_DFE_DIS__PRE                                          0x0

#define   QAM_SL_MODE_RADIUS_MIX__B                                         9
#define   QAM_SL_MODE_RADIUS_MIX__W                                         1
#define   QAM_SL_MODE_RADIUS_MIX__M                                         0x200
#define   QAM_SL_MODE_RADIUS_MIX__PRE                                       0x0

#define   QAM_SL_MODE_TILT_COMP__B                                          10
#define   QAM_SL_MODE_TILT_COMP__W                                          1
#define   QAM_SL_MODE_TILT_COMP__M                                          0x400
#define   QAM_SL_MODE_TILT_COMP__PRE                                        0x0

#define QAM_SL_K_FACTOR__A                                                  0x1430011
#define QAM_SL_K_FACTOR__W                                                  4
#define QAM_SL_K_FACTOR__M                                                  0xF
#define QAM_SL_K_FACTOR__PRE                                                0x0
#define QAM_SL_MEDIAN__A                                                    0x1430012
#define QAM_SL_MEDIAN__W                                                    14
#define QAM_SL_MEDIAN__M                                                    0x3FFF
#define QAM_SL_MEDIAN__PRE                                                  0x0

#define   QAM_SL_MEDIAN_LENGTH__B                                           0
#define   QAM_SL_MEDIAN_LENGTH__W                                           2
#define   QAM_SL_MEDIAN_LENGTH__M                                           0x3
#define   QAM_SL_MEDIAN_LENGTH__PRE                                         0x0

#define   QAM_SL_MEDIAN_CORRECT__B                                          2
#define   QAM_SL_MEDIAN_CORRECT__W                                          4
#define   QAM_SL_MEDIAN_CORRECT__M                                          0x3C
#define   QAM_SL_MEDIAN_CORRECT__PRE                                        0x0

#define   QAM_SL_MEDIAN_TOLERANCE__B                                        6
#define   QAM_SL_MEDIAN_TOLERANCE__W                                        7
#define   QAM_SL_MEDIAN_TOLERANCE__M                                        0x1FC0
#define   QAM_SL_MEDIAN_TOLERANCE__PRE                                      0x0

#define   QAM_SL_MEDIAN_FAST__B                                             13
#define   QAM_SL_MEDIAN_FAST__W                                             1
#define   QAM_SL_MEDIAN_FAST__M                                             0x2000
#define   QAM_SL_MEDIAN_FAST__PRE                                           0x0

#define QAM_SL_ALPHA__A                                                     0x1430013
#define QAM_SL_ALPHA__W                                                     3
#define QAM_SL_ALPHA__M                                                     0x7
#define QAM_SL_ALPHA__PRE                                                   0x0

#define QAM_SL_PHASELIMIT__A                                                0x1430014
#define QAM_SL_PHASELIMIT__W                                                9
#define QAM_SL_PHASELIMIT__M                                                0x1FF
#define QAM_SL_PHASELIMIT__PRE                                              0x0
#define QAM_SL_MTA_LENGTH__A                                                0x1430015
#define QAM_SL_MTA_LENGTH__W                                                2
#define QAM_SL_MTA_LENGTH__M                                                0x3
#define QAM_SL_MTA_LENGTH__PRE                                              0x1

#define   QAM_SL_MTA_LENGTH_LENGTH__B                                       0
#define   QAM_SL_MTA_LENGTH_LENGTH__W                                       2
#define   QAM_SL_MTA_LENGTH_LENGTH__M                                       0x3
#define   QAM_SL_MTA_LENGTH_LENGTH__PRE                                     0x1

#define QAM_SL_MEDIAN_ERROR__A                                              0x1430016
#define QAM_SL_MEDIAN_ERROR__W                                              10
#define QAM_SL_MEDIAN_ERROR__M                                              0x3FF
#define QAM_SL_MEDIAN_ERROR__PRE                                            0x0

#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B                                 0
#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W                                 10
#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M                                 0x3FF
#define   QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE                               0x0

#define QAM_SL_ERR_POWER__A                                                 0x1430017
#define QAM_SL_ERR_POWER__W                                                 16
#define QAM_SL_ERR_POWER__M                                                 0xFFFF
#define QAM_SL_ERR_POWER__PRE                                               0x0

#define QAM_DQ_COMM_EXEC__A                                                 0x1440000
#define QAM_DQ_COMM_EXEC__W                                                 2
#define QAM_DQ_COMM_EXEC__M                                                 0x3
#define QAM_DQ_COMM_EXEC__PRE                                               0x0
#define   QAM_DQ_COMM_EXEC_STOP                                             0x0
#define   QAM_DQ_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_DQ_COMM_EXEC_HOLD                                             0x2

#define QAM_DQ_MODE__A                                                      0x1440010
#define QAM_DQ_MODE__W                                                      5
#define QAM_DQ_MODE__M                                                      0x1F
#define QAM_DQ_MODE__PRE                                                    0x0

#define   QAM_DQ_MODE_TAPRESET__B                                           0
#define   QAM_DQ_MODE_TAPRESET__W                                           1
#define   QAM_DQ_MODE_TAPRESET__M                                           0x1
#define   QAM_DQ_MODE_TAPRESET__PRE                                         0x0
#define     QAM_DQ_MODE_TAPRESET_RST                                        0x1

#define   QAM_DQ_MODE_TAPLMS__B                                             1
#define   QAM_DQ_MODE_TAPLMS__W                                             1
#define   QAM_DQ_MODE_TAPLMS__M                                             0x2
#define   QAM_DQ_MODE_TAPLMS__PRE                                           0x0
#define     QAM_DQ_MODE_TAPLMS_UPD                                          0x2

#define   QAM_DQ_MODE_TAPDRAIN__B                                           2
#define   QAM_DQ_MODE_TAPDRAIN__W                                           1
#define   QAM_DQ_MODE_TAPDRAIN__M                                           0x4
#define   QAM_DQ_MODE_TAPDRAIN__PRE                                         0x0
#define     QAM_DQ_MODE_TAPDRAIN_DRAIN                                      0x4

#define   QAM_DQ_MODE_FB__B                                                 3
#define   QAM_DQ_MODE_FB__W                                                 2
#define   QAM_DQ_MODE_FB__M                                                 0x18
#define   QAM_DQ_MODE_FB__PRE                                               0x0
#define     QAM_DQ_MODE_FB_CMA                                              0x0
#define     QAM_DQ_MODE_FB_RADIUS                                           0x8
#define     QAM_DQ_MODE_FB_DFB                                              0x10
#define     QAM_DQ_MODE_FB_TRELLIS                                          0x18

#define QAM_DQ_MU_FACTOR__A                                                 0x1440011
#define QAM_DQ_MU_FACTOR__W                                                 3
#define QAM_DQ_MU_FACTOR__M                                                 0x7
#define QAM_DQ_MU_FACTOR__PRE                                               0x0

#define QAM_DQ_LA_FACTOR__A                                                 0x1440012
#define QAM_DQ_LA_FACTOR__W                                                 4
#define QAM_DQ_LA_FACTOR__M                                                 0xF
#define QAM_DQ_LA_FACTOR__PRE                                               0xC

#define QAM_DQ_CMA_RATIO__A                                                 0x1440013
#define QAM_DQ_CMA_RATIO__W                                                 14
#define QAM_DQ_CMA_RATIO__M                                                 0x3FFF
#define QAM_DQ_CMA_RATIO__PRE                                               0x3CF9
#define   QAM_DQ_CMA_RATIO_QPSK                                             0x2000
#define   QAM_DQ_CMA_RATIO_QAM16                                            0x34CD
#define   QAM_DQ_CMA_RATIO_QAM64                                            0x3A00
#define   QAM_DQ_CMA_RATIO_QAM256                                           0x3B4D
#define   QAM_DQ_CMA_RATIO_QAM1024                                          0x3BA0

#define QAM_DQ_QUAL_RADSEL__A                                               0x1440014
#define QAM_DQ_QUAL_RADSEL__W                                               3
#define QAM_DQ_QUAL_RADSEL__M                                               0x7
#define QAM_DQ_QUAL_RADSEL__PRE                                             0x0

#define   QAM_DQ_QUAL_RADSEL_BIT__B                                         0
#define   QAM_DQ_QUAL_RADSEL_BIT__W                                         3
#define   QAM_DQ_QUAL_RADSEL_BIT__M                                         0x7
#define   QAM_DQ_QUAL_RADSEL_BIT__PRE                                       0x0
#define     QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS                              0x0
#define     QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA                                 0x6

#define QAM_DQ_QUAL_ENA__A                                                  0x1440015
#define QAM_DQ_QUAL_ENA__W                                                  1
#define QAM_DQ_QUAL_ENA__M                                                  0x1
#define QAM_DQ_QUAL_ENA__PRE                                                0x0

#define   QAM_DQ_QUAL_ENA_ENA__B                                            0
#define   QAM_DQ_QUAL_ENA_ENA__W                                            1
#define   QAM_DQ_QUAL_ENA_ENA__M                                            0x1
#define   QAM_DQ_QUAL_ENA_ENA__PRE                                          0x0
#define     QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING                              0x1

#define QAM_DQ_QUAL_FUN0__A                                                 0x1440018
#define QAM_DQ_QUAL_FUN0__W                                                 6
#define QAM_DQ_QUAL_FUN0__M                                                 0x3F
#define QAM_DQ_QUAL_FUN0__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN0_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN0_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN0_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN0_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN1__A                                                 0x1440019
#define QAM_DQ_QUAL_FUN1__W                                                 6
#define QAM_DQ_QUAL_FUN1__M                                                 0x3F
#define QAM_DQ_QUAL_FUN1__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN1_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN1_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN1_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN1_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN2__A                                                 0x144001A
#define QAM_DQ_QUAL_FUN2__W                                                 6
#define QAM_DQ_QUAL_FUN2__M                                                 0x3F
#define QAM_DQ_QUAL_FUN2__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN2_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN2_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN2_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN2_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN3__A                                                 0x144001B
#define QAM_DQ_QUAL_FUN3__W                                                 6
#define QAM_DQ_QUAL_FUN3__M                                                 0x3F
#define QAM_DQ_QUAL_FUN3__PRE                                               0x4

#define   QAM_DQ_QUAL_FUN3_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN3_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN3_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN3_BIT__PRE                                         0x4

#define QAM_DQ_QUAL_FUN4__A                                                 0x144001C
#define QAM_DQ_QUAL_FUN4__W                                                 6
#define QAM_DQ_QUAL_FUN4__M                                                 0x3F
#define QAM_DQ_QUAL_FUN4__PRE                                               0x6

#define   QAM_DQ_QUAL_FUN4_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN4_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN4_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN4_BIT__PRE                                         0x6

#define QAM_DQ_QUAL_FUN5__A                                                 0x144001D
#define QAM_DQ_QUAL_FUN5__W                                                 6
#define QAM_DQ_QUAL_FUN5__M                                                 0x3F
#define QAM_DQ_QUAL_FUN5__PRE                                               0x6

#define   QAM_DQ_QUAL_FUN5_BIT__B                                           0
#define   QAM_DQ_QUAL_FUN5_BIT__W                                           6
#define   QAM_DQ_QUAL_FUN5_BIT__M                                           0x3F
#define   QAM_DQ_QUAL_FUN5_BIT__PRE                                         0x6

#define QAM_DQ_RAW_LIM__A                                                   0x144001E
#define QAM_DQ_RAW_LIM__W                                                   5
#define QAM_DQ_RAW_LIM__M                                                   0x1F
#define QAM_DQ_RAW_LIM__PRE                                                 0x1F

#define   QAM_DQ_RAW_LIM_BIT__B                                             0
#define   QAM_DQ_RAW_LIM_BIT__W                                             5
#define   QAM_DQ_RAW_LIM_BIT__M                                             0x1F
#define   QAM_DQ_RAW_LIM_BIT__PRE                                           0x1F

#define QAM_DQ_TAP_RE_EL0__A                                                0x1440020
#define QAM_DQ_TAP_RE_EL0__W                                                12
#define QAM_DQ_TAP_RE_EL0__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL0__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL0_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL0_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL0_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL0_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL0__A                                                0x1440021
#define QAM_DQ_TAP_IM_EL0__W                                                12
#define QAM_DQ_TAP_IM_EL0__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL0__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL0_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL0_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL0_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL0_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL1__A                                                0x1440022
#define QAM_DQ_TAP_RE_EL1__W                                                12
#define QAM_DQ_TAP_RE_EL1__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL1__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL1_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL1_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL1_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL1_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL1__A                                                0x1440023
#define QAM_DQ_TAP_IM_EL1__W                                                12
#define QAM_DQ_TAP_IM_EL1__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL1__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL1_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL1_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL1_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL1_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL2__A                                                0x1440024
#define QAM_DQ_TAP_RE_EL2__W                                                12
#define QAM_DQ_TAP_RE_EL2__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL2__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL2_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL2_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL2_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL2_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL2__A                                                0x1440025
#define QAM_DQ_TAP_IM_EL2__W                                                12
#define QAM_DQ_TAP_IM_EL2__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL2__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL2_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL2_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL2_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL2_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL3__A                                                0x1440026
#define QAM_DQ_TAP_RE_EL3__W                                                12
#define QAM_DQ_TAP_RE_EL3__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL3__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL3_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL3_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL3_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL3_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL3__A                                                0x1440027
#define QAM_DQ_TAP_IM_EL3__W                                                12
#define QAM_DQ_TAP_IM_EL3__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL3__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL3_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL3_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL3_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL3_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL4__A                                                0x1440028
#define QAM_DQ_TAP_RE_EL4__W                                                12
#define QAM_DQ_TAP_RE_EL4__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL4__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL4_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL4_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL4_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL4_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL4__A                                                0x1440029
#define QAM_DQ_TAP_IM_EL4__W                                                12
#define QAM_DQ_TAP_IM_EL4__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL4__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL4_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL4_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL4_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL4_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL5__A                                                0x144002A
#define QAM_DQ_TAP_RE_EL5__W                                                12
#define QAM_DQ_TAP_RE_EL5__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL5__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL5_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL5_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL5_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL5_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL5__A                                                0x144002B
#define QAM_DQ_TAP_IM_EL5__W                                                12
#define QAM_DQ_TAP_IM_EL5__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL5__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL5_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL5_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL5_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL5_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL6__A                                                0x144002C
#define QAM_DQ_TAP_RE_EL6__W                                                12
#define QAM_DQ_TAP_RE_EL6__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL6__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL6_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL6_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL6_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL6_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL6__A                                                0x144002D
#define QAM_DQ_TAP_IM_EL6__W                                                12
#define QAM_DQ_TAP_IM_EL6__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL6__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL6_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL6_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL6_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL6_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL7__A                                                0x144002E
#define QAM_DQ_TAP_RE_EL7__W                                                12
#define QAM_DQ_TAP_RE_EL7__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL7__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL7_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL7_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL7_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL7_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL7__A                                                0x144002F
#define QAM_DQ_TAP_IM_EL7__W                                                12
#define QAM_DQ_TAP_IM_EL7__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL7__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL7_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL7_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL7_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL7_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL8__A                                                0x1440030
#define QAM_DQ_TAP_RE_EL8__W                                                12
#define QAM_DQ_TAP_RE_EL8__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL8__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL8_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL8_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL8_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL8_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL8__A                                                0x1440031
#define QAM_DQ_TAP_IM_EL8__W                                                12
#define QAM_DQ_TAP_IM_EL8__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL8__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL8_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL8_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL8_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL8_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL9__A                                                0x1440032
#define QAM_DQ_TAP_RE_EL9__W                                                12
#define QAM_DQ_TAP_RE_EL9__M                                                0xFFF
#define QAM_DQ_TAP_RE_EL9__PRE                                              0x2

#define   QAM_DQ_TAP_RE_EL9_TAP__B                                          0
#define   QAM_DQ_TAP_RE_EL9_TAP__W                                          12
#define   QAM_DQ_TAP_RE_EL9_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_RE_EL9_TAP__PRE                                        0x2

#define QAM_DQ_TAP_IM_EL9__A                                                0x1440033
#define QAM_DQ_TAP_IM_EL9__W                                                12
#define QAM_DQ_TAP_IM_EL9__M                                                0xFFF
#define QAM_DQ_TAP_IM_EL9__PRE                                              0x2

#define   QAM_DQ_TAP_IM_EL9_TAP__B                                          0
#define   QAM_DQ_TAP_IM_EL9_TAP__W                                          12
#define   QAM_DQ_TAP_IM_EL9_TAP__M                                          0xFFF
#define   QAM_DQ_TAP_IM_EL9_TAP__PRE                                        0x2

#define QAM_DQ_TAP_RE_EL10__A                                               0x1440034
#define QAM_DQ_TAP_RE_EL10__W                                               12
#define QAM_DQ_TAP_RE_EL10__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL10__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL10_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL10_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL10_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL10_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL10__A                                               0x1440035
#define QAM_DQ_TAP_IM_EL10__W                                               12
#define QAM_DQ_TAP_IM_EL10__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL10__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL10_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL10_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL10_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL10_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL11__A                                               0x1440036
#define QAM_DQ_TAP_RE_EL11__W                                               12
#define QAM_DQ_TAP_RE_EL11__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL11__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL11_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL11_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL11_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL11_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL11__A                                               0x1440037
#define QAM_DQ_TAP_IM_EL11__W                                               12
#define QAM_DQ_TAP_IM_EL11__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL11__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL11_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL11_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL11_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL11_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL12__A                                               0x1440038
#define QAM_DQ_TAP_RE_EL12__W                                               12
#define QAM_DQ_TAP_RE_EL12__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL12__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL12_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL12_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL12_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL12_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL12__A                                               0x1440039
#define QAM_DQ_TAP_IM_EL12__W                                               12
#define QAM_DQ_TAP_IM_EL12__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL12__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL12_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL12_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL12_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL12_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL13__A                                               0x144003A
#define QAM_DQ_TAP_RE_EL13__W                                               12
#define QAM_DQ_TAP_RE_EL13__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL13__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL13_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL13_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL13_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL13_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL13__A                                               0x144003B
#define QAM_DQ_TAP_IM_EL13__W                                               12
#define QAM_DQ_TAP_IM_EL13__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL13__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL13_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL13_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL13_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL13_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL14__A                                               0x144003C
#define QAM_DQ_TAP_RE_EL14__W                                               12
#define QAM_DQ_TAP_RE_EL14__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL14__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL14_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL14_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL14_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL14_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL14__A                                               0x144003D
#define QAM_DQ_TAP_IM_EL14__W                                               12
#define QAM_DQ_TAP_IM_EL14__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL14__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL14_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL14_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL14_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL14_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL15__A                                               0x144003E
#define QAM_DQ_TAP_RE_EL15__W                                               12
#define QAM_DQ_TAP_RE_EL15__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL15__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL15_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL15_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL15_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL15_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL15__A                                               0x144003F
#define QAM_DQ_TAP_IM_EL15__W                                               12
#define QAM_DQ_TAP_IM_EL15__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL15__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL15_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL15_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL15_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL15_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL16__A                                               0x1440040
#define QAM_DQ_TAP_RE_EL16__W                                               12
#define QAM_DQ_TAP_RE_EL16__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL16__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL16_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL16_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL16_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL16_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL16__A                                               0x1440041
#define QAM_DQ_TAP_IM_EL16__W                                               12
#define QAM_DQ_TAP_IM_EL16__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL16__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL16_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL16_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL16_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL16_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL17__A                                               0x1440042
#define QAM_DQ_TAP_RE_EL17__W                                               12
#define QAM_DQ_TAP_RE_EL17__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL17__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL17_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL17_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL17_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL17_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL17__A                                               0x1440043
#define QAM_DQ_TAP_IM_EL17__W                                               12
#define QAM_DQ_TAP_IM_EL17__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL17__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL17_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL17_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL17_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL17_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL18__A                                               0x1440044
#define QAM_DQ_TAP_RE_EL18__W                                               12
#define QAM_DQ_TAP_RE_EL18__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL18__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL18_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL18_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL18_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL18_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL18__A                                               0x1440045
#define QAM_DQ_TAP_IM_EL18__W                                               12
#define QAM_DQ_TAP_IM_EL18__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL18__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL18_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL18_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL18_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL18_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL19__A                                               0x1440046
#define QAM_DQ_TAP_RE_EL19__W                                               12
#define QAM_DQ_TAP_RE_EL19__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL19__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL19_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL19_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL19_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL19_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL19__A                                               0x1440047
#define QAM_DQ_TAP_IM_EL19__W                                               12
#define QAM_DQ_TAP_IM_EL19__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL19__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL19_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL19_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL19_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL19_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL20__A                                               0x1440048
#define QAM_DQ_TAP_RE_EL20__W                                               12
#define QAM_DQ_TAP_RE_EL20__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL20__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL20_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL20_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL20_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL20_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL20__A                                               0x1440049
#define QAM_DQ_TAP_IM_EL20__W                                               12
#define QAM_DQ_TAP_IM_EL20__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL20__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL20_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL20_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL20_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL20_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL21__A                                               0x144004A
#define QAM_DQ_TAP_RE_EL21__W                                               12
#define QAM_DQ_TAP_RE_EL21__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL21__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL21_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL21_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL21_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL21_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL21__A                                               0x144004B
#define QAM_DQ_TAP_IM_EL21__W                                               12
#define QAM_DQ_TAP_IM_EL21__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL21__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL21_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL21_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL21_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL21_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL22__A                                               0x144004C
#define QAM_DQ_TAP_RE_EL22__W                                               12
#define QAM_DQ_TAP_RE_EL22__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL22__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL22_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL22_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL22_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL22_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL22__A                                               0x144004D
#define QAM_DQ_TAP_IM_EL22__W                                               12
#define QAM_DQ_TAP_IM_EL22__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL22__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL22_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL22_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL22_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL22_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL23__A                                               0x144004E
#define QAM_DQ_TAP_RE_EL23__W                                               12
#define QAM_DQ_TAP_RE_EL23__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL23__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL23_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL23_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL23_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL23_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL23__A                                               0x144004F
#define QAM_DQ_TAP_IM_EL23__W                                               12
#define QAM_DQ_TAP_IM_EL23__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL23__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL23_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL23_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL23_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL23_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL24__A                                               0x1440050
#define QAM_DQ_TAP_RE_EL24__W                                               12
#define QAM_DQ_TAP_RE_EL24__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL24__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL24_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL24_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL24_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL24_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL24__A                                               0x1440051
#define QAM_DQ_TAP_IM_EL24__W                                               12
#define QAM_DQ_TAP_IM_EL24__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL24__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL24_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL24_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL24_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL24_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL25__A                                               0x1440052
#define QAM_DQ_TAP_RE_EL25__W                                               12
#define QAM_DQ_TAP_RE_EL25__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL25__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL25_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL25_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL25_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL25_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL25__A                                               0x1440053
#define QAM_DQ_TAP_IM_EL25__W                                               12
#define QAM_DQ_TAP_IM_EL25__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL25__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL25_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL25_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL25_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL25_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL26__A                                               0x1440054
#define QAM_DQ_TAP_RE_EL26__W                                               12
#define QAM_DQ_TAP_RE_EL26__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL26__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL26_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL26_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL26_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL26_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL26__A                                               0x1440055
#define QAM_DQ_TAP_IM_EL26__W                                               12
#define QAM_DQ_TAP_IM_EL26__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL26__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL26_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL26_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL26_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL26_TAP__PRE                                       0x2

#define QAM_DQ_TAP_RE_EL27__A                                               0x1440056
#define QAM_DQ_TAP_RE_EL27__W                                               12
#define QAM_DQ_TAP_RE_EL27__M                                               0xFFF
#define QAM_DQ_TAP_RE_EL27__PRE                                             0x2

#define   QAM_DQ_TAP_RE_EL27_TAP__B                                         0
#define   QAM_DQ_TAP_RE_EL27_TAP__W                                         12
#define   QAM_DQ_TAP_RE_EL27_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_RE_EL27_TAP__PRE                                       0x2

#define QAM_DQ_TAP_IM_EL27__A                                               0x1440057
#define QAM_DQ_TAP_IM_EL27__W                                               12
#define QAM_DQ_TAP_IM_EL27__M                                               0xFFF
#define QAM_DQ_TAP_IM_EL27__PRE                                             0x2

#define   QAM_DQ_TAP_IM_EL27_TAP__B                                         0
#define   QAM_DQ_TAP_IM_EL27_TAP__W                                         12
#define   QAM_DQ_TAP_IM_EL27_TAP__M                                         0xFFF
#define   QAM_DQ_TAP_IM_EL27_TAP__PRE                                       0x2

#define QAM_LC_COMM_EXEC__A                                                 0x1450000
#define QAM_LC_COMM_EXEC__W                                                 2
#define QAM_LC_COMM_EXEC__M                                                 0x3
#define QAM_LC_COMM_EXEC__PRE                                               0x0
#define   QAM_LC_COMM_EXEC_STOP                                             0x0
#define   QAM_LC_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_LC_COMM_EXEC_HOLD                                             0x2

#define QAM_LC_COMM_MB__A                                                   0x1450002
#define QAM_LC_COMM_MB__W                                                   2
#define QAM_LC_COMM_MB__M                                                   0x3
#define QAM_LC_COMM_MB__PRE                                                 0x0
#define   QAM_LC_COMM_MB_CTL__B                                             0
#define   QAM_LC_COMM_MB_CTL__W                                             1
#define   QAM_LC_COMM_MB_CTL__M                                             0x1
#define   QAM_LC_COMM_MB_CTL__PRE                                           0x0
#define     QAM_LC_COMM_MB_CTL_OFF                                          0x0
#define     QAM_LC_COMM_MB_CTL_ON                                           0x1
#define   QAM_LC_COMM_MB_OBS__B                                             1
#define   QAM_LC_COMM_MB_OBS__W                                             1
#define   QAM_LC_COMM_MB_OBS__M                                             0x2
#define   QAM_LC_COMM_MB_OBS__PRE                                           0x0
#define     QAM_LC_COMM_MB_OBS_OFF                                          0x0
#define     QAM_LC_COMM_MB_OBS_ON                                           0x2

#define QAM_LC_COMM_INT_REQ__A                                              0x1450003
#define QAM_LC_COMM_INT_REQ__W                                              1
#define QAM_LC_COMM_INT_REQ__M                                              0x1
#define QAM_LC_COMM_INT_REQ__PRE                                            0x0
#define QAM_LC_COMM_INT_STA__A                                              0x1450005
#define QAM_LC_COMM_INT_STA__W                                              3
#define QAM_LC_COMM_INT_STA__M                                              0x7
#define QAM_LC_COMM_INT_STA__PRE                                            0x0

#define   QAM_LC_COMM_INT_STA_READY__B                                      0
#define   QAM_LC_COMM_INT_STA_READY__W                                      1
#define   QAM_LC_COMM_INT_STA_READY__M                                      0x1
#define   QAM_LC_COMM_INT_STA_READY__PRE                                    0x0

#define   QAM_LC_COMM_INT_STA_OVERFLOW__B                                   1
#define   QAM_LC_COMM_INT_STA_OVERFLOW__W                                   1
#define   QAM_LC_COMM_INT_STA_OVERFLOW__M                                   0x2
#define   QAM_LC_COMM_INT_STA_OVERFLOW__PRE                                 0x0

#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__B                                  2
#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__W                                  1
#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__M                                  0x4
#define   QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE                                0x0

#define QAM_LC_COMM_INT_MSK__A                                              0x1450006
#define QAM_LC_COMM_INT_MSK__W                                              3
#define QAM_LC_COMM_INT_MSK__M                                              0x7
#define QAM_LC_COMM_INT_MSK__PRE                                            0x0
#define   QAM_LC_COMM_INT_MSK_READY__B                                      0
#define   QAM_LC_COMM_INT_MSK_READY__W                                      1
#define   QAM_LC_COMM_INT_MSK_READY__M                                      0x1
#define   QAM_LC_COMM_INT_MSK_READY__PRE                                    0x0
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__B                                   1
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__W                                   1
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__M                                   0x2
#define   QAM_LC_COMM_INT_MSK_OVERFLOW__PRE                                 0x0
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__B                                  2
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__W                                  1
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__M                                  0x4
#define   QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE                                0x0

#define QAM_LC_COMM_INT_STM__A                                              0x1450007
#define QAM_LC_COMM_INT_STM__W                                              3
#define QAM_LC_COMM_INT_STM__M                                              0x7
#define QAM_LC_COMM_INT_STM__PRE                                            0x0
#define   QAM_LC_COMM_INT_STM_READY__B                                      0
#define   QAM_LC_COMM_INT_STM_READY__W                                      1
#define   QAM_LC_COMM_INT_STM_READY__M                                      0x1
#define   QAM_LC_COMM_INT_STM_READY__PRE                                    0x0
#define   QAM_LC_COMM_INT_STM_OVERFLOW__B                                   1
#define   QAM_LC_COMM_INT_STM_OVERFLOW__W                                   1
#define   QAM_LC_COMM_INT_STM_OVERFLOW__M                                   0x2
#define   QAM_LC_COMM_INT_STM_OVERFLOW__PRE                                 0x0
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__B                                  2
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__W                                  1
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__M                                  0x4
#define   QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE                                0x0

#define QAM_LC_MODE__A                                                      0x1450010
#define QAM_LC_MODE__W                                                      3
#define QAM_LC_MODE__M                                                      0x7
#define QAM_LC_MODE__PRE                                                    0x7

#define   QAM_LC_MODE_ENABLE_A__B                                           0
#define   QAM_LC_MODE_ENABLE_A__W                                           1
#define   QAM_LC_MODE_ENABLE_A__M                                           0x1
#define   QAM_LC_MODE_ENABLE_A__PRE                                         0x1

#define   QAM_LC_MODE_ENABLE_F__B                                           1
#define   QAM_LC_MODE_ENABLE_F__W                                           1
#define   QAM_LC_MODE_ENABLE_F__M                                           0x2
#define   QAM_LC_MODE_ENABLE_F__PRE                                         0x2

#define   QAM_LC_MODE_ENABLE_R__B                                           2
#define   QAM_LC_MODE_ENABLE_R__W                                           1
#define   QAM_LC_MODE_ENABLE_R__M                                           0x4
#define   QAM_LC_MODE_ENABLE_R__PRE                                         0x4

#define QAM_LC_CA__A                                                        0x1450011
#define QAM_LC_CA__W                                                        6
#define QAM_LC_CA__M                                                        0x3F
#define QAM_LC_CA__PRE                                                      0x28

#define   QAM_LC_CA_COEF__B                                                 0
#define   QAM_LC_CA_COEF__W                                                 6
#define   QAM_LC_CA_COEF__M                                                 0x3F
#define   QAM_LC_CA_COEF__PRE                                               0x28

#define QAM_LC_CF__A                                                        0x1450012
#define QAM_LC_CF__W                                                        8
#define QAM_LC_CF__M                                                        0xFF
#define QAM_LC_CF__PRE                                                      0x8C

#define   QAM_LC_CF_COEF__B                                                 0
#define   QAM_LC_CF_COEF__W                                                 8
#define   QAM_LC_CF_COEF__M                                                 0xFF
#define   QAM_LC_CF_COEF__PRE                                               0x8C

#define QAM_LC_CF1__A                                                       0x1450013
#define QAM_LC_CF1__W                                                       8
#define QAM_LC_CF1__M                                                       0xFF
#define QAM_LC_CF1__PRE                                                     0x1E

#define   QAM_LC_CF1_COEF__B                                                0
#define   QAM_LC_CF1_COEF__W                                                8
#define   QAM_LC_CF1_COEF__M                                                0xFF
#define   QAM_LC_CF1_COEF__PRE                                              0x1E

#define QAM_LC_CP__A                                                        0x1450014
#define QAM_LC_CP__W                                                        8
#define QAM_LC_CP__M                                                        0xFF
#define QAM_LC_CP__PRE                                                      0x78

#define   QAM_LC_CP_COEF__B                                                 0
#define   QAM_LC_CP_COEF__W                                                 8
#define   QAM_LC_CP_COEF__M                                                 0xFF
#define   QAM_LC_CP_COEF__PRE                                               0x78

#define QAM_LC_CI__A                                                        0x1450015
#define QAM_LC_CI__W                                                        8
#define QAM_LC_CI__M                                                        0xFF
#define QAM_LC_CI__PRE                                                      0x46

#define   QAM_LC_CI_COEF__B                                                 0
#define   QAM_LC_CI_COEF__W                                                 8
#define   QAM_LC_CI_COEF__M                                                 0xFF
#define   QAM_LC_CI_COEF__PRE                                               0x46

#define QAM_LC_EP__A                                                        0x1450016
#define QAM_LC_EP__W                                                        6
#define QAM_LC_EP__M                                                        0x3F
#define QAM_LC_EP__PRE                                                      0x0

#define   QAM_LC_EP_COEF__B                                                 0
#define   QAM_LC_EP_COEF__W                                                 6
#define   QAM_LC_EP_COEF__M                                                 0x3F
#define   QAM_LC_EP_COEF__PRE                                               0x0

#define QAM_LC_EI__A                                                        0x1450017
#define QAM_LC_EI__W                                                        6
#define QAM_LC_EI__M                                                        0x3F
#define QAM_LC_EI__PRE                                                      0x0

#define   QAM_LC_EI_COEF__B                                                 0
#define   QAM_LC_EI_COEF__W                                                 6
#define   QAM_LC_EI_COEF__M                                                 0x3F
#define   QAM_LC_EI_COEF__PRE                                               0x0

#define QAM_LC_QUAL_TAB0__A                                                 0x1450018
#define QAM_LC_QUAL_TAB0__W                                                 5
#define QAM_LC_QUAL_TAB0__M                                                 0x1F
#define QAM_LC_QUAL_TAB0__PRE                                               0x1

#define   QAM_LC_QUAL_TAB0_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB0_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB0_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB0_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB1__A                                                 0x1450019
#define QAM_LC_QUAL_TAB1__W                                                 5
#define QAM_LC_QUAL_TAB1__M                                                 0x1F
#define QAM_LC_QUAL_TAB1__PRE                                               0x1

#define   QAM_LC_QUAL_TAB1_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB1_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB1_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB1_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB2__A                                                 0x145001A
#define QAM_LC_QUAL_TAB2__W                                                 5
#define QAM_LC_QUAL_TAB2__M                                                 0x1F
#define QAM_LC_QUAL_TAB2__PRE                                               0x1

#define   QAM_LC_QUAL_TAB2_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB2_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB2_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB2_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB3__A                                                 0x145001B
#define QAM_LC_QUAL_TAB3__W                                                 5
#define QAM_LC_QUAL_TAB3__M                                                 0x1F
#define QAM_LC_QUAL_TAB3__PRE                                               0x1

#define   QAM_LC_QUAL_TAB3_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB3_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB3_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB3_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB4__A                                                 0x145001C
#define QAM_LC_QUAL_TAB4__W                                                 5
#define QAM_LC_QUAL_TAB4__M                                                 0x1F
#define QAM_LC_QUAL_TAB4__PRE                                               0x1

#define   QAM_LC_QUAL_TAB4_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB4_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB4_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB4_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB5__A                                                 0x145001D
#define QAM_LC_QUAL_TAB5__W                                                 5
#define QAM_LC_QUAL_TAB5__M                                                 0x1F
#define QAM_LC_QUAL_TAB5__PRE                                               0x1

#define   QAM_LC_QUAL_TAB5_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB5_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB5_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB5_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB6__A                                                 0x145001E
#define QAM_LC_QUAL_TAB6__W                                                 5
#define QAM_LC_QUAL_TAB6__M                                                 0x1F
#define QAM_LC_QUAL_TAB6__PRE                                               0x1

#define   QAM_LC_QUAL_TAB6_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB6_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB6_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB6_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB8__A                                                 0x145001F
#define QAM_LC_QUAL_TAB8__W                                                 5
#define QAM_LC_QUAL_TAB8__M                                                 0x1F
#define QAM_LC_QUAL_TAB8__PRE                                               0x1

#define   QAM_LC_QUAL_TAB8_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB8_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB8_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB8_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB9__A                                                 0x1450020
#define QAM_LC_QUAL_TAB9__W                                                 5
#define QAM_LC_QUAL_TAB9__M                                                 0x1F
#define QAM_LC_QUAL_TAB9__PRE                                               0x1

#define   QAM_LC_QUAL_TAB9_VALUE__B                                         0
#define   QAM_LC_QUAL_TAB9_VALUE__W                                         5
#define   QAM_LC_QUAL_TAB9_VALUE__M                                         0x1F
#define   QAM_LC_QUAL_TAB9_VALUE__PRE                                       0x1

#define QAM_LC_QUAL_TAB10__A                                                0x1450021
#define QAM_LC_QUAL_TAB10__W                                                5
#define QAM_LC_QUAL_TAB10__M                                                0x1F
#define QAM_LC_QUAL_TAB10__PRE                                              0x1

#define   QAM_LC_QUAL_TAB10_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB10_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB10_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB10_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB12__A                                                0x1450022
#define QAM_LC_QUAL_TAB12__W                                                5
#define QAM_LC_QUAL_TAB12__M                                                0x1F
#define QAM_LC_QUAL_TAB12__PRE                                              0x1

#define   QAM_LC_QUAL_TAB12_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB12_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB12_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB12_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB15__A                                                0x1450023
#define QAM_LC_QUAL_TAB15__W                                                5
#define QAM_LC_QUAL_TAB15__M                                                0x1F
#define QAM_LC_QUAL_TAB15__PRE                                              0x1

#define   QAM_LC_QUAL_TAB15_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB15_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB15_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB15_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB16__A                                                0x1450024
#define QAM_LC_QUAL_TAB16__W                                                5
#define QAM_LC_QUAL_TAB16__M                                                0x1F
#define QAM_LC_QUAL_TAB16__PRE                                              0x1

#define   QAM_LC_QUAL_TAB16_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB16_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB16_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB16_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB20__A                                                0x1450025
#define QAM_LC_QUAL_TAB20__W                                                5
#define QAM_LC_QUAL_TAB20__M                                                0x1F
#define QAM_LC_QUAL_TAB20__PRE                                              0x1

#define   QAM_LC_QUAL_TAB20_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB20_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB20_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB20_VALUE__PRE                                      0x1

#define QAM_LC_QUAL_TAB25__A                                                0x1450026
#define QAM_LC_QUAL_TAB25__W                                                5
#define QAM_LC_QUAL_TAB25__M                                                0x1F
#define QAM_LC_QUAL_TAB25__PRE                                              0x1

#define   QAM_LC_QUAL_TAB25_VALUE__B                                        0
#define   QAM_LC_QUAL_TAB25_VALUE__W                                        5
#define   QAM_LC_QUAL_TAB25_VALUE__M                                        0x1F
#define   QAM_LC_QUAL_TAB25_VALUE__PRE                                      0x1

#define QAM_LC_EQ_TIMING__A                                                 0x1450027
#define QAM_LC_EQ_TIMING__W                                                 10
#define QAM_LC_EQ_TIMING__M                                                 0x3FF
#define QAM_LC_EQ_TIMING__PRE                                               0x0

#define   QAM_LC_EQ_TIMING_OFFS__B                                          0
#define   QAM_LC_EQ_TIMING_OFFS__W                                          10
#define   QAM_LC_EQ_TIMING_OFFS__M                                          0x3FF
#define   QAM_LC_EQ_TIMING_OFFS__PRE                                        0x0

#define QAM_LC_LPF_FACTORP__A                                               0x1450028
#define QAM_LC_LPF_FACTORP__W                                               3
#define QAM_LC_LPF_FACTORP__M                                               0x7
#define QAM_LC_LPF_FACTORP__PRE                                             0x3

#define   QAM_LC_LPF_FACTORP_FACTOR__B                                      0
#define   QAM_LC_LPF_FACTORP_FACTOR__W                                      3
#define   QAM_LC_LPF_FACTORP_FACTOR__M                                      0x7
#define   QAM_LC_LPF_FACTORP_FACTOR__PRE                                    0x3

#define QAM_LC_LPF_FACTORI__A                                               0x1450029
#define QAM_LC_LPF_FACTORI__W                                               3
#define QAM_LC_LPF_FACTORI__M                                               0x7
#define QAM_LC_LPF_FACTORI__PRE                                             0x3

#define   QAM_LC_LPF_FACTORI_FACTOR__B                                      0
#define   QAM_LC_LPF_FACTORI_FACTOR__W                                      3
#define   QAM_LC_LPF_FACTORI_FACTOR__M                                      0x7
#define   QAM_LC_LPF_FACTORI_FACTOR__PRE                                    0x3

#define QAM_LC_RATE_LIMIT__A                                                0x145002A
#define QAM_LC_RATE_LIMIT__W                                                2
#define QAM_LC_RATE_LIMIT__M                                                0x3
#define QAM_LC_RATE_LIMIT__PRE                                              0x3

#define   QAM_LC_RATE_LIMIT_LIMIT__B                                        0
#define   QAM_LC_RATE_LIMIT_LIMIT__W                                        2
#define   QAM_LC_RATE_LIMIT_LIMIT__M                                        0x3
#define   QAM_LC_RATE_LIMIT_LIMIT__PRE                                      0x3

#define QAM_LC_SYMBOL_FREQ__A                                               0x145002B
#define QAM_LC_SYMBOL_FREQ__W                                               10
#define QAM_LC_SYMBOL_FREQ__M                                               0x3FF
#define QAM_LC_SYMBOL_FREQ__PRE                                             0x199

#define   QAM_LC_SYMBOL_FREQ_FREQ__B                                        0
#define   QAM_LC_SYMBOL_FREQ_FREQ__W                                        10
#define   QAM_LC_SYMBOL_FREQ_FREQ__M                                        0x3FF
#define   QAM_LC_SYMBOL_FREQ_FREQ__PRE                                      0x199
#define     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64                                0x197
#define     QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256                               0x1B2

#define QAM_LC_MTA_LENGTH__A                                                0x145002C
#define QAM_LC_MTA_LENGTH__W                                                2
#define QAM_LC_MTA_LENGTH__M                                                0x3
#define QAM_LC_MTA_LENGTH__PRE                                              0x2

#define   QAM_LC_MTA_LENGTH_LENGTH__B                                       0
#define   QAM_LC_MTA_LENGTH_LENGTH__W                                       2
#define   QAM_LC_MTA_LENGTH_LENGTH__M                                       0x3
#define   QAM_LC_MTA_LENGTH_LENGTH__PRE                                     0x2

#define QAM_LC_AMP_ACCU__A                                                  0x145002D
#define QAM_LC_AMP_ACCU__W                                                  14
#define QAM_LC_AMP_ACCU__M                                                  0x3FFF
#define QAM_LC_AMP_ACCU__PRE                                                0x600

#define   QAM_LC_AMP_ACCU_ACCU__B                                           0
#define   QAM_LC_AMP_ACCU_ACCU__W                                           14
#define   QAM_LC_AMP_ACCU_ACCU__M                                           0x3FFF
#define   QAM_LC_AMP_ACCU_ACCU__PRE                                         0x600

#define QAM_LC_FREQ_ACCU__A                                                 0x145002E
#define QAM_LC_FREQ_ACCU__W                                                 10
#define QAM_LC_FREQ_ACCU__M                                                 0x3FF
#define QAM_LC_FREQ_ACCU__PRE                                               0x0

#define   QAM_LC_FREQ_ACCU_ACCU__B                                          0
#define   QAM_LC_FREQ_ACCU_ACCU__W                                          10
#define   QAM_LC_FREQ_ACCU_ACCU__M                                          0x3FF
#define   QAM_LC_FREQ_ACCU_ACCU__PRE                                        0x0

#define QAM_LC_RATE_ACCU__A                                                 0x145002F
#define QAM_LC_RATE_ACCU__W                                                 10
#define QAM_LC_RATE_ACCU__M                                                 0x3FF
#define QAM_LC_RATE_ACCU__PRE                                               0x0

#define   QAM_LC_RATE_ACCU_ACCU__B                                          0
#define   QAM_LC_RATE_ACCU_ACCU__W                                          10
#define   QAM_LC_RATE_ACCU_ACCU__M                                          0x3FF
#define   QAM_LC_RATE_ACCU_ACCU__PRE                                        0x0

#define QAM_LC_AMPLITUDE__A                                                 0x1450030
#define QAM_LC_AMPLITUDE__W                                                 10
#define QAM_LC_AMPLITUDE__M                                                 0x3FF
#define QAM_LC_AMPLITUDE__PRE                                               0x0

#define   QAM_LC_AMPLITUDE_SIZE__B                                          0
#define   QAM_LC_AMPLITUDE_SIZE__W                                          10
#define   QAM_LC_AMPLITUDE_SIZE__M                                          0x3FF
#define   QAM_LC_AMPLITUDE_SIZE__PRE                                        0x0

#define QAM_LC_RAD_ERROR__A                                                 0x1450031
#define QAM_LC_RAD_ERROR__W                                                 10
#define QAM_LC_RAD_ERROR__M                                                 0x3FF
#define QAM_LC_RAD_ERROR__PRE                                               0x0

#define   QAM_LC_RAD_ERROR_SIZE__B                                          0
#define   QAM_LC_RAD_ERROR_SIZE__W                                          10
#define   QAM_LC_RAD_ERROR_SIZE__M                                          0x3FF
#define   QAM_LC_RAD_ERROR_SIZE__PRE                                        0x0

#define QAM_LC_FREQ_OFFS__A                                                 0x1450032
#define QAM_LC_FREQ_OFFS__W                                                 10
#define QAM_LC_FREQ_OFFS__M                                                 0x3FF
#define QAM_LC_FREQ_OFFS__PRE                                               0x0

#define   QAM_LC_FREQ_OFFS_OFFS__B                                          0
#define   QAM_LC_FREQ_OFFS_OFFS__W                                          10
#define   QAM_LC_FREQ_OFFS_OFFS__M                                          0x3FF
#define   QAM_LC_FREQ_OFFS_OFFS__PRE                                        0x0

#define QAM_LC_PHASE_ERROR__A                                               0x1450033
#define QAM_LC_PHASE_ERROR__W                                               10
#define QAM_LC_PHASE_ERROR__M                                               0x3FF
#define QAM_LC_PHASE_ERROR__PRE                                             0x0

#define   QAM_LC_PHASE_ERROR_SIZE__B                                        0
#define   QAM_LC_PHASE_ERROR_SIZE__W                                        10
#define   QAM_LC_PHASE_ERROR_SIZE__M                                        0x3FF
#define   QAM_LC_PHASE_ERROR_SIZE__PRE                                      0x0

#define QAM_VD_COMM_EXEC__A                                                 0x1460000
#define QAM_VD_COMM_EXEC__W                                                 2
#define QAM_VD_COMM_EXEC__M                                                 0x3
#define QAM_VD_COMM_EXEC__PRE                                               0x0
#define   QAM_VD_COMM_EXEC_STOP                                             0x0
#define   QAM_VD_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_VD_COMM_EXEC_HOLD                                             0x2

#define QAM_VD_COMM_MB__A                                                   0x1460002
#define QAM_VD_COMM_MB__W                                                   2
#define QAM_VD_COMM_MB__M                                                   0x3
#define QAM_VD_COMM_MB__PRE                                                 0x0
#define   QAM_VD_COMM_MB_CTL__B                                             0
#define   QAM_VD_COMM_MB_CTL__W                                             1
#define   QAM_VD_COMM_MB_CTL__M                                             0x1
#define   QAM_VD_COMM_MB_CTL__PRE                                           0x0
#define     QAM_VD_COMM_MB_CTL_OFF                                          0x0
#define     QAM_VD_COMM_MB_CTL_ON                                           0x1
#define   QAM_VD_COMM_MB_OBS__B                                             1
#define   QAM_VD_COMM_MB_OBS__W                                             1
#define   QAM_VD_COMM_MB_OBS__M                                             0x2
#define   QAM_VD_COMM_MB_OBS__PRE                                           0x0
#define     QAM_VD_COMM_MB_OBS_OFF                                          0x0
#define     QAM_VD_COMM_MB_OBS_ON                                           0x2

#define QAM_VD_COMM_INT_REQ__A                                              0x1460003
#define QAM_VD_COMM_INT_REQ__W                                              1
#define QAM_VD_COMM_INT_REQ__M                                              0x1
#define QAM_VD_COMM_INT_REQ__PRE                                            0x0
#define QAM_VD_COMM_INT_STA__A                                              0x1460005
#define QAM_VD_COMM_INT_STA__W                                              2
#define QAM_VD_COMM_INT_STA__M                                              0x3
#define QAM_VD_COMM_INT_STA__PRE                                            0x0

#define   QAM_VD_COMM_INT_STA_LOCK_INT__B                                   0
#define   QAM_VD_COMM_INT_STA_LOCK_INT__W                                   1
#define   QAM_VD_COMM_INT_STA_LOCK_INT__M                                   0x1
#define   QAM_VD_COMM_INT_STA_LOCK_INT__PRE                                 0x0

#define   QAM_VD_COMM_INT_STA_PERIOD_INT__B                                 1
#define   QAM_VD_COMM_INT_STA_PERIOD_INT__W                                 1
#define   QAM_VD_COMM_INT_STA_PERIOD_INT__M                                 0x2
#define   QAM_VD_COMM_INT_STA_PERIOD_INT__PRE                               0x0

#define QAM_VD_COMM_INT_MSK__A                                              0x1460006
#define QAM_VD_COMM_INT_MSK__W                                              2
#define QAM_VD_COMM_INT_MSK__M                                              0x3
#define QAM_VD_COMM_INT_MSK__PRE                                            0x0
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__B                                   0
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__W                                   1
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__M                                   0x1
#define   QAM_VD_COMM_INT_MSK_LOCK_INT__PRE                                 0x0
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__B                                 1
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__W                                 1
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__M                                 0x2
#define   QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE                               0x0

#define QAM_VD_COMM_INT_STM__A                                              0x1460007
#define QAM_VD_COMM_INT_STM__W                                              2
#define QAM_VD_COMM_INT_STM__M                                              0x3
#define QAM_VD_COMM_INT_STM__PRE                                            0x0
#define   QAM_VD_COMM_INT_STM_LOCK_INT__B                                   0
#define   QAM_VD_COMM_INT_STM_LOCK_INT__W                                   1
#define   QAM_VD_COMM_INT_STM_LOCK_INT__M                                   0x1
#define   QAM_VD_COMM_INT_STM_LOCK_INT__PRE                                 0x0
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__B                                 1
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__W                                 1
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__M                                 0x2
#define   QAM_VD_COMM_INT_STM_PERIOD_INT__PRE                               0x0

#define QAM_VD_STATUS__A                                                    0x1460010
#define QAM_VD_STATUS__W                                                    1
#define QAM_VD_STATUS__M                                                    0x1
#define QAM_VD_STATUS__PRE                                                  0x0

#define   QAM_VD_STATUS_LOCK__B                                             0
#define   QAM_VD_STATUS_LOCK__W                                             1
#define   QAM_VD_STATUS_LOCK__M                                             0x1
#define   QAM_VD_STATUS_LOCK__PRE                                           0x0

#define QAM_VD_UNLOCK_CONTROL__A                                            0x1460011
#define QAM_VD_UNLOCK_CONTROL__W                                            1
#define QAM_VD_UNLOCK_CONTROL__M                                            0x1
#define QAM_VD_UNLOCK_CONTROL__PRE                                          0x0

#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B                              0
#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W                              1
#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M                              0x1
#define   QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE                            0x0

#define QAM_VD_MIN_VOTING_ROUNDS__A                                         0x1460012
#define QAM_VD_MIN_VOTING_ROUNDS__W                                         6
#define QAM_VD_MIN_VOTING_ROUNDS__M                                         0x3F
#define QAM_VD_MIN_VOTING_ROUNDS__PRE                                       0x10

#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B                                0
#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W                                6
#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M                                0x3F
#define   QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE                              0x10

#define QAM_VD_MAX_VOTING_ROUNDS__A                                         0x1460013
#define QAM_VD_MAX_VOTING_ROUNDS__W                                         6
#define QAM_VD_MAX_VOTING_ROUNDS__M                                         0x3F
#define QAM_VD_MAX_VOTING_ROUNDS__PRE                                       0x10

#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B                                0
#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W                                6
#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M                                0x3F
#define   QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE                              0x10

#define QAM_VD_TRACEBACK_DEPTH__A                                           0x1460014
#define QAM_VD_TRACEBACK_DEPTH__W                                           5
#define QAM_VD_TRACEBACK_DEPTH__M                                           0x1F
#define QAM_VD_TRACEBACK_DEPTH__PRE                                         0x10

#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__B                                  0
#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__W                                  5
#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__M                                  0x1F
#define   QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE                                0x10

#define QAM_VD_UNLOCK__A                                                    0x1460015
#define QAM_VD_UNLOCK__W                                                    1
#define QAM_VD_UNLOCK__M                                                    0x1
#define QAM_VD_UNLOCK__PRE                                                  0x0
#define QAM_VD_MEASUREMENT_PERIOD__A                                        0x1460016
#define QAM_VD_MEASUREMENT_PERIOD__W                                        16
#define QAM_VD_MEASUREMENT_PERIOD__M                                        0xFFFF
#define QAM_VD_MEASUREMENT_PERIOD__PRE                                      0x8236

#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__B                               0
#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__W                               16
#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__M                               0xFFFF
#define   QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE                             0x8236

#define QAM_VD_MEASUREMENT_PRESCALE__A                                      0x1460017
#define QAM_VD_MEASUREMENT_PRESCALE__W                                      16
#define QAM_VD_MEASUREMENT_PRESCALE__M                                      0xFFFF
#define QAM_VD_MEASUREMENT_PRESCALE__PRE                                    0x4

#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B                           0
#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W                           16
#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M                           0xFFFF
#define   QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE                         0x4

#define QAM_VD_DELTA_PATH_METRIC__A                                         0x1460018
#define QAM_VD_DELTA_PATH_METRIC__W                                         16
#define QAM_VD_DELTA_PATH_METRIC__M                                         0xFFFF
#define QAM_VD_DELTA_PATH_METRIC__PRE                                       0xFFFF

#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B                            0
#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W                            12
#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M                            0xFFF
#define   QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE                          0xFFF

#define   QAM_VD_DELTA_PATH_METRIC_EXP__B                                   12
#define   QAM_VD_DELTA_PATH_METRIC_EXP__W                                   4
#define   QAM_VD_DELTA_PATH_METRIC_EXP__M                                   0xF000
#define   QAM_VD_DELTA_PATH_METRIC_EXP__PRE                                 0xF000

#define QAM_VD_NR_QSYM_ERRORS__A                                            0x1460019
#define QAM_VD_NR_QSYM_ERRORS__W                                            16
#define QAM_VD_NR_QSYM_ERRORS__M                                            0xFFFF
#define QAM_VD_NR_QSYM_ERRORS__PRE                                          0xFFFF

#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B                               0
#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W                               12
#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M                               0xFFF
#define   QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE                             0xFFF

#define   QAM_VD_NR_QSYM_ERRORS_EXP__B                                      12
#define   QAM_VD_NR_QSYM_ERRORS_EXP__W                                      4
#define   QAM_VD_NR_QSYM_ERRORS_EXP__M                                      0xF000
#define   QAM_VD_NR_QSYM_ERRORS_EXP__PRE                                    0xF000

#define QAM_VD_NR_SYMBOL_ERRORS__A                                          0x146001A
#define QAM_VD_NR_SYMBOL_ERRORS__W                                          16
#define QAM_VD_NR_SYMBOL_ERRORS__M                                          0xFFFF
#define QAM_VD_NR_SYMBOL_ERRORS__PRE                                        0xFFFF

#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B                             0
#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W                             12
#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M                             0xFFF
#define   QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE                           0xFFF

#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__B                                    12
#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__W                                    4
#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__M                                    0xF000
#define   QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE                                  0xF000

#define QAM_VD_RELOCK_COUNT__A                                              0x146001B
#define QAM_VD_RELOCK_COUNT__W                                              16
#define QAM_VD_RELOCK_COUNT__M                                              0xFFFF
#define QAM_VD_RELOCK_COUNT__PRE                                            0x0

#define   QAM_VD_RELOCK_COUNT_COUNT__B                                      0
#define   QAM_VD_RELOCK_COUNT_COUNT__W                                      8
#define   QAM_VD_RELOCK_COUNT_COUNT__M                                      0xFF
#define   QAM_VD_RELOCK_COUNT_COUNT__PRE                                    0x0

#define QAM_SY_COMM_EXEC__A                                                 0x1470000
#define QAM_SY_COMM_EXEC__W                                                 2
#define QAM_SY_COMM_EXEC__M                                                 0x3
#define QAM_SY_COMM_EXEC__PRE                                               0x0
#define   QAM_SY_COMM_EXEC_STOP                                             0x0
#define   QAM_SY_COMM_EXEC_ACTIVE                                           0x1
#define   QAM_SY_COMM_EXEC_HOLD                                             0x2

#define QAM_SY_COMM_MB__A                                                   0x1470002
#define QAM_SY_COMM_MB__W                                                   2
#define QAM_SY_COMM_MB__M                                                   0x3
#define QAM_SY_COMM_MB__PRE                                                 0x0
#define   QAM_SY_COMM_MB_CTL__B                                             0
#define   QAM_SY_COMM_MB_CTL__W                                             1
#define   QAM_SY_COMM_MB_CTL__M                                             0x1
#define   QAM_SY_COMM_MB_CTL__PRE                                           0x0
#define     QAM_SY_COMM_MB_CTL_OFF                                          0x0
#define     QAM_SY_COMM_MB_CTL_ON                                           0x1
#define   QAM_SY_COMM_MB_OBS__B                                             1
#define   QAM_SY_COMM_MB_OBS__W                                             1
#define   QAM_SY_COMM_MB_OBS__M                                             0x2
#define   QAM_SY_COMM_MB_OBS__PRE                                           0x0
#define     QAM_SY_COMM_MB_OBS_OFF                                          0x0
#define     QAM_SY_COMM_MB_OBS_ON                                           0x2

#define QAM_SY_COMM_INT_REQ__A                                              0x1470003
#define QAM_SY_COMM_INT_REQ__W                                              1
#define QAM_SY_COMM_INT_REQ__M                                              0x1
#define QAM_SY_COMM_INT_REQ__PRE                                            0x0
#define QAM_SY_COMM_INT_STA__A                                              0x1470005
#define QAM_SY_COMM_INT_STA__W                                              4
#define QAM_SY_COMM_INT_STA__M                                              0xF
#define QAM_SY_COMM_INT_STA__PRE                                            0x0

#define   QAM_SY_COMM_INT_STA_LOCK_INT__B                                   0
#define   QAM_SY_COMM_INT_STA_LOCK_INT__W                                   1
#define   QAM_SY_COMM_INT_STA_LOCK_INT__M                                   0x1
#define   QAM_SY_COMM_INT_STA_LOCK_INT__PRE                                 0x0

#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__B                                 1
#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__W                                 1
#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__M                                 0x2
#define   QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE                               0x0

#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__B                                2
#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__W                                1
#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__M                                0x4
#define   QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE                              0x0

#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__B                               3
#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__W                               1
#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__M                               0x8
#define   QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE                             0x0

#define QAM_SY_COMM_INT_MSK__A                                              0x1470006
#define QAM_SY_COMM_INT_MSK__W                                              4
#define QAM_SY_COMM_INT_MSK__M                                              0xF
#define QAM_SY_COMM_INT_MSK__PRE                                            0x0
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__B                                   0
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__W                                   1
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__M                                   0x1
#define   QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE                                 0x0
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B                                 1
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W                                 1
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M                                 0x2
#define   QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE                               0x0
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B                                2
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W                                1
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M                                0x4
#define   QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE                              0x0
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B                               3
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W                               1
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M                               0x8
#define   QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE                             0x0

#define QAM_SY_COMM_INT_STM__A                                              0x1470007
#define QAM_SY_COMM_INT_STM__W                                              4
#define QAM_SY_COMM_INT_STM__M                                              0xF
#define QAM_SY_COMM_INT_STM__PRE                                            0x0
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__B                                   0
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__W                                   1
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__M                                   0x1
#define   QAM_SY_COMM_INT_STM_LOCK_MSK__PRE                                 0x0
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__B                                 1
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__W                                 1
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__M                                 0x2
#define   QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE                               0x0
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B                                2
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W                                1
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M                                0x4
#define   QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE                              0x0
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B                               3
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W                               1
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M                               0x8
#define   QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE                             0x0

#define QAM_SY_STATUS__A                                                    0x1470010
#define QAM_SY_STATUS__W                                                    2
#define QAM_SY_STATUS__M                                                    0x3
#define QAM_SY_STATUS__PRE                                                  0x0

#define   QAM_SY_STATUS_SYNC_STATE__B                                       0
#define   QAM_SY_STATUS_SYNC_STATE__W                                       2
#define   QAM_SY_STATUS_SYNC_STATE__M                                       0x3
#define   QAM_SY_STATUS_SYNC_STATE__PRE                                     0x0

#define QAM_SY_TIMEOUT__A                                                   0x1470011
#define QAM_SY_TIMEOUT__W                                                   16
#define QAM_SY_TIMEOUT__M                                                   0xFFFF
#define QAM_SY_TIMEOUT__PRE                                                 0x3A98

#define QAM_SY_SYNC_LWM__A                                                  0x1470012
#define QAM_SY_SYNC_LWM__W                                                  4
#define QAM_SY_SYNC_LWM__M                                                  0xF
#define QAM_SY_SYNC_LWM__PRE                                                0x2

#define QAM_SY_SYNC_AWM__A                                                  0x1470013
#define QAM_SY_SYNC_AWM__W                                                  4
#define QAM_SY_SYNC_AWM__M                                                  0xF
#define QAM_SY_SYNC_AWM__PRE                                                0x3

#define QAM_SY_SYNC_HWM__A                                                  0x1470014
#define QAM_SY_SYNC_HWM__W                                                  4
#define QAM_SY_SYNC_HWM__M                                                  0xF
#define QAM_SY_SYNC_HWM__PRE                                                0x5

#define QAM_SY_UNLOCK__A                                                    0x1470015
#define QAM_SY_UNLOCK__W                                                    1
#define QAM_SY_UNLOCK__M                                                    0x1
#define QAM_SY_UNLOCK__PRE                                                  0x0
#define QAM_SY_CONTROL_WORD__A                                              0x1470016
#define QAM_SY_CONTROL_WORD__W                                              4
#define QAM_SY_CONTROL_WORD__M                                              0xF
#define QAM_SY_CONTROL_WORD__PRE                                            0x0

#define   QAM_SY_CONTROL_WORD_CTRL_WORD__B                                  0
#define   QAM_SY_CONTROL_WORD_CTRL_WORD__W                                  4
#define   QAM_SY_CONTROL_WORD_CTRL_WORD__M                                  0xF
#define   QAM_SY_CONTROL_WORD_CTRL_WORD__PRE                                0x0

#define QAM_VD_ISS_RAM__A                                                   0x1480000

#define QAM_VD_QSS_RAM__A                                                   0x1490000

#define QAM_VD_SYM_RAM__A                                                   0x14A0000

#define SCU_COMM_EXEC__A                                                    0x800000
#define SCU_COMM_EXEC__W                                                    2
#define SCU_COMM_EXEC__M                                                    0x3
#define SCU_COMM_EXEC__PRE                                                  0x0
#define   SCU_COMM_EXEC_STOP                                                0x0
#define   SCU_COMM_EXEC_ACTIVE                                              0x1
#define   SCU_COMM_EXEC_HOLD                                                0x2

#define SCU_COMM_STATE__A                                                   0x800001
#define SCU_COMM_STATE__W                                                   16
#define SCU_COMM_STATE__M                                                   0xFFFF
#define SCU_COMM_STATE__PRE                                                 0x0

#define   SCU_COMM_STATE_COMM_STATE__B                                      0
#define   SCU_COMM_STATE_COMM_STATE__W                                      16
#define   SCU_COMM_STATE_COMM_STATE__M                                      0xFFFF
#define   SCU_COMM_STATE_COMM_STATE__PRE                                    0x0

#define SCU_TOP_COMM_EXEC__A                                                0x810000
#define SCU_TOP_COMM_EXEC__W                                                2
#define SCU_TOP_COMM_EXEC__M                                                0x3
#define SCU_TOP_COMM_EXEC__PRE                                              0x0
#define   SCU_TOP_COMM_EXEC_STOP                                            0x0
#define   SCU_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   SCU_TOP_COMM_EXEC_HOLD                                            0x2

#define SCU_TOP_COMM_STATE__A                                               0x810001
#define SCU_TOP_COMM_STATE__W                                               16
#define SCU_TOP_COMM_STATE__M                                               0xFFFF
#define SCU_TOP_COMM_STATE__PRE                                             0x0
#define SCU_TOP_MWAIT_CTR__A                                                0x810010
#define SCU_TOP_MWAIT_CTR__W                                                2
#define SCU_TOP_MWAIT_CTR__M                                                0x3
#define SCU_TOP_MWAIT_CTR__PRE                                              0x0

#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__B                                    0
#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__W                                    1
#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__M                                    0x1
#define   SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE                                  0x0
#define     SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF                           0x0
#define     SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON                            0x1

#define   SCU_TOP_MWAIT_CTR_READY_DIS__B                                    1
#define   SCU_TOP_MWAIT_CTR_READY_DIS__W                                    1
#define   SCU_TOP_MWAIT_CTR_READY_DIS__M                                    0x2
#define   SCU_TOP_MWAIT_CTR_READY_DIS__PRE                                  0x0
#define     SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON                              0x0
#define     SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF                             0x2

#define SCU_LOW_RAM__A                                                      0x820000

#define   SCU_LOW_RAM_LOW__B                                                0
#define   SCU_LOW_RAM_LOW__W                                                16
#define   SCU_LOW_RAM_LOW__M                                                0xFFFF
#define   SCU_LOW_RAM_LOW__PRE                                              0x0

#define SCU_HIGH_RAM__A                                                     0x830000

#define   SCU_HIGH_RAM_HIGH__B                                              0
#define   SCU_HIGH_RAM_HIGH__W                                              16
#define   SCU_HIGH_RAM_HIGH__M                                              0xFFFF
#define   SCU_HIGH_RAM_HIGH__PRE                                            0x0

#define SCU_RAM_AGC_RF_MAX__A                                               0x831E96
#define SCU_RAM_AGC_RF_MAX__W                                               15
#define SCU_RAM_AGC_RF_MAX__M                                               0x7FFF
#define SCU_RAM_AGC_RF_MAX__PRE                                             0x0

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A                                  0x831E97
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W                                  16
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M                                  0xFFFF
#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE                                0x0

#define SCU_RAM_AGC_KI_CYCCNT__A                                            0x831E98
#define SCU_RAM_AGC_KI_CYCCNT__W                                            16
#define SCU_RAM_AGC_KI_CYCCNT__M                                            0xFFFF
#define SCU_RAM_AGC_KI_CYCCNT__PRE                                          0x0

#define SCU_RAM_AGC_KI_CYCLEN__A                                            0x831E99
#define SCU_RAM_AGC_KI_CYCLEN__W                                            16
#define SCU_RAM_AGC_KI_CYCLEN__M                                            0xFFFF
#define SCU_RAM_AGC_KI_CYCLEN__PRE                                          0x0

#define SCU_RAM_AGC_SNS_CYCLEN__A                                           0x831E9A
#define SCU_RAM_AGC_SNS_CYCLEN__W                                           16
#define SCU_RAM_AGC_SNS_CYCLEN__M                                           0xFFFF
#define SCU_RAM_AGC_SNS_CYCLEN__PRE                                         0x0

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A                                       0x831E9B
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W                                       16
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M                                       0xFFFF
#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE                                     0x0

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A                                       0x831E9C
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W                                       16
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M                                       0xFFFF
#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE                                     0x0
#define SCU_RAM_AGC_KI__A                                                   0x831E9D
#define SCU_RAM_AGC_KI__W                                                   15
#define SCU_RAM_AGC_KI__M                                                   0x7FFF
#define SCU_RAM_AGC_KI__PRE                                                 0x0

#define   SCU_RAM_AGC_KI_DGAIN__B                                           0
#define   SCU_RAM_AGC_KI_DGAIN__W                                           4
#define   SCU_RAM_AGC_KI_DGAIN__M                                           0xF
#define   SCU_RAM_AGC_KI_DGAIN__PRE                                         0x0

#define   SCU_RAM_AGC_KI_RF__B                                              4
#define   SCU_RAM_AGC_KI_RF__W                                              4
#define   SCU_RAM_AGC_KI_RF__M                                              0xF0
#define   SCU_RAM_AGC_KI_RF__PRE                                            0x0

#define   SCU_RAM_AGC_KI_IF__B                                              8
#define   SCU_RAM_AGC_KI_IF__W                                              4
#define   SCU_RAM_AGC_KI_IF__M                                              0xF00
#define   SCU_RAM_AGC_KI_IF__PRE                                            0x0

#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__B                                  12
#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__W                                  1
#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__M                                  0x1000
#define   SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE                                0x0

#define   SCU_RAM_AGC_KI_INV_IF_POL__B                                      13
#define   SCU_RAM_AGC_KI_INV_IF_POL__W                                      1
#define   SCU_RAM_AGC_KI_INV_IF_POL__M                                      0x2000
#define   SCU_RAM_AGC_KI_INV_IF_POL__PRE                                    0x0

#define   SCU_RAM_AGC_KI_INV_RF_POL__B                                      14
#define   SCU_RAM_AGC_KI_INV_RF_POL__W                                      1
#define   SCU_RAM_AGC_KI_INV_RF_POL__M                                      0x4000
#define   SCU_RAM_AGC_KI_INV_RF_POL__PRE                                    0x0

#define SCU_RAM_AGC_KI_RED__A                                               0x831E9E
#define SCU_RAM_AGC_KI_RED__W                                               6
#define SCU_RAM_AGC_KI_RED__M                                               0x3F
#define SCU_RAM_AGC_KI_RED__PRE                                             0x0

#define   SCU_RAM_AGC_KI_RED_INNER_RED__B                                   0
#define   SCU_RAM_AGC_KI_RED_INNER_RED__W                                   2
#define   SCU_RAM_AGC_KI_RED_INNER_RED__M                                   0x3
#define   SCU_RAM_AGC_KI_RED_INNER_RED__PRE                                 0x0

#define   SCU_RAM_AGC_KI_RED_RAGC_RED__B                                    2
#define   SCU_RAM_AGC_KI_RED_RAGC_RED__W                                    2
#define   SCU_RAM_AGC_KI_RED_RAGC_RED__M                                    0xC
#define   SCU_RAM_AGC_KI_RED_RAGC_RED__PRE                                  0x0

#define   SCU_RAM_AGC_KI_RED_IAGC_RED__B                                    4
#define   SCU_RAM_AGC_KI_RED_IAGC_RED__W                                    2
#define   SCU_RAM_AGC_KI_RED_IAGC_RED__M                                    0x30
#define   SCU_RAM_AGC_KI_RED_IAGC_RED__PRE                                  0x0

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A                                     0x831E9F
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W                                     16
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M                                     0xFFFF
#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE                                   0x0

#define SCU_RAM_AGC_KI_MINGAIN__A                                           0x831EA0
#define SCU_RAM_AGC_KI_MINGAIN__W                                           16
#define SCU_RAM_AGC_KI_MINGAIN__M                                           0xFFFF
#define SCU_RAM_AGC_KI_MINGAIN__PRE                                         0x0

#define SCU_RAM_AGC_KI_MAXGAIN__A                                           0x831EA1
#define SCU_RAM_AGC_KI_MAXGAIN__W                                           16
#define SCU_RAM_AGC_KI_MAXGAIN__M                                           0xFFFF
#define SCU_RAM_AGC_KI_MAXGAIN__PRE                                         0x0

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A                                     0x831EA2
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W                                     16
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M                                     0xFFFF
#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE                                   0x0
#define SCU_RAM_AGC_KI_MIN__A                                               0x831EA3
#define SCU_RAM_AGC_KI_MIN__W                                               12
#define SCU_RAM_AGC_KI_MIN__M                                               0xFFF
#define SCU_RAM_AGC_KI_MIN__PRE                                             0x0

#define   SCU_RAM_AGC_KI_MIN_DGAIN__B                                       0
#define   SCU_RAM_AGC_KI_MIN_DGAIN__W                                       4
#define   SCU_RAM_AGC_KI_MIN_DGAIN__M                                       0xF
#define   SCU_RAM_AGC_KI_MIN_DGAIN__PRE                                     0x0

#define   SCU_RAM_AGC_KI_MIN_RF__B                                          4
#define   SCU_RAM_AGC_KI_MIN_RF__W                                          4
#define   SCU_RAM_AGC_KI_MIN_RF__M                                          0xF0
#define   SCU_RAM_AGC_KI_MIN_RF__PRE                                        0x0

#define   SCU_RAM_AGC_KI_MIN_IF__B                                          8
#define   SCU_RAM_AGC_KI_MIN_IF__W                                          4
#define   SCU_RAM_AGC_KI_MIN_IF__M                                          0xF00
#define   SCU_RAM_AGC_KI_MIN_IF__PRE                                        0x0

#define SCU_RAM_AGC_KI_MAX__A                                               0x831EA4
#define SCU_RAM_AGC_KI_MAX__W                                               12
#define SCU_RAM_AGC_KI_MAX__M                                               0xFFF
#define SCU_RAM_AGC_KI_MAX__PRE                                             0x0

#define   SCU_RAM_AGC_KI_MAX_DGAIN__B                                       0
#define   SCU_RAM_AGC_KI_MAX_DGAIN__W                                       4
#define   SCU_RAM_AGC_KI_MAX_DGAIN__M                                       0xF
#define   SCU_RAM_AGC_KI_MAX_DGAIN__PRE                                     0x0

#define   SCU_RAM_AGC_KI_MAX_RF__B                                          4
#define   SCU_RAM_AGC_KI_MAX_RF__W                                          4
#define   SCU_RAM_AGC_KI_MAX_RF__M                                          0xF0
#define   SCU_RAM_AGC_KI_MAX_RF__PRE                                        0x0

#define   SCU_RAM_AGC_KI_MAX_IF__B                                          8
#define   SCU_RAM_AGC_KI_MAX_IF__W                                          4
#define   SCU_RAM_AGC_KI_MAX_IF__M                                          0xF00
#define   SCU_RAM_AGC_KI_MAX_IF__PRE                                        0x0

#define SCU_RAM_AGC_CLP_SUM__A                                              0x831EA5
#define SCU_RAM_AGC_CLP_SUM__W                                              16
#define SCU_RAM_AGC_CLP_SUM__M                                              0xFFFF
#define SCU_RAM_AGC_CLP_SUM__PRE                                            0x0

#define SCU_RAM_AGC_CLP_SUM_MIN__A                                          0x831EA6
#define SCU_RAM_AGC_CLP_SUM_MIN__W                                          16
#define SCU_RAM_AGC_CLP_SUM_MIN__M                                          0xFFFF
#define SCU_RAM_AGC_CLP_SUM_MIN__PRE                                        0x0

#define SCU_RAM_AGC_CLP_SUM_MAX__A                                          0x831EA7
#define SCU_RAM_AGC_CLP_SUM_MAX__W                                          16
#define SCU_RAM_AGC_CLP_SUM_MAX__M                                          0xFFFF
#define SCU_RAM_AGC_CLP_SUM_MAX__PRE                                        0x0

#define SCU_RAM_AGC_CLP_CYCLEN__A                                           0x831EA8
#define SCU_RAM_AGC_CLP_CYCLEN__W                                           16
#define SCU_RAM_AGC_CLP_CYCLEN__M                                           0xFFFF
#define SCU_RAM_AGC_CLP_CYCLEN__PRE                                         0x0

#define SCU_RAM_AGC_CLP_CYCCNT__A                                           0x831EA9
#define SCU_RAM_AGC_CLP_CYCCNT__W                                           16
#define SCU_RAM_AGC_CLP_CYCCNT__M                                           0xFFFF
#define SCU_RAM_AGC_CLP_CYCCNT__PRE                                         0x0

#define SCU_RAM_AGC_CLP_DIR_TO__A                                           0x831EAA
#define SCU_RAM_AGC_CLP_DIR_TO__W                                           8
#define SCU_RAM_AGC_CLP_DIR_TO__M                                           0xFF
#define SCU_RAM_AGC_CLP_DIR_TO__PRE                                         0x0

#define SCU_RAM_AGC_CLP_DIR_WD__A                                           0x831EAB
#define SCU_RAM_AGC_CLP_DIR_WD__W                                           8
#define SCU_RAM_AGC_CLP_DIR_WD__M                                           0xFF
#define SCU_RAM_AGC_CLP_DIR_WD__PRE                                         0x0

#define SCU_RAM_AGC_CLP_DIR_STP__A                                          0x831EAC
#define SCU_RAM_AGC_CLP_DIR_STP__W                                          16
#define SCU_RAM_AGC_CLP_DIR_STP__M                                          0xFFFF
#define SCU_RAM_AGC_CLP_DIR_STP__PRE                                        0x0

#define SCU_RAM_AGC_SNS_SUM__A                                              0x831EAD
#define SCU_RAM_AGC_SNS_SUM__W                                              16
#define SCU_RAM_AGC_SNS_SUM__M                                              0xFFFF
#define SCU_RAM_AGC_SNS_SUM__PRE                                            0x0

#define SCU_RAM_AGC_SNS_SUM_MIN__A                                          0x831EAE
#define SCU_RAM_AGC_SNS_SUM_MIN__W                                          16
#define SCU_RAM_AGC_SNS_SUM_MIN__M                                          0xFFFF
#define SCU_RAM_AGC_SNS_SUM_MIN__PRE                                        0x0

#define SCU_RAM_AGC_SNS_SUM_MAX__A                                          0x831EAF
#define SCU_RAM_AGC_SNS_SUM_MAX__W                                          16
#define SCU_RAM_AGC_SNS_SUM_MAX__M                                          0xFFFF
#define SCU_RAM_AGC_SNS_SUM_MAX__PRE                                        0x0

#define SCU_RAM_AGC_SNS_CYCCNT__A                                           0x831EB0
#define SCU_RAM_AGC_SNS_CYCCNT__W                                           16
#define SCU_RAM_AGC_SNS_CYCCNT__M                                           0xFFFF
#define SCU_RAM_AGC_SNS_CYCCNT__PRE                                         0x0

#define SCU_RAM_AGC_SNS_DIR_TO__A                                           0x831EB1
#define SCU_RAM_AGC_SNS_DIR_TO__W                                           8
#define SCU_RAM_AGC_SNS_DIR_TO__M                                           0xFF
#define SCU_RAM_AGC_SNS_DIR_TO__PRE                                         0x0

#define SCU_RAM_AGC_SNS_DIR_WD__A                                           0x831EB2
#define SCU_RAM_AGC_SNS_DIR_WD__W                                           8
#define SCU_RAM_AGC_SNS_DIR_WD__M                                           0xFF
#define SCU_RAM_AGC_SNS_DIR_WD__PRE                                         0x0

#define SCU_RAM_AGC_SNS_DIR_STP__A                                          0x831EB3
#define SCU_RAM_AGC_SNS_DIR_STP__W                                          16
#define SCU_RAM_AGC_SNS_DIR_STP__M                                          0xFFFF
#define SCU_RAM_AGC_SNS_DIR_STP__PRE                                        0x0

#define SCU_RAM_AGC_INGAIN__A                                               0x831EB4
#define SCU_RAM_AGC_INGAIN__W                                               16
#define SCU_RAM_AGC_INGAIN__M                                               0xFFFF
#define SCU_RAM_AGC_INGAIN__PRE                                             0x0

#define SCU_RAM_AGC_INGAIN_TGT__A                                           0x831EB5
#define SCU_RAM_AGC_INGAIN_TGT__W                                           15
#define SCU_RAM_AGC_INGAIN_TGT__M                                           0x7FFF
#define SCU_RAM_AGC_INGAIN_TGT__PRE                                         0x0

#define SCU_RAM_AGC_INGAIN_TGT_MIN__A                                       0x831EB6
#define SCU_RAM_AGC_INGAIN_TGT_MIN__W                                       15
#define SCU_RAM_AGC_INGAIN_TGT_MIN__M                                       0x7FFF
#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE                                     0x0

#define SCU_RAM_AGC_INGAIN_TGT_MAX__A                                       0x831EB7
#define SCU_RAM_AGC_INGAIN_TGT_MAX__W                                       15
#define SCU_RAM_AGC_INGAIN_TGT_MAX__M                                       0x7FFF
#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE                                     0x0

#define SCU_RAM_AGC_IF_IACCU_HI__A                                          0x831EB8
#define SCU_RAM_AGC_IF_IACCU_HI__W                                          16
#define SCU_RAM_AGC_IF_IACCU_HI__M                                          0xFFFF
#define SCU_RAM_AGC_IF_IACCU_HI__PRE                                        0x0

#define SCU_RAM_AGC_IF_IACCU_LO__A                                          0x831EB9
#define SCU_RAM_AGC_IF_IACCU_LO__W                                          8
#define SCU_RAM_AGC_IF_IACCU_LO__M                                          0xFF
#define SCU_RAM_AGC_IF_IACCU_LO__PRE                                        0x0

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A                                      0x831EBA
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W                                      15
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M                                      0x7FFF
#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE                                    0x0

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A                                  0x831EBB
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W                                  15
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M                                  0x7FFF
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE                                0x0

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A                                  0x831EBC
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W                                  15
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M                                  0x7FFF
#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE                                0x0

#define SCU_RAM_AGC_RF_IACCU_HI__A                                          0x831EBD
#define SCU_RAM_AGC_RF_IACCU_HI__W                                          16
#define SCU_RAM_AGC_RF_IACCU_HI__M                                          0xFFFF
#define SCU_RAM_AGC_RF_IACCU_HI__PRE                                        0x0

#define SCU_RAM_AGC_RF_IACCU_LO__A                                          0x831EBE
#define SCU_RAM_AGC_RF_IACCU_LO__W                                          8
#define SCU_RAM_AGC_RF_IACCU_LO__M                                          0xFF
#define SCU_RAM_AGC_RF_IACCU_LO__PRE                                        0x0

#define SCU_RAM_AGC_RF_IACCU_HI_CO__A                                       0x831EBF
#define SCU_RAM_AGC_RF_IACCU_HI_CO__W                                       16
#define SCU_RAM_AGC_RF_IACCU_HI_CO__M                                       0xFFFF
#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE                                     0x0

#define SCU_RAM_SP__A                                                       0x831EC0
#define SCU_RAM_SP__W                                                       16
#define SCU_RAM_SP__M                                                       0xFFFF
#define SCU_RAM_SP__PRE                                                     0x0

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A                                  0x831EC1
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W                                  16
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M                                  0xFFFF
#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE                                0x0

#define SCU_RAM_AGC_KI_MIN_IFGAIN__A                                        0x831EC2
#define SCU_RAM_AGC_KI_MIN_IFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MIN_IFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE                                      0x0

#define SCU_RAM_AGC_KI_MAX_IFGAIN__A                                        0x831EC3
#define SCU_RAM_AGC_KI_MAX_IFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MAX_IFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE                                      0x0

#define SCU_RAM_FEC_MEAS_COUNT__A                                           0x831EC4
#define SCU_RAM_FEC_MEAS_COUNT__W                                           16
#define SCU_RAM_FEC_MEAS_COUNT__M                                           0xFFFF
#define SCU_RAM_FEC_MEAS_COUNT__PRE                                         0x0

#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A                                0x831EC5
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W                                16
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M                                0xFFFF
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE                              0x0

#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A                                0x831EC6
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W                                16
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M                                0xFFFF
#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE                              0x0
#define SCU_RAM_GPIO__A                                                     0x831EC7
#define SCU_RAM_GPIO__W                                                     1
#define SCU_RAM_GPIO__M                                                     0x1
#define SCU_RAM_GPIO__PRE                                                   0x0

#define   SCU_RAM_GPIO_HW_LOCK_IND__B                                       0
#define   SCU_RAM_GPIO_HW_LOCK_IND__W                                       1
#define   SCU_RAM_GPIO_HW_LOCK_IND__M                                       0x1
#define   SCU_RAM_GPIO_HW_LOCK_IND__PRE                                     0x0
#define     SCU_RAM_GPIO_HW_LOCK_IND_DISABLE                                0x0
#define     SCU_RAM_GPIO_HW_LOCK_IND_ENABLE                                 0x1

#define SCU_RAM_AGC_CLP_CTRL_MODE__A                                        0x831EC8
#define SCU_RAM_AGC_CLP_CTRL_MODE__W                                        8
#define SCU_RAM_AGC_CLP_CTRL_MODE__M                                        0xFF
#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE                                      0x0

#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B                           0
#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W                           1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M                           0x1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE                         0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false                      0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true                       0x1

#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B                          1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W                          1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M                          0x2
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE                        0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE                0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE               0x2

#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B                         2
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W                         1
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M                         0x4
#define   SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE                       0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE              0x0
#define     SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE               0x4

#define SCU_RAM_AGC_KI_MIN_RFGAIN__A                                        0x831EC9
#define SCU_RAM_AGC_KI_MIN_RFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MIN_RFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE                                      0x0

#define SCU_RAM_AGC_KI_MAX_RFGAIN__A                                        0x831ECA
#define SCU_RAM_AGC_KI_MAX_RFGAIN__W                                        16
#define SCU_RAM_AGC_KI_MAX_RFGAIN__M                                        0xFFFF
#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE                                      0x0

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A                                   0x831ECB
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W                                   16
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M                                   0xFFFF
#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE                                 0x0

#define SCU_RAM_INHIBIT_1__A                                                0x831ECC
#define SCU_RAM_INHIBIT_1__W                                                16
#define SCU_RAM_INHIBIT_1__M                                                0xFFFF
#define SCU_RAM_INHIBIT_1__PRE                                              0x0

#define SCU_RAM_HTOL_BUF_0__A                                               0x831ECD
#define SCU_RAM_HTOL_BUF_0__W                                               16
#define SCU_RAM_HTOL_BUF_0__M                                               0xFFFF
#define SCU_RAM_HTOL_BUF_0__PRE                                             0x0

#define SCU_RAM_HTOL_BUF_1__A                                               0x831ECE
#define SCU_RAM_HTOL_BUF_1__W                                               16
#define SCU_RAM_HTOL_BUF_1__M                                               0xFFFF
#define SCU_RAM_HTOL_BUF_1__PRE                                             0x0

#define SCU_RAM_INHIBIT_2__A                                                0x831ECF
#define SCU_RAM_INHIBIT_2__W                                                16
#define SCU_RAM_INHIBIT_2__M                                                0xFFFF
#define SCU_RAM_INHIBIT_2__PRE                                              0x0

#define SCU_RAM_TR_SHORT_BUF_0__A                                           0x831ED0
#define SCU_RAM_TR_SHORT_BUF_0__W                                           16
#define SCU_RAM_TR_SHORT_BUF_0__M                                           0xFFFF
#define SCU_RAM_TR_SHORT_BUF_0__PRE                                         0x0

#define SCU_RAM_TR_SHORT_BUF_1__A                                           0x831ED1
#define SCU_RAM_TR_SHORT_BUF_1__W                                           16
#define SCU_RAM_TR_SHORT_BUF_1__M                                           0xFFFF
#define SCU_RAM_TR_SHORT_BUF_1__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_0__A                                            0x831ED2
#define SCU_RAM_TR_LONG_BUF_0__W                                            16
#define SCU_RAM_TR_LONG_BUF_0__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_0__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_1__A                                            0x831ED3
#define SCU_RAM_TR_LONG_BUF_1__W                                            16
#define SCU_RAM_TR_LONG_BUF_1__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_1__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_2__A                                            0x831ED4
#define SCU_RAM_TR_LONG_BUF_2__W                                            16
#define SCU_RAM_TR_LONG_BUF_2__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_2__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_3__A                                            0x831ED5
#define SCU_RAM_TR_LONG_BUF_3__W                                            16
#define SCU_RAM_TR_LONG_BUF_3__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_3__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_4__A                                            0x831ED6
#define SCU_RAM_TR_LONG_BUF_4__W                                            16
#define SCU_RAM_TR_LONG_BUF_4__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_4__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_5__A                                            0x831ED7
#define SCU_RAM_TR_LONG_BUF_5__W                                            16
#define SCU_RAM_TR_LONG_BUF_5__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_5__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_6__A                                            0x831ED8
#define SCU_RAM_TR_LONG_BUF_6__W                                            16
#define SCU_RAM_TR_LONG_BUF_6__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_6__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_7__A                                            0x831ED9
#define SCU_RAM_TR_LONG_BUF_7__W                                            16
#define SCU_RAM_TR_LONG_BUF_7__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_7__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_8__A                                            0x831EDA
#define SCU_RAM_TR_LONG_BUF_8__W                                            16
#define SCU_RAM_TR_LONG_BUF_8__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_8__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_9__A                                            0x831EDB
#define SCU_RAM_TR_LONG_BUF_9__W                                            16
#define SCU_RAM_TR_LONG_BUF_9__M                                            0xFFFF
#define SCU_RAM_TR_LONG_BUF_9__PRE                                          0x0

#define SCU_RAM_TR_LONG_BUF_10__A                                           0x831EDC
#define SCU_RAM_TR_LONG_BUF_10__W                                           16
#define SCU_RAM_TR_LONG_BUF_10__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_10__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_11__A                                           0x831EDD
#define SCU_RAM_TR_LONG_BUF_11__W                                           16
#define SCU_RAM_TR_LONG_BUF_11__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_11__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_12__A                                           0x831EDE
#define SCU_RAM_TR_LONG_BUF_12__W                                           16
#define SCU_RAM_TR_LONG_BUF_12__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_12__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_13__A                                           0x831EDF
#define SCU_RAM_TR_LONG_BUF_13__W                                           16
#define SCU_RAM_TR_LONG_BUF_13__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_13__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_14__A                                           0x831EE0
#define SCU_RAM_TR_LONG_BUF_14__W                                           16
#define SCU_RAM_TR_LONG_BUF_14__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_14__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_15__A                                           0x831EE1
#define SCU_RAM_TR_LONG_BUF_15__W                                           16
#define SCU_RAM_TR_LONG_BUF_15__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_15__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_16__A                                           0x831EE2
#define SCU_RAM_TR_LONG_BUF_16__W                                           16
#define SCU_RAM_TR_LONG_BUF_16__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_16__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_17__A                                           0x831EE3
#define SCU_RAM_TR_LONG_BUF_17__W                                           16
#define SCU_RAM_TR_LONG_BUF_17__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_17__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_18__A                                           0x831EE4
#define SCU_RAM_TR_LONG_BUF_18__W                                           16
#define SCU_RAM_TR_LONG_BUF_18__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_18__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_19__A                                           0x831EE5
#define SCU_RAM_TR_LONG_BUF_19__W                                           16
#define SCU_RAM_TR_LONG_BUF_19__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_19__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_20__A                                           0x831EE6
#define SCU_RAM_TR_LONG_BUF_20__W                                           16
#define SCU_RAM_TR_LONG_BUF_20__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_20__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_21__A                                           0x831EE7
#define SCU_RAM_TR_LONG_BUF_21__W                                           16
#define SCU_RAM_TR_LONG_BUF_21__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_21__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_22__A                                           0x831EE8
#define SCU_RAM_TR_LONG_BUF_22__W                                           16
#define SCU_RAM_TR_LONG_BUF_22__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_22__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_23__A                                           0x831EE9
#define SCU_RAM_TR_LONG_BUF_23__W                                           16
#define SCU_RAM_TR_LONG_BUF_23__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_23__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_24__A                                           0x831EEA
#define SCU_RAM_TR_LONG_BUF_24__W                                           16
#define SCU_RAM_TR_LONG_BUF_24__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_24__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_25__A                                           0x831EEB
#define SCU_RAM_TR_LONG_BUF_25__W                                           16
#define SCU_RAM_TR_LONG_BUF_25__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_25__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_26__A                                           0x831EEC
#define SCU_RAM_TR_LONG_BUF_26__W                                           16
#define SCU_RAM_TR_LONG_BUF_26__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_26__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_27__A                                           0x831EED
#define SCU_RAM_TR_LONG_BUF_27__W                                           16
#define SCU_RAM_TR_LONG_BUF_27__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_27__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_28__A                                           0x831EEE
#define SCU_RAM_TR_LONG_BUF_28__W                                           16
#define SCU_RAM_TR_LONG_BUF_28__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_28__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_29__A                                           0x831EEF
#define SCU_RAM_TR_LONG_BUF_29__W                                           16
#define SCU_RAM_TR_LONG_BUF_29__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_29__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_30__A                                           0x831EF0
#define SCU_RAM_TR_LONG_BUF_30__W                                           16
#define SCU_RAM_TR_LONG_BUF_30__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_30__PRE                                         0x0

#define SCU_RAM_TR_LONG_BUF_31__A                                           0x831EF1
#define SCU_RAM_TR_LONG_BUF_31__W                                           16
#define SCU_RAM_TR_LONG_BUF_31__M                                           0xFFFF
#define SCU_RAM_TR_LONG_BUF_31__PRE                                         0x0
#define SCU_RAM_ATV_AMS_MAX__A                                              0x831EF2
#define SCU_RAM_ATV_AMS_MAX__W                                              11
#define SCU_RAM_ATV_AMS_MAX__M                                              0x7FF
#define SCU_RAM_ATV_AMS_MAX__PRE                                            0x0

#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__B                                    0
#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__W                                    11
#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__M                                    0x7FF
#define   SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE                                  0x0

#define SCU_RAM_ATV_AMS_MIN__A                                              0x831EF3
#define SCU_RAM_ATV_AMS_MIN__W                                              11
#define SCU_RAM_ATV_AMS_MIN__M                                              0x7FF
#define SCU_RAM_ATV_AMS_MIN__PRE                                            0x0

#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__B                                    0
#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__W                                    11
#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__M                                    0x7FF
#define   SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE                                  0x0

#define SCU_RAM_ATV_FIELD_CNT__A                                            0x831EF4
#define SCU_RAM_ATV_FIELD_CNT__W                                            9
#define SCU_RAM_ATV_FIELD_CNT__M                                            0x1FF
#define SCU_RAM_ATV_FIELD_CNT__PRE                                          0x0

#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B                                0
#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W                                9
#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M                                0x1FF
#define   SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE                              0x0

#define SCU_RAM_ATV_AAGC_FAST__A                                            0x831EF5
#define SCU_RAM_ATV_AAGC_FAST__W                                            1
#define SCU_RAM_ATV_AAGC_FAST__M                                            0x1
#define SCU_RAM_ATV_AAGC_FAST__PRE                                          0x0

#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B                                0
#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W                                1
#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M                                0x1
#define   SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE                              0x0
#define     SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF                             0x0
#define     SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON                              0x1

#define SCU_RAM_ATV_AAGC_LP2__A                                             0x831EF6
#define SCU_RAM_ATV_AAGC_LP2__W                                             16
#define SCU_RAM_ATV_AAGC_LP2__M                                             0xFFFF
#define SCU_RAM_ATV_AAGC_LP2__PRE                                           0x0

#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B                                  0
#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W                                  16
#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M                                  0xFFFF
#define   SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE                                0x0

#define SCU_RAM_ATV_BP_LVL__A                                               0x831EF7
#define SCU_RAM_ATV_BP_LVL__W                                               11
#define SCU_RAM_ATV_BP_LVL__M                                               0x7FF
#define SCU_RAM_ATV_BP_LVL__PRE                                             0x0

#define   SCU_RAM_ATV_BP_LVL_BP_LVL__B                                      0
#define   SCU_RAM_ATV_BP_LVL_BP_LVL__W                                      11
#define   SCU_RAM_ATV_BP_LVL_BP_LVL__M                                      0x7FF
#define   SCU_RAM_ATV_BP_LVL_BP_LVL__PRE                                    0x0

#define SCU_RAM_ATV_BP_RELY__A                                              0x831EF8
#define SCU_RAM_ATV_BP_RELY__W                                              8
#define SCU_RAM_ATV_BP_RELY__M                                              0xFF
#define SCU_RAM_ATV_BP_RELY__PRE                                            0x0

#define   SCU_RAM_ATV_BP_RELY_BP_RELY__B                                    0
#define   SCU_RAM_ATV_BP_RELY_BP_RELY__W                                    8
#define   SCU_RAM_ATV_BP_RELY_BP_RELY__M                                    0xFF
#define   SCU_RAM_ATV_BP_RELY_BP_RELY__PRE                                  0x0

#define SCU_RAM_ATV_BP_MTA__A                                               0x831EF9
#define SCU_RAM_ATV_BP_MTA__W                                               14
#define SCU_RAM_ATV_BP_MTA__M                                               0x3FFF
#define SCU_RAM_ATV_BP_MTA__PRE                                             0x0

#define   SCU_RAM_ATV_BP_MTA_BP_MTA__B                                      0
#define   SCU_RAM_ATV_BP_MTA_BP_MTA__W                                      14
#define   SCU_RAM_ATV_BP_MTA_BP_MTA__M                                      0x3FFF
#define   SCU_RAM_ATV_BP_MTA_BP_MTA__PRE                                    0x0

#define SCU_RAM_ATV_BP_REF__A                                               0x831EFA
#define SCU_RAM_ATV_BP_REF__W                                               11
#define SCU_RAM_ATV_BP_REF__M                                               0x7FF
#define SCU_RAM_ATV_BP_REF__PRE                                             0x0

#define   SCU_RAM_ATV_BP_REF_BP_REF__B                                      0
#define   SCU_RAM_ATV_BP_REF_BP_REF__W                                      11
#define   SCU_RAM_ATV_BP_REF_BP_REF__M                                      0x7FF
#define   SCU_RAM_ATV_BP_REF_BP_REF__PRE                                    0x0

#define SCU_RAM_ATV_BP_REF_MIN__A                                           0x831EFB
#define SCU_RAM_ATV_BP_REF_MIN__W                                           11
#define SCU_RAM_ATV_BP_REF_MIN__M                                           0x7FF
#define SCU_RAM_ATV_BP_REF_MIN__PRE                                         0x0

#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B                              0
#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W                              11
#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M                              0x7FF
#define   SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE                            0x0

#define SCU_RAM_ATV_BP_REF_MAX__A                                           0x831EFC
#define SCU_RAM_ATV_BP_REF_MAX__W                                           11
#define SCU_RAM_ATV_BP_REF_MAX__M                                           0x7FF
#define SCU_RAM_ATV_BP_REF_MAX__PRE                                         0x0

#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B                              0
#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W                              11
#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M                              0x7FF
#define   SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE                            0x0

#define SCU_RAM_ATV_BP_CNT__A                                               0x831EFD
#define SCU_RAM_ATV_BP_CNT__W                                               8
#define SCU_RAM_ATV_BP_CNT__M                                               0xFF
#define SCU_RAM_ATV_BP_CNT__PRE                                             0x0

#define   SCU_RAM_ATV_BP_CNT_BP_CNT__B                                      0
#define   SCU_RAM_ATV_BP_CNT_BP_CNT__W                                      8
#define   SCU_RAM_ATV_BP_CNT_BP_CNT__M                                      0xFF
#define   SCU_RAM_ATV_BP_CNT_BP_CNT__PRE                                    0x0

#define SCU_RAM_ATV_BP_XD_CNT__A                                            0x831EFE
#define SCU_RAM_ATV_BP_XD_CNT__W                                            12
#define SCU_RAM_ATV_BP_XD_CNT__M                                            0xFFF
#define SCU_RAM_ATV_BP_XD_CNT__PRE                                          0x0

#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B                                0
#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W                                12
#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M                                0xFFF
#define   SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE                              0x0

#define SCU_RAM_ATV_PAGC_KI_MIN__A                                          0x831EFF
#define SCU_RAM_ATV_PAGC_KI_MIN__W                                          12
#define SCU_RAM_ATV_PAGC_KI_MIN__M                                          0xFFF
#define SCU_RAM_ATV_PAGC_KI_MIN__PRE                                        0x0

#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B                            0
#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W                            12
#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M                            0xFFF
#define   SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE                          0x0

#define SCU_RAM_ATV_BPC_KI_MIN__A                                           0x831F00
#define SCU_RAM_ATV_BPC_KI_MIN__W                                           12
#define SCU_RAM_ATV_BPC_KI_MIN__M                                           0xFFF
#define SCU_RAM_ATV_BPC_KI_MIN__PRE                                         0x0

#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B                              0
#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W                              12
#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M                              0xFFF
#define   SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE                            0x0

#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A                                0x831F01
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W                                16
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M                                0xFFFF
#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE                              0x0

#define SCU_RAM_ORX_RF_RX_DATA_RATE__A                                      0x831F02
#define SCU_RAM_ORX_RF_RX_DATA_RATE__W                                      8
#define SCU_RAM_ORX_RF_RX_DATA_RATE__M                                      0xFF
#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE                                    0x0
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC                      0x0
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC                      0x1
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT                  0x40
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT                  0x41
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC                      0x80
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC                      0x81
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC                      0xC0
#define   SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC                      0xC1

#define SCU_RAM_ORX_SCU_STATE__A                                            0x831F03
#define SCU_RAM_ORX_SCU_STATE__W                                            8
#define SCU_RAM_ORX_SCU_STATE__M                                            0xFF
#define SCU_RAM_ORX_SCU_STATE__PRE                                          0x0
#define   SCU_RAM_ORX_SCU_STATE_RESET                                       0x0
#define   SCU_RAM_ORX_SCU_STATE_AGN_HUNT                                    0x1
#define   SCU_RAM_ORX_SCU_STATE_DGN_HUNT                                    0x2
#define   SCU_RAM_ORX_SCU_STATE_AGC_HUNT                                    0x3
#define   SCU_RAM_ORX_SCU_STATE_FRQ_HUNT                                    0x4
#define   SCU_RAM_ORX_SCU_STATE_PHA_HUNT                                    0x8
#define   SCU_RAM_ORX_SCU_STATE_TIM_HUNT                                    0x10
#define   SCU_RAM_ORX_SCU_STATE_EQU_HUNT                                    0x20
#define   SCU_RAM_ORX_SCU_STATE_EQT_HUNT                                    0x30
#define   SCU_RAM_ORX_SCU_STATE_SYNC                                        0x40

#define SCU_RAM_ORX_SCU_LOCK__A                                             0x831F04
#define SCU_RAM_ORX_SCU_LOCK__W                                             16
#define SCU_RAM_ORX_SCU_LOCK__M                                             0xFFFF
#define SCU_RAM_ORX_SCU_LOCK__PRE                                           0x0

#define SCU_RAM_ORX_TARGET_MODE__A                                          0x831F05
#define SCU_RAM_ORX_TARGET_MODE__W                                          2
#define SCU_RAM_ORX_TARGET_MODE__M                                          0x3
#define SCU_RAM_ORX_TARGET_MODE__PRE                                        0x0
#define   SCU_RAM_ORX_TARGET_MODE_1544KBPS                                  0x0
#define   SCU_RAM_ORX_TARGET_MODE_3088KBPS                                  0x1
#define   SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT                             0x2
#define   SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO                               0x3

#define SCU_RAM_ORX_MER_MIN_DB__A                                           0x831F06
#define SCU_RAM_ORX_MER_MIN_DB__W                                           8
#define SCU_RAM_ORX_MER_MIN_DB__M                                           0xFF
#define SCU_RAM_ORX_MER_MIN_DB__PRE                                         0x0

#define SCU_RAM_ORX_RF_GAIN__A                                              0x831F07
#define SCU_RAM_ORX_RF_GAIN__W                                              16
#define SCU_RAM_ORX_RF_GAIN__M                                              0xFFFF
#define SCU_RAM_ORX_RF_GAIN__PRE                                            0x0

#define SCU_RAM_ORX_RF_GAIN_MIN__A                                          0x831F08
#define SCU_RAM_ORX_RF_GAIN_MIN__W                                          16
#define SCU_RAM_ORX_RF_GAIN_MIN__M                                          0xFFFF
#define SCU_RAM_ORX_RF_GAIN_MIN__PRE                                        0x0

#define SCU_RAM_ORX_RF_GAIN_MAX__A                                          0x831F09
#define SCU_RAM_ORX_RF_GAIN_MAX__W                                          16
#define SCU_RAM_ORX_RF_GAIN_MAX__M                                          0xFFFF
#define SCU_RAM_ORX_RF_GAIN_MAX__PRE                                        0x0

#define SCU_RAM_ORX_IF_GAIN__A                                              0x831F0A
#define SCU_RAM_ORX_IF_GAIN__W                                              16
#define SCU_RAM_ORX_IF_GAIN__M                                              0xFFFF
#define SCU_RAM_ORX_IF_GAIN__PRE                                            0x0

#define SCU_RAM_ORX_IF_GAIN_MIN__A                                          0x831F0B
#define SCU_RAM_ORX_IF_GAIN_MIN__W                                          16
#define SCU_RAM_ORX_IF_GAIN_MIN__M                                          0xFFFF
#define SCU_RAM_ORX_IF_GAIN_MIN__PRE                                        0x0

#define SCU_RAM_ORX_IF_GAIN_MAX__A                                          0x831F0C
#define SCU_RAM_ORX_IF_GAIN_MAX__W                                          16
#define SCU_RAM_ORX_IF_GAIN_MAX__M                                          0xFFFF
#define SCU_RAM_ORX_IF_GAIN_MAX__PRE                                        0x0

#define SCU_RAM_ORX_AGN_HEADR__A                                            0x831F0D
#define SCU_RAM_ORX_AGN_HEADR__W                                            16
#define SCU_RAM_ORX_AGN_HEADR__M                                            0xFFFF
#define SCU_RAM_ORX_AGN_HEADR__PRE                                          0x0

#define SCU_RAM_ORX_AGN_HEADR_STP__A                                        0x831F0E
#define SCU_RAM_ORX_AGN_HEADR_STP__W                                        8
#define SCU_RAM_ORX_AGN_HEADR_STP__M                                        0xFF
#define SCU_RAM_ORX_AGN_HEADR_STP__PRE                                      0x0

#define SCU_RAM_ORX_AGN_KI__A                                               0x831F0F
#define SCU_RAM_ORX_AGN_KI__W                                               8
#define SCU_RAM_ORX_AGN_KI__M                                               0xFF
#define SCU_RAM_ORX_AGN_KI__PRE                                             0x0

#define SCU_RAM_ORX_AGN_LOCK_TH__A                                          0x831F10
#define SCU_RAM_ORX_AGN_LOCK_TH__W                                          16
#define SCU_RAM_ORX_AGN_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_AGN_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_AGN_LOCK_WD__A                                          0x831F11
#define SCU_RAM_ORX_AGN_LOCK_WD__W                                          16
#define SCU_RAM_ORX_AGN_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_AGN_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A                                       0x831F12
#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A                                       0x831F13
#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_AGN_LOCK_TOTH__A                                        0x831F14
#define SCU_RAM_ORX_AGN_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_AGN_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_AGN_LOCK_MASK__A                                        0x831F15
#define SCU_RAM_ORX_AGN_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_AGN_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_DGN__A                                                  0x831F16
#define SCU_RAM_ORX_DGN__W                                                  16
#define SCU_RAM_ORX_DGN__M                                                  0xFFFF
#define SCU_RAM_ORX_DGN__PRE                                                0x0

#define SCU_RAM_ORX_DGN_MIN__A                                              0x831F17
#define SCU_RAM_ORX_DGN_MIN__W                                              16
#define SCU_RAM_ORX_DGN_MIN__M                                              0xFFFF
#define SCU_RAM_ORX_DGN_MIN__PRE                                            0x0

#define SCU_RAM_ORX_DGN_MAX__A                                              0x831F18
#define SCU_RAM_ORX_DGN_MAX__W                                              16
#define SCU_RAM_ORX_DGN_MAX__M                                              0xFFFF
#define SCU_RAM_ORX_DGN_MAX__PRE                                            0x0

#define SCU_RAM_ORX_DGN_AMP__A                                              0x831F19
#define SCU_RAM_ORX_DGN_AMP__W                                              16
#define SCU_RAM_ORX_DGN_AMP__M                                              0xFFFF
#define SCU_RAM_ORX_DGN_AMP__PRE                                            0x0

#define SCU_RAM_ORX_DGN_AMPTARGET__A                                        0x831F1A
#define SCU_RAM_ORX_DGN_AMPTARGET__W                                        16
#define SCU_RAM_ORX_DGN_AMPTARGET__M                                        0xFFFF
#define SCU_RAM_ORX_DGN_AMPTARGET__PRE                                      0x0

#define SCU_RAM_ORX_DGN_KI__A                                               0x831F1B
#define SCU_RAM_ORX_DGN_KI__W                                               8
#define SCU_RAM_ORX_DGN_KI__M                                               0xFF
#define SCU_RAM_ORX_DGN_KI__PRE                                             0x0

#define SCU_RAM_ORX_DGN_LOCK_TH__A                                          0x831F1C
#define SCU_RAM_ORX_DGN_LOCK_TH__W                                          16
#define SCU_RAM_ORX_DGN_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_DGN_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_DGN_LOCK_WD__A                                          0x831F1D
#define SCU_RAM_ORX_DGN_LOCK_WD__W                                          16
#define SCU_RAM_ORX_DGN_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_DGN_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A                                       0x831F1E
#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A                                       0x831F1F
#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_DGN_LOCK_TOTH__A                                        0x831F20
#define SCU_RAM_ORX_DGN_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_DGN_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_DGN_LOCK_MASK__A                                        0x831F21
#define SCU_RAM_ORX_DGN_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_DGN_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_FREQ_GAIN_CORR__A                                       0x831F22
#define SCU_RAM_ORX_FREQ_GAIN_CORR__W                                       8
#define SCU_RAM_ORX_FREQ_GAIN_CORR__M                                       0xFF
#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE                                     0x0
#define   SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS                               0x60
#define   SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS                               0x80
#define   SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS                               0xC0

#define SCU_RAM_ORX_FRQ_OFFSET__A                                           0x831F23
#define SCU_RAM_ORX_FRQ_OFFSET__W                                           16
#define SCU_RAM_ORX_FRQ_OFFSET__M                                           0xFFFF
#define SCU_RAM_ORX_FRQ_OFFSET__PRE                                         0x0

#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A                                       0x831F24
#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W                                       15
#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M                                       0x7FFF
#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE                                     0x0

#define SCU_RAM_ORX_FRQ_KI__A                                               0x831F25
#define SCU_RAM_ORX_FRQ_KI__W                                               8
#define SCU_RAM_ORX_FRQ_KI__M                                               0xFF
#define SCU_RAM_ORX_FRQ_KI__PRE                                             0x0

#define SCU_RAM_ORX_FRQ_DIFF__A                                             0x831F26
#define SCU_RAM_ORX_FRQ_DIFF__W                                             16
#define SCU_RAM_ORX_FRQ_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_FRQ_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_FRQ_LOCK_TH__A                                          0x831F27
#define SCU_RAM_ORX_FRQ_LOCK_TH__W                                          16
#define SCU_RAM_ORX_FRQ_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_FRQ_LOCK_WD__A                                          0x831F28
#define SCU_RAM_ORX_FRQ_LOCK_WD__W                                          16
#define SCU_RAM_ORX_FRQ_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A                                       0x831F29
#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A                                       0x831F2A
#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A                                        0x831F2B
#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_FRQ_LOCK_MASK__A                                        0x831F2C
#define SCU_RAM_ORX_FRQ_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_FRQ_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_PHA_DIFF__A                                             0x831F2D
#define SCU_RAM_ORX_PHA_DIFF__W                                             16
#define SCU_RAM_ORX_PHA_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_PHA_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_PHA_LOCK_TH__A                                          0x831F2E
#define SCU_RAM_ORX_PHA_LOCK_TH__W                                          16
#define SCU_RAM_ORX_PHA_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_PHA_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_PHA_LOCK_WD__A                                          0x831F2F
#define SCU_RAM_ORX_PHA_LOCK_WD__W                                          16
#define SCU_RAM_ORX_PHA_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_PHA_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A                                       0x831F30
#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A                                       0x831F31
#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_PHA_LOCK_TOTH__A                                        0x831F32
#define SCU_RAM_ORX_PHA_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_PHA_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_PHA_LOCK_MASK__A                                        0x831F33
#define SCU_RAM_ORX_PHA_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_PHA_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_TIM_OFFSET__A                                           0x831F34
#define SCU_RAM_ORX_TIM_OFFSET__W                                           16
#define SCU_RAM_ORX_TIM_OFFSET__M                                           0xFFFF
#define SCU_RAM_ORX_TIM_OFFSET__PRE                                         0x0

#define SCU_RAM_ORX_TIM_DIFF__A                                             0x831F35
#define SCU_RAM_ORX_TIM_DIFF__W                                             16
#define SCU_RAM_ORX_TIM_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_TIM_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_TIM_LOCK_TH__A                                          0x831F36
#define SCU_RAM_ORX_TIM_LOCK_TH__W                                          16
#define SCU_RAM_ORX_TIM_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_TIM_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_TIM_LOCK_WD__A                                          0x831F37
#define SCU_RAM_ORX_TIM_LOCK_WD__W                                          16
#define SCU_RAM_ORX_TIM_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_TIM_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A                                       0x831F38
#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A                                       0x831F39
#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_TIM_LOCK_TOTH__A                                        0x831F3A
#define SCU_RAM_ORX_TIM_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_TIM_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_TIM_LOCK_MASK__A                                        0x831F3B
#define SCU_RAM_ORX_TIM_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_TIM_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_EQU_DIFF__A                                             0x831F3C
#define SCU_RAM_ORX_EQU_DIFF__W                                             16
#define SCU_RAM_ORX_EQU_DIFF__M                                             0xFFFF
#define SCU_RAM_ORX_EQU_DIFF__PRE                                           0x0

#define SCU_RAM_ORX_EQU_LOCK_TH__A                                          0x831F3D
#define SCU_RAM_ORX_EQU_LOCK_TH__W                                          16
#define SCU_RAM_ORX_EQU_LOCK_TH__M                                          0xFFFF
#define SCU_RAM_ORX_EQU_LOCK_TH__PRE                                        0x0

#define SCU_RAM_ORX_EQU_LOCK_WD__A                                          0x831F3E
#define SCU_RAM_ORX_EQU_LOCK_WD__W                                          16
#define SCU_RAM_ORX_EQU_LOCK_WD__M                                          0xFFFF
#define SCU_RAM_ORX_EQU_LOCK_WD__PRE                                        0x0

#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A                                       0x831F3F
#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W                                       16
#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A                                       0x831F40
#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W                                       16
#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M                                       0xFFFF
#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE                                     0x0

#define SCU_RAM_ORX_EQU_LOCK_TOTH__A                                        0x831F41
#define SCU_RAM_ORX_EQU_LOCK_TOTH__W                                        16
#define SCU_RAM_ORX_EQU_LOCK_TOTH__M                                        0xFFFF
#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE                                      0x0

#define SCU_RAM_ORX_EQU_LOCK_MASK__A                                        0x831F42
#define SCU_RAM_ORX_EQU_LOCK_MASK__W                                        8
#define SCU_RAM_ORX_EQU_LOCK_MASK__M                                        0xFF
#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE                                      0x0

#define SCU_RAM_ORX_FLT_FRQ__A                                              0x831F43
#define SCU_RAM_ORX_FLT_FRQ__W                                              16
#define SCU_RAM_ORX_FLT_FRQ__M                                              0xFFFF
#define SCU_RAM_ORX_FLT_FRQ__PRE                                            0x0
#define SCU_RAM_ORX_RST_CPH__A                                              0x831F44
#define SCU_RAM_ORX_RST_CPH__W                                              4
#define SCU_RAM_ORX_RST_CPH__M                                              0xF
#define SCU_RAM_ORX_RST_CPH__PRE                                            0x0

#define   SCU_RAM_ORX_RST_CPH_RST_CPH__B                                    0
#define   SCU_RAM_ORX_RST_CPH_RST_CPH__W                                    4
#define   SCU_RAM_ORX_RST_CPH_RST_CPH__M                                    0xF
#define   SCU_RAM_ORX_RST_CPH_RST_CPH__PRE                                  0x0

#define SCU_RAM_ORX_RST_CTI__A                                              0x831F45
#define SCU_RAM_ORX_RST_CTI__W                                              4
#define SCU_RAM_ORX_RST_CTI__M                                              0xF
#define SCU_RAM_ORX_RST_CTI__PRE                                            0x0

#define   SCU_RAM_ORX_RST_CTI_RST_CTI__B                                    0
#define   SCU_RAM_ORX_RST_CTI_RST_CTI__W                                    4
#define   SCU_RAM_ORX_RST_CTI_RST_CTI__M                                    0xF
#define   SCU_RAM_ORX_RST_CTI_RST_CTI__PRE                                  0x0

#define SCU_RAM_ORX_RST_KRN__A                                              0x831F46
#define SCU_RAM_ORX_RST_KRN__W                                              4
#define SCU_RAM_ORX_RST_KRN__M                                              0xF
#define SCU_RAM_ORX_RST_KRN__PRE                                            0x0

#define   SCU_RAM_ORX_RST_KRN_RST_KRN__B                                    0
#define   SCU_RAM_ORX_RST_KRN_RST_KRN__W                                    4
#define   SCU_RAM_ORX_RST_KRN_RST_KRN__M                                    0xF
#define   SCU_RAM_ORX_RST_KRN_RST_KRN__PRE                                  0x0

#define SCU_RAM_ORX_RST_KRP__A                                              0x831F47
#define SCU_RAM_ORX_RST_KRP__W                                              4
#define SCU_RAM_ORX_RST_KRP__M                                              0xF
#define SCU_RAM_ORX_RST_KRP__PRE                                            0x0

#define   SCU_RAM_ORX_RST_KRP_RST_KRP__B                                    0
#define   SCU_RAM_ORX_RST_KRP_RST_KRP__W                                    4
#define   SCU_RAM_ORX_RST_KRP_RST_KRP__M                                    0xF
#define   SCU_RAM_ORX_RST_KRP_RST_KRP__PRE                                  0x0

#define SCU_RAM_ATV_STANDARD__A                                             0x831F48
#define SCU_RAM_ATV_STANDARD__W                                             12
#define SCU_RAM_ATV_STANDARD__M                                             0xFFF
#define SCU_RAM_ATV_STANDARD__PRE                                           0x0

#define   SCU_RAM_ATV_STANDARD_STANDARD__B                                  0
#define   SCU_RAM_ATV_STANDARD_STANDARD__W                                  12
#define   SCU_RAM_ATV_STANDARD_STANDARD__M                                  0xFFF
#define   SCU_RAM_ATV_STANDARD_STANDARD__PRE                                0x0
#define     SCU_RAM_ATV_STANDARD_STANDARD_MN                                0x2
#define     SCU_RAM_ATV_STANDARD_STANDARD_B                                 0x103
#define     SCU_RAM_ATV_STANDARD_STANDARD_G                                 0x3
#define     SCU_RAM_ATV_STANDARD_STANDARD_DK                                0x4
#define     SCU_RAM_ATV_STANDARD_STANDARD_L                                 0x9
#define     SCU_RAM_ATV_STANDARD_STANDARD_LP                                0x109
#define     SCU_RAM_ATV_STANDARD_STANDARD_I                                 0xA
#define     SCU_RAM_ATV_STANDARD_STANDARD_FM                                0x40

#define SCU_RAM_ATV_DETECT__A                                               0x831F49
#define SCU_RAM_ATV_DETECT__W                                               1
#define SCU_RAM_ATV_DETECT__M                                               0x1
#define SCU_RAM_ATV_DETECT__PRE                                             0x0

#define   SCU_RAM_ATV_DETECT_DETECT__B                                      0
#define   SCU_RAM_ATV_DETECT_DETECT__W                                      1
#define   SCU_RAM_ATV_DETECT_DETECT__M                                      0x1
#define   SCU_RAM_ATV_DETECT_DETECT__PRE                                    0x0
#define     SCU_RAM_ATV_DETECT_DETECT_false                                 0x0
#define     SCU_RAM_ATV_DETECT_DETECT_true                                  0x1

#define SCU_RAM_ATV_DETECT_TH__A                                            0x831F4A
#define SCU_RAM_ATV_DETECT_TH__W                                            8
#define SCU_RAM_ATV_DETECT_TH__M                                            0xFF
#define SCU_RAM_ATV_DETECT_TH__PRE                                          0x0

#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__B                                0
#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__W                                8
#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__M                                0xFF
#define   SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE                              0x0

#define SCU_RAM_ATV_LOCK__A                                                 0x831F4B
#define SCU_RAM_ATV_LOCK__W                                                 2
#define SCU_RAM_ATV_LOCK__M                                                 0x3
#define SCU_RAM_ATV_LOCK__PRE                                               0x0

#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B                                   0
#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W                                   1
#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M                                   0x1
#define   SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE                                 0x0
#define     SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK                            0x0
#define     SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK                               0x1

#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__B                                     1
#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__W                                     1
#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__M                                     0x2
#define   SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE                                   0x0
#define     SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC                              0x0
#define     SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC                                 0x2

#define SCU_RAM_ATV_CR_LOCK__A                                              0x831F4C
#define SCU_RAM_ATV_CR_LOCK__W                                              11
#define SCU_RAM_ATV_CR_LOCK__M                                              0x7FF
#define SCU_RAM_ATV_CR_LOCK__PRE                                            0x0

#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__B                                    0
#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__W                                    11
#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__M                                    0x7FF
#define   SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE                                  0x0

#define SCU_RAM_ATV_AGC_MODE__A                                             0x831F4D
#define SCU_RAM_ATV_AGC_MODE__W                                             8
#define SCU_RAM_ATV_AGC_MODE__M                                             0xFF
#define SCU_RAM_ATV_AGC_MODE__PRE                                           0x0

#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B                                  2
#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W                                  1
#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M                                  0x4
#define   SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE                                0x0
#define     SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST                          0x0
#define     SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW                          0x4

#define   SCU_RAM_ATV_AGC_MODE_BP_EN__B                                     3
#define   SCU_RAM_ATV_AGC_MODE_BP_EN__W                                     1
#define   SCU_RAM_ATV_AGC_MODE_BP_EN__M                                     0x8
#define   SCU_RAM_ATV_AGC_MODE_BP_EN__PRE                                   0x0
#define     SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE                          0x0
#define     SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE                           0x8

#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__B                                   4
#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__W                                   2
#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__M                                   0x30
#define   SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE                                 0x0
#define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF                        0x0
#define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM                         0x10
#define     SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM                         0x20

#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B                              6
#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W                              1
#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M                              0x40
#define   SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE                            0x0
#define     SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE                  0x0
#define     SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE                   0x40

#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B                                 7
#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W                                 1
#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M                                 0x80
#define   SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE                               0x0
#define     SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE                       0x0
#define     SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE                      0x80

#define SCU_RAM_ATV_RSV_01__A                                               0x831F4E
#define SCU_RAM_ATV_RSV_01__W                                               16
#define SCU_RAM_ATV_RSV_01__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_01__PRE                                             0x0

#define SCU_RAM_ATV_RSV_02__A                                               0x831F4F
#define SCU_RAM_ATV_RSV_02__W                                               16
#define SCU_RAM_ATV_RSV_02__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_02__PRE                                             0x0

#define SCU_RAM_ATV_RSV_03__A                                               0x831F50
#define SCU_RAM_ATV_RSV_03__W                                               16
#define SCU_RAM_ATV_RSV_03__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_03__PRE                                             0x0

#define SCU_RAM_ATV_RSV_04__A                                               0x831F51
#define SCU_RAM_ATV_RSV_04__W                                               16
#define SCU_RAM_ATV_RSV_04__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_04__PRE                                             0x0
#define SCU_RAM_ATV_FAGC_TH_RED__A                                          0x831F52
#define SCU_RAM_ATV_FAGC_TH_RED__W                                          8
#define SCU_RAM_ATV_FAGC_TH_RED__M                                          0xFF
#define SCU_RAM_ATV_FAGC_TH_RED__PRE                                        0x0

#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B                            0
#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W                            8
#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M                            0xFF
#define   SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE                          0x0

#define SCU_RAM_ATV_AMS_MAX_REF__A                                          0x831F53
#define SCU_RAM_ATV_AMS_MAX_REF__W                                          11
#define SCU_RAM_ATV_AMS_MAX_REF__M                                          0x7FF
#define SCU_RAM_ATV_AMS_MAX_REF__PRE                                        0x0

#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B                            0
#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W                            11
#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M                            0x7FF
#define   SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE                          0x0
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN                       0x2BC
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK                          0x2D0
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I                           0x314
#define     SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP                         0x28A

#define SCU_RAM_ATV_ACT_AMX__A                                              0x831F54
#define SCU_RAM_ATV_ACT_AMX__W                                              11
#define SCU_RAM_ATV_ACT_AMX__M                                              0x7FF
#define SCU_RAM_ATV_ACT_AMX__PRE                                            0x0

#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__B                                    0
#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__W                                    11
#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__M                                    0x7FF
#define   SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE                                  0x0

#define SCU_RAM_ATV_ACT_AMI__A                                              0x831F55
#define SCU_RAM_ATV_ACT_AMI__W                                              11
#define SCU_RAM_ATV_ACT_AMI__M                                              0x7FF
#define SCU_RAM_ATV_ACT_AMI__PRE                                            0x0

#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__B                                    0
#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__W                                    11
#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__M                                    0x7FF
#define   SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE                                  0x0

#define SCU_RAM_ATV_RSV_05__A                                               0x831F56
#define SCU_RAM_ATV_RSV_05__W                                               16
#define SCU_RAM_ATV_RSV_05__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_05__PRE                                             0x0

#define SCU_RAM_ATV_RSV_06__A                                               0x831F57
#define SCU_RAM_ATV_RSV_06__W                                               16
#define SCU_RAM_ATV_RSV_06__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_06__PRE                                             0x0

#define SCU_RAM_ATV_RSV_07__A                                               0x831F58
#define SCU_RAM_ATV_RSV_07__W                                               16
#define SCU_RAM_ATV_RSV_07__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_07__PRE                                             0x0

#define SCU_RAM_ATV_RSV_08__A                                               0x831F59
#define SCU_RAM_ATV_RSV_08__W                                               16
#define SCU_RAM_ATV_RSV_08__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_08__PRE                                             0x0

#define SCU_RAM_ATV_RSV_09__A                                               0x831F5A
#define SCU_RAM_ATV_RSV_09__W                                               16
#define SCU_RAM_ATV_RSV_09__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_09__PRE                                             0x0

#define SCU_RAM_ATV_RSV_10__A                                               0x831F5B
#define SCU_RAM_ATV_RSV_10__W                                               16
#define SCU_RAM_ATV_RSV_10__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_10__PRE                                             0x0

#define SCU_RAM_ATV_RSV_11__A                                               0x831F5C
#define SCU_RAM_ATV_RSV_11__W                                               16
#define SCU_RAM_ATV_RSV_11__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_11__PRE                                             0x0

#define SCU_RAM_ATV_RSV_12__A                                               0x831F5D
#define SCU_RAM_ATV_RSV_12__W                                               16
#define SCU_RAM_ATV_RSV_12__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_12__PRE                                             0x0
#define SCU_RAM_ATV_VID_GAIN_HI__A                                          0x831F5E
#define SCU_RAM_ATV_VID_GAIN_HI__W                                          16
#define SCU_RAM_ATV_VID_GAIN_HI__M                                          0xFFFF
#define SCU_RAM_ATV_VID_GAIN_HI__PRE                                        0x0

#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B                            0
#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W                            16
#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M                            0xFFFF
#define   SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE                          0x0

#define SCU_RAM_ATV_VID_GAIN_LO__A                                          0x831F5F
#define SCU_RAM_ATV_VID_GAIN_LO__W                                          8
#define SCU_RAM_ATV_VID_GAIN_LO__M                                          0xFF
#define SCU_RAM_ATV_VID_GAIN_LO__PRE                                        0x0

#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B                            0
#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W                            8
#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M                            0xFF
#define   SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE                          0x0

#define SCU_RAM_ATV_RSV_13__A                                               0x831F60
#define SCU_RAM_ATV_RSV_13__W                                               16
#define SCU_RAM_ATV_RSV_13__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_13__PRE                                             0x0

#define SCU_RAM_ATV_RSV_14__A                                               0x831F61
#define SCU_RAM_ATV_RSV_14__W                                               16
#define SCU_RAM_ATV_RSV_14__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_14__PRE                                             0x0

#define SCU_RAM_ATV_RSV_15__A                                               0x831F62
#define SCU_RAM_ATV_RSV_15__W                                               16
#define SCU_RAM_ATV_RSV_15__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_15__PRE                                             0x0

#define SCU_RAM_ATV_RSV_16__A                                               0x831F63
#define SCU_RAM_ATV_RSV_16__W                                               16
#define SCU_RAM_ATV_RSV_16__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_16__PRE                                             0x0
#define SCU_RAM_ATV_AAGC_CNT__A                                             0x831F64
#define SCU_RAM_ATV_AAGC_CNT__W                                             8
#define SCU_RAM_ATV_AAGC_CNT__M                                             0xFF
#define SCU_RAM_ATV_AAGC_CNT__PRE                                           0x0

#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B                                  0
#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W                                  8
#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M                                  0xFF
#define   SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE                                0x0

#define SCU_RAM_ATV_SIF_GAIN__A                                             0x831F65
#define SCU_RAM_ATV_SIF_GAIN__W                                             11
#define SCU_RAM_ATV_SIF_GAIN__M                                             0x7FF
#define SCU_RAM_ATV_SIF_GAIN__PRE                                           0x0

#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B                                  0
#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W                                  11
#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M                                  0x7FF
#define   SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE                                0x0

#define SCU_RAM_ATV_RSV_17__A                                               0x831F66
#define SCU_RAM_ATV_RSV_17__W                                               16
#define SCU_RAM_ATV_RSV_17__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_17__PRE                                             0x0

#define SCU_RAM_ATV_RSV_18__A                                               0x831F67
#define SCU_RAM_ATV_RSV_18__W                                               16
#define SCU_RAM_ATV_RSV_18__M                                               0xFFFF
#define SCU_RAM_ATV_RSV_18__PRE                                             0x0

#define SCU_RAM_ATV_RATE_OFS__A                                             0x831F68
#define SCU_RAM_ATV_RATE_OFS__W                                             12
#define SCU_RAM_ATV_RATE_OFS__M                                             0xFFF
#define SCU_RAM_ATV_RATE_OFS__PRE                                           0x0

#define SCU_RAM_ATV_LO_INCR__A                                              0x831F69
#define SCU_RAM_ATV_LO_INCR__W                                              12
#define SCU_RAM_ATV_LO_INCR__M                                              0xFFF
#define SCU_RAM_ATV_LO_INCR__PRE                                            0x0

#define SCU_RAM_ATV_IIR_CRIT__A                                             0x831F6A
#define SCU_RAM_ATV_IIR_CRIT__W                                             12
#define SCU_RAM_ATV_IIR_CRIT__M                                             0xFFF
#define SCU_RAM_ATV_IIR_CRIT__PRE                                           0x0

#define SCU_RAM_ATV_DEF_RATE_OFS__A                                         0x831F6B
#define SCU_RAM_ATV_DEF_RATE_OFS__W                                         12
#define SCU_RAM_ATV_DEF_RATE_OFS__M                                         0xFFF
#define SCU_RAM_ATV_DEF_RATE_OFS__PRE                                       0x0

#define SCU_RAM_ATV_DEF_LO_INCR__A                                          0x831F6C
#define SCU_RAM_ATV_DEF_LO_INCR__W                                          12
#define SCU_RAM_ATV_DEF_LO_INCR__M                                          0xFFF
#define SCU_RAM_ATV_DEF_LO_INCR__PRE                                        0x0

#define SCU_RAM_ATV_ENABLE_IIR_WA__A                                        0x831F6D
#define SCU_RAM_ATV_ENABLE_IIR_WA__W                                        1
#define SCU_RAM_ATV_ENABLE_IIR_WA__M                                        0x1
#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE                                      0x0

#define SCU_RAM_ATV_MOD_CONTROL__A                                          0x831F6E
#define SCU_RAM_ATV_MOD_CONTROL__W                                          12
#define SCU_RAM_ATV_MOD_CONTROL__M                                          0xFFF
#define SCU_RAM_ATV_MOD_CONTROL__PRE                                        0x0

#define SCU_RAM_ATV_PAGC_KI_MAX__A                                          0x831F6F
#define SCU_RAM_ATV_PAGC_KI_MAX__W                                          12
#define SCU_RAM_ATV_PAGC_KI_MAX__M                                          0xFFF
#define SCU_RAM_ATV_PAGC_KI_MAX__PRE                                        0x0

#define SCU_RAM_ATV_BPC_KI_MAX__A                                           0x831F70
#define SCU_RAM_ATV_BPC_KI_MAX__W                                           12
#define SCU_RAM_ATV_BPC_KI_MAX__M                                           0xFFF
#define SCU_RAM_ATV_BPC_KI_MAX__PRE                                         0x0

#define SCU_RAM_ATV_NAGC_KI_MAX__A                                          0x831F71
#define SCU_RAM_ATV_NAGC_KI_MAX__W                                          12
#define SCU_RAM_ATV_NAGC_KI_MAX__M                                          0xFFF
#define SCU_RAM_ATV_NAGC_KI_MAX__PRE                                        0x0
#define SCU_RAM_ATV_NAGC_KI_MIN__A                                          0x831F72
#define SCU_RAM_ATV_NAGC_KI_MIN__W                                          12
#define SCU_RAM_ATV_NAGC_KI_MIN__M                                          0xFFF
#define SCU_RAM_ATV_NAGC_KI_MIN__PRE                                        0x0

#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B                            0
#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W                            12
#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M                            0xFFF
#define   SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE                          0x0

#define SCU_RAM_ATV_KI_CHANGE_TH__A                                         0x831F73
#define SCU_RAM_ATV_KI_CHANGE_TH__W                                         8
#define SCU_RAM_ATV_KI_CHANGE_TH__M                                         0xFF
#define SCU_RAM_ATV_KI_CHANGE_TH__PRE                                       0x0

#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B                          0
#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W                          8
#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M                          0xFF
#define   SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE                        0x0
#define     SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD                   0x14
#define     SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD                   0x28

#define SCU_RAM_QAM_PARAM_ANNEX__A                                          0x831F74
#define SCU_RAM_QAM_PARAM_ANNEX__W                                          2
#define SCU_RAM_QAM_PARAM_ANNEX__M                                          0x3
#define SCU_RAM_QAM_PARAM_ANNEX__PRE                                        0x0

#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__B                                    0
#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__W                                    2
#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__M                                    0x3
#define   SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A                             0x0
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B                             0x1
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C                             0x2
#define     SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D                             0x3

#define SCU_RAM_QAM_PARAM_CONSTELLATION__A                                  0x831F75
#define SCU_RAM_QAM_PARAM_CONSTELLATION__W                                  3
#define SCU_RAM_QAM_PARAM_CONSTELLATION__M                                  0x7
#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W                            3
#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M                            0x7
#define   SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE                          0x0
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN                     0x0
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16                      0x3
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32                      0x4
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64                      0x5
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128                     0x6
#define     SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256                     0x7

#define SCU_RAM_QAM_PARAM_INTERLEAVE__A                                     0x831F76
#define SCU_RAM_QAM_PARAM_INTERLEAVE__W                                     8
#define SCU_RAM_QAM_PARAM_INTERLEAVE__M                                     0xFF
#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE                                   0x0

#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B                               0
#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W                               8
#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M                               0xFF
#define   SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE                             0x0
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1                        0x0
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2                     0x1
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2                        0x2
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2                         0x3
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3                        0x4
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4                         0x5
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4                        0x6
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8                         0x7
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5                        0x8
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16                         0x9
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6                        0xA
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7                        0xC
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8                        0xE
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17                        0x10
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4                          0x11
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN                        0xFE
#define     SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO                           0xFF

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A                                  0x831F77
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W                                  16
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE                          0x0

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A                                  0x831F78
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W                                  16
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE                          0x0

#define SCU_RAM_QAM_EQ_CENTERTAP__A                                         0x831F79
#define SCU_RAM_QAM_EQ_CENTERTAP__W                                         16
#define SCU_RAM_QAM_EQ_CENTERTAP__M                                         0xFFFF
#define SCU_RAM_QAM_EQ_CENTERTAP__PRE                                       0x0

#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__B                                   0
#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__W                                   8
#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__M                                   0xFF
#define   SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE                                 0x0

#define SCU_RAM_QAM_WR_RSV_0__A                                             0x831F7A
#define SCU_RAM_QAM_WR_RSV_0__W                                             16
#define SCU_RAM_QAM_WR_RSV_0__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_0__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_0_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_0_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_0_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_0_BIT__PRE                                     0x0

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A                                  0x831F7B
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W                                  16
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE                          0x0

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A                                  0x831F7C
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W                                  16
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M                                  0xFFFF
#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE                                0x0

#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B                            0
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W                            16
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE                          0x0

#define SCU_RAM_QAM_WR_RSV_5__A                                             0x831F7D
#define SCU_RAM_QAM_WR_RSV_5__W                                             16
#define SCU_RAM_QAM_WR_RSV_5__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_5__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_5_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_5_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_5_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_5_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_6__A                                             0x831F7E
#define SCU_RAM_QAM_WR_RSV_6__W                                             16
#define SCU_RAM_QAM_WR_RSV_6__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_6__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_6_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_6_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_6_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_6_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_7__A                                             0x831F7F
#define SCU_RAM_QAM_WR_RSV_7__W                                             16
#define SCU_RAM_QAM_WR_RSV_7__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_7__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_7_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_7_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_7_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_7_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_8__A                                             0x831F80
#define SCU_RAM_QAM_WR_RSV_8__W                                             16
#define SCU_RAM_QAM_WR_RSV_8__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_8__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_8_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_8_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_8_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_8_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_9__A                                             0x831F81
#define SCU_RAM_QAM_WR_RSV_9__W                                             16
#define SCU_RAM_QAM_WR_RSV_9__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_9__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_9_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_9_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_9_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_9_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_10__A                                            0x831F82
#define SCU_RAM_QAM_WR_RSV_10__W                                            16
#define SCU_RAM_QAM_WR_RSV_10__M                                            0xFFFF
#define SCU_RAM_QAM_WR_RSV_10__PRE                                          0x0

#define   SCU_RAM_QAM_WR_RSV_10_BIT__B                                      0
#define   SCU_RAM_QAM_WR_RSV_10_BIT__W                                      16
#define   SCU_RAM_QAM_WR_RSV_10_BIT__M                                      0xFFFF
#define   SCU_RAM_QAM_WR_RSV_10_BIT__PRE                                    0x0

#define SCU_RAM_QAM_FSM_FMHUM_TO__A                                         0x831F83
#define SCU_RAM_QAM_FSM_FMHUM_TO__W                                         16
#define SCU_RAM_QAM_FSM_FMHUM_TO__M                                         0xFFFF
#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE                                       0x0

#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B                                   0
#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W                                   16
#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE                                 0x0
#define     SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO                        0x0

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A                                   0x831F84
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W                                   16
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M                                   0xFFFF
#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE                                 0x0

#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B                             0
#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W                             16
#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M                             0xFFFF
#define   SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE                           0x0

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A                                  0x831F85
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W                                  16
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M                                  0xFFFF
#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE                                0x0

#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B                            0
#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W                            16
#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M                            0xFFFF
#define   SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE                          0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A                                    0x831F86
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A                                    0x831F87
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A                                    0x831F88
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A                                    0x831F89
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A                                    0x831F8A
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W                                    16
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M                                    0xFFFF
#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B                              0
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W                              16
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M                              0xFFFF
#define   SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE                            0x0

#define SCU_RAM_QAM_FSM_STATE_TGT__A                                        0x831F8B
#define SCU_RAM_QAM_FSM_STATE_TGT__W                                        4
#define SCU_RAM_QAM_FSM_STATE_TGT__M                                        0xF
#define SCU_RAM_QAM_FSM_STATE_TGT__PRE                                      0x0

#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__B                                  0
#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__W                                  4
#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__M                                  0xF
#define   SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE                                0x0
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP                       0x0
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE                      0x1
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ                      0x2
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT                   0x3
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE                     0x4
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE                  0x5
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING                          0x6
#define     SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST                    0x7

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A                                    0x831F8C
#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W                                    9
#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M                                    0x1FF
#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE                                  0x0

#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B                          0
#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M                          0x1
#define   SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE                        0x0

#define SCU_RAM_QAM_FSM_ATH__A                                              0x831F8D
#define SCU_RAM_QAM_FSM_ATH__W                                              16
#define SCU_RAM_QAM_FSM_ATH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_ATH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_ATH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_ATH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_ATH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_ATH_BIT__PRE                                      0x0

#define SCU_RAM_QAM_FSM_RTH__A                                              0x831F8E
#define SCU_RAM_QAM_FSM_RTH__W                                              16
#define SCU_RAM_QAM_FSM_RTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_RTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_RTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_RTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_RTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_RTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_16                                  0x8C
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_32                                  0x50
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_64                                  0x4E
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_128                                 0x32
#define     SCU_RAM_QAM_FSM_RTH_BIT_QAM_256                                 0x2D

#define SCU_RAM_QAM_FSM_FTH__A                                              0x831F8F
#define SCU_RAM_QAM_FSM_FTH__W                                              16
#define SCU_RAM_QAM_FSM_FTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_FTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_FTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_FTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_FTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_FTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_16                                  0x32
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_32                                  0x1E
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_64                                  0x1E
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_128                                 0x14
#define     SCU_RAM_QAM_FSM_FTH_BIT_QAM_256                                 0x14

#define SCU_RAM_QAM_FSM_PTH__A                                              0x831F90
#define SCU_RAM_QAM_FSM_PTH__W                                              16
#define SCU_RAM_QAM_FSM_PTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_PTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_PTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_PTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_PTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_PTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_16                                  0xC8
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_32                                  0x96
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_64                                  0x8C
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_128                                 0x64
#define     SCU_RAM_QAM_FSM_PTH_BIT_QAM_256                                 0x64

#define SCU_RAM_QAM_FSM_MTH__A                                              0x831F91
#define SCU_RAM_QAM_FSM_MTH__W                                              16
#define SCU_RAM_QAM_FSM_MTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_MTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_MTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_MTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_MTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_MTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_16                                  0x5A
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_32                                  0x50
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_64                                  0x46
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_128                                 0x3C
#define     SCU_RAM_QAM_FSM_MTH_BIT_QAM_256                                 0x50

#define SCU_RAM_QAM_FSM_CTH__A                                              0x831F92
#define SCU_RAM_QAM_FSM_CTH__W                                              16
#define SCU_RAM_QAM_FSM_CTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_CTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_CTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_CTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_CTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_CTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_16                                  0xA0
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_32                                  0x8C
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_64                                  0x8C
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_128                                 0x8C
#define     SCU_RAM_QAM_FSM_CTH_BIT_QAM_256                                 0x8C

#define SCU_RAM_QAM_FSM_QTH__A                                              0x831F93
#define SCU_RAM_QAM_FSM_QTH__W                                              16
#define SCU_RAM_QAM_FSM_QTH__M                                              0xFFFF
#define SCU_RAM_QAM_FSM_QTH__PRE                                            0x0

#define   SCU_RAM_QAM_FSM_QTH_BIT__B                                        0
#define   SCU_RAM_QAM_FSM_QTH_BIT__W                                        16
#define   SCU_RAM_QAM_FSM_QTH_BIT__M                                        0xFFFF
#define   SCU_RAM_QAM_FSM_QTH_BIT__PRE                                      0x0
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_16                                  0xE6
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_32                                  0xAA
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_64                                  0xC3
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_128                                 0x8C
#define     SCU_RAM_QAM_FSM_QTH_BIT_QAM_256                                 0x96

#define SCU_RAM_QAM_FSM_RATE_LIM__A                                         0x831F94
#define SCU_RAM_QAM_FSM_RATE_LIM__W                                         16
#define SCU_RAM_QAM_FSM_RATE_LIM__M                                         0xFFFF
#define SCU_RAM_QAM_FSM_RATE_LIM__PRE                                       0x0

#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__B                                   0
#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__W                                   16
#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE                                 0x0
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16                             0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32                             0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64                             0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128                            0x46
#define     SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256                            0x46

#define SCU_RAM_QAM_FSM_FREQ_LIM__A                                         0x831F95
#define SCU_RAM_QAM_FSM_FREQ_LIM__W                                         16
#define SCU_RAM_QAM_FSM_FREQ_LIM__M                                         0xFFFF
#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE                                       0x0

#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B                                   0
#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W                                   16
#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE                                 0x0
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16                             0x1E
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32                             0x14
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64                             0x28
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128                            0x8
#define     SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256                            0x28

#define SCU_RAM_QAM_FSM_COUNT_LIM__A                                        0x831F96
#define SCU_RAM_QAM_FSM_COUNT_LIM__W                                        16
#define SCU_RAM_QAM_FSM_COUNT_LIM__M                                        0xFFFF
#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE                                      0x0

#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B                                  0
#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W                                  16
#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M                                  0xFFFF
#define   SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE                                0x0
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16                            0x4
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32                            0x6
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64                            0x6
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128                           0x7
#define     SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256                           0x6

#define SCU_RAM_QAM_LC_CA_COARSE__A                                         0x831F97
#define SCU_RAM_QAM_LC_CA_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CA_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CA_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CA_MEDIUM__A                                         0x831F98
#define SCU_RAM_QAM_LC_CA_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CA_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CA_FINE__A                                           0x831F99
#define SCU_RAM_QAM_LC_CA_FINE__W                                           16
#define SCU_RAM_QAM_LC_CA_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CA_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CA_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CA_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CA_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CA_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CP_COARSE__A                                         0x831F9A
#define SCU_RAM_QAM_LC_CP_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CP_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CP_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CP_MEDIUM__A                                         0x831F9B
#define SCU_RAM_QAM_LC_CP_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CP_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CP_FINE__A                                           0x831F9C
#define SCU_RAM_QAM_LC_CP_FINE__W                                           16
#define SCU_RAM_QAM_LC_CP_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CP_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CP_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CP_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CP_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CP_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CI_COARSE__A                                         0x831F9D
#define SCU_RAM_QAM_LC_CI_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CI_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CI_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CI_MEDIUM__A                                         0x831F9E
#define SCU_RAM_QAM_LC_CI_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CI_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CI_FINE__A                                           0x831F9F
#define SCU_RAM_QAM_LC_CI_FINE__W                                           16
#define SCU_RAM_QAM_LC_CI_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CI_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CI_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CI_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CI_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CI_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_EP_COARSE__A                                         0x831FA0
#define SCU_RAM_QAM_LC_EP_COARSE__W                                         16
#define SCU_RAM_QAM_LC_EP_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EP_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EP_MEDIUM__A                                         0x831FA1
#define SCU_RAM_QAM_LC_EP_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_EP_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EP_FINE__A                                           0x831FA2
#define SCU_RAM_QAM_LC_EP_FINE__W                                           16
#define SCU_RAM_QAM_LC_EP_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_EP_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_EP_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_EP_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_EP_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_EP_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_EI_COARSE__A                                         0x831FA3
#define SCU_RAM_QAM_LC_EI_COARSE__W                                         16
#define SCU_RAM_QAM_LC_EI_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EI_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EI_MEDIUM__A                                         0x831FA4
#define SCU_RAM_QAM_LC_EI_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_EI_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_EI_FINE__A                                           0x831FA5
#define SCU_RAM_QAM_LC_EI_FINE__W                                           16
#define SCU_RAM_QAM_LC_EI_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_EI_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_EI_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_EI_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_EI_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_EI_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CF_COARSE__A                                         0x831FA6
#define SCU_RAM_QAM_LC_CF_COARSE__W                                         16
#define SCU_RAM_QAM_LC_CF_COARSE__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CF_COARSE__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CF_MEDIUM__A                                         0x831FA7
#define SCU_RAM_QAM_LC_CF_MEDIUM__W                                         16
#define SCU_RAM_QAM_LC_CF_MEDIUM__M                                         0xFFFF
#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE                                       0x0

#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B                                   0
#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W                                   8
#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M                                   0xFF
#define   SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE                                 0x0

#define SCU_RAM_QAM_LC_CF_FINE__A                                           0x831FA8
#define SCU_RAM_QAM_LC_CF_FINE__W                                           16
#define SCU_RAM_QAM_LC_CF_FINE__M                                           0xFFFF
#define SCU_RAM_QAM_LC_CF_FINE__PRE                                         0x0

#define   SCU_RAM_QAM_LC_CF_FINE_BIT__B                                     0
#define   SCU_RAM_QAM_LC_CF_FINE_BIT__W                                     8
#define   SCU_RAM_QAM_LC_CF_FINE_BIT__M                                     0xFF
#define   SCU_RAM_QAM_LC_CF_FINE_BIT__PRE                                   0x0

#define SCU_RAM_QAM_LC_CF1_COARSE__A                                        0x831FA9
#define SCU_RAM_QAM_LC_CF1_COARSE__W                                        16
#define SCU_RAM_QAM_LC_CF1_COARSE__M                                        0xFFFF
#define SCU_RAM_QAM_LC_CF1_COARSE__PRE                                      0x0

#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__B                                  0
#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__W                                  8
#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__M                                  0xFF
#define   SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE                                0x0

#define SCU_RAM_QAM_LC_CF1_MEDIUM__A                                        0x831FAA
#define SCU_RAM_QAM_LC_CF1_MEDIUM__W                                        16
#define SCU_RAM_QAM_LC_CF1_MEDIUM__M                                        0xFFFF
#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE                                      0x0

#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B                                  0
#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W                                  8
#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M                                  0xFF
#define   SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE                                0x0

#define SCU_RAM_QAM_LC_CF1_FINE__A                                          0x831FAB
#define SCU_RAM_QAM_LC_CF1_FINE__W                                          16
#define SCU_RAM_QAM_LC_CF1_FINE__M                                          0xFFFF
#define SCU_RAM_QAM_LC_CF1_FINE__PRE                                        0x0

#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__B                                    0
#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__W                                    8
#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__M                                    0xFF
#define   SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE                                  0x0

#define SCU_RAM_QAM_SL_SIG_POWER__A                                         0x831FAC
#define SCU_RAM_QAM_SL_SIG_POWER__W                                         16
#define SCU_RAM_QAM_SL_SIG_POWER__M                                         0xFFFF
#define SCU_RAM_QAM_SL_SIG_POWER__PRE                                       0x0

#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__B                                   0
#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__W                                   16
#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE                                 0x0

#define SCU_RAM_QAM_EQ_CMA_RAD0__A                                          0x831FAD
#define SCU_RAM_QAM_EQ_CMA_RAD0__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD0__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64                              0x3418
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128                             0x1814
#define     SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256                             0x2CEE

#define SCU_RAM_QAM_EQ_CMA_RAD1__A                                          0x831FAE
#define SCU_RAM_QAM_EQ_CMA_RAD1__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD1__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64                              0x314A
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128                             0x19C6
#define     SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256                             0x2F34

#define SCU_RAM_QAM_EQ_CMA_RAD2__A                                          0x831FAF
#define SCU_RAM_QAM_EQ_CMA_RAD2__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD2__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64                              0x2ED4
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128                             0x18FA
#define     SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256                             0x30FF

#define SCU_RAM_QAM_EQ_CMA_RAD3__A                                          0x831FB0
#define SCU_RAM_QAM_EQ_CMA_RAD3__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD3__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64                              0x35F1
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128                             0x1909
#define     SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256                             0x3283

#define SCU_RAM_QAM_EQ_CMA_RAD4__A                                          0x831FB1
#define SCU_RAM_QAM_EQ_CMA_RAD4__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD4__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64                              0x35F1
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128                             0x1A00
#define     SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256                             0x353D

#define SCU_RAM_QAM_EQ_CMA_RAD5__A                                          0x831FB2
#define SCU_RAM_QAM_EQ_CMA_RAD5__W                                          14
#define SCU_RAM_QAM_EQ_CMA_RAD5__M                                          0x3FFF
#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE                                        0x0

#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B                                    0
#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W                                    14
#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M                                    0x3FFF
#define   SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE                                  0x0
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16                              0x34CD
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32                              0x1A33
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64                              0x3CF9
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128                             0x1C46
#define     SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256                             0x3C19

#define SCU_RAM_QAM_CTL_ENA__A                                              0x831FB3
#define SCU_RAM_QAM_CTL_ENA__W                                              16
#define SCU_RAM_QAM_CTL_ENA__M                                              0xFFFF
#define SCU_RAM_QAM_CTL_ENA__PRE                                            0x0

#define   SCU_RAM_QAM_CTL_ENA_AMP__B                                        0
#define   SCU_RAM_QAM_CTL_ENA_AMP__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_AMP__M                                        0x1
#define   SCU_RAM_QAM_CTL_ENA_AMP__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_ACQ__B                                        1
#define   SCU_RAM_QAM_CTL_ENA_ACQ__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_ACQ__M                                        0x2
#define   SCU_RAM_QAM_CTL_ENA_ACQ__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_EQU__B                                        2
#define   SCU_RAM_QAM_CTL_ENA_EQU__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_EQU__M                                        0x4
#define   SCU_RAM_QAM_CTL_ENA_EQU__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_SLC__B                                        3
#define   SCU_RAM_QAM_CTL_ENA_SLC__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_SLC__M                                        0x8
#define   SCU_RAM_QAM_CTL_ENA_SLC__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_LC__B                                         4
#define   SCU_RAM_QAM_CTL_ENA_LC__W                                         1
#define   SCU_RAM_QAM_CTL_ENA_LC__M                                         0x10
#define   SCU_RAM_QAM_CTL_ENA_LC__PRE                                       0x0

#define   SCU_RAM_QAM_CTL_ENA_AGC__B                                        5
#define   SCU_RAM_QAM_CTL_ENA_AGC__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_AGC__M                                        0x20
#define   SCU_RAM_QAM_CTL_ENA_AGC__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_FEC__B                                        6
#define   SCU_RAM_QAM_CTL_ENA_FEC__W                                        1
#define   SCU_RAM_QAM_CTL_ENA_FEC__M                                        0x40
#define   SCU_RAM_QAM_CTL_ENA_FEC__PRE                                      0x0

#define   SCU_RAM_QAM_CTL_ENA_AXIS__B                                       7
#define   SCU_RAM_QAM_CTL_ENA_AXIS__W                                       1
#define   SCU_RAM_QAM_CTL_ENA_AXIS__M                                       0x80
#define   SCU_RAM_QAM_CTL_ENA_AXIS__PRE                                     0x0

#define   SCU_RAM_QAM_CTL_ENA_FMHUM__B                                      8
#define   SCU_RAM_QAM_CTL_ENA_FMHUM__W                                      1
#define   SCU_RAM_QAM_CTL_ENA_FMHUM__M                                      0x100
#define   SCU_RAM_QAM_CTL_ENA_FMHUM__PRE                                    0x0

#define   SCU_RAM_QAM_CTL_ENA_EQTIME__B                                     9
#define   SCU_RAM_QAM_CTL_ENA_EQTIME__W                                     1
#define   SCU_RAM_QAM_CTL_ENA_EQTIME__M                                     0x200
#define   SCU_RAM_QAM_CTL_ENA_EQTIME__PRE                                   0x0

#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__B                                     10
#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__W                                     1
#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__M                                     0x400
#define   SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE                                   0x0

#define SCU_RAM_QAM_WR_RSV_1__A                                             0x831FB4
#define SCU_RAM_QAM_WR_RSV_1__W                                             16
#define SCU_RAM_QAM_WR_RSV_1__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_1__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_1_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_1_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_1_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_1_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_2__A                                             0x831FB5
#define SCU_RAM_QAM_WR_RSV_2__W                                             16
#define SCU_RAM_QAM_WR_RSV_2__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_2__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_2_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_2_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_2_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_2_BIT__PRE                                     0x0

#define SCU_RAM_QAM_WR_RSV_3__A                                             0x831FB6
#define SCU_RAM_QAM_WR_RSV_3__W                                             16
#define SCU_RAM_QAM_WR_RSV_3__M                                             0xFFFF
#define SCU_RAM_QAM_WR_RSV_3__PRE                                           0x0

#define   SCU_RAM_QAM_WR_RSV_3_BIT__B                                       0
#define   SCU_RAM_QAM_WR_RSV_3_BIT__W                                       16
#define   SCU_RAM_QAM_WR_RSV_3_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_WR_RSV_3_BIT__PRE                                     0x0

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A                                 0x831FB7
#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W                                 3
#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M                                 0x7
#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE                               0x0

#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B                           0
#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W                           3
#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M                           0x7
#define   SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE                         0x0
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN                    0x0
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16                     0x3
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32                     0x4
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64                     0x5
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128                    0x6
#define     SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256                    0x7

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A                                    0x831FB8
#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W                                    8
#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M                                    0xFF
#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE                                  0x0

#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B                              0
#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W                              8
#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M                              0xFF
#define   SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE                            0x0
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1                       0x0
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2                    0x1
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2                       0x2
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2                        0x3
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3                       0x4
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4                        0x5
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4                       0x6
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8                        0x7
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5                       0x8
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16                        0x9
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6                       0xA
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7                       0xC
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8                       0xE
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17                       0x10
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4                         0x11
#define     SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN                       0xFE

#define SCU_RAM_QAM_RD_RSV_4__A                                             0x831FB9
#define SCU_RAM_QAM_RD_RSV_4__W                                             16
#define SCU_RAM_QAM_RD_RSV_4__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_4__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_4_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_4_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_4_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_4_BIT__PRE                                     0x0

#define SCU_RAM_QAM_LOCKED__A                                               0x831FBA
#define SCU_RAM_QAM_LOCKED__W                                               16
#define SCU_RAM_QAM_LOCKED__M                                               0xFFFF
#define SCU_RAM_QAM_LOCKED__PRE                                             0x0

#define   SCU_RAM_QAM_LOCKED_INTLEVEL__B                                    0
#define   SCU_RAM_QAM_LOCKED_INTLEVEL__W                                    8
#define   SCU_RAM_QAM_LOCKED_INTLEVEL__M                                    0xFF
#define   SCU_RAM_QAM_LOCKED_INTLEVEL__PRE                                  0x0
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED                          0x0
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK                              0x1
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK                             0x2
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK                             0x3
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK                          0x4
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK                          0x5
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK                            0x6
#define     SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK                         0x7

#define   SCU_RAM_QAM_LOCKED_LOCKED__B                                      8
#define   SCU_RAM_QAM_LOCKED_LOCKED__W                                      8
#define   SCU_RAM_QAM_LOCKED_LOCKED__M                                      0xFF00
#define   SCU_RAM_QAM_LOCKED_LOCKED__PRE                                    0x0
#define     SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED                            0x0
#define     SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED                          0x4000
#define     SCU_RAM_QAM_LOCKED_LOCKED_LOCKED                                0x8000
#define     SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK                            0xC000

#define SCU_RAM_QAM_EVENTS_OCC_HI__A                                        0x831FBB
#define SCU_RAM_QAM_EVENTS_OCC_HI__W                                        16
#define SCU_RAM_QAM_EVENTS_OCC_HI__M                                        0xFFFF
#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE                                      0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B                               0
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W                               1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M                               0x1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE                             0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B                          1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M                          0x2
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B                                 2
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M                                 0x4
#define   SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE                               0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B                           3
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M                           0x8
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B                          4
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M                          0x10
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B                              5
#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M                              0x20
#define   SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B                            6
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W                            1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M                            0x40
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE                          0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B                           7
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M                           0x80
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B                              8
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M                              0x100
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B                            9
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W                            1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M                            0x200
#define   SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE                          0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B                              10
#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M                              0x400
#define   SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B                              11
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W                              1
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M                              0x800
#define   SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE                            0x0

#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B                                  12
#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W                                  4
#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M                                  0xF000
#define   SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE                                0x0

#define SCU_RAM_QAM_EVENTS_OCC_LO__A                                        0x831FBC
#define SCU_RAM_QAM_EVENTS_OCC_LO__W                                        16
#define SCU_RAM_QAM_EVENTS_OCC_LO__M                                        0xFFFF
#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE                                      0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B                                0
#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W                                1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M                                0x1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE                              0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M                                 0x2
#define   SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE                               0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B                                2
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W                                1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M                                0x4
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE                              0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B                                3
#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W                                1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M                                0x8
#define   SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE                              0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B                               4
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W                               1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M                               0x10
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE                             0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__B                                  5
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__W                                  1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__M                                  0x20
#define   SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE                                0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B                                 6
#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W                                 1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M                                 0x40
#define   SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE                               0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B                             7
#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W                             1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M                             0x80
#define   SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE                           0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__B                                  8
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__W                                  1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__M                                  0x100
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE                                0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B                           9
#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M                           0x200
#define   SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B                           10
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M                           0x400
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B                          11
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M                          0x800
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B                          12
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M                          0x1000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE                        0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B                             13
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W                             1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M                             0x2000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE                           0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B                           14
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W                           1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M                           0x4000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE                         0x0

#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B                          15
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W                          1
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M                          0x8000
#define   SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE                        0x0

#define SCU_RAM_QAM_EVENTS_SCHED_HI__A                                      0x831FBD
#define SCU_RAM_QAM_EVENTS_SCHED_HI__W                                      16
#define SCU_RAM_QAM_EVENTS_SCHED_HI__M                                      0xFFFF
#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE                                    0x0

#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B                                0
#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W                                16
#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M                                0xFFFF
#define   SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE                              0x0

#define SCU_RAM_QAM_EVENTS_SCHED_LO__A                                      0x831FBE
#define SCU_RAM_QAM_EVENTS_SCHED_LO__W                                      16
#define SCU_RAM_QAM_EVENTS_SCHED_LO__M                                      0xFFFF
#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE                                    0x0

#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B                                0
#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W                                16
#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M                                0xFFFF
#define   SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE                              0x0

#define SCU_RAM_QAM_TASKLETS_SCHED__A                                       0x831FBF
#define SCU_RAM_QAM_TASKLETS_SCHED__W                                       16
#define SCU_RAM_QAM_TASKLETS_SCHED__M                                       0xFFFF
#define SCU_RAM_QAM_TASKLETS_SCHED__PRE                                     0x0

#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__B                                 0
#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__W                                 16
#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__M                                 0xFFFF
#define   SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE                               0x0

#define SCU_RAM_QAM_TASKLETS_RUN__A                                         0x831FC0
#define SCU_RAM_QAM_TASKLETS_RUN__W                                         16
#define SCU_RAM_QAM_TASKLETS_RUN__M                                         0xFFFF
#define SCU_RAM_QAM_TASKLETS_RUN__PRE                                       0x0

#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__B                                   0
#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__W                                   16
#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__M                                   0xFFFF
#define   SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE                                 0x0

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A                                 0x831FC1
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W                                 16
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M                                 0xFFFF
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE                               0x0

#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B                           0
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W                           16
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M                           0xFFFF
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE                         0x0

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A                                 0x831FC2
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W                                 16
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M                                 0xFFFF
#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE                               0x0

#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B                           0
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W                           16
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M                           0xFFFF
#define   SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE                         0x0

#define SCU_RAM_QAM_RD_RSV_5__A                                             0x831FC3
#define SCU_RAM_QAM_RD_RSV_5__W                                             16
#define SCU_RAM_QAM_RD_RSV_5__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_5__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_5_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_5_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_5_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_5_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_6__A                                             0x831FC4
#define SCU_RAM_QAM_RD_RSV_6__W                                             16
#define SCU_RAM_QAM_RD_RSV_6__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_6__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_6_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_6_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_6_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_6_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_7__A                                             0x831FC5
#define SCU_RAM_QAM_RD_RSV_7__W                                             16
#define SCU_RAM_QAM_RD_RSV_7__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_7__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_7_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_7_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_7_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_7_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_8__A                                             0x831FC6
#define SCU_RAM_QAM_RD_RSV_8__W                                             16
#define SCU_RAM_QAM_RD_RSV_8__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_8__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_8_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_8_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_8_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_8_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_9__A                                             0x831FC7
#define SCU_RAM_QAM_RD_RSV_9__W                                             16
#define SCU_RAM_QAM_RD_RSV_9__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_9__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_9_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_9_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_9_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_9_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_10__A                                            0x831FC8
#define SCU_RAM_QAM_RD_RSV_10__W                                            16
#define SCU_RAM_QAM_RD_RSV_10__M                                            0xFFFF
#define SCU_RAM_QAM_RD_RSV_10__PRE                                          0x0

#define   SCU_RAM_QAM_RD_RSV_10_BIT__B                                      0
#define   SCU_RAM_QAM_RD_RSV_10_BIT__W                                      16
#define   SCU_RAM_QAM_RD_RSV_10_BIT__M                                      0xFFFF
#define   SCU_RAM_QAM_RD_RSV_10_BIT__PRE                                    0x0

#define SCU_RAM_QAM_AGC_TPOW_OFFS__A                                        0x831FC9
#define SCU_RAM_QAM_AGC_TPOW_OFFS__W                                        16
#define SCU_RAM_QAM_AGC_TPOW_OFFS__M                                        0xFFFF
#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE                                      0x0

#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B                                  0
#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W                                  16
#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M                                  0xFFFF
#define   SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE                                0x0

#define SCU_RAM_QAM_FSM_STATE__A                                            0x831FCA
#define SCU_RAM_QAM_FSM_STATE__W                                            4
#define SCU_RAM_QAM_FSM_STATE__M                                            0xF
#define SCU_RAM_QAM_FSM_STATE__PRE                                          0x0

#define   SCU_RAM_QAM_FSM_STATE_BIT__B                                      0
#define   SCU_RAM_QAM_FSM_STATE_BIT__W                                      4
#define   SCU_RAM_QAM_FSM_STATE_BIT__M                                      0xF
#define   SCU_RAM_QAM_FSM_STATE_BIT__PRE                                    0x0
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP                           0x0
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE                          0x1
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ                          0x2
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT                       0x3
#define     SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE                         0x4
#define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE                      0x5
#define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING                              0x6
#define     SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST                        0x7

#define SCU_RAM_QAM_FSM_STATE_NEW__A                                        0x831FCB
#define SCU_RAM_QAM_FSM_STATE_NEW__W                                        4
#define SCU_RAM_QAM_FSM_STATE_NEW__M                                        0xF
#define SCU_RAM_QAM_FSM_STATE_NEW__PRE                                      0x0

#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__B                                  0
#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__W                                  4
#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__M                                  0xF
#define   SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE                                0x0
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP                       0x0
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE                      0x1
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ                      0x2
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT                   0x3
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE                     0x4
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE                  0x5
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING                          0x6
#define     SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST                    0x7

#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A                                       0x831FCC
#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W                                       9
#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M                                       0x1FF
#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE                                     0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B                             0
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W                             1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M                             0x1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE                           0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M                         0x2
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE                       0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B                          2
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M                          0x4
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE                        0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B                            3
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W                            1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M                            0x8
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE                          0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B                         4
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M                         0x10
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE                       0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B                          5
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M                          0x20
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE                        0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B                         6
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W                         1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M                         0x40
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE                       0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B                           7
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W                           1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M                           0x80
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE                         0x0

#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B                          8
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W                          1
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M                          0x100
#define   SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE                        0x0

#define SCU_RAM_QAM_FSM_RATE_VARIATION__A                                   0x831FCD
#define SCU_RAM_QAM_FSM_RATE_VARIATION__W                                   16
#define SCU_RAM_QAM_FSM_RATE_VARIATION__M                                   0xFFFF
#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE                                 0x0

#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B                             0
#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W                             16
#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M                             0xFFFF
#define   SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE                           0x0

#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A                                   0x831FCE
#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W                                   16
#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M                                   0xFFFF
#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE                                 0x0

#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B                             0
#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W                             16
#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M                             0xFFFF
#define   SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE                           0x0

#define SCU_RAM_QAM_ERR_STATE__A                                            0x831FCF
#define SCU_RAM_QAM_ERR_STATE__W                                            4
#define SCU_RAM_QAM_ERR_STATE__M                                            0xF
#define SCU_RAM_QAM_ERR_STATE__PRE                                          0x0

#define   SCU_RAM_QAM_ERR_STATE_BIT__B                                      0
#define   SCU_RAM_QAM_ERR_STATE_BIT__W                                      4
#define   SCU_RAM_QAM_ERR_STATE_BIT__M                                      0xF
#define   SCU_RAM_QAM_ERR_STATE_BIT__PRE                                    0x0
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP                           0x0
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE                          0x1
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ                          0x2
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT                       0x3
#define     SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE                         0x4
#define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE                      0x5
#define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING                              0x6
#define     SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST                        0x7

#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A                                       0x831FD0
#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W                                       9
#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M                                       0x1FF
#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE                                     0x0

#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B                             0
#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W                             1
#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M                             0x1
#define   SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE                           0x0

#define SCU_RAM_QAM_EQ_LOCK__A                                              0x831FD1
#define SCU_RAM_QAM_EQ_LOCK__W                                              1
#define SCU_RAM_QAM_EQ_LOCK__M                                              0x1
#define SCU_RAM_QAM_EQ_LOCK__PRE                                            0x0

#define   SCU_RAM_QAM_EQ_LOCK_BIT__B                                        0
#define   SCU_RAM_QAM_EQ_LOCK_BIT__W                                        1
#define   SCU_RAM_QAM_EQ_LOCK_BIT__M                                        0x1
#define   SCU_RAM_QAM_EQ_LOCK_BIT__PRE                                      0x0

#define SCU_RAM_QAM_EQ_STATE__A                                             0x831FD2
#define SCU_RAM_QAM_EQ_STATE__W                                             16
#define SCU_RAM_QAM_EQ_STATE__M                                             0xFFFF
#define SCU_RAM_QAM_EQ_STATE__PRE                                           0x0

#define   SCU_RAM_QAM_EQ_STATE_BIT__B                                       0
#define   SCU_RAM_QAM_EQ_STATE_BIT__W                                       16
#define   SCU_RAM_QAM_EQ_STATE_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_EQ_STATE_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_0__A                                             0x831FD3
#define SCU_RAM_QAM_RD_RSV_0__W                                             16
#define SCU_RAM_QAM_RD_RSV_0__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_0__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_0_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_0_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_0_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_0_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_1__A                                             0x831FD4
#define SCU_RAM_QAM_RD_RSV_1__W                                             16
#define SCU_RAM_QAM_RD_RSV_1__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_1__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_1_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_1_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_1_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_1_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_2__A                                             0x831FD5
#define SCU_RAM_QAM_RD_RSV_2__W                                             16
#define SCU_RAM_QAM_RD_RSV_2__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_2__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_2_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_2_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_2_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_2_BIT__PRE                                     0x0

#define SCU_RAM_QAM_RD_RSV_3__A                                             0x831FD6
#define SCU_RAM_QAM_RD_RSV_3__W                                             16
#define SCU_RAM_QAM_RD_RSV_3__M                                             0xFFFF
#define SCU_RAM_QAM_RD_RSV_3__PRE                                           0x0

#define   SCU_RAM_QAM_RD_RSV_3_BIT__B                                       0
#define   SCU_RAM_QAM_RD_RSV_3_BIT__W                                       16
#define   SCU_RAM_QAM_RD_RSV_3_BIT__M                                       0xFFFF
#define   SCU_RAM_QAM_RD_RSV_3_BIT__PRE                                     0x0

#define SCU_RAM_VSB_CTL_MODE__A                                             0x831FD7
#define SCU_RAM_VSB_CTL_MODE__W                                             2
#define SCU_RAM_VSB_CTL_MODE__M                                             0x3
#define SCU_RAM_VSB_CTL_MODE__PRE                                           0x0

#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B                          0
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W                          1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M                          0x1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE                        0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF                       0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON                        0x1

#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B                          1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W                          1
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M                          0x2
#define   SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE                        0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF                       0x0
#define     SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON                        0x2

#define SCU_RAM_VSB_NOTCH_THRESHOLD__A                                      0x831FD8
#define SCU_RAM_VSB_NOTCH_THRESHOLD__W                                      16
#define SCU_RAM_VSB_NOTCH_THRESHOLD__M                                      0xFFFF
#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE                                    0x0

#define SCU_RAM_VSB_RSV_0__A                                                0x831FD9
#define SCU_RAM_VSB_RSV_0__W                                                16
#define SCU_RAM_VSB_RSV_0__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_0__PRE                                              0x0

#define SCU_RAM_VSB_RSV_1__A                                                0x831FDA
#define SCU_RAM_VSB_RSV_1__W                                                16
#define SCU_RAM_VSB_RSV_1__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_1__PRE                                              0x0

#define SCU_RAM_VSB_RSV_2__A                                                0x831FDB
#define SCU_RAM_VSB_RSV_2__W                                                16
#define SCU_RAM_VSB_RSV_2__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_2__PRE                                              0x0

#define SCU_RAM_VSB_RSV_3__A                                                0x831FDC
#define SCU_RAM_VSB_RSV_3__W                                                16
#define SCU_RAM_VSB_RSV_3__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_3__PRE                                              0x0

#define SCU_RAM_VSB_RSV_4__A                                                0x831FDD
#define SCU_RAM_VSB_RSV_4__W                                                16
#define SCU_RAM_VSB_RSV_4__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_4__PRE                                              0x0

#define SCU_RAM_VSB_RSV_5__A                                                0x831FDE
#define SCU_RAM_VSB_RSV_5__W                                                16
#define SCU_RAM_VSB_RSV_5__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_5__PRE                                              0x0

#define SCU_RAM_VSB_RSV_6__A                                                0x831FDF
#define SCU_RAM_VSB_RSV_6__W                                                16
#define SCU_RAM_VSB_RSV_6__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_6__PRE                                              0x0

#define SCU_RAM_VSB_RSV_7__A                                                0x831FE0
#define SCU_RAM_VSB_RSV_7__W                                                16
#define SCU_RAM_VSB_RSV_7__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_7__PRE                                              0x0

#define SCU_RAM_VSB_RSV_8__A                                                0x831FE1
#define SCU_RAM_VSB_RSV_8__W                                                16
#define SCU_RAM_VSB_RSV_8__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_8__PRE                                              0x0

#define SCU_RAM_VSB_RSV_9__A                                                0x831FE2
#define SCU_RAM_VSB_RSV_9__W                                                16
#define SCU_RAM_VSB_RSV_9__M                                                0xFFFF
#define SCU_RAM_VSB_RSV_9__PRE                                              0x0

#define SCU_RAM_VSB_RSV_10__A                                               0x831FE3
#define SCU_RAM_VSB_RSV_10__W                                               16
#define SCU_RAM_VSB_RSV_10__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_10__PRE                                             0x0

#define SCU_RAM_VSB_RSV_11__A                                               0x831FE4
#define SCU_RAM_VSB_RSV_11__W                                               16
#define SCU_RAM_VSB_RSV_11__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_11__PRE                                             0x0

#define SCU_RAM_VSB_RSV_12__A                                               0x831FE5
#define SCU_RAM_VSB_RSV_12__W                                               16
#define SCU_RAM_VSB_RSV_12__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_12__PRE                                             0x0

#define SCU_RAM_VSB_RSV_13__A                                               0x831FE6
#define SCU_RAM_VSB_RSV_13__W                                               16
#define SCU_RAM_VSB_RSV_13__M                                               0xFFFF
#define SCU_RAM_VSB_RSV_13__PRE                                             0x0

#define SCU_RAM_VSB_AGC_POW_TGT__A                                          0x831FE7
#define SCU_RAM_VSB_AGC_POW_TGT__W                                          15
#define SCU_RAM_VSB_AGC_POW_TGT__M                                          0x7FFF
#define SCU_RAM_VSB_AGC_POW_TGT__PRE                                        0x0

#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A                                     0x831FE8
#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W                                     8
#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M                                     0xFF
#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE                                   0x0

#define SCU_RAM_VSB_FIELD_NUMBER__A                                         0x831FE9
#define SCU_RAM_VSB_FIELD_NUMBER__W                                         9
#define SCU_RAM_VSB_FIELD_NUMBER__M                                         0x1FF
#define SCU_RAM_VSB_FIELD_NUMBER__PRE                                       0x0

#define SCU_RAM_VSB_SEGMENT_NUMBER__A                                       0x831FEA
#define SCU_RAM_VSB_SEGMENT_NUMBER__W                                       10
#define SCU_RAM_VSB_SEGMENT_NUMBER__M                                       0x3FF
#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE                                     0x0

#define SCU_RAM_DRIVER_VER_HI__A                                            0x831FEB
#define SCU_RAM_DRIVER_VER_HI__W                                            16
#define SCU_RAM_DRIVER_VER_HI__M                                            0xFFFF
#define SCU_RAM_DRIVER_VER_HI__PRE                                          0x0

#define SCU_RAM_DRIVER_VER_LO__A                                            0x831FEC
#define SCU_RAM_DRIVER_VER_LO__W                                            16
#define SCU_RAM_DRIVER_VER_LO__M                                            0xFFFF
#define SCU_RAM_DRIVER_VER_LO__PRE                                          0x0

#define SCU_RAM_PARAM_15__A                                                 0x831FED
#define SCU_RAM_PARAM_15__W                                                 16
#define SCU_RAM_PARAM_15__M                                                 0xFFFF
#define SCU_RAM_PARAM_15__PRE                                               0x0

#define SCU_RAM_PARAM_14__A                                                 0x831FEE
#define SCU_RAM_PARAM_14__W                                                 16
#define SCU_RAM_PARAM_14__M                                                 0xFFFF
#define SCU_RAM_PARAM_14__PRE                                               0x0

#define SCU_RAM_PARAM_13__A                                                 0x831FEF
#define SCU_RAM_PARAM_13__W                                                 16
#define SCU_RAM_PARAM_13__M                                                 0xFFFF
#define SCU_RAM_PARAM_13__PRE                                               0x0

#define SCU_RAM_PARAM_12__A                                                 0x831FF0
#define SCU_RAM_PARAM_12__W                                                 16
#define SCU_RAM_PARAM_12__M                                                 0xFFFF
#define SCU_RAM_PARAM_12__PRE                                               0x0

#define SCU_RAM_PARAM_11__A                                                 0x831FF1
#define SCU_RAM_PARAM_11__W                                                 16
#define SCU_RAM_PARAM_11__M                                                 0xFFFF
#define SCU_RAM_PARAM_11__PRE                                               0x0

#define SCU_RAM_PARAM_10__A                                                 0x831FF2
#define SCU_RAM_PARAM_10__W                                                 16
#define SCU_RAM_PARAM_10__M                                                 0xFFFF
#define SCU_RAM_PARAM_10__PRE                                               0x0

#define SCU_RAM_PARAM_9__A                                                  0x831FF3
#define SCU_RAM_PARAM_9__W                                                  16
#define SCU_RAM_PARAM_9__M                                                  0xFFFF
#define SCU_RAM_PARAM_9__PRE                                                0x0

#define SCU_RAM_PARAM_8__A                                                  0x831FF4
#define SCU_RAM_PARAM_8__W                                                  16
#define SCU_RAM_PARAM_8__M                                                  0xFFFF
#define SCU_RAM_PARAM_8__PRE                                                0x0

#define SCU_RAM_PARAM_7__A                                                  0x831FF5
#define SCU_RAM_PARAM_7__W                                                  16
#define SCU_RAM_PARAM_7__M                                                  0xFFFF
#define SCU_RAM_PARAM_7__PRE                                                0x0

#define SCU_RAM_PARAM_6__A                                                  0x831FF6
#define SCU_RAM_PARAM_6__W                                                  16
#define SCU_RAM_PARAM_6__M                                                  0xFFFF
#define SCU_RAM_PARAM_6__PRE                                                0x0

#define SCU_RAM_PARAM_5__A                                                  0x831FF7
#define SCU_RAM_PARAM_5__W                                                  16
#define SCU_RAM_PARAM_5__M                                                  0xFFFF
#define SCU_RAM_PARAM_5__PRE                                                0x0

#define SCU_RAM_PARAM_4__A                                                  0x831FF8
#define SCU_RAM_PARAM_4__W                                                  16
#define SCU_RAM_PARAM_4__M                                                  0xFFFF
#define SCU_RAM_PARAM_4__PRE                                                0x0

#define SCU_RAM_PARAM_3__A                                                  0x831FF9
#define SCU_RAM_PARAM_3__W                                                  16
#define SCU_RAM_PARAM_3__M                                                  0xFFFF
#define SCU_RAM_PARAM_3__PRE                                                0x0

#define SCU_RAM_PARAM_2__A                                                  0x831FFA
#define SCU_RAM_PARAM_2__W                                                  16
#define SCU_RAM_PARAM_2__M                                                  0xFFFF
#define SCU_RAM_PARAM_2__PRE                                                0x0

#define SCU_RAM_PARAM_1__A                                                  0x831FFB
#define SCU_RAM_PARAM_1__W                                                  16
#define SCU_RAM_PARAM_1__M                                                  0xFFFF
#define SCU_RAM_PARAM_1__PRE                                                0x0
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED                     0x0
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED                   0x4000
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED                         0x8000
#define   SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK                     0xC000

#define SCU_RAM_PARAM_0__A                                                  0x831FFC
#define SCU_RAM_PARAM_0__W                                                  16
#define SCU_RAM_PARAM_0__M                                                  0xFFFF
#define SCU_RAM_PARAM_0__PRE                                                0x0
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD                      0x2
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD                       0x103
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD                       0x3
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD                      0x4
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD                       0x9
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD                      0x109
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD                       0xA
#define   SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD                      0x40
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A                          0x0
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B                          0x1
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C                          0x2
#define   SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D                          0x3
#define   SCU_RAM_PARAM_0_RESULT_OK                                         0x0
#define   SCU_RAM_PARAM_0_RESULT_UNKCMD                                     0xFFFF
#define   SCU_RAM_PARAM_0_RESULT_UNKSTD                                     0xFFFE
#define   SCU_RAM_PARAM_0_RESULT_INVPAR                                     0xFFFD
#define   SCU_RAM_PARAM_0_RESULT_SIZE                                       0xFFFC

#define SCU_RAM_COMMAND__A                                                  0x831FFD
#define SCU_RAM_COMMAND__W                                                  16
#define SCU_RAM_COMMAND__M                                                  0xFFFF
#define SCU_RAM_COMMAND__PRE                                                0x0
#define   SCU_RAM_COMMAND_CMD_DEMOD_RESET                                   0x1
#define   SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV                                 0x2
#define   SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM                               0x3
#define   SCU_RAM_COMMAND_CMD_DEMOD_START                                   0x4
#define   SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK                                0x5
#define   SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM                               0x6
#define   SCU_RAM_COMMAND_CMD_DEMOD_HOLD                                    0x7
#define   SCU_RAM_COMMAND_CMD_DEMOD_RESUME                                  0x8
#define   SCU_RAM_COMMAND_CMD_DEMOD_STOP                                    0x9
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE                          0x80
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE                        0x81
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL                            0x82
#define   SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR                           0x83
#define   SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE                            0x84
#define   SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE                         0x85
#define   SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS                            0x80
#define   SCU_RAM_COMMAND_CMD_DEBUG_HTOL                                    0x81
#define   SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER                       0x82
#define   SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK                       0x83
#define   SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK                        0x84
#define   SCU_RAM_COMMAND_CMD_ADMIN_NOP                                     0xFF
#define   SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION                             0xFE
#define   SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION                        0xFD
#define   SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS                         0xC0

#define   SCU_RAM_COMMAND_STANDARD__B                                       8
#define   SCU_RAM_COMMAND_STANDARD__W                                       8
#define   SCU_RAM_COMMAND_STANDARD__M                                       0xFF00
#define   SCU_RAM_COMMAND_STANDARD__PRE                                     0x0
#define     SCU_RAM_COMMAND_STANDARD_ATV                                    0x100
#define     SCU_RAM_COMMAND_STANDARD_QAM                                    0x200
#define     SCU_RAM_COMMAND_STANDARD_VSB                                    0x300
#define     SCU_RAM_COMMAND_STANDARD_OFDM                                   0x400
#define     SCU_RAM_COMMAND_STANDARD_OOB                                    0x8000
#define     SCU_RAM_COMMAND_STANDARD_TOP                                    0xFF00

#define SCU_RAM_VERSION_HI__A                                               0x831FFE
#define SCU_RAM_VERSION_HI__W                                               16
#define SCU_RAM_VERSION_HI__M                                               0xFFFF
#define SCU_RAM_VERSION_HI__PRE                                             0x0

#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__B                                12
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__W                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__M                                0xF000
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE                              0x0

#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__B                                8
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__W                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__M                                0xF00
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE                              0x0

#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__B                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__W                                4
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__M                                0xF0
#define   SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE                              0x0

#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__B                                0
#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__W                                4
#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__M                                0xF
#define   SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE                              0x0

#define SCU_RAM_VERSION_LO__A                                               0x831FFF
#define SCU_RAM_VERSION_LO__W                                               16
#define SCU_RAM_VERSION_LO__M                                               0xFFFF
#define SCU_RAM_VERSION_LO__PRE                                             0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__B                                12
#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__M                                0xF000
#define   SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE                              0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__B                                8
#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__M                                0xF00
#define   SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE                              0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__B                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__M                                0xF0
#define   SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE                              0x0

#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__B                                0
#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__W                                4
#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__M                                0xF
#define   SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE                              0x0

#define SIO_COMM_EXEC__A                                                    0x400000
#define SIO_COMM_EXEC__W                                                    2
#define SIO_COMM_EXEC__M                                                    0x3
#define SIO_COMM_EXEC__PRE                                                  0x0
#define   SIO_COMM_EXEC_STOP                                                0x0
#define   SIO_COMM_EXEC_ACTIVE                                              0x1
#define   SIO_COMM_EXEC_HOLD                                                0x2

#define SIO_COMM_STATE__A                                                   0x400001
#define SIO_COMM_STATE__W                                                   16
#define SIO_COMM_STATE__M                                                   0xFFFF
#define SIO_COMM_STATE__PRE                                                 0x0
#define SIO_COMM_MB__A                                                      0x400002
#define SIO_COMM_MB__W                                                      16
#define SIO_COMM_MB__M                                                      0xFFFF
#define SIO_COMM_MB__PRE                                                    0x0
#define SIO_COMM_INT_REQ__A                                                 0x400003
#define SIO_COMM_INT_REQ__W                                                 16
#define SIO_COMM_INT_REQ__M                                                 0xFFFF
#define SIO_COMM_INT_REQ__PRE                                               0x0

#define   SIO_COMM_INT_REQ_HI_REQ__B                                        0
#define   SIO_COMM_INT_REQ_HI_REQ__W                                        1
#define   SIO_COMM_INT_REQ_HI_REQ__M                                        0x1
#define   SIO_COMM_INT_REQ_HI_REQ__PRE                                      0x0

#define   SIO_COMM_INT_REQ_SA_REQ__B                                        1
#define   SIO_COMM_INT_REQ_SA_REQ__W                                        1
#define   SIO_COMM_INT_REQ_SA_REQ__M                                        0x2
#define   SIO_COMM_INT_REQ_SA_REQ__PRE                                      0x0

#define SIO_COMM_INT_STA__A                                                 0x400005
#define SIO_COMM_INT_STA__W                                                 16
#define SIO_COMM_INT_STA__M                                                 0xFFFF
#define SIO_COMM_INT_STA__PRE                                               0x0
#define SIO_COMM_INT_MSK__A                                                 0x400006
#define SIO_COMM_INT_MSK__W                                                 16
#define SIO_COMM_INT_MSK__M                                                 0xFFFF
#define SIO_COMM_INT_MSK__PRE                                               0x0
#define SIO_COMM_INT_STM__A                                                 0x400007
#define SIO_COMM_INT_STM__W                                                 16
#define SIO_COMM_INT_STM__M                                                 0xFFFF
#define SIO_COMM_INT_STM__PRE                                               0x0

#define SIO_TOP_COMM_EXEC__A                                                0x410000
#define SIO_TOP_COMM_EXEC__W                                                2
#define SIO_TOP_COMM_EXEC__M                                                0x3
#define SIO_TOP_COMM_EXEC__PRE                                              0x0
#define   SIO_TOP_COMM_EXEC_STOP                                            0x0
#define   SIO_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   SIO_TOP_COMM_EXEC_HOLD                                            0x2

#define SIO_TOP_COMM_KEY__A                                                 0x41000F
#define SIO_TOP_COMM_KEY__W                                                 16
#define SIO_TOP_COMM_KEY__M                                                 0xFFFF
#define SIO_TOP_COMM_KEY__PRE                                               0x0
#define   SIO_TOP_COMM_KEY_KEY                                              0xFABA

#define SIO_TOP_JTAGID_LO__A                                                0x410012
#define SIO_TOP_JTAGID_LO__W                                                16
#define SIO_TOP_JTAGID_LO__M                                                0xFFFF
#define SIO_TOP_JTAGID_LO__PRE                                              0x0

#define SIO_TOP_JTAGID_HI__A                                                0x410013
#define SIO_TOP_JTAGID_HI__W                                                16
#define SIO_TOP_JTAGID_HI__M                                                0xFFFF
#define SIO_TOP_JTAGID_HI__PRE                                              0x0

#define SIO_HI_RA_RAM_S0_FLG_SMM__A                                         0x420010
#define SIO_HI_RA_RAM_S0_FLG_SMM__W                                         1
#define SIO_HI_RA_RAM_S0_FLG_SMM__M                                         0x1
#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE                                       0x0

#define SIO_HI_RA_RAM_S0_DEV_ID__A                                          0x420011
#define SIO_HI_RA_RAM_S0_DEV_ID__W                                          7
#define SIO_HI_RA_RAM_S0_DEV_ID__M                                          0x7F
#define SIO_HI_RA_RAM_S0_DEV_ID__PRE                                        0x52

#define SIO_HI_RA_RAM_S0_FLG_CRC__A                                         0x420012
#define SIO_HI_RA_RAM_S0_FLG_CRC__W                                         1
#define SIO_HI_RA_RAM_S0_FLG_CRC__M                                         0x1
#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE                                       0x0
#define SIO_HI_RA_RAM_S0_FLG_ACC__A                                         0x420013
#define SIO_HI_RA_RAM_S0_FLG_ACC__W                                         4
#define SIO_HI_RA_RAM_S0_FLG_ACC__M                                         0xF
#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE                                       0x0

#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B                                0
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W                                2
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M                                0x3
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE                              0x0

#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B                            2
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W                            1
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M                            0x4
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE                          0x0

#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B                            3
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W                            1
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M                            0x8
#define   SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE                          0x0

#define SIO_HI_RA_RAM_S0_STATE__A                                           0x420014
#define SIO_HI_RA_RAM_S0_STATE__W                                           1
#define SIO_HI_RA_RAM_S0_STATE__M                                           0x1
#define SIO_HI_RA_RAM_S0_STATE__PRE                                         0x0

#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B                              0
#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W                              1
#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M                              0x1
#define   SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE                            0x0

#define SIO_HI_RA_RAM_S0_BLK_BNK__A                                         0x420015
#define SIO_HI_RA_RAM_S0_BLK_BNK__W                                         12
#define SIO_HI_RA_RAM_S0_BLK_BNK__M                                         0xFFF
#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE                                       0x82

#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B                            0
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W                            6
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M                            0x3F
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE                          0x2

#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B                            6
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W                            6
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M                            0xFC0
#define   SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE                          0x80

#define SIO_HI_RA_RAM_S0_ADDR__A                                            0x420016
#define SIO_HI_RA_RAM_S0_ADDR__W                                            16
#define SIO_HI_RA_RAM_S0_ADDR__M                                            0xFFFF
#define SIO_HI_RA_RAM_S0_ADDR__PRE                                          0x0

#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B                              0
#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W                              16
#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M                              0xFFFF
#define   SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE                            0x0

#define SIO_HI_RA_RAM_S0_CRC__A                                             0x420017
#define SIO_HI_RA_RAM_S0_CRC__W                                             16
#define SIO_HI_RA_RAM_S0_CRC__M                                             0xFFFF
#define SIO_HI_RA_RAM_S0_CRC__PRE                                           0x0

#define SIO_HI_RA_RAM_S0_BUFFER__A                                          0x420018
#define SIO_HI_RA_RAM_S0_BUFFER__W                                          16
#define SIO_HI_RA_RAM_S0_BUFFER__M                                          0xFFFF
#define SIO_HI_RA_RAM_S0_BUFFER__PRE                                        0x0

#define SIO_HI_RA_RAM_S0_RMWBUF__A                                          0x420019
#define SIO_HI_RA_RAM_S0_RMWBUF__W                                          16
#define SIO_HI_RA_RAM_S0_RMWBUF__M                                          0xFFFF
#define SIO_HI_RA_RAM_S0_RMWBUF__PRE                                        0x0

#define SIO_HI_RA_RAM_S0_FLG_VB__A                                          0x42001A
#define SIO_HI_RA_RAM_S0_FLG_VB__W                                          1
#define SIO_HI_RA_RAM_S0_FLG_VB__M                                          0x1
#define SIO_HI_RA_RAM_S0_FLG_VB__PRE                                        0x0

#define SIO_HI_RA_RAM_S0_TEMP0__A                                           0x42001B
#define SIO_HI_RA_RAM_S0_TEMP0__W                                           16
#define SIO_HI_RA_RAM_S0_TEMP0__M                                           0xFFFF
#define SIO_HI_RA_RAM_S0_TEMP0__PRE                                         0x0

#define SIO_HI_RA_RAM_S0_TEMP1__A                                           0x42001C
#define SIO_HI_RA_RAM_S0_TEMP1__W                                           16
#define SIO_HI_RA_RAM_S0_TEMP1__M                                           0xFFFF
#define SIO_HI_RA_RAM_S0_TEMP1__PRE                                         0x0

#define SIO_HI_RA_RAM_S0_OFFSET__A                                          0x42001D
#define SIO_HI_RA_RAM_S0_OFFSET__W                                          16
#define SIO_HI_RA_RAM_S0_OFFSET__M                                          0xFFFF
#define SIO_HI_RA_RAM_S0_OFFSET__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_FLG_SMM__A                                         0x420020
#define SIO_HI_RA_RAM_S1_FLG_SMM__W                                         1
#define SIO_HI_RA_RAM_S1_FLG_SMM__M                                         0x1
#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE                                       0x0

#define SIO_HI_RA_RAM_S1_DEV_ID__A                                          0x420021
#define SIO_HI_RA_RAM_S1_DEV_ID__W                                          7
#define SIO_HI_RA_RAM_S1_DEV_ID__M                                          0x7F
#define SIO_HI_RA_RAM_S1_DEV_ID__PRE                                        0x52

#define SIO_HI_RA_RAM_S1_FLG_CRC__A                                         0x420022
#define SIO_HI_RA_RAM_S1_FLG_CRC__W                                         1
#define SIO_HI_RA_RAM_S1_FLG_CRC__M                                         0x1
#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE                                       0x0
#define SIO_HI_RA_RAM_S1_FLG_ACC__A                                         0x420023
#define SIO_HI_RA_RAM_S1_FLG_ACC__W                                         4
#define SIO_HI_RA_RAM_S1_FLG_ACC__M                                         0xF
#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE                                       0x0

#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B                                0
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W                                2
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M                                0x3
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE                              0x0

#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B                            2
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W                            1
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M                            0x4
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE                          0x0

#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B                            3
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W                            1
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M                            0x8
#define   SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE                          0x0

#define SIO_HI_RA_RAM_S1_STATE__A                                           0x420024
#define SIO_HI_RA_RAM_S1_STATE__W                                           1
#define SIO_HI_RA_RAM_S1_STATE__M                                           0x1
#define SIO_HI_RA_RAM_S1_STATE__PRE                                         0x0

#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B                              0
#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W                              1
#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M                              0x1
#define   SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE                            0x0

#define SIO_HI_RA_RAM_S1_BLK_BNK__A                                         0x420025
#define SIO_HI_RA_RAM_S1_BLK_BNK__W                                         12
#define SIO_HI_RA_RAM_S1_BLK_BNK__M                                         0xFFF
#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE                                       0x82

#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B                            0
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W                            6
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M                            0x3F
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE                          0x2

#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B                            6
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W                            6
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M                            0xFC0
#define   SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE                          0x80

#define SIO_HI_RA_RAM_S1_ADDR__A                                            0x420026
#define SIO_HI_RA_RAM_S1_ADDR__W                                            16
#define SIO_HI_RA_RAM_S1_ADDR__M                                            0xFFFF
#define SIO_HI_RA_RAM_S1_ADDR__PRE                                          0x0

#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B                              0
#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W                              16
#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M                              0xFFFF
#define   SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE                            0x0

#define SIO_HI_RA_RAM_S1_CRC__A                                             0x420027
#define SIO_HI_RA_RAM_S1_CRC__W                                             16
#define SIO_HI_RA_RAM_S1_CRC__M                                             0xFFFF
#define SIO_HI_RA_RAM_S1_CRC__PRE                                           0x0

#define SIO_HI_RA_RAM_S1_BUFFER__A                                          0x420028
#define SIO_HI_RA_RAM_S1_BUFFER__W                                          16
#define SIO_HI_RA_RAM_S1_BUFFER__M                                          0xFFFF
#define SIO_HI_RA_RAM_S1_BUFFER__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_RMWBUF__A                                          0x420029
#define SIO_HI_RA_RAM_S1_RMWBUF__W                                          16
#define SIO_HI_RA_RAM_S1_RMWBUF__M                                          0xFFFF
#define SIO_HI_RA_RAM_S1_RMWBUF__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_FLG_VB__A                                          0x42002A
#define SIO_HI_RA_RAM_S1_FLG_VB__W                                          1
#define SIO_HI_RA_RAM_S1_FLG_VB__M                                          0x1
#define SIO_HI_RA_RAM_S1_FLG_VB__PRE                                        0x0

#define SIO_HI_RA_RAM_S1_TEMP0__A                                           0x42002B
#define SIO_HI_RA_RAM_S1_TEMP0__W                                           16
#define SIO_HI_RA_RAM_S1_TEMP0__M                                           0xFFFF
#define SIO_HI_RA_RAM_S1_TEMP0__PRE                                         0x0

#define SIO_HI_RA_RAM_S1_TEMP1__A                                           0x42002C
#define SIO_HI_RA_RAM_S1_TEMP1__W                                           16
#define SIO_HI_RA_RAM_S1_TEMP1__M                                           0xFFFF
#define SIO_HI_RA_RAM_S1_TEMP1__PRE                                         0x0

#define SIO_HI_RA_RAM_S1_OFFSET__A                                          0x42002D
#define SIO_HI_RA_RAM_S1_OFFSET__W                                          16
#define SIO_HI_RA_RAM_S1_OFFSET__M                                          0xFFFF
#define SIO_HI_RA_RAM_S1_OFFSET__PRE                                        0x0
#define SIO_HI_RA_RAM_SEMA__A                                               0x420030
#define SIO_HI_RA_RAM_SEMA__W                                               1
#define SIO_HI_RA_RAM_SEMA__M                                               0x1
#define SIO_HI_RA_RAM_SEMA__PRE                                             0x0
#define   SIO_HI_RA_RAM_SEMA_FREE                                           0x0
#define   SIO_HI_RA_RAM_SEMA_BUSY                                           0x1

#define SIO_HI_RA_RAM_RES__A                                                0x420031
#define SIO_HI_RA_RAM_RES__W                                                3
#define SIO_HI_RA_RAM_RES__M                                                0x7
#define SIO_HI_RA_RAM_RES__PRE                                              0x0
#define   SIO_HI_RA_RAM_RES_OK                                              0x0
#define   SIO_HI_RA_RAM_RES_ERROR                                           0x1
#define   SIO_HI_RA_RAM_RES_I2C_START_FOUND                                 0x1
#define   SIO_HI_RA_RAM_RES_I2C_STOP_FOUND                                  0x2
#define   SIO_HI_RA_RAM_RES_I2C_ARB_LOST                                    0x3
#define   SIO_HI_RA_RAM_RES_I2C_ERROR                                       0x4

#define SIO_HI_RA_RAM_CMD__A                                                0x420032
#define SIO_HI_RA_RAM_CMD__W                                                4
#define SIO_HI_RA_RAM_CMD__M                                                0xF
#define SIO_HI_RA_RAM_CMD__PRE                                              0x0
#define   SIO_HI_RA_RAM_CMD_NULL                                            0x0
#define   SIO_HI_RA_RAM_CMD_UIO                                             0x1
#define   SIO_HI_RA_RAM_CMD_RESET                                           0x2
#define   SIO_HI_RA_RAM_CMD_CONFIG                                          0x3
#define   SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER                               0x4
#define   SIO_HI_RA_RAM_CMD_I2C_TRANSMIT                                    0x5
#define   SIO_HI_RA_RAM_CMD_EXEC                                            0x6
#define   SIO_HI_RA_RAM_CMD_BRDCTRL                                         0x7
#define   SIO_HI_RA_RAM_CMD_ATOMIC_COPY                                     0x8

#define SIO_HI_RA_RAM_PAR_1__A                                              0x420033
#define SIO_HI_RA_RAM_PAR_1__W                                              16
#define SIO_HI_RA_RAM_PAR_1__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_1__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_1_PAR1__B                                       0
#define   SIO_HI_RA_RAM_PAR_1_PAR1__W                                       16
#define   SIO_HI_RA_RAM_PAR_1_PAR1__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_1_PAR1__PRE                                     0x0
#define     SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY                                0x3945

#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B                                 0
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W                                 1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M                                 0x1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE                               0x0

#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B                                  1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W                                  1
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M                                  0x2
#define   SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE                                0x0
#define     SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE                           0x0
#define     SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE                            0x2

#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B                                  0
#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W                                  10
#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M                                  0x3FF
#define   SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE                                0x0

#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_2__A                                              0x420034
#define SIO_HI_RA_RAM_PAR_2__W                                              16
#define SIO_HI_RA_RAM_PAR_2__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_2__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_2_PAR2__B                                       0
#define   SIO_HI_RA_RAM_PAR_2_PAR2__W                                       16
#define   SIO_HI_RA_RAM_PAR_2_PAR2__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_PAR2__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__B                                    0
#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__W                                    7
#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__M                                    0x7F
#define   SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE                                  0x25

#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B                                  0
#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W                                  16
#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M                                  0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE                                0x0

#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__B                                    2
#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__W                                    1
#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__M                                    0x4
#define   SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE                                  0x0
#define     SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN                                0x0
#define     SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED                              0x4

#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_3__A                                              0x420035
#define SIO_HI_RA_RAM_PAR_3__W                                              16
#define SIO_HI_RA_RAM_PAR_3__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_3__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_3_PAR3__B                                       0
#define   SIO_HI_RA_RAM_PAR_3_PAR3__W                                       16
#define   SIO_HI_RA_RAM_PAR_3_PAR3__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_3_PAR3__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B                                0
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W                                7
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M                                0x7F
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE                              0x3F

#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B                                7
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W                                7
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M                                0x3F80
#define   SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE                              0x1F80

#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__B                                    0
#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__W                                    16
#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__M                                    0xFFFF
#define   SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE                                  0x0

#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__B                                    0
#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__W                                    3
#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__M                                    0x7
#define   SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE                                  0x0

#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__B                                     3
#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__W                                     1
#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__M                                     0x8
#define   SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE                                   0x0
#define     SIO_HI_RA_RAM_PAR_3_ACP_RW_READ                                 0x0
#define     SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE                                0x8

#define SIO_HI_RA_RAM_PAR_4__A                                              0x420036
#define SIO_HI_RA_RAM_PAR_4__W                                              16
#define SIO_HI_RA_RAM_PAR_4__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_4__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_4_PAR4__B                                       0
#define   SIO_HI_RA_RAM_PAR_4_PAR4__W                                       16
#define   SIO_HI_RA_RAM_PAR_4_PAR4__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_4_PAR4__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__B                                    0
#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__W                                    8
#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__M                                    0xFF
#define   SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE                                  0xC1

#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B                                0
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M                                0x3F
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B                                6
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W                                6
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M                                0xFC0
#define   SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_5__A                                              0x420037
#define SIO_HI_RA_RAM_PAR_5__W                                              16
#define SIO_HI_RA_RAM_PAR_5__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_5__PRE                                            0x0
#define   SIO_HI_RA_RAM_PAR_5_PAR5__B                                       0
#define   SIO_HI_RA_RAM_PAR_5_PAR5__W                                       16
#define   SIO_HI_RA_RAM_PAR_5_PAR5__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_5_PAR5__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B                                   0
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W                                   1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M                                   0x1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE                                 0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE                           0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE                              0x1

#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B                                   1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W                                   1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M                                   0x2
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE                                 0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE                           0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE                              0x2

#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B                                  3
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W                                  1
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M                                  0x8
#define   SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE                                0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE                             0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ                               0x8

#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B                                  5
#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W                                  1
#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M                                  0x20
#define   SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE                                0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE                           0x0
#define     SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE                            0x20

#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE                              0x0

#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B                                0
#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W                                16
#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M                                0xFFFF
#define   SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE                              0x0

#define SIO_HI_RA_RAM_PAR_6__A                                              0x420038
#define SIO_HI_RA_RAM_PAR_6__W                                              16
#define SIO_HI_RA_RAM_PAR_6__M                                              0xFFFF
#define SIO_HI_RA_RAM_PAR_6__PRE                                            0x95FF
#define   SIO_HI_RA_RAM_PAR_6_PAR6__B                                       0
#define   SIO_HI_RA_RAM_PAR_6_PAR6__W                                       16
#define   SIO_HI_RA_RAM_PAR_6_PAR6__M                                       0xFFFF
#define   SIO_HI_RA_RAM_PAR_6_PAR6__PRE                                     0x0

#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__B                                    0
#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__W                                    8
#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__M                                    0xFF
#define   SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE                                  0xFF

#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__B                                    8
#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__W                                    8
#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__M                                    0xFF00
#define   SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE                                  0x9500

#define SIO_HI_RA_RAM_AB_TEMP__A                                            0x42006E
#define SIO_HI_RA_RAM_AB_TEMP__W                                            16
#define SIO_HI_RA_RAM_AB_TEMP__M                                            0xFFFF
#define SIO_HI_RA_RAM_AB_TEMP__PRE                                          0x0

#define SIO_HI_RA_RAM_I2C_CTL__A                                            0x42006F
#define SIO_HI_RA_RAM_I2C_CTL__W                                            16
#define SIO_HI_RA_RAM_I2C_CTL__M                                            0xFFFF
#define SIO_HI_RA_RAM_I2C_CTL__PRE                                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY0__A                                          0x420070
#define SIO_HI_RA_RAM_VB_ENTRY0__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY0__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY0__PRE                                        0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B                             0
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W                             4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M                             0xF
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE                           0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B                             4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W                             4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M                             0xF0
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE                           0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B                            8
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W                            4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M                            0xF00
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE                          0x0

#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B                            12
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W                            4
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M                            0xF000
#define   SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE                          0x0

#define SIO_HI_RA_RAM_VB_OFFSET0__A                                         0x420071
#define SIO_HI_RA_RAM_VB_OFFSET0__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET0__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET0__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B                           0
#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W                           16
#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M                           0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE                         0x0

#define SIO_HI_RA_RAM_VB_ENTRY1__A                                          0x420072
#define SIO_HI_RA_RAM_VB_ENTRY1__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY1__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY1__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET1__A                                         0x420073
#define SIO_HI_RA_RAM_VB_OFFSET1__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET1__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET1__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY2__A                                          0x420074
#define SIO_HI_RA_RAM_VB_ENTRY2__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY2__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY2__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET2__A                                         0x420075
#define SIO_HI_RA_RAM_VB_OFFSET2__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET2__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET2__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY3__A                                          0x420076
#define SIO_HI_RA_RAM_VB_ENTRY3__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY3__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY3__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET3__A                                         0x420077
#define SIO_HI_RA_RAM_VB_OFFSET3__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET3__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET3__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY4__A                                          0x420078
#define SIO_HI_RA_RAM_VB_ENTRY4__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY4__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY4__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET4__A                                         0x420079
#define SIO_HI_RA_RAM_VB_OFFSET4__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET4__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET4__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY5__A                                          0x42007A
#define SIO_HI_RA_RAM_VB_ENTRY5__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY5__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY5__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET5__A                                         0x42007B
#define SIO_HI_RA_RAM_VB_OFFSET5__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET5__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET5__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY6__A                                          0x42007C
#define SIO_HI_RA_RAM_VB_ENTRY6__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY6__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY6__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET6__A                                         0x42007D
#define SIO_HI_RA_RAM_VB_OFFSET6__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET6__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET6__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_RA_RAM_VB_ENTRY7__A                                          0x42007E
#define SIO_HI_RA_RAM_VB_ENTRY7__W                                          16
#define SIO_HI_RA_RAM_VB_ENTRY7__M                                          0xFFFF
#define SIO_HI_RA_RAM_VB_ENTRY7__PRE                                        0x0
#define SIO_HI_RA_RAM_VB_OFFSET7__A                                         0x42007F
#define SIO_HI_RA_RAM_VB_OFFSET7__W                                         16
#define SIO_HI_RA_RAM_VB_OFFSET7__M                                         0xFFFF
#define SIO_HI_RA_RAM_VB_OFFSET7__PRE                                       0x0

#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B                            0
#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W                            16
#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M                            0xFFFF
#define   SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE                          0x0

#define SIO_HI_IF_RAM_TRP_BPT_0__A                                          0x430000
#define SIO_HI_IF_RAM_TRP_BPT_0__W                                          12
#define SIO_HI_IF_RAM_TRP_BPT_0__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_BPT_0__PRE                                        0x0
#define SIO_HI_IF_RAM_TRP_BPT_1__A                                          0x430001
#define SIO_HI_IF_RAM_TRP_BPT_1__W                                          12
#define SIO_HI_IF_RAM_TRP_BPT_1__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_BPT_1__PRE                                        0x0
#define SIO_HI_IF_RAM_TRP_STK_0__A                                          0x430002
#define SIO_HI_IF_RAM_TRP_STK_0__W                                          12
#define SIO_HI_IF_RAM_TRP_STK_0__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_STK_0__PRE                                        0x0
#define SIO_HI_IF_RAM_TRP_STK_1__A                                          0x430003
#define SIO_HI_IF_RAM_TRP_STK_1__W                                          12
#define SIO_HI_IF_RAM_TRP_STK_1__M                                          0xFFF
#define SIO_HI_IF_RAM_TRP_STK_1__PRE                                        0x0
#define SIO_HI_IF_RAM_FUN_BASE__A                                           0x430300
#define SIO_HI_IF_RAM_FUN_BASE__W                                           12
#define SIO_HI_IF_RAM_FUN_BASE__M                                           0xFFF
#define SIO_HI_IF_RAM_FUN_BASE__PRE                                         0x0

#define SIO_HI_IF_COMM_EXEC__A                                              0x440000
#define SIO_HI_IF_COMM_EXEC__W                                              2
#define SIO_HI_IF_COMM_EXEC__M                                              0x3
#define SIO_HI_IF_COMM_EXEC__PRE                                            0x0
#define   SIO_HI_IF_COMM_EXEC_STOP                                          0x0
#define   SIO_HI_IF_COMM_EXEC_ACTIVE                                        0x1
#define   SIO_HI_IF_COMM_EXEC_HOLD                                          0x2
#define   SIO_HI_IF_COMM_EXEC_STEP                                          0x3

#define SIO_HI_IF_COMM_STATE__A                                             0x440001
#define SIO_HI_IF_COMM_STATE__W                                             10
#define SIO_HI_IF_COMM_STATE__M                                             0x3FF
#define SIO_HI_IF_COMM_STATE__PRE                                           0x0
#define SIO_HI_IF_COMM_INT_REQ__A                                           0x440003
#define SIO_HI_IF_COMM_INT_REQ__W                                           1
#define SIO_HI_IF_COMM_INT_REQ__M                                           0x1
#define SIO_HI_IF_COMM_INT_REQ__PRE                                         0x0
#define SIO_HI_IF_COMM_INT_STA__A                                           0x440005
#define SIO_HI_IF_COMM_INT_STA__W                                           1
#define SIO_HI_IF_COMM_INT_STA__M                                           0x1
#define SIO_HI_IF_COMM_INT_STA__PRE                                         0x0
#define   SIO_HI_IF_COMM_INT_STA_STAT__B                                    0
#define   SIO_HI_IF_COMM_INT_STA_STAT__W                                    1
#define   SIO_HI_IF_COMM_INT_STA_STAT__M                                    0x1
#define   SIO_HI_IF_COMM_INT_STA_STAT__PRE                                  0x0

#define SIO_HI_IF_COMM_INT_MSK__A                                           0x440006
#define SIO_HI_IF_COMM_INT_MSK__W                                           1
#define SIO_HI_IF_COMM_INT_MSK__M                                           0x1
#define SIO_HI_IF_COMM_INT_MSK__PRE                                         0x0
#define   SIO_HI_IF_COMM_INT_MSK_STAT__B                                    0
#define   SIO_HI_IF_COMM_INT_MSK_STAT__W                                    1
#define   SIO_HI_IF_COMM_INT_MSK_STAT__M                                    0x1
#define   SIO_HI_IF_COMM_INT_MSK_STAT__PRE                                  0x0

#define SIO_HI_IF_COMM_INT_STM__A                                           0x440007
#define SIO_HI_IF_COMM_INT_STM__W                                           1
#define SIO_HI_IF_COMM_INT_STM__M                                           0x1
#define SIO_HI_IF_COMM_INT_STM__PRE                                         0x0
#define   SIO_HI_IF_COMM_INT_STM_STAT__B                                    0
#define   SIO_HI_IF_COMM_INT_STM_STAT__W                                    1
#define   SIO_HI_IF_COMM_INT_STM_STAT__M                                    0x1
#define   SIO_HI_IF_COMM_INT_STM_STAT__PRE                                  0x0

#define SIO_HI_IF_STK_0__A                                                  0x440010
#define SIO_HI_IF_STK_0__W                                                  10
#define SIO_HI_IF_STK_0__M                                                  0x3FF
#define SIO_HI_IF_STK_0__PRE                                                0x2

#define   SIO_HI_IF_STK_0_ADDR__B                                           0
#define   SIO_HI_IF_STK_0_ADDR__W                                           10
#define   SIO_HI_IF_STK_0_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_0_ADDR__PRE                                         0x2

#define SIO_HI_IF_STK_1__A                                                  0x440011
#define SIO_HI_IF_STK_1__W                                                  10
#define SIO_HI_IF_STK_1__M                                                  0x3FF
#define SIO_HI_IF_STK_1__PRE                                                0x2
#define   SIO_HI_IF_STK_1_ADDR__B                                           0
#define   SIO_HI_IF_STK_1_ADDR__W                                           10
#define   SIO_HI_IF_STK_1_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_1_ADDR__PRE                                         0x2

#define SIO_HI_IF_STK_2__A                                                  0x440012
#define SIO_HI_IF_STK_2__W                                                  10
#define SIO_HI_IF_STK_2__M                                                  0x3FF
#define SIO_HI_IF_STK_2__PRE                                                0x2
#define   SIO_HI_IF_STK_2_ADDR__B                                           0
#define   SIO_HI_IF_STK_2_ADDR__W                                           10
#define   SIO_HI_IF_STK_2_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_2_ADDR__PRE                                         0x2

#define SIO_HI_IF_STK_3__A                                                  0x440013
#define SIO_HI_IF_STK_3__W                                                  10
#define SIO_HI_IF_STK_3__M                                                  0x3FF
#define SIO_HI_IF_STK_3__PRE                                                0x2

#define   SIO_HI_IF_STK_3_ADDR__B                                           0
#define   SIO_HI_IF_STK_3_ADDR__W                                           10
#define   SIO_HI_IF_STK_3_ADDR__M                                           0x3FF
#define   SIO_HI_IF_STK_3_ADDR__PRE                                         0x2

#define SIO_HI_IF_BPT_IDX__A                                                0x44001F
#define SIO_HI_IF_BPT_IDX__W                                                1
#define SIO_HI_IF_BPT_IDX__M                                                0x1
#define SIO_HI_IF_BPT_IDX__PRE                                              0x0

#define   SIO_HI_IF_BPT_IDX_ADDR__B                                         0
#define   SIO_HI_IF_BPT_IDX_ADDR__W                                         1
#define   SIO_HI_IF_BPT_IDX_ADDR__M                                         0x1
#define   SIO_HI_IF_BPT_IDX_ADDR__PRE                                       0x0

#define SIO_HI_IF_BPT__A                                                    0x440020
#define SIO_HI_IF_BPT__W                                                    10
#define SIO_HI_IF_BPT__M                                                    0x3FF
#define SIO_HI_IF_BPT__PRE                                                  0x2

#define   SIO_HI_IF_BPT_ADDR__B                                             0
#define   SIO_HI_IF_BPT_ADDR__W                                             10
#define   SIO_HI_IF_BPT_ADDR__M                                             0x3FF
#define   SIO_HI_IF_BPT_ADDR__PRE                                           0x2

#define SIO_CC_COMM_EXEC__A                                                 0x450000
#define SIO_CC_COMM_EXEC__W                                                 2
#define SIO_CC_COMM_EXEC__M                                                 0x3
#define SIO_CC_COMM_EXEC__PRE                                               0x0
#define   SIO_CC_COMM_EXEC_STOP                                             0x0
#define   SIO_CC_COMM_EXEC_ACTIVE                                           0x1
#define   SIO_CC_COMM_EXEC_HOLD                                             0x2

#define SIO_CC_PLL_MODE__A                                                  0x450010
#define SIO_CC_PLL_MODE__W                                                  6
#define SIO_CC_PLL_MODE__M                                                  0x3F
#define SIO_CC_PLL_MODE__PRE                                                0x0

#define   SIO_CC_PLL_MODE_FREF_SEL__B                                       0
#define   SIO_CC_PLL_MODE_FREF_SEL__W                                       2
#define   SIO_CC_PLL_MODE_FREF_SEL__M                                       0x3
#define   SIO_CC_PLL_MODE_FREF_SEL__PRE                                     0x0
#define     SIO_CC_PLL_MODE_FREF_SEL_OHW                                    0x0
#define     SIO_CC_PLL_MODE_FREF_SEL_27_00                                  0x1
#define     SIO_CC_PLL_MODE_FREF_SEL_20_25                                  0x2
#define     SIO_CC_PLL_MODE_FREF_SEL_4_00                                   0x3

#define   SIO_CC_PLL_MODE_LOCKSEL__B                                        2
#define   SIO_CC_PLL_MODE_LOCKSEL__W                                        2
#define   SIO_CC_PLL_MODE_LOCKSEL__M                                        0xC
#define   SIO_CC_PLL_MODE_LOCKSEL__PRE                                      0x0

#define   SIO_CC_PLL_MODE_BYPASS__B                                         4
#define   SIO_CC_PLL_MODE_BYPASS__W                                         2
#define   SIO_CC_PLL_MODE_BYPASS__M                                         0x30
#define   SIO_CC_PLL_MODE_BYPASS__PRE                                       0x0
#define     SIO_CC_PLL_MODE_BYPASS_OHW                                      0x0
#define     SIO_CC_PLL_MODE_BYPASS_OFF                                      0x10
#define     SIO_CC_PLL_MODE_BYPASS_ON                                       0x20

#define SIO_CC_PLL_TEST__A                                                  0x450011
#define SIO_CC_PLL_TEST__W                                                  8
#define SIO_CC_PLL_TEST__M                                                  0xFF
#define SIO_CC_PLL_TEST__PRE                                                0x0

#define SIO_CC_PLL_LOCK__A                                                  0x450012
#define SIO_CC_PLL_LOCK__W                                                  1
#define SIO_CC_PLL_LOCK__M                                                  0x1
#define SIO_CC_PLL_LOCK__PRE                                                0x0
#define SIO_CC_CLK_MODE__A                                                  0x450014
#define SIO_CC_CLK_MODE__W                                                  5
#define SIO_CC_CLK_MODE__M                                                  0x1F
#define SIO_CC_CLK_MODE__PRE                                                0x0

#define   SIO_CC_CLK_MODE_DELAY__B                                          0
#define   SIO_CC_CLK_MODE_DELAY__W                                          4
#define   SIO_CC_CLK_MODE_DELAY__M                                          0xF
#define   SIO_CC_CLK_MODE_DELAY__PRE                                        0x0

#define   SIO_CC_CLK_MODE_INVERT__B                                         4
#define   SIO_CC_CLK_MODE_INVERT__W                                         1
#define   SIO_CC_CLK_MODE_INVERT__M                                         0x10
#define   SIO_CC_CLK_MODE_INVERT__PRE                                       0x0

#define SIO_CC_PWD_MODE__A                                                  0x450015
#define SIO_CC_PWD_MODE__W                                                  3
#define SIO_CC_PWD_MODE__M                                                  0x7
#define SIO_CC_PWD_MODE__PRE                                                0x0

#define   SIO_CC_PWD_MODE_LEVEL__B                                          0
#define   SIO_CC_PWD_MODE_LEVEL__W                                          2
#define   SIO_CC_PWD_MODE_LEVEL__M                                          0x3
#define   SIO_CC_PWD_MODE_LEVEL__PRE                                        0x0
#define     SIO_CC_PWD_MODE_LEVEL_NONE                                      0x0
#define     SIO_CC_PWD_MODE_LEVEL_CLOCK                                     0x1
#define     SIO_CC_PWD_MODE_LEVEL_PLL                                       0x2
#define     SIO_CC_PWD_MODE_LEVEL_OSC                                       0x3

#define   SIO_CC_PWD_MODE_USE_LOCK__B                                       2
#define   SIO_CC_PWD_MODE_USE_LOCK__W                                       1
#define   SIO_CC_PWD_MODE_USE_LOCK__M                                       0x4
#define   SIO_CC_PWD_MODE_USE_LOCK__PRE                                     0x0

#define SIO_CC_SOFT_RST__A                                                  0x450016
#define SIO_CC_SOFT_RST__W                                                  2
#define SIO_CC_SOFT_RST__M                                                  0x3
#define SIO_CC_SOFT_RST__PRE                                                0x0

#define   SIO_CC_SOFT_RST_SYS__B                                            0
#define   SIO_CC_SOFT_RST_SYS__W                                            1
#define   SIO_CC_SOFT_RST_SYS__M                                            0x1
#define   SIO_CC_SOFT_RST_SYS__PRE                                          0x0

#define   SIO_CC_SOFT_RST_OSC__B                                            1
#define   SIO_CC_SOFT_RST_OSC__W                                            1
#define   SIO_CC_SOFT_RST_OSC__M                                            0x2
#define   SIO_CC_SOFT_RST_OSC__PRE                                          0x0

#define SIO_CC_UPDATE__A                                                    0x450017
#define SIO_CC_UPDATE__W                                                    16
#define SIO_CC_UPDATE__M                                                    0xFFFF
#define SIO_CC_UPDATE__PRE                                                  0x0
#define   SIO_CC_UPDATE_KEY                                                 0xFABA

#define SIO_SA_COMM_EXEC__A                                                 0x460000
#define SIO_SA_COMM_EXEC__W                                                 2
#define SIO_SA_COMM_EXEC__M                                                 0x3
#define SIO_SA_COMM_EXEC__PRE                                               0x0
#define   SIO_SA_COMM_EXEC_STOP                                             0x0
#define   SIO_SA_COMM_EXEC_ACTIVE                                           0x1
#define   SIO_SA_COMM_EXEC_HOLD                                             0x2

#define SIO_SA_COMM_INT_REQ__A                                              0x460003
#define SIO_SA_COMM_INT_REQ__W                                              1
#define SIO_SA_COMM_INT_REQ__M                                              0x1
#define SIO_SA_COMM_INT_REQ__PRE                                            0x0
#define SIO_SA_COMM_INT_STA__A                                              0x460005
#define SIO_SA_COMM_INT_STA__W                                              4
#define SIO_SA_COMM_INT_STA__M                                              0xF
#define SIO_SA_COMM_INT_STA__PRE                                            0x0

#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__B                             0
#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__W                             1
#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__M                             0x1
#define   SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE                           0x0

#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B                          1
#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W                          1
#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M                          0x2
#define   SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE                        0x0

#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__B                             2
#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__W                             1
#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__M                             0x4
#define   SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE                           0x0

#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B                           3
#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W                           1
#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M                           0x8
#define   SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE                         0x0

#define SIO_SA_COMM_INT_MSK__A                                              0x460006
#define SIO_SA_COMM_INT_MSK__W                                              4
#define SIO_SA_COMM_INT_MSK__M                                              0xF
#define SIO_SA_COMM_INT_MSK__PRE                                            0x0

#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B                            0
#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M                            0x1
#define   SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B                         1
#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W                         1
#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M                         0x2
#define   SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE                       0x0

#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B                            2
#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M                            0x4
#define   SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B                          3
#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W                          1
#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M                          0x8
#define   SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE                        0x0

#define SIO_SA_COMM_INT_STM__A                                              0x460007
#define SIO_SA_COMM_INT_STM__W                                              4
#define SIO_SA_COMM_INT_STM__M                                              0xF
#define SIO_SA_COMM_INT_STM__PRE                                            0x0

#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B                            0
#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M                            0x1
#define   SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B                         1
#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W                         1
#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M                         0x2
#define   SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE                       0x0

#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B                            2
#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W                            1
#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M                            0x4
#define   SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE                          0x0

#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B                          3
#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W                          1
#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M                          0x8
#define   SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE                        0x0

#define SIO_SA_PRESCALER__A                                                 0x460010
#define SIO_SA_PRESCALER__W                                                 13
#define SIO_SA_PRESCALER__M                                                 0x1FFF
#define SIO_SA_PRESCALER__PRE                                               0x18B7
#define SIO_SA_TX_DATA0__A                                                  0x460011
#define SIO_SA_TX_DATA0__W                                                  16
#define SIO_SA_TX_DATA0__M                                                  0xFFFF
#define SIO_SA_TX_DATA0__PRE                                                0x0
#define SIO_SA_TX_DATA1__A                                                  0x460012
#define SIO_SA_TX_DATA1__W                                                  16
#define SIO_SA_TX_DATA1__M                                                  0xFFFF
#define SIO_SA_TX_DATA1__PRE                                                0x0
#define SIO_SA_TX_DATA2__A                                                  0x460013
#define SIO_SA_TX_DATA2__W                                                  16
#define SIO_SA_TX_DATA2__M                                                  0xFFFF
#define SIO_SA_TX_DATA2__PRE                                                0x0
#define SIO_SA_TX_DATA3__A                                                  0x460014
#define SIO_SA_TX_DATA3__W                                                  16
#define SIO_SA_TX_DATA3__M                                                  0xFFFF
#define SIO_SA_TX_DATA3__PRE                                                0x0
#define SIO_SA_TX_LENGTH__A                                                 0x460015
#define SIO_SA_TX_LENGTH__W                                                 6
#define SIO_SA_TX_LENGTH__M                                                 0x3F
#define SIO_SA_TX_LENGTH__PRE                                               0x0
#define SIO_SA_TX_COMMAND__A                                                0x460016
#define SIO_SA_TX_COMMAND__W                                                2
#define SIO_SA_TX_COMMAND__M                                                0x3
#define SIO_SA_TX_COMMAND__PRE                                              0x3

#define   SIO_SA_TX_COMMAND_TX_INVERT__B                                    0
#define   SIO_SA_TX_COMMAND_TX_INVERT__W                                    1
#define   SIO_SA_TX_COMMAND_TX_INVERT__M                                    0x1
#define   SIO_SA_TX_COMMAND_TX_INVERT__PRE                                  0x1

#define   SIO_SA_TX_COMMAND_TX_ENABLE__B                                    1
#define   SIO_SA_TX_COMMAND_TX_ENABLE__W                                    1
#define   SIO_SA_TX_COMMAND_TX_ENABLE__M                                    0x2
#define   SIO_SA_TX_COMMAND_TX_ENABLE__PRE                                  0x2

#define SIO_SA_TX_STATUS__A                                                 0x460017
#define SIO_SA_TX_STATUS__W                                                 2
#define SIO_SA_TX_STATUS__M                                                 0x3
#define SIO_SA_TX_STATUS__PRE                                               0x0

#define   SIO_SA_TX_STATUS_BUSY__B                                          0
#define   SIO_SA_TX_STATUS_BUSY__W                                          1
#define   SIO_SA_TX_STATUS_BUSY__M                                          0x1
#define   SIO_SA_TX_STATUS_BUSY__PRE                                        0x0

#define   SIO_SA_TX_STATUS_BUFF_FULL__B                                     1
#define   SIO_SA_TX_STATUS_BUFF_FULL__W                                     1
#define   SIO_SA_TX_STATUS_BUFF_FULL__M                                     0x2
#define   SIO_SA_TX_STATUS_BUFF_FULL__PRE                                   0x0

#define SIO_SA_RX_DATA0__A                                                  0x460018
#define SIO_SA_RX_DATA0__W                                                  16
#define SIO_SA_RX_DATA0__M                                                  0xFFFF
#define SIO_SA_RX_DATA0__PRE                                                0x0
#define SIO_SA_RX_DATA1__A                                                  0x460019
#define SIO_SA_RX_DATA1__W                                                  16
#define SIO_SA_RX_DATA1__M                                                  0xFFFF
#define SIO_SA_RX_DATA1__PRE                                                0x0
#define SIO_SA_RX_LENGTH__A                                                 0x46001A
#define SIO_SA_RX_LENGTH__W                                                 6
#define SIO_SA_RX_LENGTH__M                                                 0x3F
#define SIO_SA_RX_LENGTH__PRE                                               0x0
#define SIO_SA_RX_COMMAND__A                                                0x46001B
#define SIO_SA_RX_COMMAND__W                                                1
#define SIO_SA_RX_COMMAND__M                                                0x1
#define SIO_SA_RX_COMMAND__PRE                                              0x1

#define   SIO_SA_RX_COMMAND_RX_INVERT__B                                    0
#define   SIO_SA_RX_COMMAND_RX_INVERT__W                                    1
#define   SIO_SA_RX_COMMAND_RX_INVERT__M                                    0x1
#define   SIO_SA_RX_COMMAND_RX_INVERT__PRE                                  0x1

#define SIO_SA_RX_STATUS__A                                                 0x46001C
#define SIO_SA_RX_STATUS__W                                                 2
#define SIO_SA_RX_STATUS__M                                                 0x3
#define SIO_SA_RX_STATUS__PRE                                               0x0

#define   SIO_SA_RX_STATUS_BUSY__B                                          0
#define   SIO_SA_RX_STATUS_BUSY__W                                          1
#define   SIO_SA_RX_STATUS_BUSY__M                                          0x1
#define   SIO_SA_RX_STATUS_BUSY__PRE                                        0x0

#define   SIO_SA_RX_STATUS_BUFF_FULL__B                                     1
#define   SIO_SA_RX_STATUS_BUFF_FULL__W                                     1
#define   SIO_SA_RX_STATUS_BUFF_FULL__M                                     0x2
#define   SIO_SA_RX_STATUS_BUFF_FULL__PRE                                   0x0

#define SIO_PDR_COMM_EXEC__A                                                0x7F0000
#define SIO_PDR_COMM_EXEC__W                                                2
#define SIO_PDR_COMM_EXEC__M                                                0x3
#define SIO_PDR_COMM_EXEC__PRE                                              0x0
#define   SIO_PDR_COMM_EXEC_STOP                                            0x0
#define   SIO_PDR_COMM_EXEC_ACTIVE                                          0x1
#define   SIO_PDR_COMM_EXEC_HOLD                                            0x2

#define SIO_PDR_MON_CFG__A                                                  0x7F0010
#define SIO_PDR_MON_CFG__W                                                  2
#define SIO_PDR_MON_CFG__M                                                  0x3
#define SIO_PDR_MON_CFG__PRE                                                0x0

#define   SIO_PDR_MON_CFG_OSEL__B                                           0
#define   SIO_PDR_MON_CFG_OSEL__W                                           1
#define   SIO_PDR_MON_CFG_OSEL__M                                           0x1
#define   SIO_PDR_MON_CFG_OSEL__PRE                                         0x0

#define   SIO_PDR_MON_CFG_IACT__B                                           1
#define   SIO_PDR_MON_CFG_IACT__W                                           1
#define   SIO_PDR_MON_CFG_IACT__M                                           0x2
#define   SIO_PDR_MON_CFG_IACT__PRE                                         0x0

#define SIO_PDR_FDB_CFG__A                                                  0x7F0011
#define SIO_PDR_FDB_CFG__W                                                  2
#define SIO_PDR_FDB_CFG__M                                                  0x3
#define SIO_PDR_FDB_CFG__PRE                                                0x0
#define   SIO_PDR_FDB_CFG_SEL__B                                            0
#define   SIO_PDR_FDB_CFG_SEL__W                                            2
#define   SIO_PDR_FDB_CFG_SEL__M                                            0x3
#define   SIO_PDR_FDB_CFG_SEL__PRE                                          0x0

#define SIO_PDR_SMA_RX_SEL__A                                               0x7F0012
#define SIO_PDR_SMA_RX_SEL__W                                               4
#define SIO_PDR_SMA_RX_SEL__M                                               0xF
#define SIO_PDR_SMA_RX_SEL__PRE                                             0x0
#define   SIO_PDR_SMA_RX_SEL_SEL__B                                         0
#define   SIO_PDR_SMA_RX_SEL_SEL__W                                         4
#define   SIO_PDR_SMA_RX_SEL_SEL__M                                         0xF
#define   SIO_PDR_SMA_RX_SEL_SEL__PRE                                       0x0

#define SIO_PDR_SMA_TX_SILENT__A                                            0x7F0013
#define SIO_PDR_SMA_TX_SILENT__W                                            1
#define SIO_PDR_SMA_TX_SILENT__M                                            0x1
#define SIO_PDR_SMA_TX_SILENT__PRE                                          0x0
#define SIO_PDR_UIO_IN_LO__A                                                0x7F0014
#define SIO_PDR_UIO_IN_LO__W                                                16
#define SIO_PDR_UIO_IN_LO__M                                                0xFFFF
#define SIO_PDR_UIO_IN_LO__PRE                                              0x0
#define   SIO_PDR_UIO_IN_LO_DATA__B                                         0
#define   SIO_PDR_UIO_IN_LO_DATA__W                                         16
#define   SIO_PDR_UIO_IN_LO_DATA__M                                         0xFFFF
#define   SIO_PDR_UIO_IN_LO_DATA__PRE                                       0x0

#define SIO_PDR_UIO_IN_HI__A                                                0x7F0015
#define SIO_PDR_UIO_IN_HI__W                                                14
#define SIO_PDR_UIO_IN_HI__M                                                0x3FFF
#define SIO_PDR_UIO_IN_HI__PRE                                              0x0
#define   SIO_PDR_UIO_IN_HI_DATA__B                                         0
#define   SIO_PDR_UIO_IN_HI_DATA__W                                         14
#define   SIO_PDR_UIO_IN_HI_DATA__M                                         0x3FFF
#define   SIO_PDR_UIO_IN_HI_DATA__PRE                                       0x0

#define SIO_PDR_UIO_OUT_LO__A                                               0x7F0016
#define SIO_PDR_UIO_OUT_LO__W                                               16
#define SIO_PDR_UIO_OUT_LO__M                                               0xFFFF
#define SIO_PDR_UIO_OUT_LO__PRE                                             0x0
#define   SIO_PDR_UIO_OUT_LO_DATA__B                                        0
#define   SIO_PDR_UIO_OUT_LO_DATA__W                                        16
#define   SIO_PDR_UIO_OUT_LO_DATA__M                                        0xFFFF
#define   SIO_PDR_UIO_OUT_LO_DATA__PRE                                      0x0

#define SIO_PDR_UIO_OUT_HI__A                                               0x7F0017
#define SIO_PDR_UIO_OUT_HI__W                                               14
#define SIO_PDR_UIO_OUT_HI__M                                               0x3FFF
#define SIO_PDR_UIO_OUT_HI__PRE                                             0x0
#define   SIO_PDR_UIO_OUT_HI_DATA__B                                        0
#define   SIO_PDR_UIO_OUT_HI_DATA__W                                        14
#define   SIO_PDR_UIO_OUT_HI_DATA__M                                        0x3FFF
#define   SIO_PDR_UIO_OUT_HI_DATA__PRE                                      0x0

#define SIO_PDR_PWM1_MODE__A                                                0x7F0018
#define SIO_PDR_PWM1_MODE__W                                                2
#define SIO_PDR_PWM1_MODE__M                                                0x3
#define SIO_PDR_PWM1_MODE__PRE                                              0x0
#define SIO_PDR_PWM1_PRESCALE__A                                            0x7F0019
#define SIO_PDR_PWM1_PRESCALE__W                                            6
#define SIO_PDR_PWM1_PRESCALE__M                                            0x3F
#define SIO_PDR_PWM1_PRESCALE__PRE                                          0x0
#define SIO_PDR_PWM1_VALUE__A                                               0x7F001A
#define SIO_PDR_PWM1_VALUE__W                                               11
#define SIO_PDR_PWM1_VALUE__M                                               0x7FF
#define SIO_PDR_PWM1_VALUE__PRE                                             0x0
#define SIO_PDR_PWM2_MODE__A                                                0x7F001C
#define SIO_PDR_PWM2_MODE__W                                                2
#define SIO_PDR_PWM2_MODE__M                                                0x3
#define SIO_PDR_PWM2_MODE__PRE                                              0x0
#define SIO_PDR_PWM2_PRESCALE__A                                            0x7F001D
#define SIO_PDR_PWM2_PRESCALE__W                                            6
#define SIO_PDR_PWM2_PRESCALE__M                                            0x3F
#define SIO_PDR_PWM2_PRESCALE__PRE                                          0x0
#define SIO_PDR_PWM2_VALUE__A                                               0x7F001E
#define SIO_PDR_PWM2_VALUE__W                                               11
#define SIO_PDR_PWM2_VALUE__M                                               0x7FF
#define SIO_PDR_PWM2_VALUE__PRE                                             0x0
#define SIO_PDR_OHW_CFG__A                                                  0x7F001F
#define SIO_PDR_OHW_CFG__W                                                  7
#define SIO_PDR_OHW_CFG__M                                                  0x7F
#define SIO_PDR_OHW_CFG__PRE                                                0x0

#define   SIO_PDR_OHW_CFG_FREF_SEL__B                                       0
#define   SIO_PDR_OHW_CFG_FREF_SEL__W                                       2
#define   SIO_PDR_OHW_CFG_FREF_SEL__M                                       0x3
#define   SIO_PDR_OHW_CFG_FREF_SEL__PRE                                     0x0

#define   SIO_PDR_OHW_CFG_BYPASS__B                                         2
#define   SIO_PDR_OHW_CFG_BYPASS__W                                         1
#define   SIO_PDR_OHW_CFG_BYPASS__M                                         0x4
#define   SIO_PDR_OHW_CFG_BYPASS__PRE                                       0x0

#define   SIO_PDR_OHW_CFG_ASEL__B                                           3
#define   SIO_PDR_OHW_CFG_ASEL__W                                           3
#define   SIO_PDR_OHW_CFG_ASEL__M                                           0x38
#define   SIO_PDR_OHW_CFG_ASEL__PRE                                         0x0

#define   SIO_PDR_OHW_CFG_SPEED__B                                          6
#define   SIO_PDR_OHW_CFG_SPEED__W                                          1
#define   SIO_PDR_OHW_CFG_SPEED__M                                          0x40
#define   SIO_PDR_OHW_CFG_SPEED__PRE                                        0x0

#define SIO_PDR_I2S_WS_CFG__A                                               0x7F0020
#define SIO_PDR_I2S_WS_CFG__W                                               9
#define SIO_PDR_I2S_WS_CFG__M                                               0x1FF
#define SIO_PDR_I2S_WS_CFG__PRE                                             0x10
#define   SIO_PDR_I2S_WS_CFG_MODE__B                                        0
#define   SIO_PDR_I2S_WS_CFG_MODE__W                                        3
#define   SIO_PDR_I2S_WS_CFG_MODE__M                                        0x7
#define   SIO_PDR_I2S_WS_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_I2S_WS_CFG_DRIVE__B                                       3
#define   SIO_PDR_I2S_WS_CFG_DRIVE__W                                       3
#define   SIO_PDR_I2S_WS_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_I2S_WS_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_I2S_WS_CFG_KEEP__B                                        6
#define   SIO_PDR_I2S_WS_CFG_KEEP__W                                        2
#define   SIO_PDR_I2S_WS_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_I2S_WS_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_I2S_WS_CFG_UIO__B                                         8
#define   SIO_PDR_I2S_WS_CFG_UIO__W                                         1
#define   SIO_PDR_I2S_WS_CFG_UIO__M                                         0x100
#define   SIO_PDR_I2S_WS_CFG_UIO__PRE                                       0x0

#define SIO_PDR_GPIO_CFG__A                                                 0x7F0021
#define SIO_PDR_GPIO_CFG__W                                                 9
#define SIO_PDR_GPIO_CFG__M                                                 0x1FF
#define SIO_PDR_GPIO_CFG__PRE                                               0x10
#define   SIO_PDR_GPIO_CFG_MODE__B                                          0
#define   SIO_PDR_GPIO_CFG_MODE__W                                          3
#define   SIO_PDR_GPIO_CFG_MODE__M                                          0x7
#define   SIO_PDR_GPIO_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_GPIO_CFG_DRIVE__B                                         3
#define   SIO_PDR_GPIO_CFG_DRIVE__W                                         3
#define   SIO_PDR_GPIO_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_GPIO_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_GPIO_CFG_KEEP__B                                          6
#define   SIO_PDR_GPIO_CFG_KEEP__W                                          2
#define   SIO_PDR_GPIO_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_GPIO_CFG_KEEP__PRE                                        0x0
#define   SIO_PDR_GPIO_CFG_UIO__B                                           8
#define   SIO_PDR_GPIO_CFG_UIO__W                                           1
#define   SIO_PDR_GPIO_CFG_UIO__M                                           0x100
#define   SIO_PDR_GPIO_CFG_UIO__PRE                                         0x0

#define SIO_PDR_IRQN_CFG__A                                                 0x7F0022
#define SIO_PDR_IRQN_CFG__W                                                 9
#define SIO_PDR_IRQN_CFG__M                                                 0x1FF
#define SIO_PDR_IRQN_CFG__PRE                                               0x10
#define   SIO_PDR_IRQN_CFG_MODE__B                                          0
#define   SIO_PDR_IRQN_CFG_MODE__W                                          3
#define   SIO_PDR_IRQN_CFG_MODE__M                                          0x7
#define   SIO_PDR_IRQN_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_IRQN_CFG_DRIVE__B                                         3
#define   SIO_PDR_IRQN_CFG_DRIVE__W                                         3
#define   SIO_PDR_IRQN_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_IRQN_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_IRQN_CFG_KEEP__B                                          6
#define   SIO_PDR_IRQN_CFG_KEEP__W                                          2
#define   SIO_PDR_IRQN_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_IRQN_CFG_KEEP__PRE                                        0x0
#define   SIO_PDR_IRQN_CFG_UIO__B                                           8
#define   SIO_PDR_IRQN_CFG_UIO__W                                           1
#define   SIO_PDR_IRQN_CFG_UIO__M                                           0x100
#define   SIO_PDR_IRQN_CFG_UIO__PRE                                         0x0

#define SIO_PDR_OOB_CRX_CFG__A                                              0x7F0023
#define SIO_PDR_OOB_CRX_CFG__W                                              9
#define SIO_PDR_OOB_CRX_CFG__M                                              0x1FF
#define SIO_PDR_OOB_CRX_CFG__PRE                                            0x10
#define   SIO_PDR_OOB_CRX_CFG_MODE__B                                       0
#define   SIO_PDR_OOB_CRX_CFG_MODE__W                                       3
#define   SIO_PDR_OOB_CRX_CFG_MODE__M                                       0x7
#define   SIO_PDR_OOB_CRX_CFG_MODE__PRE                                     0x0
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__B                                      3
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__W                                      3
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__M                                      0x38
#define   SIO_PDR_OOB_CRX_CFG_DRIVE__PRE                                    0x10
#define   SIO_PDR_OOB_CRX_CFG_KEEP__B                                       6
#define   SIO_PDR_OOB_CRX_CFG_KEEP__W                                       2
#define   SIO_PDR_OOB_CRX_CFG_KEEP__M                                       0xC0
#define   SIO_PDR_OOB_CRX_CFG_KEEP__PRE                                     0x0
#define   SIO_PDR_OOB_CRX_CFG_UIO__B                                        8
#define   SIO_PDR_OOB_CRX_CFG_UIO__W                                        1
#define   SIO_PDR_OOB_CRX_CFG_UIO__M                                        0x100
#define   SIO_PDR_OOB_CRX_CFG_UIO__PRE                                      0x0

#define SIO_PDR_OOB_DRX_CFG__A                                              0x7F0024
#define SIO_PDR_OOB_DRX_CFG__W                                              9
#define SIO_PDR_OOB_DRX_CFG__M                                              0x1FF
#define SIO_PDR_OOB_DRX_CFG__PRE                                            0x10
#define   SIO_PDR_OOB_DRX_CFG_MODE__B                                       0
#define   SIO_PDR_OOB_DRX_CFG_MODE__W                                       3
#define   SIO_PDR_OOB_DRX_CFG_MODE__M                                       0x7
#define   SIO_PDR_OOB_DRX_CFG_MODE__PRE                                     0x0
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__B                                      3
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__W                                      3
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__M                                      0x38
#define   SIO_PDR_OOB_DRX_CFG_DRIVE__PRE                                    0x10
#define   SIO_PDR_OOB_DRX_CFG_KEEP__B                                       6
#define   SIO_PDR_OOB_DRX_CFG_KEEP__W                                       2
#define   SIO_PDR_OOB_DRX_CFG_KEEP__M                                       0xC0
#define   SIO_PDR_OOB_DRX_CFG_KEEP__PRE                                     0x0
#define   SIO_PDR_OOB_DRX_CFG_UIO__B                                        8
#define   SIO_PDR_OOB_DRX_CFG_UIO__W                                        1
#define   SIO_PDR_OOB_DRX_CFG_UIO__M                                        0x100
#define   SIO_PDR_OOB_DRX_CFG_UIO__PRE                                      0x0

#define SIO_PDR_MSTRT_CFG__A                                                0x7F0025
#define SIO_PDR_MSTRT_CFG__W                                                9
#define SIO_PDR_MSTRT_CFG__M                                                0x1FF
#define SIO_PDR_MSTRT_CFG__PRE                                              0x50
#define   SIO_PDR_MSTRT_CFG_MODE__B                                         0
#define   SIO_PDR_MSTRT_CFG_MODE__W                                         3
#define   SIO_PDR_MSTRT_CFG_MODE__M                                         0x7
#define   SIO_PDR_MSTRT_CFG_MODE__PRE                                       0x0
#define   SIO_PDR_MSTRT_CFG_DRIVE__B                                        3
#define   SIO_PDR_MSTRT_CFG_DRIVE__W                                        3
#define   SIO_PDR_MSTRT_CFG_DRIVE__M                                        0x38
#define   SIO_PDR_MSTRT_CFG_DRIVE__PRE                                      0x10
#define   SIO_PDR_MSTRT_CFG_KEEP__B                                         6
#define   SIO_PDR_MSTRT_CFG_KEEP__W                                         2
#define   SIO_PDR_MSTRT_CFG_KEEP__M                                         0xC0
#define   SIO_PDR_MSTRT_CFG_KEEP__PRE                                       0x40
#define   SIO_PDR_MSTRT_CFG_UIO__B                                          8
#define   SIO_PDR_MSTRT_CFG_UIO__W                                          1
#define   SIO_PDR_MSTRT_CFG_UIO__M                                          0x100
#define   SIO_PDR_MSTRT_CFG_UIO__PRE                                        0x0

#define SIO_PDR_MERR_CFG__A                                                 0x7F0026
#define SIO_PDR_MERR_CFG__W                                                 9
#define SIO_PDR_MERR_CFG__M                                                 0x1FF
#define SIO_PDR_MERR_CFG__PRE                                               0x50
#define   SIO_PDR_MERR_CFG_MODE__B                                          0
#define   SIO_PDR_MERR_CFG_MODE__W                                          3
#define   SIO_PDR_MERR_CFG_MODE__M                                          0x7
#define   SIO_PDR_MERR_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_MERR_CFG_DRIVE__B                                         3
#define   SIO_PDR_MERR_CFG_DRIVE__W                                         3
#define   SIO_PDR_MERR_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_MERR_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_MERR_CFG_KEEP__B                                          6
#define   SIO_PDR_MERR_CFG_KEEP__W                                          2
#define   SIO_PDR_MERR_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_MERR_CFG_KEEP__PRE                                        0x40
#define   SIO_PDR_MERR_CFG_UIO__B                                           8
#define   SIO_PDR_MERR_CFG_UIO__W                                           1
#define   SIO_PDR_MERR_CFG_UIO__M                                           0x100
#define   SIO_PDR_MERR_CFG_UIO__PRE                                         0x0

#define SIO_PDR_MCLK_CFG__A                                                 0x7F0028
#define SIO_PDR_MCLK_CFG__W                                                 9
#define SIO_PDR_MCLK_CFG__M                                                 0x1FF
#define SIO_PDR_MCLK_CFG__PRE                                               0x50
#define   SIO_PDR_MCLK_CFG_MODE__B                                          0
#define   SIO_PDR_MCLK_CFG_MODE__W                                          3
#define   SIO_PDR_MCLK_CFG_MODE__M                                          0x7
#define   SIO_PDR_MCLK_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_MCLK_CFG_DRIVE__B                                         3
#define   SIO_PDR_MCLK_CFG_DRIVE__W                                         3
#define   SIO_PDR_MCLK_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_MCLK_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_MCLK_CFG_KEEP__B                                          6
#define   SIO_PDR_MCLK_CFG_KEEP__W                                          2
#define   SIO_PDR_MCLK_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_MCLK_CFG_KEEP__PRE                                        0x40
#define   SIO_PDR_MCLK_CFG_UIO__B                                           8
#define   SIO_PDR_MCLK_CFG_UIO__W                                           1
#define   SIO_PDR_MCLK_CFG_UIO__M                                           0x100
#define   SIO_PDR_MCLK_CFG_UIO__PRE                                         0x0

#define SIO_PDR_MVAL_CFG__A                                                 0x7F0029
#define SIO_PDR_MVAL_CFG__W                                                 9
#define SIO_PDR_MVAL_CFG__M                                                 0x1FF
#define SIO_PDR_MVAL_CFG__PRE                                               0x50
#define   SIO_PDR_MVAL_CFG_MODE__B                                          0
#define   SIO_PDR_MVAL_CFG_MODE__W                                          3
#define   SIO_PDR_MVAL_CFG_MODE__M                                          0x7
#define   SIO_PDR_MVAL_CFG_MODE__PRE                                        0x0
#define   SIO_PDR_MVAL_CFG_DRIVE__B                                         3
#define   SIO_PDR_MVAL_CFG_DRIVE__W                                         3
#define   SIO_PDR_MVAL_CFG_DRIVE__M                                         0x38
#define   SIO_PDR_MVAL_CFG_DRIVE__PRE                                       0x10
#define   SIO_PDR_MVAL_CFG_KEEP__B                                          6
#define   SIO_PDR_MVAL_CFG_KEEP__W                                          2
#define   SIO_PDR_MVAL_CFG_KEEP__M                                          0xC0
#define   SIO_PDR_MVAL_CFG_KEEP__PRE                                        0x40
#define   SIO_PDR_MVAL_CFG_UIO__B                                           8
#define   SIO_PDR_MVAL_CFG_UIO__W                                           1
#define   SIO_PDR_MVAL_CFG_UIO__M                                           0x100
#define   SIO_PDR_MVAL_CFG_UIO__PRE                                         0x0

#define SIO_PDR_MD0_CFG__A                                                  0x7F002A
#define SIO_PDR_MD0_CFG__W                                                  9
#define SIO_PDR_MD0_CFG__M                                                  0x1FF
#define SIO_PDR_MD0_CFG__PRE                                                0x50
#define   SIO_PDR_MD0_CFG_MODE__B                                           0
#define   SIO_PDR_MD0_CFG_MODE__W                                           3
#define   SIO_PDR_MD0_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD0_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD0_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD0_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD0_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD0_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD0_CFG_KEEP__B                                           6
#define   SIO_PDR_MD0_CFG_KEEP__W                                           2
#define   SIO_PDR_MD0_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD0_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD0_CFG_UIO__B                                            8
#define   SIO_PDR_MD0_CFG_UIO__W                                            1
#define   SIO_PDR_MD0_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD0_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD1_CFG__A                                                  0x7F002B
#define SIO_PDR_MD1_CFG__W                                                  9
#define SIO_PDR_MD1_CFG__M                                                  0x1FF
#define SIO_PDR_MD1_CFG__PRE                                                0x50
#define   SIO_PDR_MD1_CFG_MODE__B                                           0
#define   SIO_PDR_MD1_CFG_MODE__W                                           3
#define   SIO_PDR_MD1_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD1_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD1_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD1_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD1_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD1_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD1_CFG_KEEP__B                                           6
#define   SIO_PDR_MD1_CFG_KEEP__W                                           2
#define   SIO_PDR_MD1_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD1_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD1_CFG_UIO__B                                            8
#define   SIO_PDR_MD1_CFG_UIO__W                                            1
#define   SIO_PDR_MD1_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD1_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD2_CFG__A                                                  0x7F002C
#define SIO_PDR_MD2_CFG__W                                                  9
#define SIO_PDR_MD2_CFG__M                                                  0x1FF
#define SIO_PDR_MD2_CFG__PRE                                                0x50
#define   SIO_PDR_MD2_CFG_MODE__B                                           0
#define   SIO_PDR_MD2_CFG_MODE__W                                           3
#define   SIO_PDR_MD2_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD2_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD2_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD2_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD2_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD2_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD2_CFG_KEEP__B                                           6
#define   SIO_PDR_MD2_CFG_KEEP__W                                           2
#define   SIO_PDR_MD2_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD2_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD2_CFG_UIO__B                                            8
#define   SIO_PDR_MD2_CFG_UIO__W                                            1
#define   SIO_PDR_MD2_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD2_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD3_CFG__A                                                  0x7F002D
#define SIO_PDR_MD3_CFG__W                                                  9
#define SIO_PDR_MD3_CFG__M                                                  0x1FF
#define SIO_PDR_MD3_CFG__PRE                                                0x50
#define   SIO_PDR_MD3_CFG_MODE__B                                           0
#define   SIO_PDR_MD3_CFG_MODE__W                                           3
#define   SIO_PDR_MD3_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD3_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD3_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD3_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD3_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD3_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD3_CFG_KEEP__B                                           6
#define   SIO_PDR_MD3_CFG_KEEP__W                                           2
#define   SIO_PDR_MD3_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD3_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD3_CFG_UIO__B                                            8
#define   SIO_PDR_MD3_CFG_UIO__W                                            1
#define   SIO_PDR_MD3_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD3_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD4_CFG__A                                                  0x7F002F
#define SIO_PDR_MD4_CFG__W                                                  9
#define SIO_PDR_MD4_CFG__M                                                  0x1FF
#define SIO_PDR_MD4_CFG__PRE                                                0x50
#define   SIO_PDR_MD4_CFG_MODE__B                                           0
#define   SIO_PDR_MD4_CFG_MODE__W                                           3
#define   SIO_PDR_MD4_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD4_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD4_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD4_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD4_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD4_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD4_CFG_KEEP__B                                           6
#define   SIO_PDR_MD4_CFG_KEEP__W                                           2
#define   SIO_PDR_MD4_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD4_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD4_CFG_UIO__B                                            8
#define   SIO_PDR_MD4_CFG_UIO__W                                            1
#define   SIO_PDR_MD4_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD4_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD5_CFG__A                                                  0x7F0030
#define SIO_PDR_MD5_CFG__W                                                  9
#define SIO_PDR_MD5_CFG__M                                                  0x1FF
#define SIO_PDR_MD5_CFG__PRE                                                0x50
#define   SIO_PDR_MD5_CFG_MODE__B                                           0
#define   SIO_PDR_MD5_CFG_MODE__W                                           3
#define   SIO_PDR_MD5_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD5_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD5_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD5_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD5_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD5_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD5_CFG_KEEP__B                                           6
#define   SIO_PDR_MD5_CFG_KEEP__W                                           2
#define   SIO_PDR_MD5_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD5_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD5_CFG_UIO__B                                            8
#define   SIO_PDR_MD5_CFG_UIO__W                                            1
#define   SIO_PDR_MD5_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD5_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD6_CFG__A                                                  0x7F0031
#define SIO_PDR_MD6_CFG__W                                                  9
#define SIO_PDR_MD6_CFG__M                                                  0x1FF
#define SIO_PDR_MD6_CFG__PRE                                                0x50
#define   SIO_PDR_MD6_CFG_MODE__B                                           0
#define   SIO_PDR_MD6_CFG_MODE__W                                           3
#define   SIO_PDR_MD6_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD6_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD6_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD6_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD6_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD6_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD6_CFG_KEEP__B                                           6
#define   SIO_PDR_MD6_CFG_KEEP__W                                           2
#define   SIO_PDR_MD6_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD6_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD6_CFG_UIO__B                                            8
#define   SIO_PDR_MD6_CFG_UIO__W                                            1
#define   SIO_PDR_MD6_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD6_CFG_UIO__PRE                                          0x0

#define SIO_PDR_MD7_CFG__A                                                  0x7F0032
#define SIO_PDR_MD7_CFG__W                                                  9
#define SIO_PDR_MD7_CFG__M                                                  0x1FF
#define SIO_PDR_MD7_CFG__PRE                                                0x50
#define   SIO_PDR_MD7_CFG_MODE__B                                           0
#define   SIO_PDR_MD7_CFG_MODE__W                                           3
#define   SIO_PDR_MD7_CFG_MODE__M                                           0x7
#define   SIO_PDR_MD7_CFG_MODE__PRE                                         0x0
#define   SIO_PDR_MD7_CFG_DRIVE__B                                          3
#define   SIO_PDR_MD7_CFG_DRIVE__W                                          3
#define   SIO_PDR_MD7_CFG_DRIVE__M                                          0x38
#define   SIO_PDR_MD7_CFG_DRIVE__PRE                                        0x10
#define   SIO_PDR_MD7_CFG_KEEP__B                                           6
#define   SIO_PDR_MD7_CFG_KEEP__W                                           2
#define   SIO_PDR_MD7_CFG_KEEP__M                                           0xC0
#define   SIO_PDR_MD7_CFG_KEEP__PRE                                         0x40
#define   SIO_PDR_MD7_CFG_UIO__B                                            8
#define   SIO_PDR_MD7_CFG_UIO__W                                            1
#define   SIO_PDR_MD7_CFG_UIO__M                                            0x100
#define   SIO_PDR_MD7_CFG_UIO__PRE                                          0x0

#define SIO_PDR_I2C_SCL1_CFG__A                                             0x7F0033
#define SIO_PDR_I2C_SCL1_CFG__W                                             9
#define SIO_PDR_I2C_SCL1_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SCL1_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SCL1_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SCL1_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SCL1_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SCL1_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SCL1_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SCL1_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SCL1_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SCL1_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SCL1_CFG_UIO__PRE                                     0x0

#define SIO_PDR_I2C_SDA1_CFG__A                                             0x7F0034
#define SIO_PDR_I2C_SDA1_CFG__W                                             9
#define SIO_PDR_I2C_SDA1_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SDA1_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SDA1_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SDA1_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SDA1_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SDA1_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SDA1_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SDA1_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SDA1_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SDA1_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SDA1_CFG_UIO__PRE                                     0x0

#define SIO_PDR_VSYNC_CFG__A                                                0x7F0036
#define SIO_PDR_VSYNC_CFG__W                                                9
#define SIO_PDR_VSYNC_CFG__M                                                0x1FF
#define SIO_PDR_VSYNC_CFG__PRE                                              0x10
#define   SIO_PDR_VSYNC_CFG_MODE__B                                         0
#define   SIO_PDR_VSYNC_CFG_MODE__W                                         3
#define   SIO_PDR_VSYNC_CFG_MODE__M                                         0x7
#define   SIO_PDR_VSYNC_CFG_MODE__PRE                                       0x0
#define   SIO_PDR_VSYNC_CFG_DRIVE__B                                        3
#define   SIO_PDR_VSYNC_CFG_DRIVE__W                                        3
#define   SIO_PDR_VSYNC_CFG_DRIVE__M                                        0x38
#define   SIO_PDR_VSYNC_CFG_DRIVE__PRE                                      0x10
#define   SIO_PDR_VSYNC_CFG_KEEP__B                                         6
#define   SIO_PDR_VSYNC_CFG_KEEP__W                                         2
#define   SIO_PDR_VSYNC_CFG_KEEP__M                                         0xC0
#define   SIO_PDR_VSYNC_CFG_KEEP__PRE                                       0x0
#define   SIO_PDR_VSYNC_CFG_UIO__B                                          8
#define   SIO_PDR_VSYNC_CFG_UIO__W                                          1
#define   SIO_PDR_VSYNC_CFG_UIO__M                                          0x100
#define   SIO_PDR_VSYNC_CFG_UIO__PRE                                        0x0

#define SIO_PDR_SMA_RX_CFG__A                                               0x7F0037
#define SIO_PDR_SMA_RX_CFG__W                                               9
#define SIO_PDR_SMA_RX_CFG__M                                               0x1FF
#define SIO_PDR_SMA_RX_CFG__PRE                                             0x10
#define   SIO_PDR_SMA_RX_CFG_MODE__B                                        0
#define   SIO_PDR_SMA_RX_CFG_MODE__W                                        3
#define   SIO_PDR_SMA_RX_CFG_MODE__M                                        0x7
#define   SIO_PDR_SMA_RX_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_SMA_RX_CFG_DRIVE__B                                       3
#define   SIO_PDR_SMA_RX_CFG_DRIVE__W                                       3
#define   SIO_PDR_SMA_RX_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_SMA_RX_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_SMA_RX_CFG_KEEP__B                                        6
#define   SIO_PDR_SMA_RX_CFG_KEEP__W                                        2
#define   SIO_PDR_SMA_RX_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_SMA_RX_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_SMA_RX_CFG_UIO__B                                         8
#define   SIO_PDR_SMA_RX_CFG_UIO__W                                         1
#define   SIO_PDR_SMA_RX_CFG_UIO__M                                         0x100
#define   SIO_PDR_SMA_RX_CFG_UIO__PRE                                       0x0

#define SIO_PDR_SMA_TX_CFG__A                                               0x7F0038
#define SIO_PDR_SMA_TX_CFG__W                                               9
#define SIO_PDR_SMA_TX_CFG__M                                               0x1FF
#define SIO_PDR_SMA_TX_CFG__PRE                                             0x90
#define   SIO_PDR_SMA_TX_CFG_MODE__B                                        0
#define   SIO_PDR_SMA_TX_CFG_MODE__W                                        3
#define   SIO_PDR_SMA_TX_CFG_MODE__M                                        0x7
#define   SIO_PDR_SMA_TX_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_SMA_TX_CFG_DRIVE__B                                       3
#define   SIO_PDR_SMA_TX_CFG_DRIVE__W                                       3
#define   SIO_PDR_SMA_TX_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_SMA_TX_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_SMA_TX_CFG_KEEP__B                                        6
#define   SIO_PDR_SMA_TX_CFG_KEEP__W                                        2
#define   SIO_PDR_SMA_TX_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_SMA_TX_CFG_KEEP__PRE                                      0x80
#define   SIO_PDR_SMA_TX_CFG_UIO__B                                         8
#define   SIO_PDR_SMA_TX_CFG_UIO__W                                         1
#define   SIO_PDR_SMA_TX_CFG_UIO__M                                         0x100
#define   SIO_PDR_SMA_TX_CFG_UIO__PRE                                       0x0

#define SIO_PDR_I2C_SDA2_CFG__A                                             0x7F003F
#define SIO_PDR_I2C_SDA2_CFG__W                                             9
#define SIO_PDR_I2C_SDA2_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SDA2_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SDA2_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SDA2_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SDA2_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SDA2_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SDA2_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SDA2_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SDA2_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SDA2_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SDA2_CFG_UIO__PRE                                     0x0

#define SIO_PDR_I2C_SCL2_CFG__A                                             0x7F0040
#define SIO_PDR_I2C_SCL2_CFG__W                                             9
#define SIO_PDR_I2C_SCL2_CFG__M                                             0x1FF
#define SIO_PDR_I2C_SCL2_CFG__PRE                                           0x11
#define   SIO_PDR_I2C_SCL2_CFG_MODE__B                                      0
#define   SIO_PDR_I2C_SCL2_CFG_MODE__W                                      3
#define   SIO_PDR_I2C_SCL2_CFG_MODE__M                                      0x7
#define   SIO_PDR_I2C_SCL2_CFG_MODE__PRE                                    0x1
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__B                                     3
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__W                                     3
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__M                                     0x38
#define   SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE                                   0x10
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__B                                      6
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__W                                      2
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__M                                      0xC0
#define   SIO_PDR_I2C_SCL2_CFG_KEEP__PRE                                    0x0
#define   SIO_PDR_I2C_SCL2_CFG_UIO__B                                       8
#define   SIO_PDR_I2C_SCL2_CFG_UIO__W                                       1
#define   SIO_PDR_I2C_SCL2_CFG_UIO__M                                       0x100
#define   SIO_PDR_I2C_SCL2_CFG_UIO__PRE                                     0x0

#define SIO_PDR_I2S_CL_CFG__A                                               0x7F0041
#define SIO_PDR_I2S_CL_CFG__W                                               9
#define SIO_PDR_I2S_CL_CFG__M                                               0x1FF
#define SIO_PDR_I2S_CL_CFG__PRE                                             0x10
#define   SIO_PDR_I2S_CL_CFG_MODE__B                                        0
#define   SIO_PDR_I2S_CL_CFG_MODE__W                                        3
#define   SIO_PDR_I2S_CL_CFG_MODE__M                                        0x7
#define   SIO_PDR_I2S_CL_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_I2S_CL_CFG_DRIVE__B                                       3
#define   SIO_PDR_I2S_CL_CFG_DRIVE__W                                       3
#define   SIO_PDR_I2S_CL_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_I2S_CL_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_I2S_CL_CFG_KEEP__B                                        6
#define   SIO_PDR_I2S_CL_CFG_KEEP__W                                        2
#define   SIO_PDR_I2S_CL_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_I2S_CL_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_I2S_CL_CFG_UIO__B                                         8
#define   SIO_PDR_I2S_CL_CFG_UIO__W                                         1
#define   SIO_PDR_I2S_CL_CFG_UIO__M                                         0x100
#define   SIO_PDR_I2S_CL_CFG_UIO__PRE                                       0x0

#define SIO_PDR_I2S_DA_CFG__A                                               0x7F0042
#define SIO_PDR_I2S_DA_CFG__W                                               9
#define SIO_PDR_I2S_DA_CFG__M                                               0x1FF
#define SIO_PDR_I2S_DA_CFG__PRE                                             0x10
#define   SIO_PDR_I2S_DA_CFG_MODE__B                                        0
#define   SIO_PDR_I2S_DA_CFG_MODE__W                                        3
#define   SIO_PDR_I2S_DA_CFG_MODE__M                                        0x7
#define   SIO_PDR_I2S_DA_CFG_MODE__PRE                                      0x0
#define   SIO_PDR_I2S_DA_CFG_DRIVE__B                                       3
#define   SIO_PDR_I2S_DA_CFG_DRIVE__W                                       3
#define   SIO_PDR_I2S_DA_CFG_DRIVE__M                                       0x38
#define   SIO_PDR_I2S_DA_CFG_DRIVE__PRE                                     0x10
#define   SIO_PDR_I2S_DA_CFG_KEEP__B                                        6
#define   SIO_PDR_I2S_DA_CFG_KEEP__W                                        2
#define   SIO_PDR_I2S_DA_CFG_KEEP__M                                        0xC0
#define   SIO_PDR_I2S_DA_CFG_KEEP__PRE                                      0x0
#define   SIO_PDR_I2S_DA_CFG_UIO__B                                         8
#define   SIO_PDR_I2S_DA_CFG_UIO__W                                         1
#define   SIO_PDR_I2S_DA_CFG_UIO__M                                         0x100
#define   SIO_PDR_I2S_DA_CFG_UIO__PRE                                       0x0

#define SIO_PDR_GPIO_GPIO_FNC__A                                            0x7F0050
#define SIO_PDR_GPIO_GPIO_FNC__W                                            2
#define SIO_PDR_GPIO_GPIO_FNC__M                                            0x3
#define SIO_PDR_GPIO_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_GPIO_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_IRQN_GPIO_FNC__A                                            0x7F0051
#define SIO_PDR_IRQN_GPIO_FNC__W                                            2
#define SIO_PDR_IRQN_GPIO_FNC__M                                            0x3
#define SIO_PDR_IRQN_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_IRQN_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MSTRT_GPIO_FNC__A                                           0x7F0052
#define SIO_PDR_MSTRT_GPIO_FNC__W                                           2
#define SIO_PDR_MSTRT_GPIO_FNC__M                                           0x3
#define SIO_PDR_MSTRT_GPIO_FNC__PRE                                         0x0
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__B                                     0
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__W                                     2
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__M                                     0x3
#define   SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE                                   0x0

#define SIO_PDR_MERR_GPIO_FNC__A                                            0x7F0053
#define SIO_PDR_MERR_GPIO_FNC__W                                            2
#define SIO_PDR_MERR_GPIO_FNC__M                                            0x3
#define SIO_PDR_MERR_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_MERR_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_MERR_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_MERR_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_MERR_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MCLK_GPIO_FNC__A                                            0x7F0054
#define SIO_PDR_MCLK_GPIO_FNC__W                                            2
#define SIO_PDR_MCLK_GPIO_FNC__M                                            0x3
#define SIO_PDR_MCLK_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_MCLK_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MVAL_GPIO_FNC__A                                            0x7F0055
#define SIO_PDR_MVAL_GPIO_FNC__W                                            2
#define SIO_PDR_MVAL_GPIO_FNC__M                                            0x3
#define SIO_PDR_MVAL_GPIO_FNC__PRE                                          0x0
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__B                                      0
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__W                                      2
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__M                                      0x3
#define   SIO_PDR_MVAL_GPIO_FNC_SEL__PRE                                    0x0

#define SIO_PDR_MD0_GPIO_FNC__A                                             0x7F0056
#define SIO_PDR_MD0_GPIO_FNC__W                                             2
#define SIO_PDR_MD0_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD0_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD0_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD0_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD0_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD0_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD1_GPIO_FNC__A                                             0x7F0057
#define SIO_PDR_MD1_GPIO_FNC__W                                             2
#define SIO_PDR_MD1_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD1_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD1_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD1_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD1_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD1_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD2_GPIO_FNC__A                                             0x7F0058
#define SIO_PDR_MD2_GPIO_FNC__W                                             2
#define SIO_PDR_MD2_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD2_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD2_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD2_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD2_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD2_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD3_GPIO_FNC__A                                             0x7F0059
#define SIO_PDR_MD3_GPIO_FNC__W                                             2
#define SIO_PDR_MD3_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD3_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD3_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD3_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD3_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD3_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD4_GPIO_FNC__A                                             0x7F005A
#define SIO_PDR_MD4_GPIO_FNC__W                                             2
#define SIO_PDR_MD4_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD4_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD4_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD4_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD4_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD4_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD5_GPIO_FNC__A                                             0x7F005B
#define SIO_PDR_MD5_GPIO_FNC__W                                             2
#define SIO_PDR_MD5_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD5_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD5_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD5_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD5_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD5_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD6_GPIO_FNC__A                                             0x7F005C
#define SIO_PDR_MD6_GPIO_FNC__W                                             2
#define SIO_PDR_MD6_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD6_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD6_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD6_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD6_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD6_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_MD7_GPIO_FNC__A                                             0x7F005D
#define SIO_PDR_MD7_GPIO_FNC__W                                             2
#define SIO_PDR_MD7_GPIO_FNC__M                                             0x3
#define SIO_PDR_MD7_GPIO_FNC__PRE                                           0x0
#define   SIO_PDR_MD7_GPIO_FNC_SEL__B                                       0
#define   SIO_PDR_MD7_GPIO_FNC_SEL__W                                       2
#define   SIO_PDR_MD7_GPIO_FNC_SEL__M                                       0x3
#define   SIO_PDR_MD7_GPIO_FNC_SEL__PRE                                     0x0

#define SIO_PDR_SMA_RX_GPIO_FNC__A                                          0x7F005E
#define SIO_PDR_SMA_RX_GPIO_FNC__W                                          2
#define SIO_PDR_SMA_RX_GPIO_FNC__M                                          0x3
#define SIO_PDR_SMA_RX_GPIO_FNC__PRE                                        0x0
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__B                                    0
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__W                                    2
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__M                                    0x3
#define   SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE                                  0x0

#define SIO_PDR_SMA_TX_GPIO_FNC__A                                          0x7F005F
#define SIO_PDR_SMA_TX_GPIO_FNC__W                                          2
#define SIO_PDR_SMA_TX_GPIO_FNC__M                                          0x3
#define SIO_PDR_SMA_TX_GPIO_FNC__PRE                                        0x0
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__B                                    0
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__W                                    2
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__M                                    0x3
#define   SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE                                  0x0

#define VSB_COMM_EXEC__A                                                    0x1C00000
#define VSB_COMM_EXEC__W                                                    2
#define VSB_COMM_EXEC__M                                                    0x3
#define VSB_COMM_EXEC__PRE                                                  0x0
#define   VSB_COMM_EXEC_STOP                                                0x0
#define   VSB_COMM_EXEC_ACTIVE                                              0x1
#define   VSB_COMM_EXEC_HOLD                                                0x2

#define VSB_COMM_MB__A                                                      0x1C00002
#define VSB_COMM_MB__W                                                      16
#define VSB_COMM_MB__M                                                      0xFFFF
#define VSB_COMM_MB__PRE                                                    0x0
#define VSB_COMM_INT_REQ__A                                                 0x1C00003
#define VSB_COMM_INT_REQ__W                                                 1
#define VSB_COMM_INT_REQ__M                                                 0x1
#define VSB_COMM_INT_REQ__PRE                                               0x0

#define   VSB_COMM_INT_REQ_TOP_INT_REQ__B                                   0
#define   VSB_COMM_INT_REQ_TOP_INT_REQ__W                                   1
#define   VSB_COMM_INT_REQ_TOP_INT_REQ__M                                   0x1
#define   VSB_COMM_INT_REQ_TOP_INT_REQ__PRE                                 0x0

#define VSB_COMM_INT_STA__A                                                 0x1C00005
#define VSB_COMM_INT_STA__W                                                 16
#define VSB_COMM_INT_STA__M                                                 0xFFFF
#define VSB_COMM_INT_STA__PRE                                               0x0

#define VSB_COMM_INT_MSK__A                                                 0x1C00006
#define VSB_COMM_INT_MSK__W                                                 16
#define VSB_COMM_INT_MSK__M                                                 0xFFFF
#define VSB_COMM_INT_MSK__PRE                                               0x0

#define VSB_COMM_INT_STM__A                                                 0x1C00007
#define VSB_COMM_INT_STM__W                                                 16
#define VSB_COMM_INT_STM__M                                                 0xFFFF
#define VSB_COMM_INT_STM__PRE                                               0x0

#define VSB_TOP_COMM_EXEC__A                                                0x1C10000
#define VSB_TOP_COMM_EXEC__W                                                2
#define VSB_TOP_COMM_EXEC__M                                                0x3
#define VSB_TOP_COMM_EXEC__PRE                                              0x0
#define   VSB_TOP_COMM_EXEC_STOP                                            0x0
#define   VSB_TOP_COMM_EXEC_ACTIVE                                          0x1
#define   VSB_TOP_COMM_EXEC_HOLD                                            0x2

#define VSB_TOP_COMM_MB__A                                                  0x1C10002
#define VSB_TOP_COMM_MB__W                                                  10
#define VSB_TOP_COMM_MB__M                                                  0x3FF
#define VSB_TOP_COMM_MB__PRE                                                0x0

#define   VSB_TOP_COMM_MB_CTL__B                                            0
#define   VSB_TOP_COMM_MB_CTL__W                                            1
#define   VSB_TOP_COMM_MB_CTL__M                                            0x1
#define   VSB_TOP_COMM_MB_CTL__PRE                                          0x0
#define     VSB_TOP_COMM_MB_CTL_CTL_OFF                                     0x0
#define     VSB_TOP_COMM_MB_CTL_CTL_ON                                      0x1

#define   VSB_TOP_COMM_MB_OBS__B                                            1
#define   VSB_TOP_COMM_MB_OBS__W                                            1
#define   VSB_TOP_COMM_MB_OBS__M                                            0x2
#define   VSB_TOP_COMM_MB_OBS__PRE                                          0x0
#define     VSB_TOP_COMM_MB_OBS_OBS_OFF                                     0x0
#define     VSB_TOP_COMM_MB_OBS_OBS_ON                                      0x2

#define   VSB_TOP_COMM_MB_MUX_CTL__B                                        2
#define   VSB_TOP_COMM_MB_MUX_CTL__W                                        4
#define   VSB_TOP_COMM_MB_MUX_CTL__M                                        0x3C
#define   VSB_TOP_COMM_MB_MUX_CTL__PRE                                      0x0

#define   VSB_TOP_COMM_MB_MUX_OBS__B                                        6
#define   VSB_TOP_COMM_MB_MUX_OBS__W                                        4
#define   VSB_TOP_COMM_MB_MUX_OBS__M                                        0x3C0
#define   VSB_TOP_COMM_MB_MUX_OBS__PRE                                      0x0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC                                 0x0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM                                 0x40
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE                       0x80
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1                             0xC0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2                             0x100
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1                               0x140
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2                               0x180
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1                               0x1C0
#define     VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2                               0x200

#define VSB_TOP_COMM_INT_REQ__A                                             0x1C10003
#define VSB_TOP_COMM_INT_REQ__W                                             1
#define VSB_TOP_COMM_INT_REQ__M                                             0x1
#define VSB_TOP_COMM_INT_REQ__PRE                                           0x0
#define VSB_TOP_COMM_INT_STA__A                                             0x1C10005
#define VSB_TOP_COMM_INT_STA__W                                             6
#define VSB_TOP_COMM_INT_STA__M                                             0x3F
#define VSB_TOP_COMM_INT_STA__PRE                                           0x0

#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B                             0
#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W                             1
#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M                             0x1
#define   VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE                           0x0

#define   VSB_TOP_COMM_INT_STA_LOCK_STA__B                                  1
#define   VSB_TOP_COMM_INT_STA_LOCK_STA__W                                  1
#define   VSB_TOP_COMM_INT_STA_LOCK_STA__M                                  0x2
#define   VSB_TOP_COMM_INT_STA_LOCK_STA__PRE                                0x0

#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__B                                2
#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__W                                1
#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__M                                0x4
#define   VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE                              0x0

#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__B                             3
#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__W                             1
#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__M                             0x8
#define   VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE                           0x0

#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B                           4
#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W                           1
#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M                           0x10
#define   VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE                         0x0

#define   VSB_TOP_COMM_INT_STA_MERSER_STA__B                                5
#define   VSB_TOP_COMM_INT_STA_MERSER_STA__W                                1
#define   VSB_TOP_COMM_INT_STA_MERSER_STA__M                                0x20
#define   VSB_TOP_COMM_INT_STA_MERSER_STA__PRE                              0x0

#define VSB_TOP_COMM_INT_MSK__A                                             0x1C10006
#define VSB_TOP_COMM_INT_MSK__W                                             6
#define VSB_TOP_COMM_INT_MSK__M                                             0x3F
#define VSB_TOP_COMM_INT_MSK__PRE                                           0x0

#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B                             0
#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W                             1
#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M                             0x1
#define   VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE                           0x0

#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__B                                  1
#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__W                                  1
#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__M                                  0x2
#define   VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE                                0x0

#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B                                2
#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W                                1
#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M                                0x4
#define   VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE                              0x0

#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B                             3
#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W                             1
#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M                             0x8
#define   VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE                           0x0

#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B                           4
#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W                           1
#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M                           0x10
#define   VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE                         0x0

#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__B                                5
#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__W                                1
#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__M                                0x20
#define   VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE                              0x0

#define VSB_TOP_COMM_INT_STM__A                                             0x1C10007
#define VSB_TOP_COMM_INT_STM__W                                             6
#define VSB_TOP_COMM_INT_STM__M                                             0x3F
#define VSB_TOP_COMM_INT_STM__PRE                                           0x0

#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B                             0
#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W                             1
#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M                             0x1
#define   VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE                           0x0

#define   VSB_TOP_COMM_INT_STM_LOCK_STM__B                                  1
#define   VSB_TOP_COMM_INT_STM_LOCK_STM__W                                  1
#define   VSB_TOP_COMM_INT_STM_LOCK_STM__M                                  0x2
#define   VSB_TOP_COMM_INT_STM_LOCK_STM__PRE                                0x0

#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__B                                2
#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__W                                1
#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__M                                0x4
#define   VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE                              0x0

#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__B                             3
#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__W                             1
#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__M                             0x8
#define   VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE                           0x0

#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B                           4
#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W                           1
#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M                           0x10
#define   VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE                         0x0

#define   VSB_TOP_COMM_INT_STM_MERSER_STM__B                                5
#define   VSB_TOP_COMM_INT_STM_MERSER_STM__W                                1
#define   VSB_TOP_COMM_INT_STM_MERSER_STM__M                                0x20
#define   VSB_TOP_COMM_INT_STM_MERSER_STM__PRE                              0x0

#define VSB_TOP_CKGN1ACQ__A                                                 0x1C10010
#define VSB_TOP_CKGN1ACQ__W                                                 8
#define VSB_TOP_CKGN1ACQ__M                                                 0xFF
#define VSB_TOP_CKGN1ACQ__PRE                                               0x4

#define VSB_TOP_CKGN1TRK__A                                                 0x1C10011
#define VSB_TOP_CKGN1TRK__W                                                 8
#define VSB_TOP_CKGN1TRK__M                                                 0xFF
#define VSB_TOP_CKGN1TRK__PRE                                               0x0

#define VSB_TOP_CKGN2ACQ__A                                                 0x1C10012
#define VSB_TOP_CKGN2ACQ__W                                                 8
#define VSB_TOP_CKGN2ACQ__M                                                 0xFF
#define VSB_TOP_CKGN2ACQ__PRE                                               0x2

#define VSB_TOP_CKGN2TRK__A                                                 0x1C10013
#define VSB_TOP_CKGN2TRK__W                                                 8
#define VSB_TOP_CKGN2TRK__M                                                 0xFF
#define VSB_TOP_CKGN2TRK__PRE                                               0x1

#define VSB_TOP_CKGN3__A                                                    0x1C10014
#define VSB_TOP_CKGN3__W                                                    8
#define VSB_TOP_CKGN3__M                                                    0xFF
#define VSB_TOP_CKGN3__PRE                                                  0x5

#define VSB_TOP_CYGN1ACQ__A                                                 0x1C10015
#define VSB_TOP_CYGN1ACQ__W                                                 8
#define VSB_TOP_CYGN1ACQ__M                                                 0xFF
#define VSB_TOP_CYGN1ACQ__PRE                                               0x3

#define VSB_TOP_CYGN1TRK__A                                                 0x1C10016
#define VSB_TOP_CYGN1TRK__W                                                 8
#define VSB_TOP_CYGN1TRK__M                                                 0xFF
#define VSB_TOP_CYGN1TRK__PRE                                               0x0

#define VSB_TOP_CYGN2ACQ__A                                                 0x1C10017
#define VSB_TOP_CYGN2ACQ__W                                                 8
#define VSB_TOP_CYGN2ACQ__M                                                 0xFF
#define VSB_TOP_CYGN2ACQ__PRE                                               0x3

#define VSB_TOP_CYGN2TRK__A                                                 0x1C10018
#define VSB_TOP_CYGN2TRK__W                                                 8
#define VSB_TOP_CYGN2TRK__M                                                 0xFF
#define VSB_TOP_CYGN2TRK__PRE                                               0x2

#define VSB_TOP_CYGN3__A                                                    0x1C10019
#define VSB_TOP_CYGN3__W                                                    8
#define VSB_TOP_CYGN3__M                                                    0xFF
#define VSB_TOP_CYGN3__PRE                                                  0x6
#define VSB_TOP_SYNCCTRLWORD__A                                             0x1C1001A
#define VSB_TOP_SYNCCTRLWORD__W                                             5
#define VSB_TOP_SYNCCTRLWORD__M                                             0x1F
#define VSB_TOP_SYNCCTRLWORD__PRE                                           0x0

#define   VSB_TOP_SYNCCTRLWORD_PRST__B                                      0
#define   VSB_TOP_SYNCCTRLWORD_PRST__W                                      1
#define   VSB_TOP_SYNCCTRLWORD_PRST__M                                      0x1
#define   VSB_TOP_SYNCCTRLWORD_PRST__PRE                                    0x0

#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__B                                   1
#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__W                                   1
#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__M                                   0x2
#define   VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE                                 0x0

#define   VSB_TOP_SYNCCTRLWORD_INVCNST__B                                   2
#define   VSB_TOP_SYNCCTRLWORD_INVCNST__W                                   1
#define   VSB_TOP_SYNCCTRLWORD_INVCNST__M                                   0x4
#define   VSB_TOP_SYNCCTRLWORD_INVCNST__PRE                                 0x0

#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B                                 3
#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W                                 1
#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M                                 0x8
#define   VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE                               0x0

#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B                               4
#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W                               1
#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M                               0x10
#define   VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE                             0x0

#define VSB_TOP_MAINSMUP__A                                                 0x1C1001B
#define VSB_TOP_MAINSMUP__W                                                 8
#define VSB_TOP_MAINSMUP__M                                                 0xFF
#define VSB_TOP_MAINSMUP__PRE                                               0xFF

#define VSB_TOP_EQSMUP__A                                                   0x1C1001C
#define VSB_TOP_EQSMUP__W                                                   8
#define VSB_TOP_EQSMUP__M                                                   0xFF
#define VSB_TOP_EQSMUP__PRE                                                 0xFF
#define VSB_TOP_SYSMUXCTRL__A                                               0x1C1001D
#define VSB_TOP_SYSMUXCTRL__W                                               13
#define VSB_TOP_SYSMUXCTRL__M                                               0x1FFF
#define VSB_TOP_SYSMUXCTRL__PRE                                             0x0

#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B                                 0
#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W                                 1
#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M                                 0x1
#define   VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE                               0x0

#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B                             1
#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W                             1
#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M                             0x2
#define   VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE                           0x0

#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B                            2
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W                            1
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M                            0x4
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE                          0x0

#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B                        3
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W                        1
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M                        0x8
#define   VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE                      0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B                            4
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W                            1
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M                            0x10
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE                          0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B                        5
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W                        1
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M                        0x20
#define   VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE                      0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B                            6
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W                            1
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M                            0x40
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE                          0x0

#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B                        7
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W                        1
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M                        0x80
#define   VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE                      0x0

#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B                              8
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W                              4
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M                              0xF00
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE                            0x0

#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B                          12
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W                          1
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M                          0x1000
#define   VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE                        0x0

#define VSB_TOP_SNRTH_RCA1__A                                               0x1C1001E
#define VSB_TOP_SNRTH_RCA1__W                                               8
#define VSB_TOP_SNRTH_RCA1__M                                               0xFF
#define VSB_TOP_SNRTH_RCA1__PRE                                             0x53

#define   VSB_TOP_SNRTH_RCA1_DN__B                                          0
#define   VSB_TOP_SNRTH_RCA1_DN__W                                          4
#define   VSB_TOP_SNRTH_RCA1_DN__M                                          0xF
#define   VSB_TOP_SNRTH_RCA1_DN__PRE                                        0x3

#define   VSB_TOP_SNRTH_RCA1_UP__B                                          4
#define   VSB_TOP_SNRTH_RCA1_UP__W                                          4
#define   VSB_TOP_SNRTH_RCA1_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_RCA1_UP__PRE                                        0x50

#define VSB_TOP_SNRTH_RCA2__A                                               0x1C1001F
#define VSB_TOP_SNRTH_RCA2__W                                               8
#define VSB_TOP_SNRTH_RCA2__M                                               0xFF
#define VSB_TOP_SNRTH_RCA2__PRE                                             0x75

#define   VSB_TOP_SNRTH_RCA2_DN__B                                          0
#define   VSB_TOP_SNRTH_RCA2_DN__W                                          4
#define   VSB_TOP_SNRTH_RCA2_DN__M                                          0xF
#define   VSB_TOP_SNRTH_RCA2_DN__PRE                                        0x5

#define   VSB_TOP_SNRTH_RCA2_UP__B                                          4
#define   VSB_TOP_SNRTH_RCA2_UP__W                                          4
#define   VSB_TOP_SNRTH_RCA2_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_RCA2_UP__PRE                                        0x70

#define VSB_TOP_SNRTH_DDM1__A                                               0x1C10020
#define VSB_TOP_SNRTH_DDM1__W                                               8
#define VSB_TOP_SNRTH_DDM1__M                                               0xFF
#define VSB_TOP_SNRTH_DDM1__PRE                                             0xCA

#define   VSB_TOP_SNRTH_DDM1_DN__B                                          0
#define   VSB_TOP_SNRTH_DDM1_DN__W                                          4
#define   VSB_TOP_SNRTH_DDM1_DN__M                                          0xF
#define   VSB_TOP_SNRTH_DDM1_DN__PRE                                        0xA

#define   VSB_TOP_SNRTH_DDM1_UP__B                                          4
#define   VSB_TOP_SNRTH_DDM1_UP__W                                          4
#define   VSB_TOP_SNRTH_DDM1_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_DDM1_UP__PRE                                        0xC0

#define VSB_TOP_SNRTH_DDM2__A                                               0x1C10021
#define VSB_TOP_SNRTH_DDM2__W                                               8
#define VSB_TOP_SNRTH_DDM2__M                                               0xFF
#define VSB_TOP_SNRTH_DDM2__PRE                                             0xCA

#define   VSB_TOP_SNRTH_DDM2_DN__B                                          0
#define   VSB_TOP_SNRTH_DDM2_DN__W                                          4
#define   VSB_TOP_SNRTH_DDM2_DN__M                                          0xF
#define   VSB_TOP_SNRTH_DDM2_DN__PRE                                        0xA

#define   VSB_TOP_SNRTH_DDM2_UP__B                                          4
#define   VSB_TOP_SNRTH_DDM2_UP__W                                          4
#define   VSB_TOP_SNRTH_DDM2_UP__M                                          0xF0
#define   VSB_TOP_SNRTH_DDM2_UP__PRE                                        0xC0

#define VSB_TOP_SNRTH_PT__A                                                 0x1C10022
#define VSB_TOP_SNRTH_PT__W                                                 8
#define VSB_TOP_SNRTH_PT__M                                                 0xFF
#define VSB_TOP_SNRTH_PT__PRE                                               0xD8

#define   VSB_TOP_SNRTH_PT_DN__B                                            0
#define   VSB_TOP_SNRTH_PT_DN__W                                            4
#define   VSB_TOP_SNRTH_PT_DN__M                                            0xF
#define   VSB_TOP_SNRTH_PT_DN__PRE                                          0x8

#define   VSB_TOP_SNRTH_PT_UP__B                                            4
#define   VSB_TOP_SNRTH_PT_UP__W                                            4
#define   VSB_TOP_SNRTH_PT_UP__M                                            0xF0
#define   VSB_TOP_SNRTH_PT_UP__PRE                                          0xD0

#define VSB_TOP_CYSMSTATES__A                                               0x1C10023
#define VSB_TOP_CYSMSTATES__W                                               8
#define VSB_TOP_CYSMSTATES__M                                               0xFF
#define VSB_TOP_CYSMSTATES__PRE                                             0x0

#define   VSB_TOP_CYSMSTATES_SYSST__B                                       0
#define   VSB_TOP_CYSMSTATES_SYSST__W                                       4
#define   VSB_TOP_CYSMSTATES_SYSST__M                                       0xF
#define   VSB_TOP_CYSMSTATES_SYSST__PRE                                     0x0

#define   VSB_TOP_CYSMSTATES_EQST__B                                        4
#define   VSB_TOP_CYSMSTATES_EQST__W                                        4
#define   VSB_TOP_CYSMSTATES_EQST__M                                        0xF0
#define   VSB_TOP_CYSMSTATES_EQST__PRE                                      0x0

#define VSB_TOP_SMALL_NOTCH_CONTROL__A                                      0x1C10024
#define VSB_TOP_SMALL_NOTCH_CONTROL__W                                      8
#define VSB_TOP_SMALL_NOTCH_CONTROL__M                                      0xFF
#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE                                    0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__B                                 0
#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__W                                 1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__M                                 0x1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE                               0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B                            1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W                            1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M                            0x2
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE                          0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B                            2
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W                            1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M                            0x4
#define   VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE                          0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B                              3
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W                              4
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M                              0x78
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE                            0x0

#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B                         7
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W                         1
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M                         0x80
#define   VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE                       0x0

#define VSB_TOP_TAPREADCYC__A                                               0x1C10025
#define VSB_TOP_TAPREADCYC__W                                               9
#define VSB_TOP_TAPREADCYC__M                                               0x1FF
#define VSB_TOP_TAPREADCYC__PRE                                             0x1

#define VSB_TOP_VALIDPKLVL__A                                               0x1C10026
#define VSB_TOP_VALIDPKLVL__W                                               13
#define VSB_TOP_VALIDPKLVL__M                                               0x1FFF
#define VSB_TOP_VALIDPKLVL__PRE                                             0x100

#define VSB_TOP_CENTROID_FINE_DELAY__A                                      0x1C10027
#define VSB_TOP_CENTROID_FINE_DELAY__W                                      10
#define VSB_TOP_CENTROID_FINE_DELAY__M                                      0x3FF
#define VSB_TOP_CENTROID_FINE_DELAY__PRE                                    0xFF

#define VSB_TOP_CENTROID_SMACH_DELAY__A                                     0x1C10028
#define VSB_TOP_CENTROID_SMACH_DELAY__W                                     10
#define VSB_TOP_CENTROID_SMACH_DELAY__M                                     0x3FF
#define VSB_TOP_CENTROID_SMACH_DELAY__PRE                                   0x1FF

#define VSB_TOP_SNR__A                                                      0x1C10029
#define VSB_TOP_SNR__W                                                      14
#define VSB_TOP_SNR__M                                                      0x3FFF
#define VSB_TOP_SNR__PRE                                                    0x0
#define VSB_TOP_LOCKSTATUS__A                                               0x1C1002A
#define VSB_TOP_LOCKSTATUS__W                                               7
#define VSB_TOP_LOCKSTATUS__M                                               0x7F
#define VSB_TOP_LOCKSTATUS__PRE                                             0x0

#define   VSB_TOP_LOCKSTATUS_VSBMODE__B                                     0
#define   VSB_TOP_LOCKSTATUS_VSBMODE__W                                     4
#define   VSB_TOP_LOCKSTATUS_VSBMODE__M                                     0xF
#define   VSB_TOP_LOCKSTATUS_VSBMODE__PRE                                   0x0

#define   VSB_TOP_LOCKSTATUS_FRMLOCK__B                                     4
#define   VSB_TOP_LOCKSTATUS_FRMLOCK__W                                     1
#define   VSB_TOP_LOCKSTATUS_FRMLOCK__M                                     0x10
#define   VSB_TOP_LOCKSTATUS_FRMLOCK__PRE                                   0x0

#define   VSB_TOP_LOCKSTATUS_CYLOCK__B                                      5
#define   VSB_TOP_LOCKSTATUS_CYLOCK__W                                      1
#define   VSB_TOP_LOCKSTATUS_CYLOCK__M                                      0x20
#define   VSB_TOP_LOCKSTATUS_CYLOCK__PRE                                    0x0

#define   VSB_TOP_LOCKSTATUS_DDMON__B                                       6
#define   VSB_TOP_LOCKSTATUS_DDMON__W                                       1
#define   VSB_TOP_LOCKSTATUS_DDMON__M                                       0x40
#define   VSB_TOP_LOCKSTATUS_DDMON__PRE                                     0x0

#define VSB_TOP_CTST__A                                                     0x1C1002B
#define VSB_TOP_CTST__W                                                     4
#define VSB_TOP_CTST__M                                                     0xF
#define VSB_TOP_CTST__PRE                                                   0x0
#define VSB_TOP_EQSMRSTCTRL__A                                              0x1C1002C
#define VSB_TOP_EQSMRSTCTRL__W                                              7
#define VSB_TOP_EQSMRSTCTRL__M                                              0x7F
#define VSB_TOP_EQSMRSTCTRL__PRE                                            0x0

#define   VSB_TOP_EQSMRSTCTRL_RCAON__B                                      0
#define   VSB_TOP_EQSMRSTCTRL_RCAON__W                                      1
#define   VSB_TOP_EQSMRSTCTRL_RCAON__M                                      0x1
#define   VSB_TOP_EQSMRSTCTRL_RCAON__PRE                                    0x0

#define   VSB_TOP_EQSMRSTCTRL_DFEON__B                                      1
#define   VSB_TOP_EQSMRSTCTRL_DFEON__W                                      1
#define   VSB_TOP_EQSMRSTCTRL_DFEON__M                                      0x2
#define   VSB_TOP_EQSMRSTCTRL_DFEON__PRE                                    0x0

#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__B                                     2
#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__W                                     1
#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__M                                     0x4
#define   VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE                                   0x0

#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__B                                     3
#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__W                                     1
#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__M                                     0x8
#define   VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE                                   0x0

#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B                                  4
#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W                                  1
#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M                                  0x10
#define   VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE                                0x0

#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__B                                 5
#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__W                                 1
#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__M                                 0x20
#define   VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE                               0x0

#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B                            6
#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W                            1
#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M                            0x40
#define   VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE                          0x0

#define VSB_TOP_EQSMTRNCTRL__A                                              0x1C1002D
#define VSB_TOP_EQSMTRNCTRL__W                                              7
#define VSB_TOP_EQSMTRNCTRL__M                                              0x7F
#define VSB_TOP_EQSMTRNCTRL__PRE                                            0x40

#define   VSB_TOP_EQSMTRNCTRL_RCAON__B                                      0
#define   VSB_TOP_EQSMTRNCTRL_RCAON__W                                      1
#define   VSB_TOP_EQSMTRNCTRL_RCAON__M                                      0x1
#define   VSB_TOP_EQSMTRNCTRL_RCAON__PRE                                    0x0

#define   VSB_TOP_EQSMTRNCTRL_DFEON__B                                      1
#define   VSB_TOP_EQSMTRNCTRL_DFEON__W                                      1
#define   VSB_TOP_EQSMTRNCTRL_DFEON__M                                      0x2
#define   VSB_TOP_EQSMTRNCTRL_DFEON__PRE                                    0x0

#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__B                                     2
#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__W                                     1
#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__M                                     0x4
#define   VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE                                   0x0

#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__B                                     3
#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__W                                     1
#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__M                                     0x8
#define   VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE                                   0x0

#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B                                  4
#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W                                  1
#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M                                  0x10
#define   VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE                                0x0

#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__B                                 5
#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__W                                 1
#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__M                                 0x20
#define   VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE                               0x0

#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B                            6
#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W                            1
#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M                            0x40
#define   VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE                          0x40

#define VSB_TOP_EQSMRCA1CTRL__A                                             0x1C1002E
#define VSB_TOP_EQSMRCA1CTRL__W                                             7
#define VSB_TOP_EQSMRCA1CTRL__M                                             0x7F
#define VSB_TOP_EQSMRCA1CTRL__PRE                                           0x1

#define   VSB_TOP_EQSMRCA1CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMRCA1CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMRCA1CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMRCA1CTRL_RCAON__PRE                                   0x1

#define   VSB_TOP_EQSMRCA1CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMRCA1CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMRCA1CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMRCA1CTRL_DFEON__PRE                                   0x0

#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE                                  0x0

#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE                                  0x0

#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE                               0x0

#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_EQSMRCA2CTRL__A                                             0x1C1002F
#define VSB_TOP_EQSMRCA2CTRL__W                                             7
#define VSB_TOP_EQSMRCA2CTRL__M                                             0x7F
#define VSB_TOP_EQSMRCA2CTRL__PRE                                           0x3

#define   VSB_TOP_EQSMRCA2CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMRCA2CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMRCA2CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMRCA2CTRL_RCAON__PRE                                   0x1

#define   VSB_TOP_EQSMRCA2CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMRCA2CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMRCA2CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMRCA2CTRL_DFEON__PRE                                   0x2

#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE                                  0x0

#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE                                  0x0

#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE                               0x0

#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_EQSMDDM1CTRL__A                                             0x1C10030
#define VSB_TOP_EQSMDDM1CTRL__W                                             7
#define VSB_TOP_EQSMDDM1CTRL__M                                             0x7F
#define VSB_TOP_EQSMDDM1CTRL__PRE                                           0x6

#define   VSB_TOP_EQSMDDM1CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMDDM1CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMDDM1CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMDDM1CTRL_RCAON__PRE                                   0x0

#define   VSB_TOP_EQSMDDM1CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMDDM1CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMDDM1CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMDDM1CTRL_DFEON__PRE                                   0x2

#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE                                  0x4

#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE                                  0x0

#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE                               0x0

#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_EQSMDDM2CTRL__A                                             0x1C10031
#define VSB_TOP_EQSMDDM2CTRL__W                                             7
#define VSB_TOP_EQSMDDM2CTRL__M                                             0x7F
#define VSB_TOP_EQSMDDM2CTRL__PRE                                           0x1E

#define   VSB_TOP_EQSMDDM2CTRL_RCAON__B                                     0
#define   VSB_TOP_EQSMDDM2CTRL_RCAON__W                                     1
#define   VSB_TOP_EQSMDDM2CTRL_RCAON__M                                     0x1
#define   VSB_TOP_EQSMDDM2CTRL_RCAON__PRE                                   0x0

#define   VSB_TOP_EQSMDDM2CTRL_DFEON__B                                     1
#define   VSB_TOP_EQSMDDM2CTRL_DFEON__W                                     1
#define   VSB_TOP_EQSMDDM2CTRL_DFEON__M                                     0x2
#define   VSB_TOP_EQSMDDM2CTRL_DFEON__PRE                                   0x2

#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__B                                    2
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__W                                    1
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__M                                    0x4
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE                                  0x4

#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__B                                    3
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__W                                    1
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__M                                    0x8
#define   VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE                                  0x8

#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B                                 4
#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W                                 1
#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M                                 0x10
#define   VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE                               0x10

#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B                                5
#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W                                1
#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M                                0x20
#define   VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE                              0x0

#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B                           6
#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W                           1
#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M                           0x40
#define   VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE                         0x0

#define VSB_TOP_SYSSMRSTCTRL__A                                             0x1C10032
#define VSB_TOP_SYSSMRSTCTRL__W                                             11
#define VSB_TOP_SYSSMRSTCTRL__M                                             0x7FF
#define VSB_TOP_SYSSMRSTCTRL__PRE                                           0x7F9

#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B                                  0
#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M                                  0x1
#define   VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE                                0x1

#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__B                                   1
#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__W                                   1
#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__M                                   0x2
#define   VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE                                 0x0

#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__B                                  2
#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__M                                  0x4
#define   VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE                                0x0

#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B                             3
#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W                             1
#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M                             0x8
#define   VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE                           0x8

#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B                                  4
#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M                                  0x10
#define   VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE                                0x10

#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B                                  5
#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M                                  0x20
#define   VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE                                0x20

#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B                                  6
#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W                                  1
#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M                                  0x40
#define   VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE                                0x40

#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__B                                     7
#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__W                                     1
#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__M                                     0x80
#define   VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE                                   0x80

#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__B                                    8
#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__W                                    1
#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__M                                    0x100
#define   VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE                                  0x100

#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B                                   9
#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W                                   1
#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M                                   0x200
#define   VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE                                 0x200

#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B                           10
#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W                           1
#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M                           0x400
#define   VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE                         0x400

#define VSB_TOP_SYSSMCYCTRL__A                                              0x1C10033
#define VSB_TOP_SYSSMCYCTRL__W                                              11
#define VSB_TOP_SYSSMCYCTRL__M                                              0x7FF
#define VSB_TOP_SYSSMCYCTRL__PRE                                            0x4E9

#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B                                   0
#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M                                   0x1
#define   VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE                                 0x1

#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__B                                    1
#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__W                                    1
#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__M                                    0x2
#define   VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE                                  0x0

#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__B                                   2
#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__M                                   0x4
#define   VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE                                 0x0

#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B                              3
#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W                              1
#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M                              0x8
#define   VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE                            0x8

#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__B                                   4
#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__M                                   0x10
#define   VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE                                 0x0

#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B                                   5
#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M                                   0x20
#define   VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE                                 0x20

#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B                                   6
#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W                                   1
#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M                                   0x40
#define   VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE                                 0x40

#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__B                                      7
#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__W                                      1
#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__M                                      0x80
#define   VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE                                    0x80

#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__B                                     8
#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__W                                     1
#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__M                                     0x100
#define   VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE                                   0x0

#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__B                                    9
#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__W                                    1
#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__M                                    0x200
#define   VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B                            10
#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W                            1
#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M                            0x400
#define   VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE                          0x400

#define VSB_TOP_SYSSMTRNCTRL__A                                             0x1C10034
#define VSB_TOP_SYSSMTRNCTRL__W                                             11
#define VSB_TOP_SYSSMTRNCTRL__M                                             0x7FF
#define VSB_TOP_SYSSMTRNCTRL__PRE                                           0x204

#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B                                  0
#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M                                  0x1
#define   VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__B                                   1
#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__W                                   1
#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__M                                   0x2
#define   VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE                                 0x0

#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__B                                  2
#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__M                                  0x4
#define   VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE                                0x4

#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B                             3
#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W                             1
#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M                             0x8
#define   VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE                           0x0

#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B                                  4
#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M                                  0x10
#define   VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B                                  5
#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M                                  0x20
#define   VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B                                  6
#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W                                  1
#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M                                  0x40
#define   VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE                                0x0

#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__B                                     7
#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__W                                     1
#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__M                                     0x80
#define   VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE                                   0x0

#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__B                                    8
#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__W                                    1
#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__M                                    0x100
#define   VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B                                   9
#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W                                   1
#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M                                   0x200
#define   VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE                                 0x200

#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B                           10
#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W                           1
#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M                           0x400
#define   VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE                         0x0

#define VSB_TOP_SYSSMEQCTRL__A                                              0x1C10035
#define VSB_TOP_SYSSMEQCTRL__W                                              11
#define VSB_TOP_SYSSMEQCTRL__M                                              0x7FF
#define VSB_TOP_SYSSMEQCTRL__PRE                                            0x304

#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B                                   0
#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M                                   0x1
#define   VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__B                                    1
#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__W                                    1
#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__M                                    0x2
#define   VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE                                  0x0

#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__B                                   2
#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__M                                   0x4
#define   VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE                                 0x4

#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B                              3
#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W                              1
#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M                              0x8
#define   VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE                            0x0

#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__B                                   4
#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__M                                   0x10
#define   VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B                                   5
#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M                                   0x20
#define   VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B                                   6
#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W                                   1
#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M                                   0x40
#define   VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE                                 0x0

#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__B                                      7
#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__W                                      1
#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__M                                      0x80
#define   VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE                                    0x0

#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__B                                     8
#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__W                                     1
#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__M                                     0x100
#define   VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE                                   0x100

#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__B                                    9
#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__W                                    1
#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__M                                    0x200
#define   VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE                                  0x200

#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B                            10
#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W                            1
#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M                            0x400
#define   VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE                          0x0

#define VSB_TOP_SYSSMAGCCTRL__A                                             0x1C10036
#define VSB_TOP_SYSSMAGCCTRL__W                                             11
#define VSB_TOP_SYSSMAGCCTRL__M                                             0x7FF
#define VSB_TOP_SYSSMAGCCTRL__PRE                                           0xF9

#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B                                  0
#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M                                  0x1
#define   VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE                                0x1

#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__B                                   1
#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__W                                   1
#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__M                                   0x2
#define   VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE                                 0x0

#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__B                                  2
#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__M                                  0x4
#define   VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE                                0x0

#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B                             3
#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W                             1
#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M                             0x8
#define   VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE                           0x8

#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B                                  4
#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M                                  0x10
#define   VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE                                0x10

#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B                                  5
#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M                                  0x20
#define   VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE                                0x20

#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B                                  6
#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W                                  1
#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M                                  0x40
#define   VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE                                0x40

#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__B                                     7
#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__W                                     1
#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__M                                     0x80
#define   VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE                                   0x80

#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__B                                    8
#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__W                                    1
#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__M                                    0x100
#define   VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B                                   9
#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W                                   1
#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M                                   0x200
#define   VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE                                 0x0

#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B                           10
#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W                           1
#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M                           0x400
#define   VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE                         0x0

#define VSB_TOP_SYSSMCTCTRL__A                                              0x1C10037
#define VSB_TOP_SYSSMCTCTRL__W                                              11
#define VSB_TOP_SYSSMCTCTRL__M                                              0x7FF
#define VSB_TOP_SYSSMCTCTRL__PRE                                            0x4A

#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B                                   0
#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M                                   0x1
#define   VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__B                                    1
#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__W                                    1
#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__M                                    0x2
#define   VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE                                  0x2

#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__B                                   2
#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__M                                   0x4
#define   VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B                              3
#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W                              1
#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M                              0x8
#define   VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE                            0x8

#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__B                                   4
#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__M                                   0x10
#define   VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B                                   5
#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M                                   0x20
#define   VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE                                 0x0

#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B                                   6
#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W                                   1
#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M                                   0x40
#define   VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE                                 0x40

#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__B                                      7
#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__W                                      1
#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__M                                      0x80
#define   VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE                                    0x0

#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__B                                     8
#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__W                                     1
#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__M                                     0x100
#define   VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE                                   0x0

#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__B                                    9
#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__W                                    1
#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__M                                    0x200
#define   VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE                                  0x0

#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B                            10
#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W                            1
#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M                            0x400
#define   VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE                          0x0

#define VSB_TOP_EQCTRL__A                                                   0x1C10038
#define VSB_TOP_EQCTRL__W                                                   10
#define VSB_TOP_EQCTRL__M                                                   0x3FF
#define VSB_TOP_EQCTRL__PRE                                                 0x6

#define   VSB_TOP_EQCTRL_STASSIGNEN__B                                      0
#define   VSB_TOP_EQCTRL_STASSIGNEN__W                                      1
#define   VSB_TOP_EQCTRL_STASSIGNEN__M                                      0x1
#define   VSB_TOP_EQCTRL_STASSIGNEN__PRE                                    0x0

#define   VSB_TOP_EQCTRL_ORCANCMAEN__B                                      1
#define   VSB_TOP_EQCTRL_ORCANCMAEN__W                                      1
#define   VSB_TOP_EQCTRL_ORCANCMAEN__M                                      0x2
#define   VSB_TOP_EQCTRL_ORCANCMAEN__PRE                                    0x2

#define   VSB_TOP_EQCTRL_ODAGCGO__B                                         2
#define   VSB_TOP_EQCTRL_ODAGCGO__W                                         1
#define   VSB_TOP_EQCTRL_ODAGCGO__M                                         0x4
#define   VSB_TOP_EQCTRL_ODAGCGO__PRE                                       0x4

#define   VSB_TOP_EQCTRL_OPTGAIN__B                                         3
#define   VSB_TOP_EQCTRL_OPTGAIN__W                                         3
#define   VSB_TOP_EQCTRL_OPTGAIN__M                                         0x38
#define   VSB_TOP_EQCTRL_OPTGAIN__PRE                                       0x0

#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__B                                     6
#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__W                                     1
#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__M                                     0x40
#define   VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE                                   0x0

#define   VSB_TOP_EQCTRL_CMAGAIN__B                                         7
#define   VSB_TOP_EQCTRL_CMAGAIN__W                                         3
#define   VSB_TOP_EQCTRL_CMAGAIN__M                                         0x380
#define   VSB_TOP_EQCTRL_CMAGAIN__PRE                                       0x0

#define VSB_TOP_PREEQAGCCTRL__A                                             0x1C10039
#define VSB_TOP_PREEQAGCCTRL__W                                             5
#define VSB_TOP_PREEQAGCCTRL__M                                             0x1F
#define VSB_TOP_PREEQAGCCTRL__PRE                                           0x10

#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B                             0
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W                             4
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M                             0xF
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE                           0x0

#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B                               4
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W                               1
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M                               0x10
#define   VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE                             0x10

#define VSB_TOP_PREEQAGCPWRREFLVLHI__A                                      0x1C1003A
#define VSB_TOP_PREEQAGCPWRREFLVLHI__W                                      8
#define VSB_TOP_PREEQAGCPWRREFLVLHI__M                                      0xFF
#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE                                    0x0

#define VSB_TOP_PREEQAGCPWRREFLVLLO__A                                      0x1C1003B
#define VSB_TOP_PREEQAGCPWRREFLVLLO__W                                      16
#define VSB_TOP_PREEQAGCPWRREFLVLLO__M                                      0xFFFF
#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE                                    0x1D66

#define VSB_TOP_CORINGSEL__A                                                0x1C1003C
#define VSB_TOP_CORINGSEL__W                                                8
#define VSB_TOP_CORINGSEL__M                                                0xFF
#define VSB_TOP_CORINGSEL__PRE                                              0x3
#define VSB_TOP_BEDETCTRL__A                                                0x1C1003D
#define VSB_TOP_BEDETCTRL__W                                                9
#define VSB_TOP_BEDETCTRL__M                                                0x1FF
#define VSB_TOP_BEDETCTRL__PRE                                              0x145

#define   VSB_TOP_BEDETCTRL_MIXRATIO__B                                     0
#define   VSB_TOP_BEDETCTRL_MIXRATIO__W                                     3
#define   VSB_TOP_BEDETCTRL_MIXRATIO__M                                     0x7
#define   VSB_TOP_BEDETCTRL_MIXRATIO__PRE                                   0x5

#define   VSB_TOP_BEDETCTRL_CYOFFSEL__B                                     3
#define   VSB_TOP_BEDETCTRL_CYOFFSEL__W                                     1
#define   VSB_TOP_BEDETCTRL_CYOFFSEL__M                                     0x8
#define   VSB_TOP_BEDETCTRL_CYOFFSEL__PRE                                   0x0

#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__B                                   4
#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__W                                   1
#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__M                                   0x10
#define   VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE                                 0x0

#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__B                                   5
#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__M                                   0x20
#define   VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE                                 0x0

#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__B                                   6
#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__M                                   0x40
#define   VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE                                 0x40

#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__B                                   7
#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__M                                   0x80
#define   VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE                                 0x0

#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__B                                   8
#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__W                                   1
#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__M                                   0x100
#define   VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE                                 0x100

#define VSB_TOP_LBAGCREFLVL__A                                              0x1C1003E
#define VSB_TOP_LBAGCREFLVL__W                                              12
#define VSB_TOP_LBAGCREFLVL__M                                              0xFFF
#define VSB_TOP_LBAGCREFLVL__PRE                                            0x200

#define VSB_TOP_UBAGCREFLVL__A                                              0x1C1003F
#define VSB_TOP_UBAGCREFLVL__W                                              12
#define VSB_TOP_UBAGCREFLVL__M                                              0xFFF
#define VSB_TOP_UBAGCREFLVL__PRE                                            0x400

#define VSB_TOP_NOTCH1_BIN_NUM__A                                           0x1C10040
#define VSB_TOP_NOTCH1_BIN_NUM__W                                           11
#define VSB_TOP_NOTCH1_BIN_NUM__M                                           0x7FF
#define VSB_TOP_NOTCH1_BIN_NUM__PRE                                         0xB2

#define VSB_TOP_NOTCH2_BIN_NUM__A                                           0x1C10041
#define VSB_TOP_NOTCH2_BIN_NUM__W                                           11
#define VSB_TOP_NOTCH2_BIN_NUM__M                                           0x7FF
#define VSB_TOP_NOTCH2_BIN_NUM__PRE                                         0x40B

#define VSB_TOP_NOTCH_START_BIN_NUM__A                                      0x1C10042
#define VSB_TOP_NOTCH_START_BIN_NUM__W                                      11
#define VSB_TOP_NOTCH_START_BIN_NUM__M                                      0x7FF
#define VSB_TOP_NOTCH_START_BIN_NUM__PRE                                    0x7C0

#define VSB_TOP_NOTCH_STOP_BIN_NUM__A                                       0x1C10043
#define VSB_TOP_NOTCH_STOP_BIN_NUM__W                                       11
#define VSB_TOP_NOTCH_STOP_BIN_NUM__M                                       0x7FF
#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE                                     0x43F

#define VSB_TOP_NOTCH_TEST_DURATION__A                                      0x1C10044
#define VSB_TOP_NOTCH_TEST_DURATION__W                                      11
#define VSB_TOP_NOTCH_TEST_DURATION__M                                      0x7FF
#define VSB_TOP_NOTCH_TEST_DURATION__PRE                                    0x7FF

#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A                                    0x1C10045
#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W                                    11
#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M                                    0x7FF
#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE                                  0x0

#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A                                  0x1C10046
#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W                                  16
#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M                                  0xFFFF
#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE                                0x0

#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A                                    0x1C10047
#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W                                    11
#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M                                    0x7FF
#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE                                  0x0

#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A                                  0x1C10048
#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W                                  16
#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M                                  0xFFFF
#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE                                0x0

#define VSB_TOP_NOTCH_SWEEP_RUNNING__A                                      0x1C10049
#define VSB_TOP_NOTCH_SWEEP_RUNNING__W                                      1
#define VSB_TOP_NOTCH_SWEEP_RUNNING__M                                      0x1
#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE                                    0x0

#define VSB_TOP_PREEQDAGCRATIO__A                                           0x1C1004A
#define VSB_TOP_PREEQDAGCRATIO__W                                           13
#define VSB_TOP_PREEQDAGCRATIO__M                                           0x1FFF
#define VSB_TOP_PREEQDAGCRATIO__PRE                                         0x0
#define VSB_TOP_AGC_TRUNCCTRL__A                                            0x1C1004B
#define VSB_TOP_AGC_TRUNCCTRL__W                                            4
#define VSB_TOP_AGC_TRUNCCTRL__M                                            0xF
#define VSB_TOP_AGC_TRUNCCTRL__PRE                                          0xF

#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B                                0
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W                                2
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M                                0x3
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE                              0x3

#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B                                2
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W                                1
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M                                0x4
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE                              0x4

#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B                                 3
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W                                 1
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M                                 0x8
#define   VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE                               0x8

#define VSB_TOP_BEAGC_DEADZONEINIT__A                                       0x1C1004C
#define VSB_TOP_BEAGC_DEADZONEINIT__W                                       8
#define VSB_TOP_BEAGC_DEADZONEINIT__M                                       0xFF
#define VSB_TOP_BEAGC_DEADZONEINIT__PRE                                     0x50

#define VSB_TOP_BEAGC_REFLEVEL__A                                           0x1C1004D
#define VSB_TOP_BEAGC_REFLEVEL__W                                           9
#define VSB_TOP_BEAGC_REFLEVEL__M                                           0x1FF
#define VSB_TOP_BEAGC_REFLEVEL__PRE                                         0xAE

#define VSB_TOP_BEAGC_GAINSHIFT__A                                          0x1C1004E
#define VSB_TOP_BEAGC_GAINSHIFT__W                                          3
#define VSB_TOP_BEAGC_GAINSHIFT__M                                          0x7
#define VSB_TOP_BEAGC_GAINSHIFT__PRE                                        0x3

#define VSB_TOP_BEAGC_REGINIT__A                                            0x1C1004F
#define VSB_TOP_BEAGC_REGINIT__W                                            15
#define VSB_TOP_BEAGC_REGINIT__M                                            0x7FFF
#define VSB_TOP_BEAGC_REGINIT__PRE                                          0x40

#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B                                14
#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W                                1
#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M                                0x4000
#define   VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE                              0x0

#define VSB_TOP_BEAGC_SCALE__A                                              0x1C10050
#define VSB_TOP_BEAGC_SCALE__W                                              14
#define VSB_TOP_BEAGC_SCALE__M                                              0x3FFF
#define VSB_TOP_BEAGC_SCALE__PRE                                            0x0

#define VSB_TOP_CFAGC_DEADZONEINIT__A                                       0x1C10051
#define VSB_TOP_CFAGC_DEADZONEINIT__W                                       8
#define VSB_TOP_CFAGC_DEADZONEINIT__M                                       0xFF
#define VSB_TOP_CFAGC_DEADZONEINIT__PRE                                     0x50

#define VSB_TOP_CFAGC_REFLEVEL__A                                           0x1C10052
#define VSB_TOP_CFAGC_REFLEVEL__W                                           9
#define VSB_TOP_CFAGC_REFLEVEL__M                                           0x1FF
#define VSB_TOP_CFAGC_REFLEVEL__PRE                                         0xAE

#define VSB_TOP_CFAGC_GAINSHIFT__A                                          0x1C10053
#define VSB_TOP_CFAGC_GAINSHIFT__W                                          3
#define VSB_TOP_CFAGC_GAINSHIFT__M                                          0x7
#define VSB_TOP_CFAGC_GAINSHIFT__PRE                                        0x3

#define VSB_TOP_CFAGC_REGINIT__A                                            0x1C10054
#define VSB_TOP_CFAGC_REGINIT__W                                            15
#define VSB_TOP_CFAGC_REGINIT__M                                            0x7FFF
#define VSB_TOP_CFAGC_REGINIT__PRE                                          0x80

#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B                                14
#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W                                1
#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M                                0x4000
#define   VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE                              0x0

#define VSB_TOP_CFAGC_SCALE__A                                              0x1C10055
#define VSB_TOP_CFAGC_SCALE__W                                              14
#define VSB_TOP_CFAGC_SCALE__M                                              0x3FFF
#define VSB_TOP_CFAGC_SCALE__PRE                                            0x0

#define VSB_TOP_CKTRKONCTL__A                                               0x1C10056
#define VSB_TOP_CKTRKONCTL__W                                               2
#define VSB_TOP_CKTRKONCTL__M                                               0x3
#define VSB_TOP_CKTRKONCTL__PRE                                             0x0

#define VSB_TOP_CYTRKONCTL__A                                               0x1C10057
#define VSB_TOP_CYTRKONCTL__W                                               2
#define VSB_TOP_CYTRKONCTL__M                                               0x3
#define VSB_TOP_CYTRKONCTL__PRE                                             0x0

#define VSB_TOP_PTONCTL__A                                                  0x1C10058
#define VSB_TOP_PTONCTL__W                                                  2
#define VSB_TOP_PTONCTL__M                                                  0x3
#define VSB_TOP_PTONCTL__PRE                                                0x0

#define VSB_TOP_NOTCH_SCALE_1__A                                            0x1C10059
#define VSB_TOP_NOTCH_SCALE_1__W                                            8
#define VSB_TOP_NOTCH_SCALE_1__M                                            0xFF
#define VSB_TOP_NOTCH_SCALE_1__PRE                                          0xA

#define VSB_TOP_NOTCH_SCALE_2__A                                            0x1C1005A
#define VSB_TOP_NOTCH_SCALE_2__W                                            8
#define VSB_TOP_NOTCH_SCALE_2__M                                            0xFF
#define VSB_TOP_NOTCH_SCALE_2__PRE                                          0xA

#define VSB_TOP_FIRSTLARGFFETAP__A                                          0x1C1005B
#define VSB_TOP_FIRSTLARGFFETAP__W                                          12
#define VSB_TOP_FIRSTLARGFFETAP__M                                          0xFFF
#define VSB_TOP_FIRSTLARGFFETAP__PRE                                        0x0

#define VSB_TOP_FIRSTLARGFFETAPADDR__A                                      0x1C1005C
#define VSB_TOP_FIRSTLARGFFETAPADDR__W                                      11
#define VSB_TOP_FIRSTLARGFFETAPADDR__M                                      0x7FF
#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE                                    0x0

#define VSB_TOP_SECONDLARGFFETAP__A                                         0x1C1005D
#define VSB_TOP_SECONDLARGFFETAP__W                                         12
#define VSB_TOP_SECONDLARGFFETAP__M                                         0xFFF
#define VSB_TOP_SECONDLARGFFETAP__PRE                                       0x0

#define VSB_TOP_SECONDLARGFFETAPADDR__A                                     0x1C1005E
#define VSB_TOP_SECONDLARGFFETAPADDR__W                                     11
#define VSB_TOP_SECONDLARGFFETAPADDR__M                                     0x7FF
#define VSB_TOP_SECONDLARGFFETAPADDR__PRE                                   0x0

#define VSB_TOP_FIRSTLARGDFETAP__A                                          0x1C1005F
#define VSB_TOP_FIRSTLARGDFETAP__W                                          12
#define VSB_TOP_FIRSTLARGDFETAP__M                                          0xFFF
#define VSB_TOP_FIRSTLARGDFETAP__PRE                                        0x0

#define VSB_TOP_FIRSTLARGDFETAPADDR__A                                      0x1C10060
#define VSB_TOP_FIRSTLARGDFETAPADDR__W                                      11
#define VSB_TOP_FIRSTLARGDFETAPADDR__M                                      0x7FF
#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE                                    0x0

#define VSB_TOP_SECONDLARGDFETAP__A                                         0x1C10061
#define VSB_TOP_SECONDLARGDFETAP__W                                         12
#define VSB_TOP_SECONDLARGDFETAP__M                                         0xFFF
#define VSB_TOP_SECONDLARGDFETAP__PRE                                       0x0

#define VSB_TOP_SECONDLARGDFETAPADDR__A                                     0x1C10062
#define VSB_TOP_SECONDLARGDFETAPADDR__W                                     11
#define VSB_TOP_SECONDLARGDFETAPADDR__M                                     0x7FF
#define VSB_TOP_SECONDLARGDFETAPADDR__PRE                                   0x0

#define VSB_TOP_PARAOWDBUS__A                                               0x1C10063
#define VSB_TOP_PARAOWDBUS__W                                               12
#define VSB_TOP_PARAOWDBUS__M                                               0xFFF
#define VSB_TOP_PARAOWDBUS__PRE                                             0x0
#define VSB_TOP_PARAOWCTRL__A                                               0x1C10064
#define VSB_TOP_PARAOWCTRL__W                                               7
#define VSB_TOP_PARAOWCTRL__M                                               0x7F
#define VSB_TOP_PARAOWCTRL__PRE                                             0x0

#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__B                                  0
#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__W                                  6
#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__M                                  0x3F
#define   VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE                                0x0

#define   VSB_TOP_PARAOWCTRL_PARAOWEN__B                                    6
#define   VSB_TOP_PARAOWCTRL_PARAOWEN__W                                    1
#define   VSB_TOP_PARAOWCTRL_PARAOWEN__M                                    0x40
#define   VSB_TOP_PARAOWCTRL_PARAOWEN__PRE                                  0x0

#define VSB_TOP_CURRENTSEGLOCAT__A                                          0x1C10065
#define VSB_TOP_CURRENTSEGLOCAT__W                                          10
#define VSB_TOP_CURRENTSEGLOCAT__M                                          0x3FF
#define VSB_TOP_CURRENTSEGLOCAT__PRE                                        0x0

#define VSB_TOP_MEASUREMENT_PERIOD__A                                       0x1C10066
#define VSB_TOP_MEASUREMENT_PERIOD__W                                       16
#define VSB_TOP_MEASUREMENT_PERIOD__M                                       0xFFFF
#define VSB_TOP_MEASUREMENT_PERIOD__PRE                                     0x0

#define VSB_TOP_NR_SYM_ERRS__A                                              0x1C10067
#define VSB_TOP_NR_SYM_ERRS__W                                              16
#define VSB_TOP_NR_SYM_ERRS__M                                              0xFFFF
#define VSB_TOP_NR_SYM_ERRS__PRE                                            0xFFFF

#define VSB_TOP_ERR_ENERGY_L__A                                             0x1C10068
#define VSB_TOP_ERR_ENERGY_L__W                                             16
#define VSB_TOP_ERR_ENERGY_L__M                                             0xFFFF
#define VSB_TOP_ERR_ENERGY_L__PRE                                           0xFFFF

#define VSB_TOP_ERR_ENERGY_H__A                                             0x1C10069
#define VSB_TOP_ERR_ENERGY_H__W                                             16
#define VSB_TOP_ERR_ENERGY_H__M                                             0xFFFF
#define VSB_TOP_ERR_ENERGY_H__PRE                                           0xFFFF

#define VSB_TOP_SLICER_SEL_8LEV__A                                          0x1C1006A
#define VSB_TOP_SLICER_SEL_8LEV__W                                          1
#define VSB_TOP_SLICER_SEL_8LEV__M                                          0x1
#define VSB_TOP_SLICER_SEL_8LEV__PRE                                        0x1

#define VSB_TOP_BNFIELD__A                                                  0x1C1006B
#define VSB_TOP_BNFIELD__W                                                  3
#define VSB_TOP_BNFIELD__M                                                  0x7
#define VSB_TOP_BNFIELD__PRE                                                0x3

#define VSB_TOP_CLPLASTNUM__A                                               0x1C1006C
#define VSB_TOP_CLPLASTNUM__W                                               8
#define VSB_TOP_CLPLASTNUM__M                                               0xFF
#define VSB_TOP_CLPLASTNUM__PRE                                             0x0

#define VSB_TOP_BNSQERR__A                                                  0x1C1006D
#define VSB_TOP_BNSQERR__W                                                  16
#define VSB_TOP_BNSQERR__M                                                  0xFFFF
#define VSB_TOP_BNSQERR__PRE                                                0x1AD

#define VSB_TOP_BNTHRESH__A                                                 0x1C1006E
#define VSB_TOP_BNTHRESH__W                                                 9
#define VSB_TOP_BNTHRESH__M                                                 0x1FF
#define VSB_TOP_BNTHRESH__PRE                                               0x120

#define VSB_TOP_BNCLPNUM__A                                                 0x1C1006F
#define VSB_TOP_BNCLPNUM__W                                                 16
#define VSB_TOP_BNCLPNUM__M                                                 0xFFFF
#define VSB_TOP_BNCLPNUM__PRE                                               0x0
#define VSB_TOP_PHASELOCKCTRL__A                                            0x1C10070
#define VSB_TOP_PHASELOCKCTRL__W                                            7
#define VSB_TOP_PHASELOCKCTRL__M                                            0x7F
#define VSB_TOP_PHASELOCKCTRL__PRE                                          0x0

#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B                           0
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W                           1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M                           0x1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE                         0x0

#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B                                1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W                                1
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M                                0x2
#define   VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE                              0x0

#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B                           2
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W                           1
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M                           0x4
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE                         0x0

#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B                                3
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W                                1
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M                                0x8
#define   VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE                              0x0

#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B                           4
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W                           1
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M                           0x10
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE                         0x0

#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B                                5
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W                                1
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M                                0x20
#define   VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE                              0x0

#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__B                                 6
#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__W                                 1
#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__M                                 0x40
#define   VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE                               0x0

#define VSB_TOP_DLOCKACCUM__A                                               0x1C10071
#define VSB_TOP_DLOCKACCUM__W                                               16
#define VSB_TOP_DLOCKACCUM__M                                               0xFFFF
#define VSB_TOP_DLOCKACCUM__PRE                                             0x0

#define VSB_TOP_PLOCKACCUM__A                                               0x1C10072
#define VSB_TOP_PLOCKACCUM__W                                               16
#define VSB_TOP_PLOCKACCUM__M                                               0xFFFF
#define VSB_TOP_PLOCKACCUM__PRE                                             0x0

#define VSB_TOP_CLOCKACCUM__A                                               0x1C10073
#define VSB_TOP_CLOCKACCUM__W                                               16
#define VSB_TOP_CLOCKACCUM__M                                               0xFFFF
#define VSB_TOP_CLOCKACCUM__PRE                                             0x0

#define VSB_TOP_DCRMVACUMI__A                                               0x1C10074
#define VSB_TOP_DCRMVACUMI__W                                               10
#define VSB_TOP_DCRMVACUMI__M                                               0x3FF
#define VSB_TOP_DCRMVACUMI__PRE                                             0x0

#define VSB_TOP_DCRMVACUMQ__A                                               0x1C10075
#define VSB_TOP_DCRMVACUMQ__W                                               10
#define VSB_TOP_DCRMVACUMQ__M                                               0x3FF
#define VSB_TOP_DCRMVACUMQ__PRE                                             0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A                                0x1C20000
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A                                0x1C20001
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A                                0x1C20002
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A                                0x1C20003
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A                                0x1C20004
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A                                0x1C20005
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A                                0x1C20006
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A                                0x1C20007
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A                                0x1C20008
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W                                12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M                                0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE                              0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A                               0x1C20009
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W                               12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M                               0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE                             0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A                               0x1C2000A
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W                               12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M                               0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE                             0x0

#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A                               0x1C2000B
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W                               12
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M                               0xFFF
#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE                             0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A                            0x1C2000C
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A                            0x1C2000D
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A                            0x1C2000E
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A                            0x1C2000F
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A                            0x1C20010
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A                            0x1C20011
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A                            0x1C20012
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A                            0x1C20013
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A                            0x1C20014
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A                           0x1C20015
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A                           0x1C20016
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A                           0x1C20017
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A                             0x1C20018
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A                             0x1C20019
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A                             0x1C2001A
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A                             0x1C2001B
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A                             0x1C2001C
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A                             0x1C2001D
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A                             0x1C2001E
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A                             0x1C2001F
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A                             0x1C20020
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A                            0x1C20021
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A                            0x1C20022
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A                            0x1C20023
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A                            0x1C20024
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A                            0x1C20025
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A                            0x1C20026
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A                            0x1C20027
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A                            0x1C20028
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A                            0x1C20029
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A                            0x1C2002A
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A                            0x1C2002B
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A                            0x1C2002C
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A                           0x1C2002D
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A                           0x1C2002E
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A                           0x1C2002F
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A                             0x1C20030
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A                             0x1C20031
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A                             0x1C20032
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A                             0x1C20033
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A                             0x1C20034
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A                             0x1C20035
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A                             0x1C20036
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A                             0x1C20037
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A                             0x1C20038
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A                            0x1C20039
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A                            0x1C2003A
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A                            0x1C2003B
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A                            0x1C2003C
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A                            0x1C2003D
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A                            0x1C2003E
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A                            0x1C2003F
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A                            0x1C20040
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A                            0x1C20041
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A                            0x1C20042
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A                            0x1C20043
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A                            0x1C20044
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A                           0x1C20045
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A                           0x1C20046
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A                           0x1C20047
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A                             0x1C20048
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A                             0x1C20049
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A                             0x1C2004A
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A                             0x1C2004B
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A                             0x1C2004C
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A                             0x1C2004D
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A                             0x1C2004E
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A                             0x1C2004F
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A                             0x1C20050
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A                            0x1C20051
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A                            0x1C20052
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A                            0x1C20053
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A                            0x1C20054
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A                            0x1C20055
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A                            0x1C20056
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A                            0x1C20057
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A                            0x1C20058
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A                            0x1C20059
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A                            0x1C2005A
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A                            0x1C2005B
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A                            0x1C2005C
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A                           0x1C2005D
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A                           0x1C2005E
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A                           0x1C2005F
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W                           12
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M                           0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE                         0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A                             0x1C20060
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A                             0x1C20061
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A                             0x1C20062
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A                             0x1C20063
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A                             0x1C20064
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A                             0x1C20065
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A                             0x1C20066
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A                             0x1C20067
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A                             0x1C20068
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W                             12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M                             0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE                           0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A                            0x1C20069
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A                            0x1C2006A
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A                            0x1C2006B
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W                            12
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M                            0xFFF
#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE                          0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A                                   0x1C2006C
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A                                   0x1C2006D
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A                                   0x1C2006E
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A                                   0x1C2006F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A                                   0x1C20070
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A                                   0x1C20071
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A                                   0x1C20072
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A                                   0x1C20073
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A                                   0x1C20074
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W                                   7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M                                   0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE                                 0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A                                  0x1C20075
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W                                  7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M                                  0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE                                0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A                                  0x1C20076
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W                                  7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M                                  0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE                                0x0

#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A                                  0x1C20077
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W                                  7
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M                                  0x7F
#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE                                0x0
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A                                    0x1C20078
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A                                    0x1C20079
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A                                    0x1C2007A
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A                                    0x1C2007B
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A                                    0x1C2007C
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A                                    0x1C2007D
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A                                    0x1C2007E
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A                                    0x1C2007F
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W                                    15
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A                                    0x1C30000
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A                                   0x1C30001
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A                                   0x1C30002
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A                                   0x1C30003
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A                                    0x1C30004
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A                                    0x1C30005
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A                                    0x1C30006
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A                                    0x1C30007
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A                                    0x1C30008
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A                                    0x1C30009
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A                                    0x1C3000A
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A                                    0x1C3000B
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A                                    0x1C3000C
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A                                   0x1C3000D
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A                                   0x1C3000E
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A                                   0x1C3000F
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A                                    0x1C30010
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A                                    0x1C30011
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A                                    0x1C30012
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A                                    0x1C30013
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A                                    0x1C30014
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A                                    0x1C30015
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A                                    0x1C30016
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A                                    0x1C30017
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A                                    0x1C30018
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A                                   0x1C30019
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A                                   0x1C3001A
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A                                   0x1C3001B
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A                                    0x1C3001C
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A                                    0x1C3001D
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A                                    0x1C3001E
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A                                    0x1C3001F
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A                                    0x1C30020
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A                                    0x1C30021
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A                                    0x1C30022
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2DATAGAIN7__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__A                                    0x1C30023
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN8__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2TRAINGAIN8__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN8_FIRDDM2DATAGAIN8__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__A                                    0x1C30024
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__W                                    15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__M                                    0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN9__PRE                                  0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__B                0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__W                7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__M                0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2TRAINGAIN9__PRE              0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__B                 8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__W                 7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__M                 0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN9_FIRDDM2DATAGAIN9__PRE               0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__A                                   0x1C30025
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN10__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2TRAINGAIN10__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN10_FIRDDM2DATAGAIN10__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__A                                   0x1C30026
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN11__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2TRAINGAIN11__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN11_FIRDDM2DATAGAIN11__PRE             0x0

#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__A                                   0x1C30027
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__W                                   15
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__M                                   0x7FFF
#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN12__PRE                                 0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__B              0
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__W              7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__M              0x7F
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2TRAINGAIN12__PRE            0x0

#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__B               8
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__W               7
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__M               0x7F00
#define   VSB_SYSCTRL_RAM1_FIRDDM2GAIN12_FIRDDM2DATAGAIN12__PRE             0x0

#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__A                                 0x1C30028
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__W                                 12
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__M                                 0xFFF
#define VSB_SYSCTRL_RAM1_DFETRAINLKRATIO__PRE                               0x0

#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__A                             0x1C30029
#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA1TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__A                              0x1C3002A
#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA1DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__A                             0x1C3002B
#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA2TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__A                              0x1C3002C
#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFERCA2DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__A                             0x1C3002D
#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM1TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__A                              0x1C3002E
#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM1DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__A                             0x1C3002F
#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__W                             12
#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__M                             0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM2TRAINLKRATIO__PRE                           0x0

#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__A                              0x1C30030
#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__W                              12
#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__M                              0xFFF
#define VSB_SYSCTRL_RAM1_DFEDDM2DATALKRATIO__PRE                            0x0

#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__A                                    0x1C30031
#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__W                                    7
#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__M                                    0x7F
#define VSB_SYSCTRL_RAM1_DFETRAINGAIN__PRE                                  0x0
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__A                                     0x1C30032
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFERCA1GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFERCA1GAIN_DFERCA1DATAGAIN__PRE                 0x0

#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__A                                     0x1C30033
#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFERCA2GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFERCA2GAIN_DFERCA2DATAGAIN__PRE                 0x0

#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__A                                     0x1C30034
#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFEDDM1GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFEDDM1GAIN_DFEDDM1DATAGAIN__PRE                 0x0

#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__A                                     0x1C30035
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__W                                     15
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__M                                     0x7FFF
#define VSB_SYSCTRL_RAM1_DFEDDM2GAIN__PRE                                   0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__B                  0
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__W                  7
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__M                  0x7F
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2TRAINGAIN__PRE                0x0

#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__B                   8
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__W                   7
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__M                   0x7F00
#define   VSB_SYSCTRL_RAM1_DFEDDM2GAIN_DFEDDM2DATAGAIN__PRE                 0x0

#define VSB_TCMEQ_RAM__A                                                    0x1C40000

#define   VSB_TCMEQ_RAM_TCMEQ_RAM__B                                        0
#define   VSB_TCMEQ_RAM_TCMEQ_RAM__W                                        16
#define   VSB_TCMEQ_RAM_TCMEQ_RAM__M                                        0xFFFF
#define   VSB_TCMEQ_RAM_TCMEQ_RAM__PRE                                      0x0

#define VSB_FCPRE_RAM__A                                                    0x1C50000

#define   VSB_FCPRE_RAM_FCPRE_RAM__B                                        0
#define   VSB_FCPRE_RAM_FCPRE_RAM__W                                        16
#define   VSB_FCPRE_RAM_FCPRE_RAM__M                                        0xFFFF
#define   VSB_FCPRE_RAM_FCPRE_RAM__PRE                                      0x0

#define VSB_EQTAP_RAM__A                                                    0x1C60000

#define   VSB_EQTAP_RAM_EQTAP_RAM__B                                        0
#define   VSB_EQTAP_RAM_EQTAP_RAM__W                                        12
#define   VSB_EQTAP_RAM_EQTAP_RAM__M                                        0xFFF
#define   VSB_EQTAP_RAM_EQTAP_RAM__PRE                                      0x0

#endif