Kconfig 11 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menuconfig MAILBOX
  3. bool "Mailbox Hardware Support"
  4. help
  5. Mailbox is a framework to control hardware communication between
  6. on-chip processors through queued messages and interrupt driven
  7. signals. Say Y if your platform supports hardware mailboxes.
  8. if MAILBOX
  9. config APPLE_MAILBOX
  10. tristate "Apple Mailbox driver"
  11. depends on ARCH_APPLE || (ARM64 && COMPILE_TEST)
  12. default ARCH_APPLE
  13. help
  14. Apple SoCs have various co-processors required for certain
  15. peripherals to work (NVMe, display controller, etc.). This
  16. driver adds support for the mailbox controller used to
  17. communicate with those.
  18. Say Y here if you have a Apple SoC.
  19. config ARM_MHU
  20. tristate "ARM MHU Mailbox"
  21. depends on ARM_AMBA
  22. help
  23. Say Y here if you want to build the ARM MHU controller driver.
  24. The controller has 3 mailbox channels, the last of which can be
  25. used in Secure mode only.
  26. config ARM_MHU_V2
  27. tristate "ARM MHUv2 Mailbox"
  28. depends on ARM_AMBA
  29. help
  30. Say Y here if you want to build the ARM MHUv2 controller driver,
  31. which provides unidirectional mailboxes between processing elements.
  32. config IMX_MBOX
  33. tristate "i.MX Mailbox"
  34. depends on ARCH_MXC || COMPILE_TEST
  35. help
  36. Mailbox implementation for i.MX Messaging Unit (MU).
  37. config PLATFORM_MHU
  38. tristate "Platform MHU Mailbox"
  39. depends on OF
  40. depends on HAS_IOMEM
  41. help
  42. Say Y here if you want to build a platform specific variant MHU
  43. controller driver.
  44. The controller has a maximum of 3 mailbox channels, the last of
  45. which can be used in Secure mode only.
  46. config PL320_MBOX
  47. bool "ARM PL320 Mailbox"
  48. depends on ARM_AMBA
  49. help
  50. An implementation of the ARM PL320 Interprocessor Communication
  51. Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
  52. send short messages between Highbank's A9 cores and the EnergyCore
  53. Management Engine, primarily for cpufreq. Say Y here if you want
  54. to use the PL320 IPCM support.
  55. config ARMADA_37XX_RWTM_MBOX
  56. tristate "Armada 37xx rWTM BIU Mailbox"
  57. depends on ARCH_MVEBU || COMPILE_TEST
  58. depends on OF
  59. help
  60. Mailbox implementation for communication with the the firmware
  61. running on the Cortex-M3 rWTM secure processor of the Armada 37xx
  62. SOC. Say Y here if you are building for such a device (for example
  63. the Turris Mox router).
  64. config OMAP2PLUS_MBOX
  65. tristate "OMAP2+ Mailbox framework support"
  66. depends on ARCH_OMAP2PLUS || ARCH_K3
  67. help
  68. Mailbox implementation for OMAP family chips with hardware for
  69. interprocessor communication involving DSP, IVA1.0 and IVA2 in
  70. OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
  71. want to use OMAP2+ Mailbox framework support.
  72. config OMAP_MBOX_KFIFO_SIZE
  73. int "Mailbox kfifo default buffer size (bytes)"
  74. depends on OMAP2PLUS_MBOX
  75. default 256
  76. help
  77. Specify the default size of mailbox's kfifo buffers (bytes).
  78. This can also be changed at runtime (via the mbox_kfifo_size
  79. module parameter).
  80. config ROCKCHIP_MBOX
  81. bool "Rockchip Soc Integrated Mailbox Support"
  82. depends on ARCH_ROCKCHIP || COMPILE_TEST
  83. help
  84. This driver provides support for inter-processor communication
  85. between CPU cores and MCU processor on Some Rockchip SOCs.
  86. Please check it that the Soc you use have Mailbox hardware.
  87. Say Y here if you want to use the Rockchip Mailbox support.
  88. config PCC
  89. bool "Platform Communication Channel Driver"
  90. depends on ACPI
  91. default n
  92. help
  93. ACPI 5.0+ spec defines a generic mode of communication
  94. between the OS and a platform such as the BMC. This medium
  95. (PCC) is typically used by CPPC (ACPI CPU Performance management),
  96. RAS (ACPI reliability protocol) and MPST (ACPI Memory power
  97. states). Select this driver if your platform implements the
  98. PCC clients mentioned above.
  99. config ALTERA_MBOX
  100. tristate "Altera Mailbox"
  101. depends on HAS_IOMEM
  102. help
  103. An implementation of the Altera Mailbox soft core. It is used
  104. to send message between processors. Say Y here if you want to use the
  105. Altera mailbox support.
  106. config BCM2835_MBOX
  107. tristate "BCM2835 Mailbox"
  108. depends on ARCH_BCM2835
  109. help
  110. An implementation of the BCM2385 Mailbox. It is used to invoke
  111. the services of the Videocore. Say Y here if you want to use the
  112. BCM2835 Mailbox.
  113. config STI_MBOX
  114. tristate "STI Mailbox framework support"
  115. depends on ARCH_STI && OF
  116. help
  117. Mailbox implementation for STMicroelectonics family chips with
  118. hardware for interprocessor communication.
  119. config TI_MESSAGE_MANAGER
  120. tristate "Texas Instruments Message Manager Driver"
  121. depends on ARCH_KEYSTONE || ARCH_K3
  122. help
  123. An implementation of Message Manager slave driver for Keystone
  124. and K3 architecture SoCs from Texas Instruments. Message Manager
  125. is a communication entity found on few of Texas Instrument's keystone
  126. and K3 architecture SoCs. These may be used for communication between
  127. multiple processors within the SoC. Select this driver if your
  128. platform has support for the hardware block.
  129. config HI3660_MBOX
  130. tristate "Hi3660 Mailbox" if EXPERT
  131. depends on (ARCH_HISI || COMPILE_TEST)
  132. depends on OF
  133. default ARCH_HISI
  134. help
  135. An implementation of the hi3660 mailbox. It is used to send message
  136. between application processors and other processors/MCU/DSP. Select
  137. Y here if you want to use Hi3660 mailbox controller.
  138. config HI6220_MBOX
  139. tristate "Hi6220 Mailbox" if EXPERT
  140. depends on (ARCH_HISI || COMPILE_TEST)
  141. depends on OF
  142. default ARCH_HISI
  143. help
  144. An implementation of the hi6220 mailbox. It is used to send message
  145. between application processors and MCU. Say Y here if you want to
  146. build Hi6220 mailbox controller driver.
  147. config MAILBOX_TEST
  148. tristate "Mailbox Test Client"
  149. depends on OF
  150. depends on HAS_IOMEM
  151. help
  152. Test client to help with testing new Controller driver
  153. implementations.
  154. config POLARFIRE_SOC_MAILBOX
  155. tristate "PolarFire SoC (MPFS) Mailbox"
  156. depends on HAS_IOMEM
  157. depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
  158. help
  159. This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
  160. To compile this driver as a module, choose M here. the
  161. module will be called mailbox-mpfs.
  162. If unsure, say N.
  163. config QCOM_APCS_IPC
  164. tristate "Qualcomm APCS IPC driver"
  165. depends on ARCH_QCOM || COMPILE_TEST
  166. help
  167. Say y here to enable support for the APCS IPC mailbox driver,
  168. providing an interface for invoking the inter-process communication
  169. signals from the application processor to other masters.
  170. config TEGRA_HSP_MBOX
  171. bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
  172. depends on ARCH_TEGRA
  173. help
  174. The Tegra HSP driver is used for the interprocessor communication
  175. between different remote processors and host processors on Tegra186
  176. and later SoCs. Say Y here if you want to have this support.
  177. If unsure say N.
  178. config XGENE_SLIMPRO_MBOX
  179. tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
  180. depends on ARCH_XGENE
  181. help
  182. An implementation of the APM X-Gene Interprocessor Communication
  183. Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
  184. It is used to send short messages between ARM64-bit cores and
  185. the SLIMpro Management Engine, primarily for PM. Say Y here if you
  186. want to use the APM X-Gene SLIMpro IPCM support.
  187. config BCM_PDC_MBOX
  188. tristate "Broadcom FlexSparx DMA Mailbox"
  189. depends on ARCH_BCM_IPROC || COMPILE_TEST
  190. help
  191. Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
  192. which provides access to various offload engines on Broadcom
  193. SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
  194. config BCM_FLEXRM_MBOX
  195. tristate "Broadcom FlexRM Mailbox"
  196. depends on ARM64
  197. depends on ARCH_BCM_IPROC || COMPILE_TEST
  198. select GENERIC_MSI_IRQ_DOMAIN
  199. default m if ARCH_BCM_IPROC
  200. help
  201. Mailbox implementation of the Broadcom FlexRM ring manager,
  202. which provides access to various offload engines on Broadcom
  203. SoCs. Say Y here if you want to use the Broadcom FlexRM.
  204. config STM32_IPCC
  205. tristate "STM32 IPCC Mailbox"
  206. depends on MACH_STM32MP157 || COMPILE_TEST
  207. help
  208. Mailbox implementation for STMicroelectonics STM32 family chips
  209. with hardware for Inter-Processor Communication Controller (IPCC)
  210. between processors. Say Y here if you want to have this support.
  211. config MTK_ADSP_MBOX
  212. tristate "MediaTek ADSP Mailbox Controller"
  213. depends on ARCH_MEDIATEK || COMPILE_TEST
  214. help
  215. Say yes here to add support for "MediaTek ADSP Mailbox Controller.
  216. This mailbox driver is used to send notification or short message
  217. between processors with ADSP. It will place the message to share
  218. buffer and will access the ipc control.
  219. config MTK_CMDQ_MBOX
  220. tristate "MediaTek CMDQ Mailbox Support"
  221. depends on ARCH_MEDIATEK || COMPILE_TEST
  222. select MTK_INFRACFG
  223. help
  224. Say yes here to add support for the MediaTek Command Queue (CMDQ)
  225. mailbox driver. The CMDQ is used to help read/write registers with
  226. critical time limitation, such as updating display configuration
  227. during the vblank.
  228. config ZYNQMP_IPI_MBOX
  229. bool "Xilinx ZynqMP IPI Mailbox"
  230. depends on ARCH_ZYNQMP && OF
  231. help
  232. Say yes here to add support for Xilinx IPI mailbox driver.
  233. This mailbox driver is used to send notification or short message
  234. between processors with Xilinx ZynqMP IPI. It will place the
  235. message to the IPI buffer and will access the IPI control
  236. registers to kick the other processor or enquire status.
  237. config SUN6I_MSGBOX
  238. tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"
  239. depends on ARCH_SUNXI || COMPILE_TEST
  240. default ARCH_SUNXI
  241. help
  242. Mailbox implementation for the hardware message box present in
  243. various Allwinner SoCs. This mailbox is used for communication
  244. between the application CPUs and the power management coprocessor.
  245. config SPRD_MBOX
  246. tristate "Spreadtrum Mailbox"
  247. depends on ARCH_SPRD || COMPILE_TEST
  248. help
  249. Mailbox driver implementation for the Spreadtrum platform. It is used
  250. to send message between application processors and MCU. Say Y here if
  251. you want to build the Spreatrum mailbox controller driver.
  252. config QCOM_IPCC
  253. tristate "Qualcomm Technologies, Inc. IPCC driver"
  254. depends on ARCH_QCOM || COMPILE_TEST
  255. help
  256. Qualcomm Technologies, Inc. Inter-Processor Communication Controller
  257. (IPCC) driver for MSM devices. The driver provides mailbox support for
  258. sending interrupts to the clients. On the other hand, the driver also
  259. acts as an interrupt controller for receiving interrupts from clients.
  260. Say Y here if you want to build this driver.
  261. config MSM_QMP
  262. tristate "QTI Mailbox Protocol(QMP)"
  263. help
  264. Say yes to add support for the QTI Mailbox Protocol mailbox driver.
  265. QMP is a lightweight communication protocol for sending messages to
  266. a remote processor. This protocol fits into the Generic Mailbox
  267. Framework. QMP uses a mailbox located in shared memory.
  268. endif