Kconfig 17 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. menu "IRQ chip support"
  3. config IRQCHIP
  4. def_bool y
  5. depends on (OF_IRQ || ACPI_GENERIC_GSI)
  6. config ARM_GIC
  7. bool
  8. select IRQ_DOMAIN_HIERARCHY
  9. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  10. config ARM_GIC_PM
  11. bool
  12. depends on PM
  13. select ARM_GIC
  14. config ARM_GIC_MAX_NR
  15. int
  16. depends on ARM_GIC
  17. default 2 if ARCH_REALVIEW
  18. default 1
  19. config ARM_GIC_V2M
  20. bool
  21. depends on PCI
  22. select ARM_GIC
  23. select PCI_MSI
  24. config GIC_NON_BANKED
  25. bool
  26. config ARM_GIC_V3
  27. bool
  28. select IRQ_DOMAIN_HIERARCHY
  29. select PARTITION_PERCPU
  30. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  31. config ARM_GIC_V3_ITS
  32. bool
  33. select GENERIC_MSI_IRQ_DOMAIN
  34. default ARM_GIC_V3
  35. config ARM_GIC_V3_ITS_PCI
  36. bool
  37. depends on ARM_GIC_V3_ITS
  38. depends on PCI
  39. depends on PCI_MSI
  40. default ARM_GIC_V3_ITS
  41. config ARM_GIC_V3_ITS_FSL_MC
  42. bool
  43. depends on ARM_GIC_V3_ITS
  44. depends on FSL_MC_BUS
  45. default ARM_GIC_V3_ITS
  46. config ARM_NVIC
  47. bool
  48. select IRQ_DOMAIN_HIERARCHY
  49. select GENERIC_IRQ_CHIP
  50. config ARM_VIC
  51. bool
  52. select IRQ_DOMAIN
  53. config ARM_VIC_NR
  54. int
  55. default 4 if ARCH_S5PV210
  56. default 2
  57. depends on ARM_VIC
  58. help
  59. The maximum number of VICs available in the system, for
  60. power management.
  61. config ARMADA_370_XP_IRQ
  62. bool
  63. select GENERIC_IRQ_CHIP
  64. select PCI_MSI if PCI
  65. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  66. config ALPINE_MSI
  67. bool
  68. depends on PCI
  69. select PCI_MSI
  70. select GENERIC_IRQ_CHIP
  71. config AL_FIC
  72. bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
  73. depends on OF || COMPILE_TEST
  74. select GENERIC_IRQ_CHIP
  75. select IRQ_DOMAIN
  76. help
  77. Support Amazon's Annapurna Labs Fabric Interrupt Controller.
  78. config ATMEL_AIC_IRQ
  79. bool
  80. select GENERIC_IRQ_CHIP
  81. select IRQ_DOMAIN
  82. select SPARSE_IRQ
  83. config ATMEL_AIC5_IRQ
  84. bool
  85. select GENERIC_IRQ_CHIP
  86. select IRQ_DOMAIN
  87. select SPARSE_IRQ
  88. config I8259
  89. bool
  90. select IRQ_DOMAIN
  91. config BCM6345_L1_IRQ
  92. bool
  93. select GENERIC_IRQ_CHIP
  94. select IRQ_DOMAIN
  95. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  96. config BCM7038_L1_IRQ
  97. tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
  98. depends on ARCH_BRCMSTB || BMIPS_GENERIC
  99. default ARCH_BRCMSTB || BMIPS_GENERIC
  100. select GENERIC_IRQ_CHIP
  101. select IRQ_DOMAIN
  102. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  103. config BCM7120_L2_IRQ
  104. tristate "Broadcom STB 7120-style L2 interrupt controller driver"
  105. depends on ARCH_BRCMSTB || BMIPS_GENERIC
  106. default ARCH_BRCMSTB || BMIPS_GENERIC
  107. select GENERIC_IRQ_CHIP
  108. select IRQ_DOMAIN
  109. config BRCMSTB_L2_IRQ
  110. tristate "Broadcom STB generic L2 interrupt controller driver"
  111. depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
  112. default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
  113. select GENERIC_IRQ_CHIP
  114. select IRQ_DOMAIN
  115. config DAVINCI_AINTC
  116. bool
  117. select GENERIC_IRQ_CHIP
  118. select IRQ_DOMAIN
  119. config DAVINCI_CP_INTC
  120. bool
  121. select GENERIC_IRQ_CHIP
  122. select IRQ_DOMAIN
  123. config DW_APB_ICTL
  124. bool
  125. select GENERIC_IRQ_CHIP
  126. select IRQ_DOMAIN_HIERARCHY
  127. config FARADAY_FTINTC010
  128. bool
  129. select IRQ_DOMAIN
  130. select SPARSE_IRQ
  131. config HISILICON_IRQ_MBIGEN
  132. bool
  133. select ARM_GIC_V3
  134. select ARM_GIC_V3_ITS
  135. config IMGPDC_IRQ
  136. bool
  137. select GENERIC_IRQ_CHIP
  138. select IRQ_DOMAIN
  139. config IXP4XX_IRQ
  140. bool
  141. select IRQ_DOMAIN
  142. select SPARSE_IRQ
  143. config MADERA_IRQ
  144. tristate
  145. config IRQ_MIPS_CPU
  146. bool
  147. select GENERIC_IRQ_CHIP
  148. select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
  149. select IRQ_DOMAIN
  150. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  151. config CLPS711X_IRQCHIP
  152. bool
  153. depends on ARCH_CLPS711X
  154. select IRQ_DOMAIN
  155. select SPARSE_IRQ
  156. default y
  157. config OMPIC
  158. bool
  159. config OR1K_PIC
  160. bool
  161. select IRQ_DOMAIN
  162. config OMAP_IRQCHIP
  163. bool
  164. select GENERIC_IRQ_CHIP
  165. select IRQ_DOMAIN
  166. config ORION_IRQCHIP
  167. bool
  168. select IRQ_DOMAIN
  169. config PIC32_EVIC
  170. bool
  171. select GENERIC_IRQ_CHIP
  172. select IRQ_DOMAIN
  173. config JCORE_AIC
  174. bool "J-Core integrated AIC" if COMPILE_TEST
  175. depends on OF
  176. select IRQ_DOMAIN
  177. help
  178. Support for the J-Core integrated AIC.
  179. config RDA_INTC
  180. bool
  181. select IRQ_DOMAIN
  182. config RENESAS_INTC_IRQPIN
  183. bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
  184. select IRQ_DOMAIN
  185. help
  186. Enable support for the Renesas Interrupt Controller for external
  187. interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
  188. config RENESAS_IRQC
  189. bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
  190. select GENERIC_IRQ_CHIP
  191. select IRQ_DOMAIN
  192. help
  193. Enable support for the Renesas Interrupt Controller for external
  194. devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
  195. config RENESAS_RZA1_IRQC
  196. bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
  197. select IRQ_DOMAIN_HIERARCHY
  198. help
  199. Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
  200. to 8 external interrupts with configurable sense select.
  201. config RENESAS_RZG2L_IRQC
  202. bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
  203. select GENERIC_IRQ_CHIP
  204. select IRQ_DOMAIN_HIERARCHY
  205. help
  206. Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
  207. for external devices.
  208. config SL28CPLD_INTC
  209. bool "Kontron sl28cpld IRQ controller"
  210. depends on MFD_SL28CPLD=y || COMPILE_TEST
  211. select REGMAP_IRQ
  212. help
  213. Interrupt controller driver for the board management controller
  214. found on the Kontron sl28 CPLD.
  215. config ST_IRQCHIP
  216. bool
  217. select REGMAP
  218. select MFD_SYSCON
  219. help
  220. Enables SysCfg Controlled IRQs on STi based platforms.
  221. config SUN4I_INTC
  222. bool
  223. config SUN6I_R_INTC
  224. bool
  225. select IRQ_DOMAIN_HIERARCHY
  226. select IRQ_FASTEOI_HIERARCHY_HANDLERS
  227. config SUNXI_NMI_INTC
  228. bool
  229. select GENERIC_IRQ_CHIP
  230. config TB10X_IRQC
  231. bool
  232. select IRQ_DOMAIN
  233. select GENERIC_IRQ_CHIP
  234. config TS4800_IRQ
  235. tristate "TS-4800 IRQ controller"
  236. select IRQ_DOMAIN
  237. depends on HAS_IOMEM
  238. depends on SOC_IMX51 || COMPILE_TEST
  239. help
  240. Support for the TS-4800 FPGA IRQ controller
  241. config VERSATILE_FPGA_IRQ
  242. bool
  243. select IRQ_DOMAIN
  244. config VERSATILE_FPGA_IRQ_NR
  245. int
  246. default 4
  247. depends on VERSATILE_FPGA_IRQ
  248. config XTENSA_MX
  249. bool
  250. select IRQ_DOMAIN
  251. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  252. config XILINX_INTC
  253. bool "Xilinx Interrupt Controller IP"
  254. depends on OF_ADDRESS
  255. select IRQ_DOMAIN
  256. help
  257. Support for the Xilinx Interrupt Controller IP core.
  258. This is used as a primary controller with MicroBlaze and can also
  259. be used as a secondary chained controller on other platforms.
  260. config IRQ_CROSSBAR
  261. bool
  262. help
  263. Support for a CROSSBAR ip that precedes the main interrupt controller.
  264. The primary irqchip invokes the crossbar's callback which inturn allocates
  265. a free irq and configures the IP. Thus the peripheral interrupts are
  266. routed to one of the free irqchip interrupt lines.
  267. config KEYSTONE_IRQ
  268. tristate "Keystone 2 IRQ controller IP"
  269. depends on ARCH_KEYSTONE
  270. help
  271. Support for Texas Instruments Keystone 2 IRQ controller IP which
  272. is part of the Keystone 2 IPC mechanism
  273. config MIPS_GIC
  274. bool
  275. select GENERIC_IRQ_IPI if SMP
  276. select IRQ_DOMAIN_HIERARCHY
  277. select MIPS_CM
  278. config INGENIC_IRQ
  279. bool
  280. depends on MACH_INGENIC
  281. default y
  282. config INGENIC_TCU_IRQ
  283. bool "Ingenic JZ47xx TCU interrupt controller"
  284. default MACH_INGENIC
  285. depends on MIPS || COMPILE_TEST
  286. select MFD_SYSCON
  287. select GENERIC_IRQ_CHIP
  288. help
  289. Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
  290. JZ47xx SoCs.
  291. If unsure, say N.
  292. config IMX_GPCV2
  293. bool
  294. select IRQ_DOMAIN
  295. help
  296. Enables the wakeup IRQs for IMX platforms with GPCv2 block
  297. config IRQ_MXS
  298. def_bool y if MACH_ASM9260 || ARCH_MXS
  299. select IRQ_DOMAIN
  300. select STMP_DEVICE
  301. config MSCC_OCELOT_IRQ
  302. bool
  303. select IRQ_DOMAIN
  304. select GENERIC_IRQ_CHIP
  305. config MVEBU_GICP
  306. bool
  307. config MVEBU_ICU
  308. bool
  309. config MVEBU_ODMI
  310. bool
  311. select GENERIC_MSI_IRQ_DOMAIN
  312. config MVEBU_PIC
  313. bool
  314. config MVEBU_SEI
  315. bool
  316. config LS_EXTIRQ
  317. def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
  318. select MFD_SYSCON
  319. config LS_SCFG_MSI
  320. def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
  321. depends on PCI && PCI_MSI
  322. config PARTITION_PERCPU
  323. bool
  324. config STM32_EXTI
  325. bool
  326. select IRQ_DOMAIN
  327. select GENERIC_IRQ_CHIP
  328. config QCOM_IRQ_COMBINER
  329. bool "QCOM IRQ combiner support"
  330. depends on ARCH_QCOM && ACPI
  331. select IRQ_DOMAIN_HIERARCHY
  332. help
  333. Say yes here to add support for the IRQ combiner devices embedded
  334. in Qualcomm Technologies chips.
  335. config IRQ_UNIPHIER_AIDET
  336. bool "UniPhier AIDET support" if COMPILE_TEST
  337. depends on ARCH_UNIPHIER || COMPILE_TEST
  338. default ARCH_UNIPHIER
  339. select IRQ_DOMAIN_HIERARCHY
  340. help
  341. Support for the UniPhier AIDET (ARM Interrupt Detector).
  342. config MESON_IRQ_GPIO
  343. tristate "Meson GPIO Interrupt Multiplexer"
  344. depends on ARCH_MESON || COMPILE_TEST
  345. default ARCH_MESON
  346. select IRQ_DOMAIN_HIERARCHY
  347. help
  348. Support Meson SoC Family GPIO Interrupt Multiplexer
  349. config GOLDFISH_PIC
  350. bool "Goldfish programmable interrupt controller"
  351. depends on MIPS && (GOLDFISH || COMPILE_TEST)
  352. select GENERIC_IRQ_CHIP
  353. select IRQ_DOMAIN
  354. help
  355. Say yes here to enable Goldfish interrupt controller driver used
  356. for Goldfish based virtual platforms.
  357. config MPM_LEGACY
  358. tristate "MPM_LEGACY"
  359. depends on ARCH_QCOM
  360. select IRQ_DOMAIN
  361. select IRQ_DOMAIN_HIERARCHY
  362. help
  363. MSM Power Manager driver to manage and configure wakeup
  364. IRQs for Legacy Qualcomm Technologies Inc (QTI) mobile chips.
  365. Say yes here to enable the MSM Power Manager interrupt
  366. controller to use as a wakeup interrupt controller.
  367. config QCOM_PDC
  368. tristate "QCOM PDC"
  369. depends on ARCH_QCOM
  370. select IRQ_DOMAIN_HIERARCHY
  371. help
  372. Power Domain Controller driver to manage and configure wakeup
  373. IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
  374. config QCOM_SHOW_RESUME_IRQ
  375. tristate "Enable logging of interrupts that could have caused resume"
  376. depends on PM
  377. depends on ARM_GIC || ARM_GIC_V3
  378. help
  379. This option logs wake up interrupts that have triggered just before
  380. the resume loop unrolls. It helps to debug to know any unnecessary
  381. wake up interrupts that causes system to come out of low power modes.
  382. Say Y if you want to debug why the system resumed.
  383. config QCOM_MPM
  384. tristate "QCOM MPM"
  385. depends on ARCH_QCOM
  386. depends on MAILBOX
  387. select IRQ_DOMAIN_HIERARCHY
  388. help
  389. MSM Power Manager driver to manage and configure wakeup
  390. IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
  391. config CSKY_MPINTC
  392. bool
  393. depends on CSKY
  394. help
  395. Say yes here to enable C-SKY SMP interrupt controller driver used
  396. for C-SKY SMP system.
  397. In fact it's not mmio map in hardware and it uses ld/st to visit the
  398. controller's register inside CPU.
  399. config CSKY_APB_INTC
  400. bool "C-SKY APB Interrupt Controller"
  401. depends on CSKY
  402. help
  403. Say yes here to enable C-SKY APB interrupt controller driver used
  404. by C-SKY single core SOC system. It uses mmio map apb-bus to visit
  405. the controller's register.
  406. config IMX_IRQSTEER
  407. bool "i.MX IRQSTEER support"
  408. depends on ARCH_MXC || COMPILE_TEST
  409. default ARCH_MXC
  410. select IRQ_DOMAIN
  411. help
  412. Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
  413. config IMX_INTMUX
  414. bool "i.MX INTMUX support" if COMPILE_TEST
  415. default y if ARCH_MXC
  416. select IRQ_DOMAIN
  417. help
  418. Support for the i.MX INTMUX interrupt multiplexer.
  419. config IMX_MU_MSI
  420. tristate "i.MX MU used as MSI controller"
  421. depends on OF && HAS_IOMEM
  422. depends on ARCH_MXC || COMPILE_TEST
  423. default m if ARCH_MXC
  424. select IRQ_DOMAIN
  425. select IRQ_DOMAIN_HIERARCHY
  426. select GENERIC_MSI_IRQ_DOMAIN
  427. help
  428. Provide a driver for the i.MX Messaging Unit block used as a
  429. CPU-to-CPU MSI controller. This requires a specially crafted DT
  430. to make use of this driver.
  431. If unsure, say N
  432. config LS1X_IRQ
  433. bool "Loongson-1 Interrupt Controller"
  434. depends on MACH_LOONGSON32
  435. default y
  436. select IRQ_DOMAIN
  437. select GENERIC_IRQ_CHIP
  438. help
  439. Support for the Loongson-1 platform Interrupt Controller.
  440. config TI_SCI_INTR_IRQCHIP
  441. bool
  442. depends on TI_SCI_PROTOCOL
  443. select IRQ_DOMAIN_HIERARCHY
  444. help
  445. This enables the irqchip driver support for K3 Interrupt router
  446. over TI System Control Interface available on some new TI's SoCs.
  447. If you wish to use interrupt router irq resources managed by the
  448. TI System Controller, say Y here. Otherwise, say N.
  449. config TI_SCI_INTA_IRQCHIP
  450. bool
  451. depends on TI_SCI_PROTOCOL
  452. select IRQ_DOMAIN_HIERARCHY
  453. select TI_SCI_INTA_MSI_DOMAIN
  454. help
  455. This enables the irqchip driver support for K3 Interrupt aggregator
  456. over TI System Control Interface available on some new TI's SoCs.
  457. If you wish to use interrupt aggregator irq resources managed by the
  458. TI System Controller, say Y here. Otherwise, say N.
  459. config TI_PRUSS_INTC
  460. tristate
  461. depends on TI_PRUSS
  462. default TI_PRUSS
  463. select IRQ_DOMAIN
  464. help
  465. This enables support for the PRU-ICSS Local Interrupt Controller
  466. present within a PRU-ICSS subsystem present on various TI SoCs.
  467. The PRUSS INTC enables various interrupts to be routed to multiple
  468. different processors within the SoC.
  469. config RISCV_INTC
  470. bool "RISC-V Local Interrupt Controller"
  471. depends on RISCV
  472. default y
  473. help
  474. This enables support for the per-HART local interrupt controller
  475. found in standard RISC-V systems. The per-HART local interrupt
  476. controller handles timer interrupts, software interrupts, and
  477. hardware interrupts. Without a per-HART local interrupt controller,
  478. a RISC-V system will be unable to handle any interrupts.
  479. If you don't know what to do here, say Y.
  480. config SIFIVE_PLIC
  481. bool "SiFive Platform-Level Interrupt Controller"
  482. depends on RISCV
  483. select IRQ_DOMAIN_HIERARCHY
  484. select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
  485. help
  486. This enables support for the PLIC chip found in SiFive (and
  487. potentially other) RISC-V systems. The PLIC controls devices
  488. interrupts and connects them to each core's local interrupt
  489. controller. Aside from timer and software interrupts, all other
  490. interrupt sources are subordinate to the PLIC.
  491. If you don't know what to do here, say Y.
  492. config EXYNOS_IRQ_COMBINER
  493. bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
  494. depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
  495. help
  496. Say yes here to add support for the IRQ combiner devices embedded
  497. in Samsung Exynos chips.
  498. config IRQ_LOONGARCH_CPU
  499. bool
  500. select GENERIC_IRQ_CHIP
  501. select IRQ_DOMAIN
  502. select GENERIC_IRQ_EFFECTIVE_AFF_MASK
  503. select LOONGSON_LIOINTC
  504. select LOONGSON_EIOINTC
  505. select LOONGSON_PCH_PIC
  506. select LOONGSON_PCH_MSI
  507. select LOONGSON_PCH_LPC
  508. help
  509. Support for the LoongArch CPU Interrupt Controller. For details of
  510. irq chip hierarchy on LoongArch platforms please read the document
  511. Documentation/loongarch/irq-chip-model.rst.
  512. config LOONGSON_LIOINTC
  513. bool "Loongson Local I/O Interrupt Controller"
  514. depends on MACH_LOONGSON64
  515. default y
  516. select IRQ_DOMAIN
  517. select GENERIC_IRQ_CHIP
  518. help
  519. Support for the Loongson Local I/O Interrupt Controller.
  520. config LOONGSON_EIOINTC
  521. bool "Loongson Extend I/O Interrupt Controller"
  522. depends on LOONGARCH
  523. depends on MACH_LOONGSON64
  524. default MACH_LOONGSON64
  525. select IRQ_DOMAIN_HIERARCHY
  526. select GENERIC_IRQ_CHIP
  527. help
  528. Support for the Loongson3 Extend I/O Interrupt Vector Controller.
  529. config LOONGSON_HTPIC
  530. bool "Loongson3 HyperTransport PIC Controller"
  531. depends on MACH_LOONGSON64 && MIPS
  532. default y
  533. select IRQ_DOMAIN
  534. select GENERIC_IRQ_CHIP
  535. help
  536. Support for the Loongson-3 HyperTransport PIC Controller.
  537. config LOONGSON_HTVEC
  538. bool "Loongson HyperTransport Interrupt Vector Controller"
  539. depends on MACH_LOONGSON64
  540. default MACH_LOONGSON64
  541. select IRQ_DOMAIN_HIERARCHY
  542. help
  543. Support for the Loongson HyperTransport Interrupt Vector Controller.
  544. config LOONGSON_PCH_PIC
  545. bool "Loongson PCH PIC Controller"
  546. depends on MACH_LOONGSON64
  547. default MACH_LOONGSON64
  548. select IRQ_DOMAIN_HIERARCHY
  549. select IRQ_FASTEOI_HIERARCHY_HANDLERS
  550. help
  551. Support for the Loongson PCH PIC Controller.
  552. config LOONGSON_PCH_MSI
  553. bool "Loongson PCH MSI Controller"
  554. depends on MACH_LOONGSON64
  555. depends on PCI
  556. default MACH_LOONGSON64
  557. select IRQ_DOMAIN_HIERARCHY
  558. select PCI_MSI
  559. help
  560. Support for the Loongson PCH MSI Controller.
  561. config LOONGSON_PCH_LPC
  562. bool "Loongson PCH LPC Controller"
  563. depends on LOONGARCH
  564. depends on MACH_LOONGSON64
  565. default MACH_LOONGSON64
  566. select IRQ_DOMAIN_HIERARCHY
  567. help
  568. Support for the Loongson PCH LPC Controller.
  569. config MST_IRQ
  570. bool "MStar Interrupt Controller"
  571. depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
  572. default ARCH_MEDIATEK
  573. select IRQ_DOMAIN
  574. select IRQ_DOMAIN_HIERARCHY
  575. help
  576. Support MStar Interrupt Controller.
  577. config WPCM450_AIC
  578. bool "Nuvoton WPCM450 Advanced Interrupt Controller"
  579. depends on ARCH_WPCM450
  580. help
  581. Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
  582. config IRQ_IDT3243X
  583. bool
  584. select GENERIC_IRQ_CHIP
  585. select IRQ_DOMAIN
  586. config APPLE_AIC
  587. bool "Apple Interrupt Controller (AIC)"
  588. depends on ARM64
  589. depends on ARCH_APPLE || COMPILE_TEST
  590. help
  591. Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
  592. such as the M1.
  593. config MCHP_EIC
  594. bool "Microchip External Interrupt Controller"
  595. depends on ARCH_AT91 || COMPILE_TEST
  596. select IRQ_DOMAIN
  597. select IRQ_DOMAIN_HIERARCHY
  598. help
  599. Support for Microchip External Interrupt Controller.
  600. config SUNPLUS_SP7021_INTC
  601. bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
  602. default SOC_SP7021
  603. help
  604. Support for the Sunplus SP7021 Interrupt Controller IP core.
  605. SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
  606. chained controller, routing all interrupt source in P-Chip to
  607. the primary controller on C-Chip.
  608. endmenu