imx8mm.c 3.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Interconnect framework driver for i.MX8MM SoC
  4. *
  5. * Copyright (c) 2019, BayLibre
  6. * Copyright (c) 2019-2020, NXP
  7. * Author: Alexandre Bailon <[email protected]>
  8. * Author: Leonard Crestez <[email protected]>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <dt-bindings/interconnect/imx8mm.h>
  13. #include "imx.h"
  14. static const struct imx_icc_node_adj_desc imx8mm_dram_adj = {
  15. .bw_mul = 1,
  16. .bw_div = 16,
  17. .phandle_name = "fsl,ddrc",
  18. };
  19. static const struct imx_icc_node_adj_desc imx8mm_noc_adj = {
  20. .bw_mul = 1,
  21. .bw_div = 16,
  22. .main_noc = true,
  23. };
  24. /*
  25. * Describe bus masters, slaves and connections between them
  26. *
  27. * This is a simplified subset of the bus diagram, there are several other
  28. * PL301 nics which are skipped/merged into PL301_MAIN
  29. */
  30. static struct imx_icc_node_desc nodes[] = {
  31. DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj,
  32. IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN),
  33. DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj),
  34. DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL),
  35. DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC),
  36. /* VPUMIX */
  37. DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO),
  38. DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO),
  39. DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO),
  40. DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC),
  41. /* GPUMIX */
  42. DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU),
  43. DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU),
  44. DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC),
  45. /* DISPLAYMIX */
  46. DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI),
  47. DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI),
  48. DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC),
  49. /* HSIO */
  50. DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO),
  51. DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO),
  52. DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO),
  53. DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC),
  54. /* Audio */
  55. DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO),
  56. DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO),
  57. DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN),
  58. /* Ethernet */
  59. DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET),
  60. DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN),
  61. /* Other */
  62. DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN),
  63. DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN),
  64. DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN),
  65. DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN),
  66. DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN),
  67. DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL,
  68. IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM),
  69. };
  70. static int imx8mm_icc_probe(struct platform_device *pdev)
  71. {
  72. return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes), NULL);
  73. }
  74. static int imx8mm_icc_remove(struct platform_device *pdev)
  75. {
  76. imx_icc_unregister(pdev);
  77. return 0;
  78. }
  79. static struct platform_driver imx8mm_icc_driver = {
  80. .probe = imx8mm_icc_probe,
  81. .remove = imx8mm_icc_remove,
  82. .driver = {
  83. .name = "imx8mm-interconnect",
  84. },
  85. };
  86. module_platform_driver(imx8mm_icc_driver);
  87. MODULE_AUTHOR("Alexandre Bailon <[email protected]>");
  88. MODULE_LICENSE("GPL v2");
  89. MODULE_ALIAS("platform:imx8mm-interconnect");