lpc32xx_ts.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * LPC32xx built-in touchscreen driver
  4. *
  5. * Copyright (C) 2010 NXP Semiconductors
  6. */
  7. #include <linux/platform_device.h>
  8. #include <linux/input.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/module.h>
  11. #include <linux/clk.h>
  12. #include <linux/io.h>
  13. #include <linux/slab.h>
  14. #include <linux/of.h>
  15. /*
  16. * Touchscreen controller register offsets
  17. */
  18. #define LPC32XX_TSC_STAT 0x00
  19. #define LPC32XX_TSC_SEL 0x04
  20. #define LPC32XX_TSC_CON 0x08
  21. #define LPC32XX_TSC_FIFO 0x0C
  22. #define LPC32XX_TSC_DTR 0x10
  23. #define LPC32XX_TSC_RTR 0x14
  24. #define LPC32XX_TSC_UTR 0x18
  25. #define LPC32XX_TSC_TTR 0x1C
  26. #define LPC32XX_TSC_DXP 0x20
  27. #define LPC32XX_TSC_MIN_X 0x24
  28. #define LPC32XX_TSC_MAX_X 0x28
  29. #define LPC32XX_TSC_MIN_Y 0x2C
  30. #define LPC32XX_TSC_MAX_Y 0x30
  31. #define LPC32XX_TSC_AUX_UTR 0x34
  32. #define LPC32XX_TSC_AUX_MIN 0x38
  33. #define LPC32XX_TSC_AUX_MAX 0x3C
  34. #define LPC32XX_TSC_STAT_FIFO_OVRRN BIT(8)
  35. #define LPC32XX_TSC_STAT_FIFO_EMPTY BIT(7)
  36. #define LPC32XX_TSC_SEL_DEFVAL 0x0284
  37. #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11)
  38. #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
  39. #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
  40. #define LPC32XX_TSC_ADCCON_POWER_UP BIT(2)
  41. #define LPC32XX_TSC_ADCCON_AUTO_EN BIT(0)
  42. #define LPC32XX_TSC_FIFO_TS_P_LEVEL BIT(31)
  43. #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16)
  44. #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF)
  45. #define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
  46. #define LPC32XX_TSC_MIN_XY_VAL 0x0
  47. #define LPC32XX_TSC_MAX_XY_VAL 0x3FF
  48. #define MOD_NAME "ts-lpc32xx"
  49. #define tsc_readl(dev, reg) \
  50. __raw_readl((dev)->tsc_base + (reg))
  51. #define tsc_writel(dev, reg, val) \
  52. __raw_writel((val), (dev)->tsc_base + (reg))
  53. struct lpc32xx_tsc {
  54. struct input_dev *dev;
  55. void __iomem *tsc_base;
  56. int irq;
  57. struct clk *clk;
  58. };
  59. static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc)
  60. {
  61. while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) &
  62. LPC32XX_TSC_STAT_FIFO_EMPTY))
  63. tsc_readl(tsc, LPC32XX_TSC_FIFO);
  64. }
  65. static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
  66. {
  67. u32 tmp, rv[4], xs[4], ys[4];
  68. int idx;
  69. struct lpc32xx_tsc *tsc = dev_id;
  70. struct input_dev *input = tsc->dev;
  71. tmp = tsc_readl(tsc, LPC32XX_TSC_STAT);
  72. if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
  73. /* FIFO overflow - throw away samples */
  74. lpc32xx_fifo_clear(tsc);
  75. return IRQ_HANDLED;
  76. }
  77. /*
  78. * Gather and normalize 4 samples. Pen-up events may have less
  79. * than 4 samples, but its ok to pop 4 and let the last sample
  80. * pen status check drop the samples.
  81. */
  82. idx = 0;
  83. while (idx < 4 &&
  84. !(tsc_readl(tsc, LPC32XX_TSC_STAT) &
  85. LPC32XX_TSC_STAT_FIFO_EMPTY)) {
  86. tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO);
  87. xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
  88. LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
  89. ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
  90. LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
  91. rv[idx] = tmp;
  92. idx++;
  93. }
  94. /* Data is only valid if pen is still down in last sample */
  95. if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) {
  96. /* Use average of 2nd and 3rd sample for position */
  97. input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2);
  98. input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2);
  99. input_report_key(input, BTN_TOUCH, 1);
  100. } else {
  101. input_report_key(input, BTN_TOUCH, 0);
  102. }
  103. input_sync(input);
  104. return IRQ_HANDLED;
  105. }
  106. static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc)
  107. {
  108. /* Disable auto mode */
  109. tsc_writel(tsc, LPC32XX_TSC_CON,
  110. tsc_readl(tsc, LPC32XX_TSC_CON) &
  111. ~LPC32XX_TSC_ADCCON_AUTO_EN);
  112. clk_disable_unprepare(tsc->clk);
  113. }
  114. static int lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc)
  115. {
  116. u32 tmp;
  117. int err;
  118. err = clk_prepare_enable(tsc->clk);
  119. if (err)
  120. return err;
  121. tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP;
  122. /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */
  123. tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
  124. LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
  125. LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10);
  126. tsc_writel(tsc, LPC32XX_TSC_CON, tmp);
  127. /* These values are all preset */
  128. tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL);
  129. tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL);
  130. tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL);
  131. tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL);
  132. tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL);
  133. /* Aux support is not used */
  134. tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0);
  135. tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0);
  136. tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0);
  137. /*
  138. * Set sample rate to about 240Hz per X/Y pair. A single measurement
  139. * consists of 4 pairs which gives about a 60Hz sample rate based on
  140. * a stable 32768Hz clock source. Values are in clocks.
  141. * Rate is (32768 / (RTR + XCONV + RTR + YCONV + DXP + TTR + UTR) / 4
  142. */
  143. tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2);
  144. tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2);
  145. tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10);
  146. tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4);
  147. tsc_writel(tsc, LPC32XX_TSC_UTR, 88);
  148. lpc32xx_fifo_clear(tsc);
  149. /* Enable automatic ts event capture */
  150. tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN);
  151. return 0;
  152. }
  153. static int lpc32xx_ts_open(struct input_dev *dev)
  154. {
  155. struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
  156. return lpc32xx_setup_tsc(tsc);
  157. }
  158. static void lpc32xx_ts_close(struct input_dev *dev)
  159. {
  160. struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
  161. lpc32xx_stop_tsc(tsc);
  162. }
  163. static int lpc32xx_ts_probe(struct platform_device *pdev)
  164. {
  165. struct lpc32xx_tsc *tsc;
  166. struct input_dev *input;
  167. struct resource *res;
  168. resource_size_t size;
  169. int irq;
  170. int error;
  171. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  172. if (!res) {
  173. dev_err(&pdev->dev, "Can't get memory resource\n");
  174. return -ENOENT;
  175. }
  176. irq = platform_get_irq(pdev, 0);
  177. if (irq < 0)
  178. return irq;
  179. tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
  180. input = input_allocate_device();
  181. if (!tsc || !input) {
  182. dev_err(&pdev->dev, "failed allocating memory\n");
  183. error = -ENOMEM;
  184. goto err_free_mem;
  185. }
  186. tsc->dev = input;
  187. tsc->irq = irq;
  188. size = resource_size(res);
  189. if (!request_mem_region(res->start, size, pdev->name)) {
  190. dev_err(&pdev->dev, "TSC registers are not free\n");
  191. error = -EBUSY;
  192. goto err_free_mem;
  193. }
  194. tsc->tsc_base = ioremap(res->start, size);
  195. if (!tsc->tsc_base) {
  196. dev_err(&pdev->dev, "Can't map memory\n");
  197. error = -ENOMEM;
  198. goto err_release_mem;
  199. }
  200. tsc->clk = clk_get(&pdev->dev, NULL);
  201. if (IS_ERR(tsc->clk)) {
  202. dev_err(&pdev->dev, "failed getting clock\n");
  203. error = PTR_ERR(tsc->clk);
  204. goto err_unmap;
  205. }
  206. input->name = MOD_NAME;
  207. input->phys = "lpc32xx/input0";
  208. input->id.bustype = BUS_HOST;
  209. input->id.vendor = 0x0001;
  210. input->id.product = 0x0002;
  211. input->id.version = 0x0100;
  212. input->dev.parent = &pdev->dev;
  213. input->open = lpc32xx_ts_open;
  214. input->close = lpc32xx_ts_close;
  215. input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
  216. input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
  217. input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL,
  218. LPC32XX_TSC_MAX_XY_VAL, 0, 0);
  219. input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL,
  220. LPC32XX_TSC_MAX_XY_VAL, 0, 0);
  221. input_set_drvdata(input, tsc);
  222. error = request_irq(tsc->irq, lpc32xx_ts_interrupt,
  223. 0, pdev->name, tsc);
  224. if (error) {
  225. dev_err(&pdev->dev, "failed requesting interrupt\n");
  226. goto err_put_clock;
  227. }
  228. error = input_register_device(input);
  229. if (error) {
  230. dev_err(&pdev->dev, "failed registering input device\n");
  231. goto err_free_irq;
  232. }
  233. platform_set_drvdata(pdev, tsc);
  234. device_init_wakeup(&pdev->dev, 1);
  235. return 0;
  236. err_free_irq:
  237. free_irq(tsc->irq, tsc);
  238. err_put_clock:
  239. clk_put(tsc->clk);
  240. err_unmap:
  241. iounmap(tsc->tsc_base);
  242. err_release_mem:
  243. release_mem_region(res->start, size);
  244. err_free_mem:
  245. input_free_device(input);
  246. kfree(tsc);
  247. return error;
  248. }
  249. static int lpc32xx_ts_remove(struct platform_device *pdev)
  250. {
  251. struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev);
  252. struct resource *res;
  253. free_irq(tsc->irq, tsc);
  254. input_unregister_device(tsc->dev);
  255. clk_put(tsc->clk);
  256. iounmap(tsc->tsc_base);
  257. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  258. release_mem_region(res->start, resource_size(res));
  259. kfree(tsc);
  260. return 0;
  261. }
  262. #ifdef CONFIG_PM
  263. static int lpc32xx_ts_suspend(struct device *dev)
  264. {
  265. struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
  266. struct input_dev *input = tsc->dev;
  267. /*
  268. * Suspend and resume can be called when the device hasn't been
  269. * enabled. If there are no users that have the device open, then
  270. * avoid calling the TSC stop and start functions as the TSC
  271. * isn't yet clocked.
  272. */
  273. mutex_lock(&input->mutex);
  274. if (input_device_enabled(input)) {
  275. if (device_may_wakeup(dev))
  276. enable_irq_wake(tsc->irq);
  277. else
  278. lpc32xx_stop_tsc(tsc);
  279. }
  280. mutex_unlock(&input->mutex);
  281. return 0;
  282. }
  283. static int lpc32xx_ts_resume(struct device *dev)
  284. {
  285. struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
  286. struct input_dev *input = tsc->dev;
  287. mutex_lock(&input->mutex);
  288. if (input_device_enabled(input)) {
  289. if (device_may_wakeup(dev))
  290. disable_irq_wake(tsc->irq);
  291. else
  292. lpc32xx_setup_tsc(tsc);
  293. }
  294. mutex_unlock(&input->mutex);
  295. return 0;
  296. }
  297. static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
  298. .suspend = lpc32xx_ts_suspend,
  299. .resume = lpc32xx_ts_resume,
  300. };
  301. #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
  302. #else
  303. #define LPC32XX_TS_PM_OPS NULL
  304. #endif
  305. #ifdef CONFIG_OF
  306. static const struct of_device_id lpc32xx_tsc_of_match[] = {
  307. { .compatible = "nxp,lpc3220-tsc", },
  308. { },
  309. };
  310. MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match);
  311. #endif
  312. static struct platform_driver lpc32xx_ts_driver = {
  313. .probe = lpc32xx_ts_probe,
  314. .remove = lpc32xx_ts_remove,
  315. .driver = {
  316. .name = MOD_NAME,
  317. .pm = LPC32XX_TS_PM_OPS,
  318. .of_match_table = of_match_ptr(lpc32xx_tsc_of_match),
  319. },
  320. };
  321. module_platform_driver(lpc32xx_ts_driver);
  322. MODULE_AUTHOR("Kevin Wells <[email protected]");
  323. MODULE_DESCRIPTION("LPC32XX TSC Driver");
  324. MODULE_LICENSE("GPL");
  325. MODULE_ALIAS("platform:lpc32xx_ts");