ltc2688.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * LTC2688 16 channel, 16 bit Voltage Output SoftSpan DAC driver
  4. *
  5. * Copyright 2022 Analog Devices Inc.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/bits.h>
  9. #include <linux/clk.h>
  10. #include <linux/device.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/iio/iio.h>
  13. #include <linux/limits.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/mod_devicetable.h>
  17. #include <linux/mutex.h>
  18. #include <linux/of.h>
  19. #include <linux/property.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/spi/spi.h>
  23. #define LTC2688_DAC_CHANNELS 16
  24. #define LTC2688_CMD_CH_CODE(x) (0x00 + (x))
  25. #define LTC2688_CMD_CH_SETTING(x) (0x10 + (x))
  26. #define LTC2688_CMD_CH_OFFSET(x) (0X20 + (x))
  27. #define LTC2688_CMD_CH_GAIN(x) (0x30 + (x))
  28. #define LTC2688_CMD_CH_CODE_UPDATE(x) (0x40 + (x))
  29. #define LTC2688_CMD_CONFIG 0x70
  30. #define LTC2688_CMD_POWERDOWN 0x71
  31. #define LTC2688_CMD_A_B_SELECT 0x72
  32. #define LTC2688_CMD_SW_TOGGLE 0x73
  33. #define LTC2688_CMD_TOGGLE_DITHER_EN 0x74
  34. #define LTC2688_CMD_THERMAL_STAT 0x77
  35. #define LTC2688_CMD_UPDATE_ALL 0x7C
  36. #define LTC2688_CMD_NOOP 0xFF
  37. #define LTC2688_READ_OPERATION 0x80
  38. /* Channel Settings */
  39. #define LTC2688_CH_SPAN_MSK GENMASK(2, 0)
  40. #define LTC2688_CH_OVERRANGE_MSK BIT(3)
  41. #define LTC2688_CH_TD_SEL_MSK GENMASK(5, 4)
  42. #define LTC2688_CH_TGP_MAX 3
  43. #define LTC2688_CH_DIT_PER_MSK GENMASK(8, 6)
  44. #define LTC2688_CH_DIT_PH_MSK GENMASK(10, 9)
  45. #define LTC2688_CH_MODE_MSK BIT(11)
  46. #define LTC2688_DITHER_RAW_MASK GENMASK(15, 2)
  47. #define LTC2688_CH_CALIBBIAS_MASK GENMASK(15, 2)
  48. #define LTC2688_DITHER_RAW_MAX_VAL (BIT(14) - 1)
  49. #define LTC2688_CH_CALIBBIAS_MAX_VAL (BIT(14) - 1)
  50. /* Configuration register */
  51. #define LTC2688_CONFIG_RST BIT(15)
  52. #define LTC2688_CONFIG_EXT_REF BIT(1)
  53. #define LTC2688_DITHER_FREQ_AVAIL_N 5
  54. enum {
  55. LTC2688_SPAN_RANGE_0V_5V,
  56. LTC2688_SPAN_RANGE_0V_10V,
  57. LTC2688_SPAN_RANGE_M5V_5V,
  58. LTC2688_SPAN_RANGE_M10V_10V,
  59. LTC2688_SPAN_RANGE_M15V_15V,
  60. LTC2688_SPAN_RANGE_MAX
  61. };
  62. enum {
  63. LTC2688_MODE_DEFAULT,
  64. LTC2688_MODE_DITHER_TOGGLE,
  65. };
  66. struct ltc2688_chan {
  67. long dither_frequency[LTC2688_DITHER_FREQ_AVAIL_N];
  68. bool overrange;
  69. bool toggle_chan;
  70. u8 mode;
  71. };
  72. struct ltc2688_state {
  73. struct spi_device *spi;
  74. struct regmap *regmap;
  75. struct regulator_bulk_data regulators[2];
  76. struct ltc2688_chan channels[LTC2688_DAC_CHANNELS];
  77. struct iio_chan_spec *iio_chan;
  78. /* lock to protect against multiple access to the device and shared data */
  79. struct mutex lock;
  80. int vref;
  81. /*
  82. * DMA (thus cache coherency maintenance) may require the
  83. * transfer buffers to live in their own cache lines.
  84. */
  85. u8 tx_data[6] __aligned(IIO_DMA_MINALIGN);
  86. u8 rx_data[3];
  87. };
  88. static int ltc2688_spi_read(void *context, const void *reg, size_t reg_size,
  89. void *val, size_t val_size)
  90. {
  91. struct ltc2688_state *st = context;
  92. struct spi_transfer xfers[] = {
  93. {
  94. .tx_buf = st->tx_data,
  95. .bits_per_word = 8,
  96. .len = reg_size + val_size,
  97. .cs_change = 1,
  98. }, {
  99. .tx_buf = st->tx_data + 3,
  100. .rx_buf = st->rx_data,
  101. .bits_per_word = 8,
  102. .len = reg_size + val_size,
  103. },
  104. };
  105. int ret;
  106. memcpy(st->tx_data, reg, reg_size);
  107. ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
  108. if (ret)
  109. return ret;
  110. memcpy(val, &st->rx_data[1], val_size);
  111. return 0;
  112. }
  113. static int ltc2688_spi_write(void *context, const void *data, size_t count)
  114. {
  115. struct ltc2688_state *st = context;
  116. return spi_write(st->spi, data, count);
  117. }
  118. static int ltc2688_span_get(const struct ltc2688_state *st, int c)
  119. {
  120. int ret, reg, span;
  121. ret = regmap_read(st->regmap, LTC2688_CMD_CH_SETTING(c), &reg);
  122. if (ret)
  123. return ret;
  124. span = FIELD_GET(LTC2688_CH_SPAN_MSK, reg);
  125. /* sanity check to make sure we don't get any weird value from the HW */
  126. if (span >= LTC2688_SPAN_RANGE_MAX)
  127. return -EIO;
  128. return span;
  129. }
  130. static const int ltc2688_span_helper[LTC2688_SPAN_RANGE_MAX][2] = {
  131. {0, 5000}, {0, 10000}, {-5000, 5000}, {-10000, 10000}, {-15000, 15000},
  132. };
  133. static int ltc2688_scale_get(const struct ltc2688_state *st, int c, int *val)
  134. {
  135. const struct ltc2688_chan *chan = &st->channels[c];
  136. int span, fs;
  137. span = ltc2688_span_get(st, c);
  138. if (span < 0)
  139. return span;
  140. fs = ltc2688_span_helper[span][1] - ltc2688_span_helper[span][0];
  141. if (chan->overrange)
  142. fs = mult_frac(fs, 105, 100);
  143. *val = DIV_ROUND_CLOSEST(fs * st->vref, 4096);
  144. return 0;
  145. }
  146. static int ltc2688_offset_get(const struct ltc2688_state *st, int c, int *val)
  147. {
  148. int span;
  149. span = ltc2688_span_get(st, c);
  150. if (span < 0)
  151. return span;
  152. if (ltc2688_span_helper[span][0] < 0)
  153. *val = -32768;
  154. else
  155. *val = 0;
  156. return 0;
  157. }
  158. enum {
  159. LTC2688_INPUT_A,
  160. LTC2688_INPUT_B,
  161. LTC2688_INPUT_B_AVAIL,
  162. LTC2688_DITHER_OFF,
  163. LTC2688_DITHER_FREQ_AVAIL,
  164. };
  165. static int ltc2688_dac_code_write(struct ltc2688_state *st, u32 chan, u32 input,
  166. u16 code)
  167. {
  168. struct ltc2688_chan *c = &st->channels[chan];
  169. int ret, reg;
  170. /* 2 LSBs set to 0 if writing dither amplitude */
  171. if (!c->toggle_chan && input == LTC2688_INPUT_B) {
  172. if (code > LTC2688_DITHER_RAW_MAX_VAL)
  173. return -EINVAL;
  174. code = FIELD_PREP(LTC2688_DITHER_RAW_MASK, code);
  175. }
  176. mutex_lock(&st->lock);
  177. /* select the correct input register to read from */
  178. ret = regmap_update_bits(st->regmap, LTC2688_CMD_A_B_SELECT, BIT(chan),
  179. input << chan);
  180. if (ret)
  181. goto out_unlock;
  182. /*
  183. * If in dither/toggle mode the dac should be updated by an
  184. * external signal (or sw toggle) and not here.
  185. */
  186. if (c->mode == LTC2688_MODE_DEFAULT)
  187. reg = LTC2688_CMD_CH_CODE_UPDATE(chan);
  188. else
  189. reg = LTC2688_CMD_CH_CODE(chan);
  190. ret = regmap_write(st->regmap, reg, code);
  191. out_unlock:
  192. mutex_unlock(&st->lock);
  193. return ret;
  194. }
  195. static int ltc2688_dac_code_read(struct ltc2688_state *st, u32 chan, u32 input,
  196. u32 *code)
  197. {
  198. struct ltc2688_chan *c = &st->channels[chan];
  199. int ret;
  200. mutex_lock(&st->lock);
  201. ret = regmap_update_bits(st->regmap, LTC2688_CMD_A_B_SELECT, BIT(chan),
  202. input << chan);
  203. if (ret)
  204. goto out_unlock;
  205. ret = regmap_read(st->regmap, LTC2688_CMD_CH_CODE(chan), code);
  206. out_unlock:
  207. mutex_unlock(&st->lock);
  208. if (!c->toggle_chan && input == LTC2688_INPUT_B)
  209. *code = FIELD_GET(LTC2688_DITHER_RAW_MASK, *code);
  210. return ret;
  211. }
  212. static const int ltc2688_raw_range[] = {0, 1, U16_MAX};
  213. static int ltc2688_read_avail(struct iio_dev *indio_dev,
  214. struct iio_chan_spec const *chan,
  215. const int **vals, int *type, int *length,
  216. long info)
  217. {
  218. switch (info) {
  219. case IIO_CHAN_INFO_RAW:
  220. *vals = ltc2688_raw_range;
  221. *type = IIO_VAL_INT;
  222. return IIO_AVAIL_RANGE;
  223. default:
  224. return -EINVAL;
  225. }
  226. }
  227. static int ltc2688_read_raw(struct iio_dev *indio_dev,
  228. struct iio_chan_spec const *chan, int *val,
  229. int *val2, long info)
  230. {
  231. struct ltc2688_state *st = iio_priv(indio_dev);
  232. int ret;
  233. switch (info) {
  234. case IIO_CHAN_INFO_RAW:
  235. ret = ltc2688_dac_code_read(st, chan->channel, LTC2688_INPUT_A,
  236. val);
  237. if (ret)
  238. return ret;
  239. return IIO_VAL_INT;
  240. case IIO_CHAN_INFO_OFFSET:
  241. ret = ltc2688_offset_get(st, chan->channel, val);
  242. if (ret)
  243. return ret;
  244. return IIO_VAL_INT;
  245. case IIO_CHAN_INFO_SCALE:
  246. ret = ltc2688_scale_get(st, chan->channel, val);
  247. if (ret)
  248. return ret;
  249. *val2 = 16;
  250. return IIO_VAL_FRACTIONAL_LOG2;
  251. case IIO_CHAN_INFO_CALIBBIAS:
  252. ret = regmap_read(st->regmap,
  253. LTC2688_CMD_CH_OFFSET(chan->channel), val);
  254. if (ret)
  255. return ret;
  256. *val = FIELD_GET(LTC2688_CH_CALIBBIAS_MASK, *val);
  257. return IIO_VAL_INT;
  258. case IIO_CHAN_INFO_CALIBSCALE:
  259. ret = regmap_read(st->regmap,
  260. LTC2688_CMD_CH_GAIN(chan->channel), val);
  261. if (ret)
  262. return ret;
  263. return IIO_VAL_INT;
  264. default:
  265. return -EINVAL;
  266. }
  267. }
  268. static int ltc2688_write_raw(struct iio_dev *indio_dev,
  269. struct iio_chan_spec const *chan, int val,
  270. int val2, long info)
  271. {
  272. struct ltc2688_state *st = iio_priv(indio_dev);
  273. switch (info) {
  274. case IIO_CHAN_INFO_RAW:
  275. if (val > U16_MAX || val < 0)
  276. return -EINVAL;
  277. return ltc2688_dac_code_write(st, chan->channel,
  278. LTC2688_INPUT_A, val);
  279. case IIO_CHAN_INFO_CALIBBIAS:
  280. if (val > LTC2688_CH_CALIBBIAS_MAX_VAL)
  281. return -EINVAL;
  282. return regmap_write(st->regmap,
  283. LTC2688_CMD_CH_OFFSET(chan->channel),
  284. FIELD_PREP(LTC2688_CH_CALIBBIAS_MASK, val));
  285. case IIO_CHAN_INFO_CALIBSCALE:
  286. return regmap_write(st->regmap,
  287. LTC2688_CMD_CH_GAIN(chan->channel), val);
  288. default:
  289. return -EINVAL;
  290. }
  291. }
  292. static ssize_t ltc2688_dither_toggle_set(struct iio_dev *indio_dev,
  293. uintptr_t private,
  294. const struct iio_chan_spec *chan,
  295. const char *buf, size_t len)
  296. {
  297. struct ltc2688_state *st = iio_priv(indio_dev);
  298. struct ltc2688_chan *c = &st->channels[chan->channel];
  299. int ret;
  300. bool en;
  301. ret = kstrtobool(buf, &en);
  302. if (ret)
  303. return ret;
  304. mutex_lock(&st->lock);
  305. ret = regmap_update_bits(st->regmap, LTC2688_CMD_TOGGLE_DITHER_EN,
  306. BIT(chan->channel), en << chan->channel);
  307. if (ret)
  308. goto out_unlock;
  309. c->mode = en ? LTC2688_MODE_DITHER_TOGGLE : LTC2688_MODE_DEFAULT;
  310. out_unlock:
  311. mutex_unlock(&st->lock);
  312. return ret ?: len;
  313. }
  314. static ssize_t ltc2688_reg_bool_get(struct iio_dev *indio_dev,
  315. uintptr_t private,
  316. const struct iio_chan_spec *chan,
  317. char *buf)
  318. {
  319. const struct ltc2688_state *st = iio_priv(indio_dev);
  320. int ret;
  321. u32 val;
  322. ret = regmap_read(st->regmap, private, &val);
  323. if (ret)
  324. return ret;
  325. return sysfs_emit(buf, "%u\n", !!(val & BIT(chan->channel)));
  326. }
  327. static ssize_t ltc2688_reg_bool_set(struct iio_dev *indio_dev,
  328. uintptr_t private,
  329. const struct iio_chan_spec *chan,
  330. const char *buf, size_t len)
  331. {
  332. const struct ltc2688_state *st = iio_priv(indio_dev);
  333. int ret;
  334. bool en;
  335. ret = kstrtobool(buf, &en);
  336. if (ret)
  337. return ret;
  338. ret = regmap_update_bits(st->regmap, private, BIT(chan->channel),
  339. en << chan->channel);
  340. if (ret)
  341. return ret;
  342. return len;
  343. }
  344. static ssize_t ltc2688_dither_freq_avail(const struct ltc2688_state *st,
  345. const struct ltc2688_chan *chan,
  346. char *buf)
  347. {
  348. int sz = 0;
  349. u32 f;
  350. for (f = 0; f < ARRAY_SIZE(chan->dither_frequency); f++)
  351. sz += sysfs_emit_at(buf, sz, "%ld ", chan->dither_frequency[f]);
  352. buf[sz - 1] = '\n';
  353. return sz;
  354. }
  355. static ssize_t ltc2688_dither_freq_get(struct iio_dev *indio_dev,
  356. uintptr_t private,
  357. const struct iio_chan_spec *chan,
  358. char *buf)
  359. {
  360. const struct ltc2688_state *st = iio_priv(indio_dev);
  361. const struct ltc2688_chan *c = &st->channels[chan->channel];
  362. u32 reg, freq;
  363. int ret;
  364. if (private == LTC2688_DITHER_FREQ_AVAIL)
  365. return ltc2688_dither_freq_avail(st, c, buf);
  366. ret = regmap_read(st->regmap, LTC2688_CMD_CH_SETTING(chan->channel),
  367. &reg);
  368. if (ret)
  369. return ret;
  370. freq = FIELD_GET(LTC2688_CH_DIT_PER_MSK, reg);
  371. if (freq >= ARRAY_SIZE(c->dither_frequency))
  372. return -EIO;
  373. return sysfs_emit(buf, "%ld\n", c->dither_frequency[freq]);
  374. }
  375. static ssize_t ltc2688_dither_freq_set(struct iio_dev *indio_dev,
  376. uintptr_t private,
  377. const struct iio_chan_spec *chan,
  378. const char *buf, size_t len)
  379. {
  380. const struct ltc2688_state *st = iio_priv(indio_dev);
  381. const struct ltc2688_chan *c = &st->channels[chan->channel];
  382. long val;
  383. u32 freq;
  384. int ret;
  385. if (private == LTC2688_DITHER_FREQ_AVAIL)
  386. return -EINVAL;
  387. ret = kstrtol(buf, 10, &val);
  388. if (ret)
  389. return ret;
  390. for (freq = 0; freq < ARRAY_SIZE(c->dither_frequency); freq++) {
  391. if (val == c->dither_frequency[freq])
  392. break;
  393. }
  394. if (freq == ARRAY_SIZE(c->dither_frequency))
  395. return -EINVAL;
  396. ret = regmap_update_bits(st->regmap,
  397. LTC2688_CMD_CH_SETTING(chan->channel),
  398. LTC2688_CH_DIT_PER_MSK,
  399. FIELD_PREP(LTC2688_CH_DIT_PER_MSK, freq));
  400. if (ret)
  401. return ret;
  402. return len;
  403. }
  404. static ssize_t ltc2688_dac_input_read(struct iio_dev *indio_dev,
  405. uintptr_t private,
  406. const struct iio_chan_spec *chan,
  407. char *buf)
  408. {
  409. struct ltc2688_state *st = iio_priv(indio_dev);
  410. int ret;
  411. u32 val;
  412. if (private == LTC2688_INPUT_B_AVAIL)
  413. return sysfs_emit(buf, "[%u %u %u]\n", ltc2688_raw_range[0],
  414. ltc2688_raw_range[1],
  415. ltc2688_raw_range[2] / 4);
  416. if (private == LTC2688_DITHER_OFF)
  417. return sysfs_emit(buf, "0\n");
  418. ret = ltc2688_dac_code_read(st, chan->channel, private, &val);
  419. if (ret)
  420. return ret;
  421. return sysfs_emit(buf, "%u\n", val);
  422. }
  423. static ssize_t ltc2688_dac_input_write(struct iio_dev *indio_dev,
  424. uintptr_t private,
  425. const struct iio_chan_spec *chan,
  426. const char *buf, size_t len)
  427. {
  428. struct ltc2688_state *st = iio_priv(indio_dev);
  429. int ret;
  430. u16 val;
  431. if (private == LTC2688_INPUT_B_AVAIL || private == LTC2688_DITHER_OFF)
  432. return -EINVAL;
  433. ret = kstrtou16(buf, 10, &val);
  434. if (ret)
  435. return ret;
  436. ret = ltc2688_dac_code_write(st, chan->channel, private, val);
  437. if (ret)
  438. return ret;
  439. return len;
  440. }
  441. static int ltc2688_get_dither_phase(struct iio_dev *dev,
  442. const struct iio_chan_spec *chan)
  443. {
  444. struct ltc2688_state *st = iio_priv(dev);
  445. int ret, regval;
  446. ret = regmap_read(st->regmap, LTC2688_CMD_CH_SETTING(chan->channel),
  447. &regval);
  448. if (ret)
  449. return ret;
  450. return FIELD_GET(LTC2688_CH_DIT_PH_MSK, regval);
  451. }
  452. static int ltc2688_set_dither_phase(struct iio_dev *dev,
  453. const struct iio_chan_spec *chan,
  454. unsigned int phase)
  455. {
  456. struct ltc2688_state *st = iio_priv(dev);
  457. return regmap_update_bits(st->regmap,
  458. LTC2688_CMD_CH_SETTING(chan->channel),
  459. LTC2688_CH_DIT_PH_MSK,
  460. FIELD_PREP(LTC2688_CH_DIT_PH_MSK, phase));
  461. }
  462. static int ltc2688_reg_access(struct iio_dev *indio_dev,
  463. unsigned int reg,
  464. unsigned int writeval,
  465. unsigned int *readval)
  466. {
  467. struct ltc2688_state *st = iio_priv(indio_dev);
  468. if (readval)
  469. return regmap_read(st->regmap, reg, readval);
  470. return regmap_write(st->regmap, reg, writeval);
  471. }
  472. static const char * const ltc2688_dither_phase[] = {
  473. "0", "1.5708", "3.14159", "4.71239",
  474. };
  475. static const struct iio_enum ltc2688_dither_phase_enum = {
  476. .items = ltc2688_dither_phase,
  477. .num_items = ARRAY_SIZE(ltc2688_dither_phase),
  478. .set = ltc2688_set_dither_phase,
  479. .get = ltc2688_get_dither_phase,
  480. };
  481. #define LTC2688_CHAN_EXT_INFO(_name, _what, _shared, _read, _write) { \
  482. .name = _name, \
  483. .read = (_read), \
  484. .write = (_write), \
  485. .private = (_what), \
  486. .shared = (_shared), \
  487. }
  488. /*
  489. * For toggle mode we only expose the symbol attr (sw_toggle) in case a TGPx is
  490. * not provided in dts.
  491. */
  492. static const struct iio_chan_spec_ext_info ltc2688_toggle_sym_ext_info[] = {
  493. LTC2688_CHAN_EXT_INFO("raw0", LTC2688_INPUT_A, IIO_SEPARATE,
  494. ltc2688_dac_input_read, ltc2688_dac_input_write),
  495. LTC2688_CHAN_EXT_INFO("raw1", LTC2688_INPUT_B, IIO_SEPARATE,
  496. ltc2688_dac_input_read, ltc2688_dac_input_write),
  497. LTC2688_CHAN_EXT_INFO("toggle_en", LTC2688_CMD_TOGGLE_DITHER_EN,
  498. IIO_SEPARATE, ltc2688_reg_bool_get,
  499. ltc2688_dither_toggle_set),
  500. LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
  501. ltc2688_reg_bool_get, ltc2688_reg_bool_set),
  502. LTC2688_CHAN_EXT_INFO("symbol", LTC2688_CMD_SW_TOGGLE, IIO_SEPARATE,
  503. ltc2688_reg_bool_get, ltc2688_reg_bool_set),
  504. {}
  505. };
  506. static const struct iio_chan_spec_ext_info ltc2688_toggle_ext_info[] = {
  507. LTC2688_CHAN_EXT_INFO("raw0", LTC2688_INPUT_A, IIO_SEPARATE,
  508. ltc2688_dac_input_read, ltc2688_dac_input_write),
  509. LTC2688_CHAN_EXT_INFO("raw1", LTC2688_INPUT_B, IIO_SEPARATE,
  510. ltc2688_dac_input_read, ltc2688_dac_input_write),
  511. LTC2688_CHAN_EXT_INFO("toggle_en", LTC2688_CMD_TOGGLE_DITHER_EN,
  512. IIO_SEPARATE, ltc2688_reg_bool_get,
  513. ltc2688_dither_toggle_set),
  514. LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
  515. ltc2688_reg_bool_get, ltc2688_reg_bool_set),
  516. {}
  517. };
  518. static struct iio_chan_spec_ext_info ltc2688_dither_ext_info[] = {
  519. LTC2688_CHAN_EXT_INFO("dither_raw", LTC2688_INPUT_B, IIO_SEPARATE,
  520. ltc2688_dac_input_read, ltc2688_dac_input_write),
  521. LTC2688_CHAN_EXT_INFO("dither_raw_available", LTC2688_INPUT_B_AVAIL,
  522. IIO_SEPARATE, ltc2688_dac_input_read,
  523. ltc2688_dac_input_write),
  524. LTC2688_CHAN_EXT_INFO("dither_offset", LTC2688_DITHER_OFF, IIO_SEPARATE,
  525. ltc2688_dac_input_read, ltc2688_dac_input_write),
  526. /*
  527. * Not IIO_ENUM because the available freq needs to be computed at
  528. * probe. We could still use it, but it didn't felt much right.
  529. */
  530. LTC2688_CHAN_EXT_INFO("dither_frequency", 0, IIO_SEPARATE,
  531. ltc2688_dither_freq_get, ltc2688_dither_freq_set),
  532. LTC2688_CHAN_EXT_INFO("dither_frequency_available",
  533. LTC2688_DITHER_FREQ_AVAIL, IIO_SEPARATE,
  534. ltc2688_dither_freq_get, ltc2688_dither_freq_set),
  535. IIO_ENUM("dither_phase", IIO_SEPARATE, &ltc2688_dither_phase_enum),
  536. IIO_ENUM_AVAILABLE("dither_phase", IIO_SEPARATE,
  537. &ltc2688_dither_phase_enum),
  538. LTC2688_CHAN_EXT_INFO("dither_en", LTC2688_CMD_TOGGLE_DITHER_EN,
  539. IIO_SEPARATE, ltc2688_reg_bool_get,
  540. ltc2688_dither_toggle_set),
  541. LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
  542. ltc2688_reg_bool_get, ltc2688_reg_bool_set),
  543. {}
  544. };
  545. static const struct iio_chan_spec_ext_info ltc2688_ext_info[] = {
  546. LTC2688_CHAN_EXT_INFO("powerdown", LTC2688_CMD_POWERDOWN, IIO_SEPARATE,
  547. ltc2688_reg_bool_get, ltc2688_reg_bool_set),
  548. {}
  549. };
  550. #define LTC2688_CHANNEL(_chan) { \
  551. .type = IIO_VOLTAGE, \
  552. .indexed = 1, \
  553. .output = 1, \
  554. .channel = (_chan), \
  555. .info_mask_separate = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
  556. BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) | \
  557. BIT(IIO_CHAN_INFO_CALIBBIAS) | BIT(IIO_CHAN_INFO_RAW), \
  558. .info_mask_separate_available = BIT(IIO_CHAN_INFO_RAW), \
  559. .ext_info = ltc2688_ext_info, \
  560. }
  561. static const struct iio_chan_spec ltc2688_channels[] = {
  562. LTC2688_CHANNEL(0),
  563. LTC2688_CHANNEL(1),
  564. LTC2688_CHANNEL(2),
  565. LTC2688_CHANNEL(3),
  566. LTC2688_CHANNEL(4),
  567. LTC2688_CHANNEL(5),
  568. LTC2688_CHANNEL(6),
  569. LTC2688_CHANNEL(7),
  570. LTC2688_CHANNEL(8),
  571. LTC2688_CHANNEL(9),
  572. LTC2688_CHANNEL(10),
  573. LTC2688_CHANNEL(11),
  574. LTC2688_CHANNEL(12),
  575. LTC2688_CHANNEL(13),
  576. LTC2688_CHANNEL(14),
  577. LTC2688_CHANNEL(15),
  578. };
  579. static void ltc2688_clk_disable(void *clk)
  580. {
  581. clk_disable_unprepare(clk);
  582. }
  583. static const int ltc2688_period[LTC2688_DITHER_FREQ_AVAIL_N] = {
  584. 4, 8, 16, 32, 64,
  585. };
  586. static int ltc2688_tgp_clk_setup(struct ltc2688_state *st,
  587. struct ltc2688_chan *chan,
  588. struct fwnode_handle *node, int tgp)
  589. {
  590. struct device *dev = &st->spi->dev;
  591. unsigned long rate;
  592. struct clk *clk;
  593. int ret, f;
  594. clk = devm_get_clk_from_child(dev, to_of_node(node), NULL);
  595. if (IS_ERR(clk))
  596. return dev_err_probe(dev, PTR_ERR(clk), "failed to get tgp clk.\n");
  597. ret = clk_prepare_enable(clk);
  598. if (ret)
  599. return dev_err_probe(dev, ret, "failed to enable tgp clk.\n");
  600. ret = devm_add_action_or_reset(dev, ltc2688_clk_disable, clk);
  601. if (ret)
  602. return ret;
  603. if (chan->toggle_chan)
  604. return 0;
  605. /* calculate available dither frequencies */
  606. rate = clk_get_rate(clk);
  607. for (f = 0; f < ARRAY_SIZE(chan->dither_frequency); f++)
  608. chan->dither_frequency[f] = DIV_ROUND_CLOSEST(rate, ltc2688_period[f]);
  609. return 0;
  610. }
  611. static int ltc2688_span_lookup(const struct ltc2688_state *st, int min, int max)
  612. {
  613. u32 span;
  614. for (span = 0; span < ARRAY_SIZE(ltc2688_span_helper); span++) {
  615. if (min == ltc2688_span_helper[span][0] &&
  616. max == ltc2688_span_helper[span][1])
  617. return span;
  618. }
  619. return -EINVAL;
  620. }
  621. static int ltc2688_channel_config(struct ltc2688_state *st)
  622. {
  623. struct device *dev = &st->spi->dev;
  624. struct fwnode_handle *child;
  625. u32 reg, clk_input, val, tmp[2];
  626. int ret, span;
  627. device_for_each_child_node(dev, child) {
  628. struct ltc2688_chan *chan;
  629. ret = fwnode_property_read_u32(child, "reg", &reg);
  630. if (ret) {
  631. fwnode_handle_put(child);
  632. return dev_err_probe(dev, ret,
  633. "Failed to get reg property\n");
  634. }
  635. if (reg >= LTC2688_DAC_CHANNELS) {
  636. fwnode_handle_put(child);
  637. return dev_err_probe(dev, -EINVAL,
  638. "reg bigger than: %d\n",
  639. LTC2688_DAC_CHANNELS);
  640. }
  641. val = 0;
  642. chan = &st->channels[reg];
  643. if (fwnode_property_read_bool(child, "adi,toggle-mode")) {
  644. chan->toggle_chan = true;
  645. /* assume sw toggle ABI */
  646. st->iio_chan[reg].ext_info = ltc2688_toggle_sym_ext_info;
  647. /*
  648. * Clear IIO_CHAN_INFO_RAW bit as toggle channels expose
  649. * out_voltage_raw{0|1} files.
  650. */
  651. __clear_bit(IIO_CHAN_INFO_RAW,
  652. &st->iio_chan[reg].info_mask_separate);
  653. }
  654. ret = fwnode_property_read_u32_array(child, "adi,output-range-microvolt",
  655. tmp, ARRAY_SIZE(tmp));
  656. if (!ret) {
  657. span = ltc2688_span_lookup(st, (int)tmp[0] / 1000,
  658. tmp[1] / 1000);
  659. if (span < 0) {
  660. fwnode_handle_put(child);
  661. return dev_err_probe(dev, -EINVAL,
  662. "output range not valid:[%d %d]\n",
  663. tmp[0], tmp[1]);
  664. }
  665. val |= FIELD_PREP(LTC2688_CH_SPAN_MSK, span);
  666. }
  667. ret = fwnode_property_read_u32(child, "adi,toggle-dither-input",
  668. &clk_input);
  669. if (!ret) {
  670. if (clk_input >= LTC2688_CH_TGP_MAX) {
  671. fwnode_handle_put(child);
  672. return dev_err_probe(dev, -EINVAL,
  673. "toggle-dither-input inv value(%d)\n",
  674. clk_input);
  675. }
  676. ret = ltc2688_tgp_clk_setup(st, chan, child, clk_input);
  677. if (ret) {
  678. fwnode_handle_put(child);
  679. return ret;
  680. }
  681. /*
  682. * 0 means software toggle which is the default mode.
  683. * Hence the +1.
  684. */
  685. val |= FIELD_PREP(LTC2688_CH_TD_SEL_MSK, clk_input + 1);
  686. /*
  687. * If a TGPx is given, we automatically assume a dither
  688. * capable channel (unless toggle is already enabled).
  689. * On top of this we just set here the dither bit in the
  690. * channel settings. It won't have any effect until the
  691. * global toggle/dither bit is enabled.
  692. */
  693. if (!chan->toggle_chan) {
  694. val |= FIELD_PREP(LTC2688_CH_MODE_MSK, 1);
  695. st->iio_chan[reg].ext_info = ltc2688_dither_ext_info;
  696. } else {
  697. /* wait, no sw toggle after all */
  698. st->iio_chan[reg].ext_info = ltc2688_toggle_ext_info;
  699. }
  700. }
  701. if (fwnode_property_read_bool(child, "adi,overrange")) {
  702. chan->overrange = true;
  703. val |= LTC2688_CH_OVERRANGE_MSK;
  704. }
  705. if (!val)
  706. continue;
  707. ret = regmap_write(st->regmap, LTC2688_CMD_CH_SETTING(reg),
  708. val);
  709. if (ret) {
  710. fwnode_handle_put(child);
  711. return dev_err_probe(dev, -EINVAL,
  712. "failed to set chan settings\n");
  713. }
  714. }
  715. return 0;
  716. }
  717. static int ltc2688_setup(struct ltc2688_state *st, struct regulator *vref)
  718. {
  719. struct device *dev = &st->spi->dev;
  720. struct gpio_desc *gpio;
  721. int ret;
  722. /*
  723. * If we have a reset pin, use that to reset the board, If not, use
  724. * the reset bit.
  725. */
  726. gpio = devm_gpiod_get_optional(dev, "clr", GPIOD_OUT_HIGH);
  727. if (IS_ERR(gpio))
  728. return dev_err_probe(dev, PTR_ERR(gpio), "Failed to get reset gpio");
  729. if (gpio) {
  730. usleep_range(1000, 1200);
  731. /* bring device out of reset */
  732. gpiod_set_value_cansleep(gpio, 0);
  733. } else {
  734. ret = regmap_update_bits(st->regmap, LTC2688_CMD_CONFIG,
  735. LTC2688_CONFIG_RST,
  736. LTC2688_CONFIG_RST);
  737. if (ret)
  738. return ret;
  739. }
  740. usleep_range(10000, 12000);
  741. /*
  742. * Duplicate the default channel configuration as it can change during
  743. * @ltc2688_channel_config()
  744. */
  745. st->iio_chan = devm_kmemdup(dev, ltc2688_channels,
  746. sizeof(ltc2688_channels), GFP_KERNEL);
  747. if (!st->iio_chan)
  748. return -ENOMEM;
  749. ret = ltc2688_channel_config(st);
  750. if (ret)
  751. return ret;
  752. if (!vref)
  753. return 0;
  754. return regmap_set_bits(st->regmap, LTC2688_CMD_CONFIG,
  755. LTC2688_CONFIG_EXT_REF);
  756. }
  757. static void ltc2688_disable_regulators(void *data)
  758. {
  759. struct ltc2688_state *st = data;
  760. regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
  761. }
  762. static void ltc2688_disable_regulator(void *regulator)
  763. {
  764. regulator_disable(regulator);
  765. }
  766. static bool ltc2688_reg_readable(struct device *dev, unsigned int reg)
  767. {
  768. switch (reg) {
  769. case LTC2688_CMD_CH_CODE(0) ... LTC2688_CMD_CH_GAIN(15):
  770. return true;
  771. case LTC2688_CMD_CONFIG ... LTC2688_CMD_THERMAL_STAT:
  772. return true;
  773. default:
  774. return false;
  775. }
  776. }
  777. static bool ltc2688_reg_writable(struct device *dev, unsigned int reg)
  778. {
  779. /*
  780. * There's a jump from 0x76 to 0x78 in the write codes and the thermal
  781. * status code is 0x77 (which is read only) so that we need to check
  782. * that special condition.
  783. */
  784. if (reg <= LTC2688_CMD_UPDATE_ALL && reg != LTC2688_CMD_THERMAL_STAT)
  785. return true;
  786. return false;
  787. }
  788. static struct regmap_bus ltc2688_regmap_bus = {
  789. .read = ltc2688_spi_read,
  790. .write = ltc2688_spi_write,
  791. .read_flag_mask = LTC2688_READ_OPERATION,
  792. .reg_format_endian_default = REGMAP_ENDIAN_BIG,
  793. .val_format_endian_default = REGMAP_ENDIAN_BIG,
  794. };
  795. static const struct regmap_config ltc2688_regmap_config = {
  796. .reg_bits = 8,
  797. .val_bits = 16,
  798. .readable_reg = ltc2688_reg_readable,
  799. .writeable_reg = ltc2688_reg_writable,
  800. /* ignoring the no op command */
  801. .max_register = LTC2688_CMD_UPDATE_ALL,
  802. };
  803. static const struct iio_info ltc2688_info = {
  804. .write_raw = ltc2688_write_raw,
  805. .read_raw = ltc2688_read_raw,
  806. .read_avail = ltc2688_read_avail,
  807. .debugfs_reg_access = ltc2688_reg_access,
  808. };
  809. static int ltc2688_probe(struct spi_device *spi)
  810. {
  811. struct ltc2688_state *st;
  812. struct iio_dev *indio_dev;
  813. struct regulator *vref_reg;
  814. struct device *dev = &spi->dev;
  815. int ret;
  816. indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
  817. if (!indio_dev)
  818. return -ENOMEM;
  819. st = iio_priv(indio_dev);
  820. st->spi = spi;
  821. /* Just write this once. No need to do it in every regmap read. */
  822. st->tx_data[3] = LTC2688_CMD_NOOP;
  823. mutex_init(&st->lock);
  824. st->regmap = devm_regmap_init(dev, &ltc2688_regmap_bus, st,
  825. &ltc2688_regmap_config);
  826. if (IS_ERR(st->regmap))
  827. return dev_err_probe(dev, PTR_ERR(st->regmap),
  828. "Failed to init regmap");
  829. st->regulators[0].supply = "vcc";
  830. st->regulators[1].supply = "iovcc";
  831. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
  832. st->regulators);
  833. if (ret)
  834. return dev_err_probe(dev, ret, "Failed to get regulators\n");
  835. ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
  836. if (ret)
  837. return dev_err_probe(dev, ret, "Failed to enable regulators\n");
  838. ret = devm_add_action_or_reset(dev, ltc2688_disable_regulators, st);
  839. if (ret)
  840. return ret;
  841. vref_reg = devm_regulator_get_optional(dev, "vref");
  842. if (IS_ERR(vref_reg)) {
  843. if (PTR_ERR(vref_reg) != -ENODEV)
  844. return dev_err_probe(dev, PTR_ERR(vref_reg),
  845. "Failed to get vref regulator");
  846. vref_reg = NULL;
  847. /* internal reference */
  848. st->vref = 4096;
  849. } else {
  850. ret = regulator_enable(vref_reg);
  851. if (ret)
  852. return dev_err_probe(dev, ret,
  853. "Failed to enable vref regulators\n");
  854. ret = devm_add_action_or_reset(dev, ltc2688_disable_regulator,
  855. vref_reg);
  856. if (ret)
  857. return ret;
  858. ret = regulator_get_voltage(vref_reg);
  859. if (ret < 0)
  860. return dev_err_probe(dev, ret, "Failed to get vref\n");
  861. st->vref = ret / 1000;
  862. }
  863. ret = ltc2688_setup(st, vref_reg);
  864. if (ret)
  865. return ret;
  866. indio_dev->name = "ltc2688";
  867. indio_dev->info = &ltc2688_info;
  868. indio_dev->modes = INDIO_DIRECT_MODE;
  869. indio_dev->channels = st->iio_chan;
  870. indio_dev->num_channels = ARRAY_SIZE(ltc2688_channels);
  871. return devm_iio_device_register(dev, indio_dev);
  872. }
  873. static const struct of_device_id ltc2688_of_id[] = {
  874. { .compatible = "adi,ltc2688" },
  875. {}
  876. };
  877. MODULE_DEVICE_TABLE(of, ltc2688_of_id);
  878. static const struct spi_device_id ltc2688_id[] = {
  879. { "ltc2688" },
  880. {}
  881. };
  882. MODULE_DEVICE_TABLE(spi, ltc2688_id);
  883. static struct spi_driver ltc2688_driver = {
  884. .driver = {
  885. .name = "ltc2688",
  886. .of_match_table = ltc2688_of_id,
  887. },
  888. .probe = ltc2688_probe,
  889. .id_table = ltc2688_id,
  890. };
  891. module_spi_driver(ltc2688_driver);
  892. MODULE_AUTHOR("Nuno Sá <[email protected]>");
  893. MODULE_DESCRIPTION("Analog Devices LTC2688 DAC");
  894. MODULE_LICENSE("GPL");