ti-ads1015.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ADS1015 - Texas Instruments Analog-to-Digital Converter
  4. *
  5. * Copyright (c) 2016, Intel Corporation.
  6. *
  7. * IIO driver for ADS1015 ADC 7-bit I2C slave address:
  8. * * 0x48 - ADDR connected to Ground
  9. * * 0x49 - ADDR connected to Vdd
  10. * * 0x4A - ADDR connected to SDA
  11. * * 0x4B - ADDR connected to SCL
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/irq.h>
  16. #include <linux/i2c.h>
  17. #include <linux/property.h>
  18. #include <linux/regmap.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/mutex.h>
  21. #include <linux/delay.h>
  22. #include <linux/iio/iio.h>
  23. #include <linux/iio/types.h>
  24. #include <linux/iio/sysfs.h>
  25. #include <linux/iio/events.h>
  26. #include <linux/iio/buffer.h>
  27. #include <linux/iio/triggered_buffer.h>
  28. #include <linux/iio/trigger_consumer.h>
  29. #define ADS1015_DRV_NAME "ads1015"
  30. #define ADS1015_CHANNELS 8
  31. #define ADS1015_CONV_REG 0x00
  32. #define ADS1015_CFG_REG 0x01
  33. #define ADS1015_LO_THRESH_REG 0x02
  34. #define ADS1015_HI_THRESH_REG 0x03
  35. #define ADS1015_CFG_COMP_QUE_SHIFT 0
  36. #define ADS1015_CFG_COMP_LAT_SHIFT 2
  37. #define ADS1015_CFG_COMP_POL_SHIFT 3
  38. #define ADS1015_CFG_COMP_MODE_SHIFT 4
  39. #define ADS1015_CFG_DR_SHIFT 5
  40. #define ADS1015_CFG_MOD_SHIFT 8
  41. #define ADS1015_CFG_PGA_SHIFT 9
  42. #define ADS1015_CFG_MUX_SHIFT 12
  43. #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
  44. #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
  45. #define ADS1015_CFG_COMP_POL_MASK BIT(3)
  46. #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
  47. #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
  48. #define ADS1015_CFG_MOD_MASK BIT(8)
  49. #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
  50. #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
  51. /* Comparator queue and disable field */
  52. #define ADS1015_CFG_COMP_DISABLE 3
  53. /* Comparator polarity field */
  54. #define ADS1015_CFG_COMP_POL_LOW 0
  55. #define ADS1015_CFG_COMP_POL_HIGH 1
  56. /* Comparator mode field */
  57. #define ADS1015_CFG_COMP_MODE_TRAD 0
  58. #define ADS1015_CFG_COMP_MODE_WINDOW 1
  59. /* device operating modes */
  60. #define ADS1015_CONTINUOUS 0
  61. #define ADS1015_SINGLESHOT 1
  62. #define ADS1015_SLEEP_DELAY_MS 2000
  63. #define ADS1015_DEFAULT_PGA 2
  64. #define ADS1015_DEFAULT_DATA_RATE 4
  65. #define ADS1015_DEFAULT_CHAN 0
  66. struct ads1015_chip_data {
  67. struct iio_chan_spec const *channels;
  68. int num_channels;
  69. const struct iio_info *info;
  70. const int *data_rate;
  71. const int data_rate_len;
  72. const int *scale;
  73. const int scale_len;
  74. bool has_comparator;
  75. };
  76. enum ads1015_channels {
  77. ADS1015_AIN0_AIN1 = 0,
  78. ADS1015_AIN0_AIN3,
  79. ADS1015_AIN1_AIN3,
  80. ADS1015_AIN2_AIN3,
  81. ADS1015_AIN0,
  82. ADS1015_AIN1,
  83. ADS1015_AIN2,
  84. ADS1015_AIN3,
  85. ADS1015_TIMESTAMP,
  86. };
  87. static const int ads1015_data_rate[] = {
  88. 128, 250, 490, 920, 1600, 2400, 3300, 3300
  89. };
  90. static const int ads1115_data_rate[] = {
  91. 8, 16, 32, 64, 128, 250, 475, 860
  92. };
  93. /*
  94. * Translation from PGA bits to full-scale positive and negative input voltage
  95. * range in mV
  96. */
  97. static const int ads1015_fullscale_range[] = {
  98. 6144, 4096, 2048, 1024, 512, 256, 256, 256
  99. };
  100. static const int ads1015_scale[] = { /* 12bit ADC */
  101. 256, 11,
  102. 512, 11,
  103. 1024, 11,
  104. 2048, 11,
  105. 4096, 11,
  106. 6144, 11
  107. };
  108. static const int ads1115_scale[] = { /* 16bit ADC */
  109. 256, 15,
  110. 512, 15,
  111. 1024, 15,
  112. 2048, 15,
  113. 4096, 15,
  114. 6144, 15
  115. };
  116. /*
  117. * Translation from COMP_QUE field value to the number of successive readings
  118. * exceed the threshold values before an interrupt is generated
  119. */
  120. static const int ads1015_comp_queue[] = { 1, 2, 4 };
  121. static const struct iio_event_spec ads1015_events[] = {
  122. {
  123. .type = IIO_EV_TYPE_THRESH,
  124. .dir = IIO_EV_DIR_RISING,
  125. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  126. BIT(IIO_EV_INFO_ENABLE),
  127. }, {
  128. .type = IIO_EV_TYPE_THRESH,
  129. .dir = IIO_EV_DIR_FALLING,
  130. .mask_separate = BIT(IIO_EV_INFO_VALUE),
  131. }, {
  132. .type = IIO_EV_TYPE_THRESH,
  133. .dir = IIO_EV_DIR_EITHER,
  134. .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
  135. BIT(IIO_EV_INFO_PERIOD),
  136. },
  137. };
  138. /*
  139. * Compile-time check whether _fitbits can accommodate up to _testbits
  140. * bits. Returns _fitbits on success, fails to compile otherwise.
  141. *
  142. * The test works such that it multiplies constant _fitbits by constant
  143. * double-negation of size of a non-empty structure, i.e. it multiplies
  144. * constant _fitbits by constant 1 in each successful compilation case.
  145. * The non-empty structure may contain C11 _Static_assert(), make use of
  146. * this and place the kernel variant of static assert in there, so that
  147. * it performs the compile-time check for _testbits <= _fitbits. Note
  148. * that it is not possible to directly use static_assert in compound
  149. * statements, hence this convoluted construct.
  150. */
  151. #define FIT_CHECK(_testbits, _fitbits) \
  152. ( \
  153. (_fitbits) * \
  154. !!sizeof(struct { \
  155. static_assert((_testbits) <= (_fitbits)); \
  156. int pad; \
  157. }) \
  158. )
  159. #define ADS1015_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
  160. .type = IIO_VOLTAGE, \
  161. .indexed = 1, \
  162. .address = _addr, \
  163. .channel = _chan, \
  164. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  165. BIT(IIO_CHAN_INFO_SCALE) | \
  166. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  167. .info_mask_shared_by_all_available = \
  168. BIT(IIO_CHAN_INFO_SCALE) | \
  169. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  170. .scan_index = _addr, \
  171. .scan_type = { \
  172. .sign = 's', \
  173. .realbits = (_realbits), \
  174. .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
  175. .shift = (_shift), \
  176. .endianness = IIO_CPU, \
  177. }, \
  178. .event_spec = (_event_spec), \
  179. .num_event_specs = (_num_event_specs), \
  180. .datasheet_name = "AIN"#_chan, \
  181. }
  182. #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
  183. .type = IIO_VOLTAGE, \
  184. .differential = 1, \
  185. .indexed = 1, \
  186. .address = _addr, \
  187. .channel = _chan, \
  188. .channel2 = _chan2, \
  189. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
  190. BIT(IIO_CHAN_INFO_SCALE) | \
  191. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  192. .info_mask_shared_by_all_available = \
  193. BIT(IIO_CHAN_INFO_SCALE) | \
  194. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  195. .scan_index = _addr, \
  196. .scan_type = { \
  197. .sign = 's', \
  198. .realbits = (_realbits), \
  199. .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
  200. .shift = (_shift), \
  201. .endianness = IIO_CPU, \
  202. }, \
  203. .event_spec = (_event_spec), \
  204. .num_event_specs = (_num_event_specs), \
  205. .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
  206. }
  207. struct ads1015_channel_data {
  208. bool enabled;
  209. unsigned int pga;
  210. unsigned int data_rate;
  211. };
  212. struct ads1015_thresh_data {
  213. unsigned int comp_queue;
  214. int high_thresh;
  215. int low_thresh;
  216. };
  217. struct ads1015_data {
  218. struct regmap *regmap;
  219. /*
  220. * Protects ADC ops, e.g: concurrent sysfs/buffered
  221. * data reads, configuration updates
  222. */
  223. struct mutex lock;
  224. struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
  225. unsigned int event_channel;
  226. unsigned int comp_mode;
  227. struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
  228. const struct ads1015_chip_data *chip;
  229. /*
  230. * Set to true when the ADC is switched to the continuous-conversion
  231. * mode and exits from a power-down state. This flag is used to avoid
  232. * getting the stale result from the conversion register.
  233. */
  234. bool conv_invalid;
  235. };
  236. static bool ads1015_event_channel_enabled(struct ads1015_data *data)
  237. {
  238. return (data->event_channel != ADS1015_CHANNELS);
  239. }
  240. static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
  241. int comp_mode)
  242. {
  243. WARN_ON(ads1015_event_channel_enabled(data));
  244. data->event_channel = chan;
  245. data->comp_mode = comp_mode;
  246. }
  247. static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
  248. {
  249. data->event_channel = ADS1015_CHANNELS;
  250. }
  251. static const struct regmap_range ads1015_writeable_ranges[] = {
  252. regmap_reg_range(ADS1015_CFG_REG, ADS1015_HI_THRESH_REG),
  253. };
  254. static const struct regmap_access_table ads1015_writeable_table = {
  255. .yes_ranges = ads1015_writeable_ranges,
  256. .n_yes_ranges = ARRAY_SIZE(ads1015_writeable_ranges),
  257. };
  258. static const struct regmap_config ads1015_regmap_config = {
  259. .reg_bits = 8,
  260. .val_bits = 16,
  261. .max_register = ADS1015_HI_THRESH_REG,
  262. .wr_table = &ads1015_writeable_table,
  263. };
  264. static const struct regmap_range tla2024_writeable_ranges[] = {
  265. regmap_reg_range(ADS1015_CFG_REG, ADS1015_CFG_REG),
  266. };
  267. static const struct regmap_access_table tla2024_writeable_table = {
  268. .yes_ranges = tla2024_writeable_ranges,
  269. .n_yes_ranges = ARRAY_SIZE(tla2024_writeable_ranges),
  270. };
  271. static const struct regmap_config tla2024_regmap_config = {
  272. .reg_bits = 8,
  273. .val_bits = 16,
  274. .max_register = ADS1015_CFG_REG,
  275. .wr_table = &tla2024_writeable_table,
  276. };
  277. static const struct iio_chan_spec ads1015_channels[] = {
  278. ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4,
  279. ads1015_events, ARRAY_SIZE(ads1015_events)),
  280. ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4,
  281. ads1015_events, ARRAY_SIZE(ads1015_events)),
  282. ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4,
  283. ads1015_events, ARRAY_SIZE(ads1015_events)),
  284. ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4,
  285. ads1015_events, ARRAY_SIZE(ads1015_events)),
  286. ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4,
  287. ads1015_events, ARRAY_SIZE(ads1015_events)),
  288. ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4,
  289. ads1015_events, ARRAY_SIZE(ads1015_events)),
  290. ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4,
  291. ads1015_events, ARRAY_SIZE(ads1015_events)),
  292. ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4,
  293. ads1015_events, ARRAY_SIZE(ads1015_events)),
  294. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  295. };
  296. static const struct iio_chan_spec ads1115_channels[] = {
  297. ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 16, 0,
  298. ads1015_events, ARRAY_SIZE(ads1015_events)),
  299. ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 16, 0,
  300. ads1015_events, ARRAY_SIZE(ads1015_events)),
  301. ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 16, 0,
  302. ads1015_events, ARRAY_SIZE(ads1015_events)),
  303. ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 16, 0,
  304. ads1015_events, ARRAY_SIZE(ads1015_events)),
  305. ADS1015_V_CHAN(0, ADS1015_AIN0, 16, 0,
  306. ads1015_events, ARRAY_SIZE(ads1015_events)),
  307. ADS1015_V_CHAN(1, ADS1015_AIN1, 16, 0,
  308. ads1015_events, ARRAY_SIZE(ads1015_events)),
  309. ADS1015_V_CHAN(2, ADS1015_AIN2, 16, 0,
  310. ads1015_events, ARRAY_SIZE(ads1015_events)),
  311. ADS1015_V_CHAN(3, ADS1015_AIN3, 16, 0,
  312. ads1015_events, ARRAY_SIZE(ads1015_events)),
  313. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  314. };
  315. static const struct iio_chan_spec tla2024_channels[] = {
  316. ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1, 12, 4, NULL, 0),
  317. ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3, 12, 4, NULL, 0),
  318. ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3, 12, 4, NULL, 0),
  319. ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3, 12, 4, NULL, 0),
  320. ADS1015_V_CHAN(0, ADS1015_AIN0, 12, 4, NULL, 0),
  321. ADS1015_V_CHAN(1, ADS1015_AIN1, 12, 4, NULL, 0),
  322. ADS1015_V_CHAN(2, ADS1015_AIN2, 12, 4, NULL, 0),
  323. ADS1015_V_CHAN(3, ADS1015_AIN3, 12, 4, NULL, 0),
  324. IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
  325. };
  326. #ifdef CONFIG_PM
  327. static int ads1015_set_power_state(struct ads1015_data *data, bool on)
  328. {
  329. int ret;
  330. struct device *dev = regmap_get_device(data->regmap);
  331. if (on) {
  332. ret = pm_runtime_resume_and_get(dev);
  333. } else {
  334. pm_runtime_mark_last_busy(dev);
  335. ret = pm_runtime_put_autosuspend(dev);
  336. }
  337. return ret < 0 ? ret : 0;
  338. }
  339. #else /* !CONFIG_PM */
  340. static int ads1015_set_power_state(struct ads1015_data *data, bool on)
  341. {
  342. return 0;
  343. }
  344. #endif /* !CONFIG_PM */
  345. static
  346. int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
  347. {
  348. const int *data_rate = data->chip->data_rate;
  349. int ret, pga, dr, dr_old, conv_time;
  350. unsigned int old, mask, cfg;
  351. if (chan < 0 || chan >= ADS1015_CHANNELS)
  352. return -EINVAL;
  353. ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
  354. if (ret)
  355. return ret;
  356. pga = data->channel_data[chan].pga;
  357. dr = data->channel_data[chan].data_rate;
  358. mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
  359. ADS1015_CFG_DR_MASK;
  360. cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
  361. dr << ADS1015_CFG_DR_SHIFT;
  362. if (ads1015_event_channel_enabled(data)) {
  363. mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
  364. cfg |= data->thresh_data[chan].comp_queue <<
  365. ADS1015_CFG_COMP_QUE_SHIFT |
  366. data->comp_mode <<
  367. ADS1015_CFG_COMP_MODE_SHIFT;
  368. }
  369. cfg = (old & ~mask) | (cfg & mask);
  370. if (old != cfg) {
  371. ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
  372. if (ret)
  373. return ret;
  374. data->conv_invalid = true;
  375. }
  376. if (data->conv_invalid) {
  377. dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
  378. conv_time = DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr_old]);
  379. conv_time += DIV_ROUND_UP(USEC_PER_SEC, data_rate[dr]);
  380. conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
  381. usleep_range(conv_time, conv_time + 1);
  382. data->conv_invalid = false;
  383. }
  384. return regmap_read(data->regmap, ADS1015_CONV_REG, val);
  385. }
  386. static irqreturn_t ads1015_trigger_handler(int irq, void *p)
  387. {
  388. struct iio_poll_func *pf = p;
  389. struct iio_dev *indio_dev = pf->indio_dev;
  390. struct ads1015_data *data = iio_priv(indio_dev);
  391. /* Ensure natural alignment of timestamp */
  392. struct {
  393. s16 chan;
  394. s64 timestamp __aligned(8);
  395. } scan;
  396. int chan, ret, res;
  397. memset(&scan, 0, sizeof(scan));
  398. mutex_lock(&data->lock);
  399. chan = find_first_bit(indio_dev->active_scan_mask,
  400. indio_dev->masklength);
  401. ret = ads1015_get_adc_result(data, chan, &res);
  402. if (ret < 0) {
  403. mutex_unlock(&data->lock);
  404. goto err;
  405. }
  406. scan.chan = res;
  407. mutex_unlock(&data->lock);
  408. iio_push_to_buffers_with_timestamp(indio_dev, &scan,
  409. iio_get_time_ns(indio_dev));
  410. err:
  411. iio_trigger_notify_done(indio_dev->trig);
  412. return IRQ_HANDLED;
  413. }
  414. static int ads1015_set_scale(struct ads1015_data *data,
  415. struct iio_chan_spec const *chan,
  416. int scale, int uscale)
  417. {
  418. int i;
  419. int fullscale = div_s64((scale * 1000000LL + uscale) <<
  420. (chan->scan_type.realbits - 1), 1000000);
  421. for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
  422. if (ads1015_fullscale_range[i] == fullscale) {
  423. data->channel_data[chan->address].pga = i;
  424. return 0;
  425. }
  426. }
  427. return -EINVAL;
  428. }
  429. static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
  430. {
  431. int i;
  432. for (i = 0; i < data->chip->data_rate_len; i++) {
  433. if (data->chip->data_rate[i] == rate) {
  434. data->channel_data[chan].data_rate = i;
  435. return 0;
  436. }
  437. }
  438. return -EINVAL;
  439. }
  440. static int ads1015_read_avail(struct iio_dev *indio_dev,
  441. struct iio_chan_spec const *chan,
  442. const int **vals, int *type, int *length,
  443. long mask)
  444. {
  445. struct ads1015_data *data = iio_priv(indio_dev);
  446. if (chan->type != IIO_VOLTAGE)
  447. return -EINVAL;
  448. switch (mask) {
  449. case IIO_CHAN_INFO_SCALE:
  450. *type = IIO_VAL_FRACTIONAL_LOG2;
  451. *vals = data->chip->scale;
  452. *length = data->chip->scale_len;
  453. return IIO_AVAIL_LIST;
  454. case IIO_CHAN_INFO_SAMP_FREQ:
  455. *type = IIO_VAL_INT;
  456. *vals = data->chip->data_rate;
  457. *length = data->chip->data_rate_len;
  458. return IIO_AVAIL_LIST;
  459. default:
  460. return -EINVAL;
  461. }
  462. }
  463. static int ads1015_read_raw(struct iio_dev *indio_dev,
  464. struct iio_chan_spec const *chan, int *val,
  465. int *val2, long mask)
  466. {
  467. int ret, idx;
  468. struct ads1015_data *data = iio_priv(indio_dev);
  469. mutex_lock(&data->lock);
  470. switch (mask) {
  471. case IIO_CHAN_INFO_RAW:
  472. ret = iio_device_claim_direct_mode(indio_dev);
  473. if (ret)
  474. break;
  475. if (ads1015_event_channel_enabled(data) &&
  476. data->event_channel != chan->address) {
  477. ret = -EBUSY;
  478. goto release_direct;
  479. }
  480. ret = ads1015_set_power_state(data, true);
  481. if (ret < 0)
  482. goto release_direct;
  483. ret = ads1015_get_adc_result(data, chan->address, val);
  484. if (ret < 0) {
  485. ads1015_set_power_state(data, false);
  486. goto release_direct;
  487. }
  488. *val = sign_extend32(*val >> chan->scan_type.shift,
  489. chan->scan_type.realbits - 1);
  490. ret = ads1015_set_power_state(data, false);
  491. if (ret < 0)
  492. goto release_direct;
  493. ret = IIO_VAL_INT;
  494. release_direct:
  495. iio_device_release_direct_mode(indio_dev);
  496. break;
  497. case IIO_CHAN_INFO_SCALE:
  498. idx = data->channel_data[chan->address].pga;
  499. *val = ads1015_fullscale_range[idx];
  500. *val2 = chan->scan_type.realbits - 1;
  501. ret = IIO_VAL_FRACTIONAL_LOG2;
  502. break;
  503. case IIO_CHAN_INFO_SAMP_FREQ:
  504. idx = data->channel_data[chan->address].data_rate;
  505. *val = data->chip->data_rate[idx];
  506. ret = IIO_VAL_INT;
  507. break;
  508. default:
  509. ret = -EINVAL;
  510. break;
  511. }
  512. mutex_unlock(&data->lock);
  513. return ret;
  514. }
  515. static int ads1015_write_raw(struct iio_dev *indio_dev,
  516. struct iio_chan_spec const *chan, int val,
  517. int val2, long mask)
  518. {
  519. struct ads1015_data *data = iio_priv(indio_dev);
  520. int ret;
  521. mutex_lock(&data->lock);
  522. switch (mask) {
  523. case IIO_CHAN_INFO_SCALE:
  524. ret = ads1015_set_scale(data, chan, val, val2);
  525. break;
  526. case IIO_CHAN_INFO_SAMP_FREQ:
  527. ret = ads1015_set_data_rate(data, chan->address, val);
  528. break;
  529. default:
  530. ret = -EINVAL;
  531. break;
  532. }
  533. mutex_unlock(&data->lock);
  534. return ret;
  535. }
  536. static int ads1015_read_event(struct iio_dev *indio_dev,
  537. const struct iio_chan_spec *chan, enum iio_event_type type,
  538. enum iio_event_direction dir, enum iio_event_info info, int *val,
  539. int *val2)
  540. {
  541. struct ads1015_data *data = iio_priv(indio_dev);
  542. int ret;
  543. unsigned int comp_queue;
  544. int period;
  545. int dr;
  546. mutex_lock(&data->lock);
  547. switch (info) {
  548. case IIO_EV_INFO_VALUE:
  549. *val = (dir == IIO_EV_DIR_RISING) ?
  550. data->thresh_data[chan->address].high_thresh :
  551. data->thresh_data[chan->address].low_thresh;
  552. ret = IIO_VAL_INT;
  553. break;
  554. case IIO_EV_INFO_PERIOD:
  555. dr = data->channel_data[chan->address].data_rate;
  556. comp_queue = data->thresh_data[chan->address].comp_queue;
  557. period = ads1015_comp_queue[comp_queue] *
  558. USEC_PER_SEC / data->chip->data_rate[dr];
  559. *val = period / USEC_PER_SEC;
  560. *val2 = period % USEC_PER_SEC;
  561. ret = IIO_VAL_INT_PLUS_MICRO;
  562. break;
  563. default:
  564. ret = -EINVAL;
  565. break;
  566. }
  567. mutex_unlock(&data->lock);
  568. return ret;
  569. }
  570. static int ads1015_write_event(struct iio_dev *indio_dev,
  571. const struct iio_chan_spec *chan, enum iio_event_type type,
  572. enum iio_event_direction dir, enum iio_event_info info, int val,
  573. int val2)
  574. {
  575. struct ads1015_data *data = iio_priv(indio_dev);
  576. const int *data_rate = data->chip->data_rate;
  577. int realbits = chan->scan_type.realbits;
  578. int ret = 0;
  579. long long period;
  580. int i;
  581. int dr;
  582. mutex_lock(&data->lock);
  583. switch (info) {
  584. case IIO_EV_INFO_VALUE:
  585. if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
  586. ret = -EINVAL;
  587. break;
  588. }
  589. if (dir == IIO_EV_DIR_RISING)
  590. data->thresh_data[chan->address].high_thresh = val;
  591. else
  592. data->thresh_data[chan->address].low_thresh = val;
  593. break;
  594. case IIO_EV_INFO_PERIOD:
  595. dr = data->channel_data[chan->address].data_rate;
  596. period = val * USEC_PER_SEC + val2;
  597. for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
  598. if (period <= ads1015_comp_queue[i] *
  599. USEC_PER_SEC / data_rate[dr])
  600. break;
  601. }
  602. data->thresh_data[chan->address].comp_queue = i;
  603. break;
  604. default:
  605. ret = -EINVAL;
  606. break;
  607. }
  608. mutex_unlock(&data->lock);
  609. return ret;
  610. }
  611. static int ads1015_read_event_config(struct iio_dev *indio_dev,
  612. const struct iio_chan_spec *chan, enum iio_event_type type,
  613. enum iio_event_direction dir)
  614. {
  615. struct ads1015_data *data = iio_priv(indio_dev);
  616. int ret = 0;
  617. mutex_lock(&data->lock);
  618. if (data->event_channel == chan->address) {
  619. switch (dir) {
  620. case IIO_EV_DIR_RISING:
  621. ret = 1;
  622. break;
  623. case IIO_EV_DIR_EITHER:
  624. ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
  625. break;
  626. default:
  627. ret = -EINVAL;
  628. break;
  629. }
  630. }
  631. mutex_unlock(&data->lock);
  632. return ret;
  633. }
  634. static int ads1015_enable_event_config(struct ads1015_data *data,
  635. const struct iio_chan_spec *chan, int comp_mode)
  636. {
  637. int low_thresh = data->thresh_data[chan->address].low_thresh;
  638. int high_thresh = data->thresh_data[chan->address].high_thresh;
  639. int ret;
  640. unsigned int val;
  641. if (ads1015_event_channel_enabled(data)) {
  642. if (data->event_channel != chan->address ||
  643. (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
  644. comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
  645. return -EBUSY;
  646. return 0;
  647. }
  648. if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
  649. low_thresh = max(-1 << (chan->scan_type.realbits - 1),
  650. high_thresh - 1);
  651. }
  652. ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
  653. low_thresh << chan->scan_type.shift);
  654. if (ret)
  655. return ret;
  656. ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
  657. high_thresh << chan->scan_type.shift);
  658. if (ret)
  659. return ret;
  660. ret = ads1015_set_power_state(data, true);
  661. if (ret < 0)
  662. return ret;
  663. ads1015_event_channel_enable(data, chan->address, comp_mode);
  664. ret = ads1015_get_adc_result(data, chan->address, &val);
  665. if (ret) {
  666. ads1015_event_channel_disable(data, chan->address);
  667. ads1015_set_power_state(data, false);
  668. }
  669. return ret;
  670. }
  671. static int ads1015_disable_event_config(struct ads1015_data *data,
  672. const struct iio_chan_spec *chan, int comp_mode)
  673. {
  674. int ret;
  675. if (!ads1015_event_channel_enabled(data))
  676. return 0;
  677. if (data->event_channel != chan->address)
  678. return 0;
  679. if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
  680. comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
  681. return 0;
  682. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  683. ADS1015_CFG_COMP_QUE_MASK,
  684. ADS1015_CFG_COMP_DISABLE <<
  685. ADS1015_CFG_COMP_QUE_SHIFT);
  686. if (ret)
  687. return ret;
  688. ads1015_event_channel_disable(data, chan->address);
  689. return ads1015_set_power_state(data, false);
  690. }
  691. static int ads1015_write_event_config(struct iio_dev *indio_dev,
  692. const struct iio_chan_spec *chan, enum iio_event_type type,
  693. enum iio_event_direction dir, int state)
  694. {
  695. struct ads1015_data *data = iio_priv(indio_dev);
  696. int ret;
  697. int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
  698. ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
  699. mutex_lock(&data->lock);
  700. /* Prevent from enabling both buffer and event at a time */
  701. ret = iio_device_claim_direct_mode(indio_dev);
  702. if (ret) {
  703. mutex_unlock(&data->lock);
  704. return ret;
  705. }
  706. if (state)
  707. ret = ads1015_enable_event_config(data, chan, comp_mode);
  708. else
  709. ret = ads1015_disable_event_config(data, chan, comp_mode);
  710. iio_device_release_direct_mode(indio_dev);
  711. mutex_unlock(&data->lock);
  712. return ret;
  713. }
  714. static irqreturn_t ads1015_event_handler(int irq, void *priv)
  715. {
  716. struct iio_dev *indio_dev = priv;
  717. struct ads1015_data *data = iio_priv(indio_dev);
  718. int val;
  719. int ret;
  720. /* Clear the latched ALERT/RDY pin */
  721. ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
  722. if (ret)
  723. return IRQ_HANDLED;
  724. if (ads1015_event_channel_enabled(data)) {
  725. enum iio_event_direction dir;
  726. u64 code;
  727. dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
  728. IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
  729. code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
  730. IIO_EV_TYPE_THRESH, dir);
  731. iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
  732. }
  733. return IRQ_HANDLED;
  734. }
  735. static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
  736. {
  737. struct ads1015_data *data = iio_priv(indio_dev);
  738. /* Prevent from enabling both buffer and event at a time */
  739. if (ads1015_event_channel_enabled(data))
  740. return -EBUSY;
  741. return ads1015_set_power_state(iio_priv(indio_dev), true);
  742. }
  743. static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
  744. {
  745. return ads1015_set_power_state(iio_priv(indio_dev), false);
  746. }
  747. static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
  748. .preenable = ads1015_buffer_preenable,
  749. .postdisable = ads1015_buffer_postdisable,
  750. .validate_scan_mask = &iio_validate_scan_mask_onehot,
  751. };
  752. static const struct iio_info ads1015_info = {
  753. .read_avail = ads1015_read_avail,
  754. .read_raw = ads1015_read_raw,
  755. .write_raw = ads1015_write_raw,
  756. .read_event_value = ads1015_read_event,
  757. .write_event_value = ads1015_write_event,
  758. .read_event_config = ads1015_read_event_config,
  759. .write_event_config = ads1015_write_event_config,
  760. };
  761. static const struct iio_info tla2024_info = {
  762. .read_avail = ads1015_read_avail,
  763. .read_raw = ads1015_read_raw,
  764. .write_raw = ads1015_write_raw,
  765. };
  766. static int ads1015_client_get_channels_config(struct i2c_client *client)
  767. {
  768. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  769. struct ads1015_data *data = iio_priv(indio_dev);
  770. struct device *dev = &client->dev;
  771. struct fwnode_handle *node;
  772. int i = -1;
  773. device_for_each_child_node(dev, node) {
  774. u32 pval;
  775. unsigned int channel;
  776. unsigned int pga = ADS1015_DEFAULT_PGA;
  777. unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
  778. if (fwnode_property_read_u32(node, "reg", &pval)) {
  779. dev_err(dev, "invalid reg on %pfw\n", node);
  780. continue;
  781. }
  782. channel = pval;
  783. if (channel >= ADS1015_CHANNELS) {
  784. dev_err(dev, "invalid channel index %d on %pfw\n",
  785. channel, node);
  786. continue;
  787. }
  788. if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
  789. pga = pval;
  790. if (pga > 6) {
  791. dev_err(dev, "invalid gain on %pfw\n", node);
  792. fwnode_handle_put(node);
  793. return -EINVAL;
  794. }
  795. }
  796. if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
  797. data_rate = pval;
  798. if (data_rate > 7) {
  799. dev_err(dev, "invalid data_rate on %pfw\n", node);
  800. fwnode_handle_put(node);
  801. return -EINVAL;
  802. }
  803. }
  804. data->channel_data[channel].pga = pga;
  805. data->channel_data[channel].data_rate = data_rate;
  806. i++;
  807. }
  808. return i < 0 ? -EINVAL : 0;
  809. }
  810. static void ads1015_get_channels_config(struct i2c_client *client)
  811. {
  812. unsigned int k;
  813. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  814. struct ads1015_data *data = iio_priv(indio_dev);
  815. if (!ads1015_client_get_channels_config(client))
  816. return;
  817. /* fallback on default configuration */
  818. for (k = 0; k < ADS1015_CHANNELS; ++k) {
  819. data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
  820. data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
  821. }
  822. }
  823. static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
  824. {
  825. return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  826. ADS1015_CFG_MOD_MASK,
  827. mode << ADS1015_CFG_MOD_SHIFT);
  828. }
  829. static int ads1015_probe(struct i2c_client *client,
  830. const struct i2c_device_id *id)
  831. {
  832. const struct ads1015_chip_data *chip;
  833. struct iio_dev *indio_dev;
  834. struct ads1015_data *data;
  835. int ret;
  836. int i;
  837. chip = device_get_match_data(&client->dev);
  838. if (!chip)
  839. chip = (const struct ads1015_chip_data *)id->driver_data;
  840. if (!chip)
  841. return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
  842. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  843. if (!indio_dev)
  844. return -ENOMEM;
  845. data = iio_priv(indio_dev);
  846. i2c_set_clientdata(client, indio_dev);
  847. mutex_init(&data->lock);
  848. indio_dev->name = ADS1015_DRV_NAME;
  849. indio_dev->modes = INDIO_DIRECT_MODE;
  850. indio_dev->channels = chip->channels;
  851. indio_dev->num_channels = chip->num_channels;
  852. indio_dev->info = chip->info;
  853. data->chip = chip;
  854. data->event_channel = ADS1015_CHANNELS;
  855. /*
  856. * Set default lower and upper threshold to min and max value
  857. * respectively.
  858. */
  859. for (i = 0; i < ADS1015_CHANNELS; i++) {
  860. int realbits = indio_dev->channels[i].scan_type.realbits;
  861. data->thresh_data[i].low_thresh = -1 << (realbits - 1);
  862. data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
  863. }
  864. /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
  865. ads1015_get_channels_config(client);
  866. data->regmap = devm_regmap_init_i2c(client, chip->has_comparator ?
  867. &ads1015_regmap_config :
  868. &tla2024_regmap_config);
  869. if (IS_ERR(data->regmap)) {
  870. dev_err(&client->dev, "Failed to allocate register map\n");
  871. return PTR_ERR(data->regmap);
  872. }
  873. ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
  874. ads1015_trigger_handler,
  875. &ads1015_buffer_setup_ops);
  876. if (ret < 0) {
  877. dev_err(&client->dev, "iio triggered buffer setup failed\n");
  878. return ret;
  879. }
  880. if (client->irq && chip->has_comparator) {
  881. unsigned long irq_trig =
  882. irqd_get_trigger_type(irq_get_irq_data(client->irq));
  883. unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
  884. ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
  885. unsigned int cfg_comp =
  886. ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
  887. 1 << ADS1015_CFG_COMP_LAT_SHIFT;
  888. switch (irq_trig) {
  889. case IRQF_TRIGGER_LOW:
  890. cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
  891. ADS1015_CFG_COMP_POL_SHIFT;
  892. break;
  893. case IRQF_TRIGGER_HIGH:
  894. cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
  895. ADS1015_CFG_COMP_POL_SHIFT;
  896. break;
  897. default:
  898. return -EINVAL;
  899. }
  900. ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
  901. cfg_comp_mask, cfg_comp);
  902. if (ret)
  903. return ret;
  904. ret = devm_request_threaded_irq(&client->dev, client->irq,
  905. NULL, ads1015_event_handler,
  906. irq_trig | IRQF_ONESHOT,
  907. client->name, indio_dev);
  908. if (ret)
  909. return ret;
  910. }
  911. ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
  912. if (ret)
  913. return ret;
  914. data->conv_invalid = true;
  915. ret = pm_runtime_set_active(&client->dev);
  916. if (ret)
  917. return ret;
  918. pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
  919. pm_runtime_use_autosuspend(&client->dev);
  920. pm_runtime_enable(&client->dev);
  921. ret = iio_device_register(indio_dev);
  922. if (ret < 0) {
  923. dev_err(&client->dev, "Failed to register IIO device\n");
  924. return ret;
  925. }
  926. return 0;
  927. }
  928. static void ads1015_remove(struct i2c_client *client)
  929. {
  930. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  931. struct ads1015_data *data = iio_priv(indio_dev);
  932. int ret;
  933. iio_device_unregister(indio_dev);
  934. pm_runtime_disable(&client->dev);
  935. pm_runtime_set_suspended(&client->dev);
  936. /* power down single shot mode */
  937. ret = ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
  938. if (ret)
  939. dev_warn(&client->dev, "Failed to power down (%pe)\n",
  940. ERR_PTR(ret));
  941. }
  942. #ifdef CONFIG_PM
  943. static int ads1015_runtime_suspend(struct device *dev)
  944. {
  945. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  946. struct ads1015_data *data = iio_priv(indio_dev);
  947. return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
  948. }
  949. static int ads1015_runtime_resume(struct device *dev)
  950. {
  951. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  952. struct ads1015_data *data = iio_priv(indio_dev);
  953. int ret;
  954. ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
  955. if (!ret)
  956. data->conv_invalid = true;
  957. return ret;
  958. }
  959. #endif
  960. static const struct dev_pm_ops ads1015_pm_ops = {
  961. SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
  962. ads1015_runtime_resume, NULL)
  963. };
  964. static const struct ads1015_chip_data ads1015_data = {
  965. .channels = ads1015_channels,
  966. .num_channels = ARRAY_SIZE(ads1015_channels),
  967. .info = &ads1015_info,
  968. .data_rate = ads1015_data_rate,
  969. .data_rate_len = ARRAY_SIZE(ads1015_data_rate),
  970. .scale = ads1015_scale,
  971. .scale_len = ARRAY_SIZE(ads1015_scale),
  972. .has_comparator = true,
  973. };
  974. static const struct ads1015_chip_data ads1115_data = {
  975. .channels = ads1115_channels,
  976. .num_channels = ARRAY_SIZE(ads1115_channels),
  977. .info = &ads1015_info,
  978. .data_rate = ads1115_data_rate,
  979. .data_rate_len = ARRAY_SIZE(ads1115_data_rate),
  980. .scale = ads1115_scale,
  981. .scale_len = ARRAY_SIZE(ads1115_scale),
  982. .has_comparator = true,
  983. };
  984. static const struct ads1015_chip_data tla2024_data = {
  985. .channels = tla2024_channels,
  986. .num_channels = ARRAY_SIZE(tla2024_channels),
  987. .info = &tla2024_info,
  988. .data_rate = ads1015_data_rate,
  989. .data_rate_len = ARRAY_SIZE(ads1015_data_rate),
  990. .scale = ads1015_scale,
  991. .scale_len = ARRAY_SIZE(ads1015_scale),
  992. .has_comparator = false,
  993. };
  994. static const struct i2c_device_id ads1015_id[] = {
  995. { "ads1015", (kernel_ulong_t)&ads1015_data },
  996. { "ads1115", (kernel_ulong_t)&ads1115_data },
  997. { "tla2024", (kernel_ulong_t)&tla2024_data },
  998. {}
  999. };
  1000. MODULE_DEVICE_TABLE(i2c, ads1015_id);
  1001. static const struct of_device_id ads1015_of_match[] = {
  1002. { .compatible = "ti,ads1015", .data = &ads1015_data },
  1003. { .compatible = "ti,ads1115", .data = &ads1115_data },
  1004. { .compatible = "ti,tla2024", .data = &tla2024_data },
  1005. {}
  1006. };
  1007. MODULE_DEVICE_TABLE(of, ads1015_of_match);
  1008. static struct i2c_driver ads1015_driver = {
  1009. .driver = {
  1010. .name = ADS1015_DRV_NAME,
  1011. .of_match_table = ads1015_of_match,
  1012. .pm = &ads1015_pm_ops,
  1013. },
  1014. .probe = ads1015_probe,
  1015. .remove = ads1015_remove,
  1016. .id_table = ads1015_id,
  1017. };
  1018. module_i2c_driver(ads1015_driver);
  1019. MODULE_AUTHOR("Daniel Baluta <[email protected]>");
  1020. MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
  1021. MODULE_LICENSE("GPL v2");