qti-glink-adc.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  4. */
  5. #include <linux/bitfield.h>
  6. #include <linux/bitops.h>
  7. #include <linux/kernel.h>
  8. #include <linux/module.h>
  9. #include <linux/mutex.h>
  10. #include <linux/of.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/property.h>
  13. #include <linux/slab.h>
  14. #include <linux/iio/iio.h>
  15. #include <linux/soc/qcom/pmic_glink.h>
  16. #define MSG_OWNER_SMB_ADC 32784
  17. #define MSG_TYPE_REQ_RESP 1
  18. #define SMB_ADC_READ_REQ_OP 0x49
  19. #define ADC_READ_WAIT_TIME_MS 1000
  20. enum glink_adc_channel {
  21. GLINK_ADC_CHAN_IIN = 1,
  22. GLINK_ADC_CHAN_ICHG = 2,
  23. GLINK_ADC_CHAN_DIE_TEMP = 3,
  24. GLINK_ADC_CHAN_MAX
  25. };
  26. enum smb_adc_read_status {
  27. SMB_ADC_READ_STATUS_SUCCESS = 0,
  28. SMB_ADC_READ_STATUS_ERR_NO_OPCODE = 0x100,
  29. SMB_ADC_READ_STATUS_ERR_FAILED = 0x200,
  30. SMB_ADC_READ_STATUS_ERR_NO_PMIC = 0x201,
  31. SMB_ADC_READ_STATUS_ERR_INVALID_PARAM = 0x202,
  32. };
  33. struct smb_adc_read_req_msg {
  34. struct pmic_glink_hdr hdr;
  35. u32 bus_id;
  36. u32 pmic_id;
  37. u32 chan;
  38. };
  39. struct smb_adc_read_resp_msg {
  40. struct pmic_glink_hdr hdr;
  41. u32 bus_id;
  42. u32 pmic_id;
  43. u32 chan;
  44. u32 raw_data;
  45. u32 conv_data;
  46. u32 status;
  47. };
  48. struct glink_adc_dev {
  49. struct pmic_glink_client *client;
  50. struct device *dev;
  51. struct mutex lock;
  52. struct completion ack;
  53. struct iio_chan_spec *iio_chans;
  54. unsigned int nchannels;
  55. struct smb_adc_read_resp_msg read_msg;
  56. };
  57. #define ADC_GLINK_CHAN(hwchan) FIELD_GET(GENMASK(7, 0), hwchan)
  58. #define ADC_GLINK_PMIC_ID(hwchan) FIELD_GET(GENMASK(15, 8), hwchan)
  59. #define ADC_GLINK_BUS_ID(hwchan) FIELD_GET(GENMASK(31, 16), hwchan)
  60. static void glink_adc_handle_read_resp(struct glink_adc_dev *adc,
  61. struct smb_adc_read_resp_msg *read_resp,
  62. size_t len)
  63. {
  64. if (len != sizeof(*read_resp)) {
  65. dev_err(adc->dev, "Invalid read response, glink packet size=%zu\n",
  66. len);
  67. return;
  68. }
  69. memcpy(&adc->read_msg, read_resp, sizeof(adc->read_msg));
  70. complete(&adc->ack);
  71. }
  72. static int glink_adc_callback(void *priv, void *data, size_t len)
  73. {
  74. struct glink_adc_dev *adc = priv;
  75. struct pmic_glink_hdr *hdr = data;
  76. dev_dbg(adc->dev, "owner: %u type: %u opcode: %#x len: %zu\n",
  77. hdr->owner, hdr->type, hdr->opcode, len);
  78. switch (hdr->opcode) {
  79. case SMB_ADC_READ_REQ_OP:
  80. glink_adc_handle_read_resp(adc, data, len);
  81. break;
  82. default:
  83. dev_err(adc->dev, "Unknown opcode %u\n", hdr->opcode);
  84. break;
  85. }
  86. return 0;
  87. }
  88. static int glink_adc_read_channel(struct glink_adc_dev *adc,
  89. struct iio_chan_spec const *chan,
  90. int *conv_data, int *raw_data)
  91. {
  92. struct smb_adc_read_req_msg msg = {{0}};
  93. int ret;
  94. msg.hdr.owner = MSG_OWNER_SMB_ADC;
  95. msg.hdr.type = MSG_TYPE_REQ_RESP;
  96. msg.hdr.opcode = SMB_ADC_READ_REQ_OP;
  97. msg.bus_id = ADC_GLINK_BUS_ID(chan->channel);
  98. msg.pmic_id = ADC_GLINK_PMIC_ID(chan->channel);
  99. msg.chan = ADC_GLINK_CHAN(chan->channel);
  100. mutex_lock(&adc->lock);
  101. reinit_completion(&adc->ack);
  102. ret = pmic_glink_write(adc->client, &msg, sizeof(msg));
  103. if (ret)
  104. goto done;
  105. ret = wait_for_completion_timeout(&adc->ack,
  106. msecs_to_jiffies(ADC_READ_WAIT_TIME_MS));
  107. if (!ret) {
  108. dev_err(adc->dev, "Error, ADC conversion timed out\n");
  109. ret = -ETIMEDOUT;
  110. goto done;
  111. }
  112. if (adc->read_msg.status != SMB_ADC_READ_STATUS_SUCCESS) {
  113. dev_err(adc->dev, "glink ADC read failed, bus_id=%u, pmic_id=%u, chan=%u, ret=%u\n",
  114. adc->read_msg.bus_id, adc->read_msg.pmic_id,
  115. adc->read_msg.chan, adc->read_msg.status);
  116. ret = -EIO;
  117. goto done;
  118. }
  119. if (conv_data)
  120. *conv_data = adc->read_msg.conv_data;
  121. if (raw_data)
  122. *raw_data = adc->read_msg.raw_data;
  123. ret = 0;
  124. done:
  125. mutex_unlock(&adc->lock);
  126. return ret;
  127. }
  128. static int glink_adc_read_raw(struct iio_dev *indio_dev,
  129. struct iio_chan_spec const *chan,
  130. int *val, int *val2, long mask)
  131. {
  132. struct glink_adc_dev *adc = iio_priv(indio_dev);
  133. int ret;
  134. switch (mask) {
  135. case IIO_CHAN_INFO_PROCESSED:
  136. ret = glink_adc_read_channel(adc, chan, val, NULL);
  137. if (ret < 0)
  138. return ret;
  139. return IIO_VAL_INT;
  140. case IIO_CHAN_INFO_RAW:
  141. ret = glink_adc_read_channel(adc, chan, NULL, val);
  142. if (ret < 0)
  143. return ret;
  144. return IIO_VAL_INT;
  145. default:
  146. return -EINVAL;
  147. }
  148. return 0;
  149. }
  150. static int glink_adc_fwnode_xlate(struct iio_dev *indio_dev,
  151. const struct fwnode_reference_args *iiospec)
  152. {
  153. int i;
  154. for (i = 0; i < indio_dev->num_channels; i++) {
  155. if (indio_dev->channels[i].channel == iiospec->args[0])
  156. return i;
  157. }
  158. return -EINVAL;
  159. }
  160. static const struct iio_info glink_adc_info = {
  161. .read_raw = glink_adc_read_raw,
  162. .fwnode_xlate = glink_adc_fwnode_xlate,
  163. };
  164. #define GLINK_ADC_CHAN(_name, _type) \
  165. { \
  166. .datasheet_name = _name, \
  167. .type = _type, \
  168. .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) \
  169. | BIT(IIO_CHAN_INFO_RAW), \
  170. } \
  171. static const struct iio_chan_spec glink_adc_channels[] = {
  172. [GLINK_ADC_CHAN_IIN] = GLINK_ADC_CHAN("iin", IIO_CURRENT),
  173. [GLINK_ADC_CHAN_ICHG] = GLINK_ADC_CHAN("ichg", IIO_CURRENT),
  174. [GLINK_ADC_CHAN_DIE_TEMP] = GLINK_ADC_CHAN("die_temp", IIO_TEMP),
  175. };
  176. static int glink_adc_get_dt_channel_data(struct glink_adc_dev *adc,
  177. struct fwnode_handle *fwnode,
  178. struct iio_chan_spec *iio_chan)
  179. {
  180. u32 reg, chan;
  181. int ret;
  182. ret = fwnode_property_read_u32(fwnode, "reg", &reg);
  183. if (ret < 0) {
  184. dev_err(adc->dev, "missing channel number %s, ret=%d\n",
  185. fwnode_get_name(fwnode), ret);
  186. return ret;
  187. }
  188. chan = ADC_GLINK_CHAN(reg);
  189. if (chan == 0 || chan >= GLINK_ADC_CHAN_MAX ||
  190. !glink_adc_channels[chan].datasheet_name) {
  191. dev_err(adc->dev, "%s invalid channel number %u\n",
  192. fwnode_get_name(fwnode), chan);
  193. return -EINVAL;
  194. }
  195. iio_chan->channel = reg;
  196. iio_chan->type = glink_adc_channels[chan].type;
  197. iio_chan->datasheet_name = glink_adc_channels[chan].datasheet_name;
  198. fwnode_property_read_string(fwnode, "label", &iio_chan->datasheet_name);
  199. iio_chan->extend_name = iio_chan->datasheet_name;
  200. iio_chan->info_mask_separate
  201. = glink_adc_channels[chan].info_mask_separate;
  202. return 0;
  203. }
  204. static int glink_adc_get_dt_data(struct glink_adc_dev *adc)
  205. {
  206. struct iio_chan_spec *iio_chan;
  207. struct fwnode_handle *child;
  208. int ret;
  209. adc->nchannels = device_get_child_node_count(adc->dev);
  210. if (!adc->nchannels) {
  211. dev_dbg(adc->dev, "no ADC channels specified\n");
  212. return -EINVAL;
  213. }
  214. adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
  215. sizeof(*adc->iio_chans), GFP_KERNEL);
  216. if (!adc->iio_chans)
  217. return -ENOMEM;
  218. iio_chan = adc->iio_chans;
  219. device_for_each_child_node(adc->dev, child) {
  220. ret = glink_adc_get_dt_channel_data(adc, child, iio_chan);
  221. if (ret < 0) {
  222. fwnode_handle_put(child);
  223. return ret;
  224. }
  225. iio_chan++;
  226. }
  227. return 0;
  228. }
  229. static int glink_adc_probe(struct platform_device *pdev)
  230. {
  231. struct glink_adc_dev *adc;
  232. struct iio_dev *indio_dev;
  233. struct pmic_glink_client_data client_data = { };
  234. int ret;
  235. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
  236. if (!indio_dev)
  237. return -ENOMEM;
  238. adc = iio_priv(indio_dev);
  239. adc->dev = &pdev->dev;
  240. mutex_init(&adc->lock);
  241. init_completion(&adc->ack);
  242. platform_set_drvdata(pdev, adc);
  243. client_data.id = MSG_OWNER_SMB_ADC;
  244. client_data.name = "adc";
  245. client_data.msg_cb = glink_adc_callback;
  246. client_data.priv = adc;
  247. ret = glink_adc_get_dt_data(adc);
  248. if (ret < 0)
  249. return ret;
  250. adc->client = pmic_glink_register_client(&pdev->dev, &client_data);
  251. if (IS_ERR(adc->client)) {
  252. ret = PTR_ERR(adc->client);
  253. if (ret != -EPROBE_DEFER)
  254. dev_err(&pdev->dev, "Error registering glink ADC, ret=%d\n",
  255. ret);
  256. return ret;
  257. }
  258. indio_dev->dev.parent = &pdev->dev;
  259. indio_dev->dev.of_node = pdev->dev.of_node;
  260. indio_dev->name = pdev->name;
  261. indio_dev->info = &glink_adc_info;
  262. indio_dev->modes = INDIO_DIRECT_MODE;
  263. indio_dev->channels = adc->iio_chans;
  264. indio_dev->num_channels = adc->nchannels;
  265. ret = devm_iio_device_register(&pdev->dev, indio_dev);
  266. if (ret < 0) {
  267. dev_err(&pdev->dev, "iio device registration failed, ret=%d\n",
  268. ret);
  269. goto fail;
  270. }
  271. return 0;
  272. fail:
  273. pmic_glink_unregister_client(adc->client);
  274. return ret;
  275. }
  276. static int glink_adc_remove(struct platform_device *pdev)
  277. {
  278. struct glink_adc_dev *adc = platform_get_drvdata(pdev);
  279. pmic_glink_unregister_client(adc->client);
  280. return 0;
  281. }
  282. static const struct of_device_id glink_adc_match_table[] = {
  283. { .compatible = "qcom,glink-adc", },
  284. {}
  285. };
  286. MODULE_DEVICE_TABLE(of, glink_adc_match_table);
  287. static struct platform_driver glink_adc_driver = {
  288. .driver = {
  289. .name = "glink_adc",
  290. .of_match_table = glink_adc_match_table,
  291. },
  292. .probe = glink_adc_probe,
  293. .remove = glink_adc_remove,
  294. };
  295. module_platform_driver(glink_adc_driver);
  296. MODULE_DESCRIPTION("Glink ADC Driver");
  297. MODULE_LICENSE("GPL");