berlin2-adc.c 10 KB

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  1. /*
  2. * Marvell Berlin2 ADC driver
  3. *
  4. * Copyright (C) 2015 Marvell Technology Group Ltd.
  5. *
  6. * Antoine Tenart <[email protected]>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/iio/iio.h>
  13. #include <linux/iio/driver.h>
  14. #include <linux/iio/machine.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel.h>
  17. #include <linux/mod_devicetable.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/slab.h>
  22. #include <linux/mfd/syscon.h>
  23. #include <linux/regmap.h>
  24. #include <linux/sched.h>
  25. #include <linux/wait.h>
  26. #define BERLIN2_SM_CTRL 0x14
  27. #define BERLIN2_SM_CTRL_SM_SOC_INT BIT(1)
  28. #define BERLIN2_SM_CTRL_SOC_SM_INT BIT(2)
  29. #define BERLIN2_SM_CTRL_ADC_SEL(x) ((x) << 5) /* 0-15 */
  30. #define BERLIN2_SM_CTRL_ADC_SEL_MASK GENMASK(8, 5)
  31. #define BERLIN2_SM_CTRL_ADC_POWER BIT(9)
  32. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV2 (0x0 << 10)
  33. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV3 (0x1 << 10)
  34. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV4 (0x2 << 10)
  35. #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV8 (0x3 << 10)
  36. #define BERLIN2_SM_CTRL_ADC_CLKSEL_MASK GENMASK(11, 10)
  37. #define BERLIN2_SM_CTRL_ADC_START BIT(12)
  38. #define BERLIN2_SM_CTRL_ADC_RESET BIT(13)
  39. #define BERLIN2_SM_CTRL_ADC_BANDGAP_RDY BIT(14)
  40. #define BERLIN2_SM_CTRL_ADC_CONT_SINGLE (0x0 << 15)
  41. #define BERLIN2_SM_CTRL_ADC_CONT_CONTINUOUS (0x1 << 15)
  42. #define BERLIN2_SM_CTRL_ADC_BUFFER_EN BIT(16)
  43. #define BERLIN2_SM_CTRL_ADC_VREF_EXT (0x0 << 17)
  44. #define BERLIN2_SM_CTRL_ADC_VREF_INT (0x1 << 17)
  45. #define BERLIN2_SM_CTRL_ADC_ROTATE BIT(19)
  46. #define BERLIN2_SM_CTRL_TSEN_EN BIT(20)
  47. #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_125 (0x0 << 21) /* 1.25 MHz */
  48. #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_250 (0x1 << 21) /* 2.5 MHz */
  49. #define BERLIN2_SM_CTRL_TSEN_MODE_0_125 (0x0 << 22) /* 0-125 C */
  50. #define BERLIN2_SM_CTRL_TSEN_MODE_10_50 (0x1 << 22) /* 10-50 C */
  51. #define BERLIN2_SM_CTRL_TSEN_RESET BIT(29)
  52. #define BERLIN2_SM_ADC_DATA 0x20
  53. #define BERLIN2_SM_ADC_MASK GENMASK(9, 0)
  54. #define BERLIN2_SM_ADC_STATUS 0x1c
  55. #define BERLIN2_SM_ADC_STATUS_DATA_RDY(x) BIT(x) /* 0-15 */
  56. #define BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK GENMASK(15, 0)
  57. #define BERLIN2_SM_ADC_STATUS_INT_EN(x) (BIT(x) << 16) /* 0-15 */
  58. #define BERLIN2_SM_ADC_STATUS_INT_EN_MASK GENMASK(31, 16)
  59. #define BERLIN2_SM_TSEN_STATUS 0x24
  60. #define BERLIN2_SM_TSEN_STATUS_DATA_RDY BIT(0)
  61. #define BERLIN2_SM_TSEN_STATUS_INT_EN BIT(1)
  62. #define BERLIN2_SM_TSEN_DATA 0x28
  63. #define BERLIN2_SM_TSEN_MASK GENMASK(9, 0)
  64. #define BERLIN2_SM_TSEN_CTRL 0x74
  65. #define BERLIN2_SM_TSEN_CTRL_START BIT(8)
  66. #define BERLIN2_SM_TSEN_CTRL_SETTLING_4 (0x0 << 21) /* 4 us */
  67. #define BERLIN2_SM_TSEN_CTRL_SETTLING_12 (0x1 << 21) /* 12 us */
  68. #define BERLIN2_SM_TSEN_CTRL_SETTLING_MASK BIT(21)
  69. #define BERLIN2_SM_TSEN_CTRL_TRIM(x) ((x) << 22)
  70. #define BERLIN2_SM_TSEN_CTRL_TRIM_MASK GENMASK(25, 22)
  71. struct berlin2_adc_priv {
  72. struct regmap *regmap;
  73. struct mutex lock;
  74. wait_queue_head_t wq;
  75. bool data_available;
  76. int data;
  77. };
  78. #define BERLIN2_ADC_CHANNEL(n, t) \
  79. { \
  80. .channel = n, \
  81. .datasheet_name = "channel"#n, \
  82. .type = t, \
  83. .indexed = 1, \
  84. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  85. }
  86. static const struct iio_chan_spec berlin2_adc_channels[] = {
  87. BERLIN2_ADC_CHANNEL(0, IIO_VOLTAGE), /* external input */
  88. BERLIN2_ADC_CHANNEL(1, IIO_VOLTAGE), /* external input */
  89. BERLIN2_ADC_CHANNEL(2, IIO_VOLTAGE), /* external input */
  90. BERLIN2_ADC_CHANNEL(3, IIO_VOLTAGE), /* external input */
  91. BERLIN2_ADC_CHANNEL(4, IIO_VOLTAGE), /* reserved */
  92. BERLIN2_ADC_CHANNEL(5, IIO_VOLTAGE), /* reserved */
  93. { /* temperature sensor */
  94. .channel = 6,
  95. .datasheet_name = "channel6",
  96. .type = IIO_TEMP,
  97. .indexed = 0,
  98. .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
  99. },
  100. BERLIN2_ADC_CHANNEL(7, IIO_VOLTAGE), /* reserved */
  101. IIO_CHAN_SOFT_TIMESTAMP(8), /* timestamp */
  102. };
  103. static int berlin2_adc_read(struct iio_dev *indio_dev, int channel)
  104. {
  105. struct berlin2_adc_priv *priv = iio_priv(indio_dev);
  106. int data, ret;
  107. mutex_lock(&priv->lock);
  108. /* Enable the interrupts */
  109. regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS,
  110. BERLIN2_SM_ADC_STATUS_INT_EN(channel));
  111. /* Configure the ADC */
  112. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  113. BERLIN2_SM_CTRL_ADC_RESET |
  114. BERLIN2_SM_CTRL_ADC_SEL_MASK |
  115. BERLIN2_SM_CTRL_ADC_START,
  116. BERLIN2_SM_CTRL_ADC_SEL(channel) |
  117. BERLIN2_SM_CTRL_ADC_START);
  118. ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
  119. msecs_to_jiffies(1000));
  120. /* Disable the interrupts */
  121. regmap_update_bits(priv->regmap, BERLIN2_SM_ADC_STATUS,
  122. BERLIN2_SM_ADC_STATUS_INT_EN(channel), 0);
  123. if (ret == 0)
  124. ret = -ETIMEDOUT;
  125. if (ret < 0) {
  126. mutex_unlock(&priv->lock);
  127. return ret;
  128. }
  129. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  130. BERLIN2_SM_CTRL_ADC_START, 0);
  131. data = priv->data;
  132. priv->data_available = false;
  133. mutex_unlock(&priv->lock);
  134. return data;
  135. }
  136. static int berlin2_adc_tsen_read(struct iio_dev *indio_dev)
  137. {
  138. struct berlin2_adc_priv *priv = iio_priv(indio_dev);
  139. int data, ret;
  140. mutex_lock(&priv->lock);
  141. /* Enable interrupts */
  142. regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS,
  143. BERLIN2_SM_TSEN_STATUS_INT_EN);
  144. /* Configure the ADC */
  145. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  146. BERLIN2_SM_CTRL_TSEN_RESET |
  147. BERLIN2_SM_CTRL_ADC_ROTATE,
  148. BERLIN2_SM_CTRL_ADC_ROTATE);
  149. /* Configure the temperature sensor */
  150. regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
  151. BERLIN2_SM_TSEN_CTRL_TRIM_MASK |
  152. BERLIN2_SM_TSEN_CTRL_SETTLING_MASK |
  153. BERLIN2_SM_TSEN_CTRL_START,
  154. BERLIN2_SM_TSEN_CTRL_TRIM(3) |
  155. BERLIN2_SM_TSEN_CTRL_SETTLING_12 |
  156. BERLIN2_SM_TSEN_CTRL_START);
  157. ret = wait_event_interruptible_timeout(priv->wq, priv->data_available,
  158. msecs_to_jiffies(1000));
  159. /* Disable interrupts */
  160. regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_STATUS,
  161. BERLIN2_SM_TSEN_STATUS_INT_EN, 0);
  162. if (ret == 0)
  163. ret = -ETIMEDOUT;
  164. if (ret < 0) {
  165. mutex_unlock(&priv->lock);
  166. return ret;
  167. }
  168. regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL,
  169. BERLIN2_SM_TSEN_CTRL_START, 0);
  170. data = priv->data;
  171. priv->data_available = false;
  172. mutex_unlock(&priv->lock);
  173. return data;
  174. }
  175. static int berlin2_adc_read_raw(struct iio_dev *indio_dev,
  176. struct iio_chan_spec const *chan, int *val,
  177. int *val2, long mask)
  178. {
  179. int temp;
  180. switch (mask) {
  181. case IIO_CHAN_INFO_RAW:
  182. if (chan->type != IIO_VOLTAGE)
  183. return -EINVAL;
  184. *val = berlin2_adc_read(indio_dev, chan->channel);
  185. if (*val < 0)
  186. return *val;
  187. return IIO_VAL_INT;
  188. case IIO_CHAN_INFO_PROCESSED:
  189. if (chan->type != IIO_TEMP)
  190. return -EINVAL;
  191. temp = berlin2_adc_tsen_read(indio_dev);
  192. if (temp < 0)
  193. return temp;
  194. if (temp > 2047)
  195. temp -= 4096;
  196. /* Convert to milli Celsius */
  197. *val = ((temp * 100000) / 264 - 270000);
  198. return IIO_VAL_INT;
  199. default:
  200. break;
  201. }
  202. return -EINVAL;
  203. }
  204. static irqreturn_t berlin2_adc_irq(int irq, void *private)
  205. {
  206. struct berlin2_adc_priv *priv = iio_priv(private);
  207. unsigned val;
  208. regmap_read(priv->regmap, BERLIN2_SM_ADC_STATUS, &val);
  209. if (val & BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK) {
  210. regmap_read(priv->regmap, BERLIN2_SM_ADC_DATA, &priv->data);
  211. priv->data &= BERLIN2_SM_ADC_MASK;
  212. val &= ~BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK;
  213. regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, val);
  214. priv->data_available = true;
  215. wake_up_interruptible(&priv->wq);
  216. }
  217. return IRQ_HANDLED;
  218. }
  219. static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private)
  220. {
  221. struct berlin2_adc_priv *priv = iio_priv(private);
  222. unsigned val;
  223. regmap_read(priv->regmap, BERLIN2_SM_TSEN_STATUS, &val);
  224. if (val & BERLIN2_SM_TSEN_STATUS_DATA_RDY) {
  225. regmap_read(priv->regmap, BERLIN2_SM_TSEN_DATA, &priv->data);
  226. priv->data &= BERLIN2_SM_TSEN_MASK;
  227. val &= ~BERLIN2_SM_TSEN_STATUS_DATA_RDY;
  228. regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, val);
  229. priv->data_available = true;
  230. wake_up_interruptible(&priv->wq);
  231. }
  232. return IRQ_HANDLED;
  233. }
  234. static const struct iio_info berlin2_adc_info = {
  235. .read_raw = berlin2_adc_read_raw,
  236. };
  237. static void berlin2_adc_powerdown(void *regmap)
  238. {
  239. regmap_update_bits(regmap, BERLIN2_SM_CTRL,
  240. BERLIN2_SM_CTRL_ADC_POWER, 0);
  241. }
  242. static int berlin2_adc_probe(struct platform_device *pdev)
  243. {
  244. struct iio_dev *indio_dev;
  245. struct berlin2_adc_priv *priv;
  246. struct device_node *parent_np = of_get_parent(pdev->dev.of_node);
  247. int irq, tsen_irq;
  248. int ret;
  249. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
  250. if (!indio_dev) {
  251. of_node_put(parent_np);
  252. return -ENOMEM;
  253. }
  254. priv = iio_priv(indio_dev);
  255. priv->regmap = syscon_node_to_regmap(parent_np);
  256. of_node_put(parent_np);
  257. if (IS_ERR(priv->regmap))
  258. return PTR_ERR(priv->regmap);
  259. irq = platform_get_irq_byname(pdev, "adc");
  260. if (irq < 0)
  261. return irq;
  262. tsen_irq = platform_get_irq_byname(pdev, "tsen");
  263. if (tsen_irq < 0)
  264. return tsen_irq;
  265. ret = devm_request_irq(&pdev->dev, irq, berlin2_adc_irq, 0,
  266. pdev->dev.driver->name, indio_dev);
  267. if (ret)
  268. return ret;
  269. ret = devm_request_irq(&pdev->dev, tsen_irq, berlin2_adc_tsen_irq,
  270. 0, pdev->dev.driver->name, indio_dev);
  271. if (ret)
  272. return ret;
  273. init_waitqueue_head(&priv->wq);
  274. mutex_init(&priv->lock);
  275. indio_dev->name = dev_name(&pdev->dev);
  276. indio_dev->modes = INDIO_DIRECT_MODE;
  277. indio_dev->info = &berlin2_adc_info;
  278. indio_dev->channels = berlin2_adc_channels;
  279. indio_dev->num_channels = ARRAY_SIZE(berlin2_adc_channels);
  280. /* Power up the ADC */
  281. regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL,
  282. BERLIN2_SM_CTRL_ADC_POWER,
  283. BERLIN2_SM_CTRL_ADC_POWER);
  284. ret = devm_add_action_or_reset(&pdev->dev, berlin2_adc_powerdown,
  285. priv->regmap);
  286. if (ret)
  287. return ret;
  288. return devm_iio_device_register(&pdev->dev, indio_dev);
  289. }
  290. static const struct of_device_id berlin2_adc_match[] = {
  291. { .compatible = "marvell,berlin2-adc", },
  292. { },
  293. };
  294. MODULE_DEVICE_TABLE(of, berlin2_adc_match);
  295. static struct platform_driver berlin2_adc_driver = {
  296. .driver = {
  297. .name = "berlin2-adc",
  298. .of_match_table = berlin2_adc_match,
  299. },
  300. .probe = berlin2_adc_probe,
  301. };
  302. module_platform_driver(berlin2_adc_driver);
  303. MODULE_AUTHOR("Antoine Tenart <[email protected]>");
  304. MODULE_DESCRIPTION("Marvell Berlin2 ADC driver");
  305. MODULE_LICENSE("GPL v2");