ad7887.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * AD7887 SPI ADC driver
  4. *
  5. * Copyright 2010-2011 Analog Devices Inc.
  6. */
  7. #include <linux/device.h>
  8. #include <linux/kernel.h>
  9. #include <linux/slab.h>
  10. #include <linux/sysfs.h>
  11. #include <linux/spi/spi.h>
  12. #include <linux/regulator/consumer.h>
  13. #include <linux/err.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/bitops.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/sysfs.h>
  19. #include <linux/iio/buffer.h>
  20. #include <linux/iio/trigger_consumer.h>
  21. #include <linux/iio/triggered_buffer.h>
  22. #include <linux/platform_data/ad7887.h>
  23. #define AD7887_REF_DIS BIT(5) /* on-chip reference disable */
  24. #define AD7887_DUAL BIT(4) /* dual-channel mode */
  25. #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
  26. #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
  27. #define AD7887_PM_MODE1 0 /* CS based shutdown */
  28. #define AD7887_PM_MODE2 1 /* full on */
  29. #define AD7887_PM_MODE3 2 /* auto shutdown after conversion */
  30. #define AD7887_PM_MODE4 3 /* standby mode */
  31. enum ad7887_channels {
  32. AD7887_CH0,
  33. AD7887_CH0_CH1,
  34. AD7887_CH1,
  35. };
  36. /**
  37. * struct ad7887_chip_info - chip specifc information
  38. * @int_vref_mv: the internal reference voltage
  39. * @channels: channels specification
  40. * @num_channels: number of channels
  41. * @dual_channels: channels specification in dual mode
  42. * @num_dual_channels: number of channels in dual mode
  43. */
  44. struct ad7887_chip_info {
  45. u16 int_vref_mv;
  46. const struct iio_chan_spec *channels;
  47. unsigned int num_channels;
  48. const struct iio_chan_spec *dual_channels;
  49. unsigned int num_dual_channels;
  50. };
  51. struct ad7887_state {
  52. struct spi_device *spi;
  53. const struct ad7887_chip_info *chip_info;
  54. struct regulator *reg;
  55. struct spi_transfer xfer[4];
  56. struct spi_message msg[3];
  57. struct spi_message *ring_msg;
  58. unsigned char tx_cmd_buf[4];
  59. /*
  60. * DMA (thus cache coherency maintenance) may require the
  61. * transfer buffers to live in their own cache lines.
  62. * Buffer needs to be large enough to hold two 16 bit samples and a
  63. * 64 bit aligned 64 bit timestamp.
  64. */
  65. unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
  66. };
  67. enum ad7887_supported_device_ids {
  68. ID_AD7887
  69. };
  70. static int ad7887_ring_preenable(struct iio_dev *indio_dev)
  71. {
  72. struct ad7887_state *st = iio_priv(indio_dev);
  73. /* We know this is a single long so can 'cheat' */
  74. switch (*indio_dev->active_scan_mask) {
  75. case (1 << 0):
  76. st->ring_msg = &st->msg[AD7887_CH0];
  77. break;
  78. case (1 << 1):
  79. st->ring_msg = &st->msg[AD7887_CH1];
  80. /* Dummy read: push CH1 setting down to hardware */
  81. spi_sync(st->spi, st->ring_msg);
  82. break;
  83. case ((1 << 1) | (1 << 0)):
  84. st->ring_msg = &st->msg[AD7887_CH0_CH1];
  85. break;
  86. }
  87. return 0;
  88. }
  89. static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
  90. {
  91. struct ad7887_state *st = iio_priv(indio_dev);
  92. /* dummy read: restore default CH0 settin */
  93. return spi_sync(st->spi, &st->msg[AD7887_CH0]);
  94. }
  95. static irqreturn_t ad7887_trigger_handler(int irq, void *p)
  96. {
  97. struct iio_poll_func *pf = p;
  98. struct iio_dev *indio_dev = pf->indio_dev;
  99. struct ad7887_state *st = iio_priv(indio_dev);
  100. int b_sent;
  101. b_sent = spi_sync(st->spi, st->ring_msg);
  102. if (b_sent)
  103. goto done;
  104. iio_push_to_buffers_with_timestamp(indio_dev, st->data,
  105. iio_get_time_ns(indio_dev));
  106. done:
  107. iio_trigger_notify_done(indio_dev->trig);
  108. return IRQ_HANDLED;
  109. }
  110. static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
  111. .preenable = &ad7887_ring_preenable,
  112. .postdisable = &ad7887_ring_postdisable,
  113. };
  114. static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
  115. {
  116. int ret = spi_sync(st->spi, &st->msg[ch]);
  117. if (ret)
  118. return ret;
  119. return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
  120. }
  121. static int ad7887_read_raw(struct iio_dev *indio_dev,
  122. struct iio_chan_spec const *chan,
  123. int *val,
  124. int *val2,
  125. long m)
  126. {
  127. int ret;
  128. struct ad7887_state *st = iio_priv(indio_dev);
  129. switch (m) {
  130. case IIO_CHAN_INFO_RAW:
  131. ret = iio_device_claim_direct_mode(indio_dev);
  132. if (ret)
  133. return ret;
  134. ret = ad7887_scan_direct(st, chan->address);
  135. iio_device_release_direct_mode(indio_dev);
  136. if (ret < 0)
  137. return ret;
  138. *val = ret >> chan->scan_type.shift;
  139. *val &= GENMASK(chan->scan_type.realbits - 1, 0);
  140. return IIO_VAL_INT;
  141. case IIO_CHAN_INFO_SCALE:
  142. if (st->reg) {
  143. *val = regulator_get_voltage(st->reg);
  144. if (*val < 0)
  145. return *val;
  146. *val /= 1000;
  147. } else {
  148. *val = st->chip_info->int_vref_mv;
  149. }
  150. *val2 = chan->scan_type.realbits;
  151. return IIO_VAL_FRACTIONAL_LOG2;
  152. }
  153. return -EINVAL;
  154. }
  155. #define AD7887_CHANNEL(x) { \
  156. .type = IIO_VOLTAGE, \
  157. .indexed = 1, \
  158. .channel = (x), \
  159. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  160. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
  161. .address = (x), \
  162. .scan_index = (x), \
  163. .scan_type = { \
  164. .sign = 'u', \
  165. .realbits = 12, \
  166. .storagebits = 16, \
  167. .shift = 0, \
  168. .endianness = IIO_BE, \
  169. }, \
  170. }
  171. static const struct iio_chan_spec ad7887_channels[] = {
  172. AD7887_CHANNEL(0),
  173. IIO_CHAN_SOFT_TIMESTAMP(1),
  174. };
  175. static const struct iio_chan_spec ad7887_dual_channels[] = {
  176. AD7887_CHANNEL(0),
  177. AD7887_CHANNEL(1),
  178. IIO_CHAN_SOFT_TIMESTAMP(2),
  179. };
  180. static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
  181. /*
  182. * More devices added in future
  183. */
  184. [ID_AD7887] = {
  185. .channels = ad7887_channels,
  186. .num_channels = ARRAY_SIZE(ad7887_channels),
  187. .dual_channels = ad7887_dual_channels,
  188. .num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
  189. .int_vref_mv = 2500,
  190. },
  191. };
  192. static const struct iio_info ad7887_info = {
  193. .read_raw = &ad7887_read_raw,
  194. };
  195. static void ad7887_reg_disable(void *data)
  196. {
  197. struct regulator *reg = data;
  198. regulator_disable(reg);
  199. }
  200. static int ad7887_probe(struct spi_device *spi)
  201. {
  202. struct ad7887_platform_data *pdata = spi->dev.platform_data;
  203. struct ad7887_state *st;
  204. struct iio_dev *indio_dev;
  205. uint8_t mode;
  206. int ret;
  207. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  208. if (indio_dev == NULL)
  209. return -ENOMEM;
  210. st = iio_priv(indio_dev);
  211. st->reg = devm_regulator_get_optional(&spi->dev, "vref");
  212. if (IS_ERR(st->reg)) {
  213. if (PTR_ERR(st->reg) != -ENODEV)
  214. return PTR_ERR(st->reg);
  215. st->reg = NULL;
  216. }
  217. if (st->reg) {
  218. ret = regulator_enable(st->reg);
  219. if (ret)
  220. return ret;
  221. ret = devm_add_action_or_reset(&spi->dev, ad7887_reg_disable, st->reg);
  222. if (ret)
  223. return ret;
  224. }
  225. st->chip_info =
  226. &ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
  227. st->spi = spi;
  228. indio_dev->name = spi_get_device_id(spi)->name;
  229. indio_dev->info = &ad7887_info;
  230. indio_dev->modes = INDIO_DIRECT_MODE;
  231. /* Setup default message */
  232. mode = AD7887_PM_MODE4;
  233. if (!st->reg)
  234. mode |= AD7887_REF_DIS;
  235. if (pdata && pdata->en_dual)
  236. mode |= AD7887_DUAL;
  237. st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;
  238. st->xfer[0].rx_buf = &st->data[0];
  239. st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
  240. st->xfer[0].len = 2;
  241. spi_message_init(&st->msg[AD7887_CH0]);
  242. spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
  243. if (pdata && pdata->en_dual) {
  244. st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;
  245. st->xfer[1].rx_buf = &st->data[0];
  246. st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
  247. st->xfer[1].len = 2;
  248. st->xfer[2].rx_buf = &st->data[2];
  249. st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
  250. st->xfer[2].len = 2;
  251. spi_message_init(&st->msg[AD7887_CH0_CH1]);
  252. spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
  253. spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
  254. st->xfer[3].rx_buf = &st->data[2];
  255. st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
  256. st->xfer[3].len = 2;
  257. spi_message_init(&st->msg[AD7887_CH1]);
  258. spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
  259. indio_dev->channels = st->chip_info->dual_channels;
  260. indio_dev->num_channels = st->chip_info->num_dual_channels;
  261. } else {
  262. indio_dev->channels = st->chip_info->channels;
  263. indio_dev->num_channels = st->chip_info->num_channels;
  264. }
  265. ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
  266. &iio_pollfunc_store_time,
  267. &ad7887_trigger_handler, &ad7887_ring_setup_ops);
  268. if (ret)
  269. return ret;
  270. return devm_iio_device_register(&spi->dev, indio_dev);
  271. }
  272. static const struct spi_device_id ad7887_id[] = {
  273. {"ad7887", ID_AD7887},
  274. {}
  275. };
  276. MODULE_DEVICE_TABLE(spi, ad7887_id);
  277. static struct spi_driver ad7887_driver = {
  278. .driver = {
  279. .name = "ad7887",
  280. },
  281. .probe = ad7887_probe,
  282. .id_table = ad7887_id,
  283. };
  284. module_spi_driver(ad7887_driver);
  285. MODULE_AUTHOR("Michael Hennerich <[email protected]>");
  286. MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
  287. MODULE_LICENSE("GPL v2");