sca3000.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
  4. *
  5. * Copyright (c) 2009 Jonathan Cameron <[email protected]>
  6. *
  7. * See industrialio/accels/sca3000.h for comments.
  8. */
  9. #include <linux/interrupt.h>
  10. #include <linux/fs.h>
  11. #include <linux/device.h>
  12. #include <linux/slab.h>
  13. #include <linux/kernel.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/sysfs.h>
  16. #include <linux/module.h>
  17. #include <linux/uaccess.h>
  18. #include <linux/iio/iio.h>
  19. #include <linux/iio/sysfs.h>
  20. #include <linux/iio/events.h>
  21. #include <linux/iio/buffer.h>
  22. #include <linux/iio/kfifo_buf.h>
  23. #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
  24. #define SCA3000_READ_REG(a) ((a) << 2)
  25. #define SCA3000_REG_REVID_ADDR 0x00
  26. #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
  27. #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
  28. #define SCA3000_REG_STATUS_ADDR 0x02
  29. #define SCA3000_LOCKED BIT(5)
  30. #define SCA3000_EEPROM_CS_ERROR BIT(1)
  31. #define SCA3000_SPI_FRAME_ERROR BIT(0)
  32. /* All reads done using register decrement so no need to directly access LSBs */
  33. #define SCA3000_REG_X_MSB_ADDR 0x05
  34. #define SCA3000_REG_Y_MSB_ADDR 0x07
  35. #define SCA3000_REG_Z_MSB_ADDR 0x09
  36. #define SCA3000_REG_RING_OUT_ADDR 0x0f
  37. /* Temp read untested - the e05 doesn't have the sensor */
  38. #define SCA3000_REG_TEMP_MSB_ADDR 0x13
  39. #define SCA3000_REG_MODE_ADDR 0x14
  40. #define SCA3000_MODE_PROT_MASK 0x28
  41. #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
  42. #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
  43. /*
  44. * Free fall detection triggers an interrupt if the acceleration
  45. * is below a threshold for equivalent of 25cm drop
  46. */
  47. #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
  48. #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
  49. #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
  50. #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
  51. /*
  52. * In motion detection mode the accelerations are band pass filtered
  53. * (approx 1 - 25Hz) and then a programmable threshold used to trigger
  54. * and interrupt.
  55. */
  56. #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
  57. #define SCA3000_REG_MODE_MODE_MASK 0x03
  58. #define SCA3000_REG_BUF_COUNT_ADDR 0x15
  59. #define SCA3000_REG_INT_STATUS_ADDR 0x16
  60. #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
  61. #define SCA3000_REG_INT_STATUS_HALF BIT(6)
  62. #define SCA3000_INT_STATUS_FREE_FALL BIT(3)
  63. #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
  64. #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
  65. #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
  66. /* Used to allow access to multiplexed registers */
  67. #define SCA3000_REG_CTRL_SEL_ADDR 0x18
  68. /* Only available for SCA3000-D03 and SCA3000-D01 */
  69. #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
  70. #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
  71. #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
  72. #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
  73. #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
  74. /*
  75. * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
  76. * will not function
  77. */
  78. #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
  79. #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
  80. #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
  81. #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
  82. #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
  83. #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
  84. #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
  85. #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
  86. /*
  87. * Control which motion detector interrupts are on.
  88. * For now only OR combinations are supported.
  89. */
  90. #define SCA3000_MD_CTRL_PROT_MASK 0xC0
  91. #define SCA3000_MD_CTRL_OR_Y BIT(0)
  92. #define SCA3000_MD_CTRL_OR_X BIT(1)
  93. #define SCA3000_MD_CTRL_OR_Z BIT(2)
  94. /* Currently unsupported */
  95. #define SCA3000_MD_CTRL_AND_Y BIT(3)
  96. #define SCA3000_MD_CTRL_AND_X BIT(4)
  97. #define SCA3000_MD_CTRL_AND_Z BIT(5)
  98. /*
  99. * Some control registers of complex access methods requiring this register to
  100. * be used to remove a lock.
  101. */
  102. #define SCA3000_REG_UNLOCK_ADDR 0x1e
  103. #define SCA3000_REG_INT_MASK_ADDR 0x21
  104. #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
  105. #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
  106. #define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
  107. #define SCA3000_REG_INT_MASK_ALL_INTS 0x02
  108. #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
  109. #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
  110. /* Values of multiplexed registers (write to ctrl_data after select) */
  111. #define SCA3000_REG_CTRL_DATA_ADDR 0x22
  112. /*
  113. * Measurement modes available on some sca3000 series chips. Code assumes others
  114. * may become available in the future.
  115. *
  116. * Bypass - Bypass the low-pass filter in the signal channel so as to increase
  117. * signal bandwidth.
  118. *
  119. * Narrow - Narrow low-pass filtering of the signal channel and half output
  120. * data rate by decimation.
  121. *
  122. * Wide - Widen low-pass filtering of signal channel to increase bandwidth
  123. */
  124. #define SCA3000_OP_MODE_BYPASS 0x01
  125. #define SCA3000_OP_MODE_NARROW 0x02
  126. #define SCA3000_OP_MODE_WIDE 0x04
  127. #define SCA3000_MAX_TX 6
  128. #define SCA3000_MAX_RX 2
  129. /**
  130. * struct sca3000_state - device instance state information
  131. * @us: the associated spi device
  132. * @info: chip variant information
  133. * @last_timestamp: the timestamp of the last event
  134. * @mo_det_use_count: reference counter for the motion detection unit
  135. * @lock: lock used to protect elements of sca3000_state
  136. * and the underlying device state.
  137. * @tx: dma-able transmit buffer
  138. * @rx: dma-able receive buffer
  139. **/
  140. struct sca3000_state {
  141. struct spi_device *us;
  142. const struct sca3000_chip_info *info;
  143. s64 last_timestamp;
  144. int mo_det_use_count;
  145. struct mutex lock;
  146. /* Can these share a cacheline ? */
  147. u8 rx[384] __aligned(IIO_DMA_MINALIGN);
  148. u8 tx[6] __aligned(IIO_DMA_MINALIGN);
  149. };
  150. /**
  151. * struct sca3000_chip_info - model dependent parameters
  152. * @scale: scale * 10^-6
  153. * @temp_output: some devices have temperature sensors.
  154. * @measurement_mode_freq: normal mode sampling frequency
  155. * @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for
  156. * the normal measurement mode.
  157. * @option_mode_1: first optional mode. Not all models have one
  158. * @option_mode_1_freq: option mode 1 sampling frequency
  159. * @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for
  160. * the first option mode.
  161. * @option_mode_2: second optional mode. Not all chips have one
  162. * @option_mode_2_freq: option mode 2 sampling frequency
  163. * @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for
  164. * the second option mode.
  165. * @mot_det_mult_xz: Bit wise multipliers to calculate the threshold
  166. * for motion detection in the x and z axis.
  167. * @mot_det_mult_y: Bit wise multipliers to calculate the threshold
  168. * for motion detection in the y axis.
  169. *
  170. * This structure is used to hold information about the functionality of a given
  171. * sca3000 variant.
  172. **/
  173. struct sca3000_chip_info {
  174. unsigned int scale;
  175. bool temp_output;
  176. int measurement_mode_freq;
  177. int measurement_mode_3db_freq;
  178. int option_mode_1;
  179. int option_mode_1_freq;
  180. int option_mode_1_3db_freq;
  181. int option_mode_2;
  182. int option_mode_2_freq;
  183. int option_mode_2_3db_freq;
  184. int mot_det_mult_xz[6];
  185. int mot_det_mult_y[7];
  186. };
  187. enum sca3000_variant {
  188. d01,
  189. e02,
  190. e04,
  191. e05,
  192. };
  193. /*
  194. * Note where option modes are not defined, the chip simply does not
  195. * support any.
  196. * Other chips in the sca3000 series use i2c and are not included here.
  197. *
  198. * Some of these devices are only listed in the family data sheet and
  199. * do not actually appear to be available.
  200. */
  201. static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
  202. [d01] = {
  203. .scale = 7357,
  204. .temp_output = true,
  205. .measurement_mode_freq = 250,
  206. .measurement_mode_3db_freq = 45,
  207. .option_mode_1 = SCA3000_OP_MODE_BYPASS,
  208. .option_mode_1_freq = 250,
  209. .option_mode_1_3db_freq = 70,
  210. .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
  211. .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
  212. },
  213. [e02] = {
  214. .scale = 9810,
  215. .measurement_mode_freq = 125,
  216. .measurement_mode_3db_freq = 40,
  217. .option_mode_1 = SCA3000_OP_MODE_NARROW,
  218. .option_mode_1_freq = 63,
  219. .option_mode_1_3db_freq = 11,
  220. .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
  221. .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
  222. },
  223. [e04] = {
  224. .scale = 19620,
  225. .measurement_mode_freq = 100,
  226. .measurement_mode_3db_freq = 38,
  227. .option_mode_1 = SCA3000_OP_MODE_NARROW,
  228. .option_mode_1_freq = 50,
  229. .option_mode_1_3db_freq = 9,
  230. .option_mode_2 = SCA3000_OP_MODE_WIDE,
  231. .option_mode_2_freq = 400,
  232. .option_mode_2_3db_freq = 70,
  233. .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
  234. .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
  235. },
  236. [e05] = {
  237. .scale = 61313,
  238. .measurement_mode_freq = 200,
  239. .measurement_mode_3db_freq = 60,
  240. .option_mode_1 = SCA3000_OP_MODE_NARROW,
  241. .option_mode_1_freq = 50,
  242. .option_mode_1_3db_freq = 9,
  243. .option_mode_2 = SCA3000_OP_MODE_WIDE,
  244. .option_mode_2_freq = 400,
  245. .option_mode_2_3db_freq = 75,
  246. .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
  247. .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
  248. },
  249. };
  250. static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
  251. {
  252. st->tx[0] = SCA3000_WRITE_REG(address);
  253. st->tx[1] = val;
  254. return spi_write(st->us, st->tx, 2);
  255. }
  256. static int sca3000_read_data_short(struct sca3000_state *st,
  257. u8 reg_address_high,
  258. int len)
  259. {
  260. struct spi_transfer xfer[2] = {
  261. {
  262. .len = 1,
  263. .tx_buf = st->tx,
  264. }, {
  265. .len = len,
  266. .rx_buf = st->rx,
  267. }
  268. };
  269. st->tx[0] = SCA3000_READ_REG(reg_address_high);
  270. return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
  271. }
  272. /**
  273. * sca3000_reg_lock_on() - test if the ctrl register lock is on
  274. * @st: Driver specific device instance data.
  275. *
  276. * Lock must be held.
  277. **/
  278. static int sca3000_reg_lock_on(struct sca3000_state *st)
  279. {
  280. int ret;
  281. ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
  282. if (ret < 0)
  283. return ret;
  284. return !(st->rx[0] & SCA3000_LOCKED);
  285. }
  286. /**
  287. * __sca3000_unlock_reg_lock() - unlock the control registers
  288. * @st: Driver specific device instance data.
  289. *
  290. * Note the device does not appear to support doing this in a single transfer.
  291. * This should only ever be used as part of ctrl reg read.
  292. * Lock must be held before calling this
  293. */
  294. static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
  295. {
  296. struct spi_transfer xfer[3] = {
  297. {
  298. .len = 2,
  299. .cs_change = 1,
  300. .tx_buf = st->tx,
  301. }, {
  302. .len = 2,
  303. .cs_change = 1,
  304. .tx_buf = st->tx + 2,
  305. }, {
  306. .len = 2,
  307. .tx_buf = st->tx + 4,
  308. },
  309. };
  310. st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
  311. st->tx[1] = 0x00;
  312. st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
  313. st->tx[3] = 0x50;
  314. st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
  315. st->tx[5] = 0xA0;
  316. return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
  317. }
  318. /**
  319. * sca3000_write_ctrl_reg() - write to a lock protect ctrl register
  320. * @st: Driver specific device instance data.
  321. * @sel: selects which registers we wish to write to
  322. * @val: the value to be written
  323. *
  324. * Certain control registers are protected against overwriting by the lock
  325. * register and use a shared write address. This function allows writing of
  326. * these registers.
  327. * Lock must be held.
  328. */
  329. static int sca3000_write_ctrl_reg(struct sca3000_state *st,
  330. u8 sel,
  331. uint8_t val)
  332. {
  333. int ret;
  334. ret = sca3000_reg_lock_on(st);
  335. if (ret < 0)
  336. goto error_ret;
  337. if (ret) {
  338. ret = __sca3000_unlock_reg_lock(st);
  339. if (ret)
  340. goto error_ret;
  341. }
  342. /* Set the control select register */
  343. ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
  344. if (ret)
  345. goto error_ret;
  346. /* Write the actual value into the register */
  347. ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
  348. error_ret:
  349. return ret;
  350. }
  351. /**
  352. * sca3000_read_ctrl_reg() - read from lock protected control register.
  353. * @st: Driver specific device instance data.
  354. * @ctrl_reg: Which ctrl register do we want to read.
  355. *
  356. * Lock must be held.
  357. */
  358. static int sca3000_read_ctrl_reg(struct sca3000_state *st,
  359. u8 ctrl_reg)
  360. {
  361. int ret;
  362. ret = sca3000_reg_lock_on(st);
  363. if (ret < 0)
  364. goto error_ret;
  365. if (ret) {
  366. ret = __sca3000_unlock_reg_lock(st);
  367. if (ret)
  368. goto error_ret;
  369. }
  370. /* Set the control select register */
  371. ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
  372. if (ret)
  373. goto error_ret;
  374. ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
  375. if (ret)
  376. goto error_ret;
  377. return st->rx[0];
  378. error_ret:
  379. return ret;
  380. }
  381. /**
  382. * sca3000_print_rev() - sysfs interface to read the chip revision number
  383. * @indio_dev: Device instance specific generic IIO data.
  384. * Driver specific device instance data can be obtained via
  385. * iio_priv(indio_dev)
  386. */
  387. static int sca3000_print_rev(struct iio_dev *indio_dev)
  388. {
  389. int ret;
  390. struct sca3000_state *st = iio_priv(indio_dev);
  391. mutex_lock(&st->lock);
  392. ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
  393. if (ret < 0)
  394. goto error_ret;
  395. dev_info(&indio_dev->dev,
  396. "sca3000 revision major=%lu, minor=%lu\n",
  397. st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
  398. st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
  399. error_ret:
  400. mutex_unlock(&st->lock);
  401. return ret;
  402. }
  403. static ssize_t
  404. sca3000_show_available_3db_freqs(struct device *dev,
  405. struct device_attribute *attr,
  406. char *buf)
  407. {
  408. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  409. struct sca3000_state *st = iio_priv(indio_dev);
  410. int len;
  411. len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
  412. if (st->info->option_mode_1)
  413. len += sprintf(buf + len, " %d",
  414. st->info->option_mode_1_3db_freq);
  415. if (st->info->option_mode_2)
  416. len += sprintf(buf + len, " %d",
  417. st->info->option_mode_2_3db_freq);
  418. len += sprintf(buf + len, "\n");
  419. return len;
  420. }
  421. static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
  422. S_IRUGO, sca3000_show_available_3db_freqs,
  423. NULL, 0);
  424. static const struct iio_event_spec sca3000_event = {
  425. .type = IIO_EV_TYPE_MAG,
  426. .dir = IIO_EV_DIR_RISING,
  427. .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
  428. };
  429. /*
  430. * Note the hack in the number of bits to pretend we have 2 more than
  431. * we do in the fifo.
  432. */
  433. #define SCA3000_CHAN(index, mod) \
  434. { \
  435. .type = IIO_ACCEL, \
  436. .modified = 1, \
  437. .channel2 = mod, \
  438. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  439. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
  440. BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
  441. .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
  442. .address = index, \
  443. .scan_index = index, \
  444. .scan_type = { \
  445. .sign = 's', \
  446. .realbits = 13, \
  447. .storagebits = 16, \
  448. .shift = 3, \
  449. .endianness = IIO_BE, \
  450. }, \
  451. .event_spec = &sca3000_event, \
  452. .num_event_specs = 1, \
  453. }
  454. static const struct iio_event_spec sca3000_freefall_event_spec = {
  455. .type = IIO_EV_TYPE_MAG,
  456. .dir = IIO_EV_DIR_FALLING,
  457. .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
  458. BIT(IIO_EV_INFO_PERIOD),
  459. };
  460. static const struct iio_chan_spec sca3000_channels[] = {
  461. SCA3000_CHAN(0, IIO_MOD_X),
  462. SCA3000_CHAN(1, IIO_MOD_Y),
  463. SCA3000_CHAN(2, IIO_MOD_Z),
  464. {
  465. .type = IIO_ACCEL,
  466. .modified = 1,
  467. .channel2 = IIO_MOD_X_AND_Y_AND_Z,
  468. .scan_index = -1, /* Fake channel */
  469. .event_spec = &sca3000_freefall_event_spec,
  470. .num_event_specs = 1,
  471. },
  472. };
  473. static const struct iio_chan_spec sca3000_channels_with_temp[] = {
  474. SCA3000_CHAN(0, IIO_MOD_X),
  475. SCA3000_CHAN(1, IIO_MOD_Y),
  476. SCA3000_CHAN(2, IIO_MOD_Z),
  477. {
  478. .type = IIO_TEMP,
  479. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
  480. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
  481. BIT(IIO_CHAN_INFO_OFFSET),
  482. /* No buffer support */
  483. .scan_index = -1,
  484. .scan_type = {
  485. .sign = 'u',
  486. .realbits = 9,
  487. .storagebits = 16,
  488. .shift = 5,
  489. .endianness = IIO_BE,
  490. },
  491. },
  492. {
  493. .type = IIO_ACCEL,
  494. .modified = 1,
  495. .channel2 = IIO_MOD_X_AND_Y_AND_Z,
  496. .scan_index = -1, /* Fake channel */
  497. .event_spec = &sca3000_freefall_event_spec,
  498. .num_event_specs = 1,
  499. },
  500. };
  501. static u8 sca3000_addresses[3][3] = {
  502. [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
  503. SCA3000_MD_CTRL_OR_X},
  504. [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
  505. SCA3000_MD_CTRL_OR_Y},
  506. [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
  507. SCA3000_MD_CTRL_OR_Z},
  508. };
  509. /**
  510. * __sca3000_get_base_freq() - obtain mode specific base frequency
  511. * @st: Private driver specific device instance specific state.
  512. * @info: chip type specific information.
  513. * @base_freq: Base frequency for the current measurement mode.
  514. *
  515. * lock must be held
  516. */
  517. static inline int __sca3000_get_base_freq(struct sca3000_state *st,
  518. const struct sca3000_chip_info *info,
  519. int *base_freq)
  520. {
  521. int ret;
  522. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  523. if (ret)
  524. goto error_ret;
  525. switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
  526. case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
  527. *base_freq = info->measurement_mode_freq;
  528. break;
  529. case SCA3000_REG_MODE_MEAS_MODE_OP_1:
  530. *base_freq = info->option_mode_1_freq;
  531. break;
  532. case SCA3000_REG_MODE_MEAS_MODE_OP_2:
  533. *base_freq = info->option_mode_2_freq;
  534. break;
  535. default:
  536. ret = -EINVAL;
  537. }
  538. error_ret:
  539. return ret;
  540. }
  541. /**
  542. * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
  543. * @st: Private driver specific device instance specific state.
  544. * @val: The frequency read back.
  545. *
  546. * lock must be held
  547. **/
  548. static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
  549. {
  550. int ret;
  551. ret = __sca3000_get_base_freq(st, st->info, val);
  552. if (ret)
  553. return ret;
  554. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
  555. if (ret < 0)
  556. return ret;
  557. if (*val > 0) {
  558. ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
  559. switch (ret) {
  560. case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
  561. *val /= 2;
  562. break;
  563. case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
  564. *val /= 4;
  565. break;
  566. }
  567. }
  568. return 0;
  569. }
  570. /**
  571. * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
  572. * @st: Private driver specific device instance specific state.
  573. * @val: The frequency desired.
  574. *
  575. * lock must be held
  576. */
  577. static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
  578. {
  579. int ret, base_freq, ctrlval;
  580. ret = __sca3000_get_base_freq(st, st->info, &base_freq);
  581. if (ret)
  582. return ret;
  583. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
  584. if (ret < 0)
  585. return ret;
  586. ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
  587. if (val == base_freq / 2)
  588. ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
  589. if (val == base_freq / 4)
  590. ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
  591. else if (val != base_freq)
  592. return -EINVAL;
  593. return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
  594. ctrlval);
  595. }
  596. static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
  597. {
  598. int ret;
  599. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  600. if (ret)
  601. return ret;
  602. /* mask bottom 2 bits - only ones that are relevant */
  603. st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
  604. switch (st->rx[0]) {
  605. case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
  606. *val = st->info->measurement_mode_3db_freq;
  607. return IIO_VAL_INT;
  608. case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
  609. return -EBUSY;
  610. case SCA3000_REG_MODE_MEAS_MODE_OP_1:
  611. *val = st->info->option_mode_1_3db_freq;
  612. return IIO_VAL_INT;
  613. case SCA3000_REG_MODE_MEAS_MODE_OP_2:
  614. *val = st->info->option_mode_2_3db_freq;
  615. return IIO_VAL_INT;
  616. default:
  617. return -EINVAL;
  618. }
  619. }
  620. static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
  621. {
  622. int ret;
  623. int mode;
  624. if (val == st->info->measurement_mode_3db_freq)
  625. mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
  626. else if (st->info->option_mode_1 &&
  627. (val == st->info->option_mode_1_3db_freq))
  628. mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
  629. else if (st->info->option_mode_2 &&
  630. (val == st->info->option_mode_2_3db_freq))
  631. mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
  632. else
  633. return -EINVAL;
  634. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  635. if (ret)
  636. return ret;
  637. st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
  638. st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
  639. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
  640. }
  641. static int sca3000_read_raw(struct iio_dev *indio_dev,
  642. struct iio_chan_spec const *chan,
  643. int *val,
  644. int *val2,
  645. long mask)
  646. {
  647. struct sca3000_state *st = iio_priv(indio_dev);
  648. int ret;
  649. u8 address;
  650. switch (mask) {
  651. case IIO_CHAN_INFO_RAW:
  652. mutex_lock(&st->lock);
  653. if (chan->type == IIO_ACCEL) {
  654. if (st->mo_det_use_count) {
  655. mutex_unlock(&st->lock);
  656. return -EBUSY;
  657. }
  658. address = sca3000_addresses[chan->address][0];
  659. ret = sca3000_read_data_short(st, address, 2);
  660. if (ret < 0) {
  661. mutex_unlock(&st->lock);
  662. return ret;
  663. }
  664. *val = sign_extend32(be16_to_cpup((__be16 *)st->rx) >>
  665. chan->scan_type.shift,
  666. chan->scan_type.realbits - 1);
  667. } else {
  668. /* get the temperature when available */
  669. ret = sca3000_read_data_short(st,
  670. SCA3000_REG_TEMP_MSB_ADDR,
  671. 2);
  672. if (ret < 0) {
  673. mutex_unlock(&st->lock);
  674. return ret;
  675. }
  676. *val = (be16_to_cpup((__be16 *)st->rx) >>
  677. chan->scan_type.shift) &
  678. GENMASK(chan->scan_type.realbits - 1, 0);
  679. }
  680. mutex_unlock(&st->lock);
  681. return IIO_VAL_INT;
  682. case IIO_CHAN_INFO_SCALE:
  683. *val = 0;
  684. if (chan->type == IIO_ACCEL)
  685. *val2 = st->info->scale;
  686. else /* temperature */
  687. *val2 = 555556;
  688. return IIO_VAL_INT_PLUS_MICRO;
  689. case IIO_CHAN_INFO_OFFSET:
  690. *val = -214;
  691. *val2 = 600000;
  692. return IIO_VAL_INT_PLUS_MICRO;
  693. case IIO_CHAN_INFO_SAMP_FREQ:
  694. mutex_lock(&st->lock);
  695. ret = sca3000_read_raw_samp_freq(st, val);
  696. mutex_unlock(&st->lock);
  697. return ret ? ret : IIO_VAL_INT;
  698. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  699. mutex_lock(&st->lock);
  700. ret = sca3000_read_3db_freq(st, val);
  701. mutex_unlock(&st->lock);
  702. return ret;
  703. default:
  704. return -EINVAL;
  705. }
  706. }
  707. static int sca3000_write_raw(struct iio_dev *indio_dev,
  708. struct iio_chan_spec const *chan,
  709. int val, int val2, long mask)
  710. {
  711. struct sca3000_state *st = iio_priv(indio_dev);
  712. int ret;
  713. switch (mask) {
  714. case IIO_CHAN_INFO_SAMP_FREQ:
  715. if (val2)
  716. return -EINVAL;
  717. mutex_lock(&st->lock);
  718. ret = sca3000_write_raw_samp_freq(st, val);
  719. mutex_unlock(&st->lock);
  720. return ret;
  721. case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
  722. if (val2)
  723. return -EINVAL;
  724. mutex_lock(&st->lock);
  725. ret = sca3000_write_3db_freq(st, val);
  726. mutex_unlock(&st->lock);
  727. return ret;
  728. default:
  729. return -EINVAL;
  730. }
  731. return ret;
  732. }
  733. /**
  734. * sca3000_read_av_freq() - sysfs function to get available frequencies
  735. * @dev: Device structure for this device.
  736. * @attr: Description of the attribute.
  737. * @buf: Incoming string
  738. *
  739. * The later modes are only relevant to the ring buffer - and depend on current
  740. * mode. Note that data sheet gives rather wide tolerances for these so integer
  741. * division will give good enough answer and not all chips have them specified
  742. * at all.
  743. **/
  744. static ssize_t sca3000_read_av_freq(struct device *dev,
  745. struct device_attribute *attr,
  746. char *buf)
  747. {
  748. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  749. struct sca3000_state *st = iio_priv(indio_dev);
  750. int len = 0, ret, val;
  751. mutex_lock(&st->lock);
  752. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  753. val = st->rx[0];
  754. mutex_unlock(&st->lock);
  755. if (ret)
  756. goto error_ret;
  757. switch (val & SCA3000_REG_MODE_MODE_MASK) {
  758. case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
  759. len += sprintf(buf + len, "%d %d %d\n",
  760. st->info->measurement_mode_freq,
  761. st->info->measurement_mode_freq / 2,
  762. st->info->measurement_mode_freq / 4);
  763. break;
  764. case SCA3000_REG_MODE_MEAS_MODE_OP_1:
  765. len += sprintf(buf + len, "%d %d %d\n",
  766. st->info->option_mode_1_freq,
  767. st->info->option_mode_1_freq / 2,
  768. st->info->option_mode_1_freq / 4);
  769. break;
  770. case SCA3000_REG_MODE_MEAS_MODE_OP_2:
  771. len += sprintf(buf + len, "%d %d %d\n",
  772. st->info->option_mode_2_freq,
  773. st->info->option_mode_2_freq / 2,
  774. st->info->option_mode_2_freq / 4);
  775. break;
  776. }
  777. return len;
  778. error_ret:
  779. return ret;
  780. }
  781. /*
  782. * Should only really be registered if ring buffer support is compiled in.
  783. * Does no harm however and doing it right would add a fair bit of complexity
  784. */
  785. static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
  786. /*
  787. * sca3000_read_event_value() - query of a threshold or period
  788. */
  789. static int sca3000_read_event_value(struct iio_dev *indio_dev,
  790. const struct iio_chan_spec *chan,
  791. enum iio_event_type type,
  792. enum iio_event_direction dir,
  793. enum iio_event_info info,
  794. int *val, int *val2)
  795. {
  796. struct sca3000_state *st = iio_priv(indio_dev);
  797. long ret;
  798. int i;
  799. switch (info) {
  800. case IIO_EV_INFO_VALUE:
  801. mutex_lock(&st->lock);
  802. ret = sca3000_read_ctrl_reg(st,
  803. sca3000_addresses[chan->address][1]);
  804. mutex_unlock(&st->lock);
  805. if (ret < 0)
  806. return ret;
  807. *val = 0;
  808. if (chan->channel2 == IIO_MOD_Y)
  809. for_each_set_bit(i, &ret,
  810. ARRAY_SIZE(st->info->mot_det_mult_y))
  811. *val += st->info->mot_det_mult_y[i];
  812. else
  813. for_each_set_bit(i, &ret,
  814. ARRAY_SIZE(st->info->mot_det_mult_xz))
  815. *val += st->info->mot_det_mult_xz[i];
  816. return IIO_VAL_INT;
  817. case IIO_EV_INFO_PERIOD:
  818. *val = 0;
  819. *val2 = 226000;
  820. return IIO_VAL_INT_PLUS_MICRO;
  821. default:
  822. return -EINVAL;
  823. }
  824. }
  825. /**
  826. * sca3000_write_event_value() - control of threshold and period
  827. * @indio_dev: Device instance specific IIO information.
  828. * @chan: Description of the channel for which the event is being
  829. * configured.
  830. * @type: The type of event being configured, here magnitude rising
  831. * as everything else is read only.
  832. * @dir: Direction of the event (here rising)
  833. * @info: What information about the event are we configuring.
  834. * Here the threshold only.
  835. * @val: Integer part of the value being written..
  836. * @val2: Non integer part of the value being written. Here always 0.
  837. */
  838. static int sca3000_write_event_value(struct iio_dev *indio_dev,
  839. const struct iio_chan_spec *chan,
  840. enum iio_event_type type,
  841. enum iio_event_direction dir,
  842. enum iio_event_info info,
  843. int val, int val2)
  844. {
  845. struct sca3000_state *st = iio_priv(indio_dev);
  846. int ret;
  847. int i;
  848. u8 nonlinear = 0;
  849. if (chan->channel2 == IIO_MOD_Y) {
  850. i = ARRAY_SIZE(st->info->mot_det_mult_y);
  851. while (i > 0)
  852. if (val >= st->info->mot_det_mult_y[--i]) {
  853. nonlinear |= (1 << i);
  854. val -= st->info->mot_det_mult_y[i];
  855. }
  856. } else {
  857. i = ARRAY_SIZE(st->info->mot_det_mult_xz);
  858. while (i > 0)
  859. if (val >= st->info->mot_det_mult_xz[--i]) {
  860. nonlinear |= (1 << i);
  861. val -= st->info->mot_det_mult_xz[i];
  862. }
  863. }
  864. mutex_lock(&st->lock);
  865. ret = sca3000_write_ctrl_reg(st,
  866. sca3000_addresses[chan->address][1],
  867. nonlinear);
  868. mutex_unlock(&st->lock);
  869. return ret;
  870. }
  871. static struct attribute *sca3000_attributes[] = {
  872. &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
  873. &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
  874. NULL,
  875. };
  876. static const struct attribute_group sca3000_attribute_group = {
  877. .attrs = sca3000_attributes,
  878. };
  879. static int sca3000_read_data(struct sca3000_state *st,
  880. u8 reg_address_high,
  881. u8 *rx,
  882. int len)
  883. {
  884. int ret;
  885. struct spi_transfer xfer[2] = {
  886. {
  887. .len = 1,
  888. .tx_buf = st->tx,
  889. }, {
  890. .len = len,
  891. .rx_buf = rx,
  892. }
  893. };
  894. st->tx[0] = SCA3000_READ_REG(reg_address_high);
  895. ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
  896. if (ret) {
  897. dev_err(&st->us->dev, "problem reading register\n");
  898. return ret;
  899. }
  900. return 0;
  901. }
  902. /**
  903. * sca3000_ring_int_process() - ring specific interrupt handling.
  904. * @val: Value of the interrupt status register.
  905. * @indio_dev: Device instance specific IIO device structure.
  906. */
  907. static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
  908. {
  909. struct sca3000_state *st = iio_priv(indio_dev);
  910. int ret, i, num_available;
  911. mutex_lock(&st->lock);
  912. if (val & SCA3000_REG_INT_STATUS_HALF) {
  913. ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
  914. 1);
  915. if (ret)
  916. goto error_ret;
  917. num_available = st->rx[0];
  918. /*
  919. * num_available is the total number of samples available
  920. * i.e. number of time points * number of channels.
  921. */
  922. ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
  923. num_available * 2);
  924. if (ret)
  925. goto error_ret;
  926. for (i = 0; i < num_available / 3; i++) {
  927. /*
  928. * Dirty hack to cover for 11 bit in fifo, 13 bit
  929. * direct reading.
  930. *
  931. * In theory the bottom two bits are undefined.
  932. * In reality they appear to always be 0.
  933. */
  934. iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
  935. }
  936. }
  937. error_ret:
  938. mutex_unlock(&st->lock);
  939. }
  940. /**
  941. * sca3000_event_handler() - handling ring and non ring events
  942. * @irq: The irq being handled.
  943. * @private: struct iio_device pointer for the device.
  944. *
  945. * Ring related interrupt handler. Depending on event, push to
  946. * the ring buffer event chrdev or the event one.
  947. *
  948. * This function is complicated by the fact that the devices can signify ring
  949. * and non ring events via the same interrupt line and they can only
  950. * be distinguished via a read of the relevant status register.
  951. */
  952. static irqreturn_t sca3000_event_handler(int irq, void *private)
  953. {
  954. struct iio_dev *indio_dev = private;
  955. struct sca3000_state *st = iio_priv(indio_dev);
  956. int ret, val;
  957. s64 last_timestamp = iio_get_time_ns(indio_dev);
  958. /*
  959. * Could lead if badly timed to an extra read of status reg,
  960. * but ensures no interrupt is missed.
  961. */
  962. mutex_lock(&st->lock);
  963. ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
  964. val = st->rx[0];
  965. mutex_unlock(&st->lock);
  966. if (ret)
  967. goto done;
  968. sca3000_ring_int_process(val, indio_dev);
  969. if (val & SCA3000_INT_STATUS_FREE_FALL)
  970. iio_push_event(indio_dev,
  971. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  972. 0,
  973. IIO_MOD_X_AND_Y_AND_Z,
  974. IIO_EV_TYPE_MAG,
  975. IIO_EV_DIR_FALLING),
  976. last_timestamp);
  977. if (val & SCA3000_INT_STATUS_Y_TRIGGER)
  978. iio_push_event(indio_dev,
  979. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  980. 0,
  981. IIO_MOD_Y,
  982. IIO_EV_TYPE_MAG,
  983. IIO_EV_DIR_RISING),
  984. last_timestamp);
  985. if (val & SCA3000_INT_STATUS_X_TRIGGER)
  986. iio_push_event(indio_dev,
  987. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  988. 0,
  989. IIO_MOD_X,
  990. IIO_EV_TYPE_MAG,
  991. IIO_EV_DIR_RISING),
  992. last_timestamp);
  993. if (val & SCA3000_INT_STATUS_Z_TRIGGER)
  994. iio_push_event(indio_dev,
  995. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  996. 0,
  997. IIO_MOD_Z,
  998. IIO_EV_TYPE_MAG,
  999. IIO_EV_DIR_RISING),
  1000. last_timestamp);
  1001. done:
  1002. return IRQ_HANDLED;
  1003. }
  1004. /*
  1005. * sca3000_read_event_config() what events are enabled
  1006. */
  1007. static int sca3000_read_event_config(struct iio_dev *indio_dev,
  1008. const struct iio_chan_spec *chan,
  1009. enum iio_event_type type,
  1010. enum iio_event_direction dir)
  1011. {
  1012. struct sca3000_state *st = iio_priv(indio_dev);
  1013. int ret;
  1014. /* read current value of mode register */
  1015. mutex_lock(&st->lock);
  1016. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1017. if (ret)
  1018. goto error_ret;
  1019. switch (chan->channel2) {
  1020. case IIO_MOD_X_AND_Y_AND_Z:
  1021. ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
  1022. break;
  1023. case IIO_MOD_X:
  1024. case IIO_MOD_Y:
  1025. case IIO_MOD_Z:
  1026. /*
  1027. * Motion detection mode cannot run at the same time as
  1028. * acceleration data being read.
  1029. */
  1030. if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
  1031. != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
  1032. ret = 0;
  1033. } else {
  1034. ret = sca3000_read_ctrl_reg(st,
  1035. SCA3000_REG_CTRL_SEL_MD_CTRL);
  1036. if (ret < 0)
  1037. goto error_ret;
  1038. /* only supporting logical or's for now */
  1039. ret = !!(ret & sca3000_addresses[chan->address][2]);
  1040. }
  1041. break;
  1042. default:
  1043. ret = -EINVAL;
  1044. }
  1045. error_ret:
  1046. mutex_unlock(&st->lock);
  1047. return ret;
  1048. }
  1049. static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
  1050. {
  1051. struct sca3000_state *st = iio_priv(indio_dev);
  1052. int ret;
  1053. /* read current value of mode register */
  1054. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1055. if (ret)
  1056. return ret;
  1057. /* if off and should be on */
  1058. if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
  1059. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1060. st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
  1061. /* if on and should be off */
  1062. else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
  1063. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1064. st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
  1065. else
  1066. return 0;
  1067. }
  1068. static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
  1069. int state)
  1070. {
  1071. struct sca3000_state *st = iio_priv(indio_dev);
  1072. int ret, ctrlval;
  1073. /*
  1074. * First read the motion detector config to find out if
  1075. * this axis is on
  1076. */
  1077. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
  1078. if (ret < 0)
  1079. return ret;
  1080. ctrlval = ret;
  1081. /* if off and should be on */
  1082. if (state && !(ctrlval & sca3000_addresses[axis][2])) {
  1083. ret = sca3000_write_ctrl_reg(st,
  1084. SCA3000_REG_CTRL_SEL_MD_CTRL,
  1085. ctrlval |
  1086. sca3000_addresses[axis][2]);
  1087. if (ret)
  1088. return ret;
  1089. st->mo_det_use_count++;
  1090. } else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
  1091. ret = sca3000_write_ctrl_reg(st,
  1092. SCA3000_REG_CTRL_SEL_MD_CTRL,
  1093. ctrlval &
  1094. ~(sca3000_addresses[axis][2]));
  1095. if (ret)
  1096. return ret;
  1097. st->mo_det_use_count--;
  1098. }
  1099. /* read current value of mode register */
  1100. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1101. if (ret)
  1102. return ret;
  1103. /* if off and should be on */
  1104. if ((st->mo_det_use_count) &&
  1105. ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
  1106. != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
  1107. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1108. (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
  1109. | SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
  1110. /* if on and should be off */
  1111. else if (!(st->mo_det_use_count) &&
  1112. ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
  1113. == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
  1114. return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1115. st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
  1116. else
  1117. return 0;
  1118. }
  1119. /**
  1120. * sca3000_write_event_config() - simple on off control for motion detector
  1121. * @indio_dev: IIO device instance specific structure. Data specific to this
  1122. * particular driver may be accessed via iio_priv(indio_dev).
  1123. * @chan: Description of the channel whose event we are configuring.
  1124. * @type: The type of event.
  1125. * @dir: The direction of the event.
  1126. * @state: Desired state of event being configured.
  1127. *
  1128. * This is a per axis control, but enabling any will result in the
  1129. * motion detector unit being enabled.
  1130. * N.B. enabling motion detector stops normal data acquisition.
  1131. * There is a complexity in knowing which mode to return to when
  1132. * this mode is disabled. Currently normal mode is assumed.
  1133. **/
  1134. static int sca3000_write_event_config(struct iio_dev *indio_dev,
  1135. const struct iio_chan_spec *chan,
  1136. enum iio_event_type type,
  1137. enum iio_event_direction dir,
  1138. int state)
  1139. {
  1140. struct sca3000_state *st = iio_priv(indio_dev);
  1141. int ret;
  1142. mutex_lock(&st->lock);
  1143. switch (chan->channel2) {
  1144. case IIO_MOD_X_AND_Y_AND_Z:
  1145. ret = sca3000_freefall_set_state(indio_dev, state);
  1146. break;
  1147. case IIO_MOD_X:
  1148. case IIO_MOD_Y:
  1149. case IIO_MOD_Z:
  1150. ret = sca3000_motion_detect_set_state(indio_dev,
  1151. chan->address,
  1152. state);
  1153. break;
  1154. default:
  1155. ret = -EINVAL;
  1156. break;
  1157. }
  1158. mutex_unlock(&st->lock);
  1159. return ret;
  1160. }
  1161. static inline
  1162. int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
  1163. {
  1164. struct sca3000_state *st = iio_priv(indio_dev);
  1165. int ret;
  1166. mutex_lock(&st->lock);
  1167. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1168. if (ret)
  1169. goto error_ret;
  1170. if (state) {
  1171. dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
  1172. ret = sca3000_write_reg(st,
  1173. SCA3000_REG_MODE_ADDR,
  1174. (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
  1175. } else
  1176. ret = sca3000_write_reg(st,
  1177. SCA3000_REG_MODE_ADDR,
  1178. (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
  1179. error_ret:
  1180. mutex_unlock(&st->lock);
  1181. return ret;
  1182. }
  1183. /**
  1184. * sca3000_hw_ring_preenable() - hw ring buffer preenable function
  1185. * @indio_dev: structure representing the IIO device. Device instance
  1186. * specific state can be accessed via iio_priv(indio_dev).
  1187. *
  1188. * Very simple enable function as the chip will allows normal reads
  1189. * during ring buffer operation so as long as it is indeed running
  1190. * before we notify the core, the precise ordering does not matter.
  1191. */
  1192. static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
  1193. {
  1194. int ret;
  1195. struct sca3000_state *st = iio_priv(indio_dev);
  1196. mutex_lock(&st->lock);
  1197. /* Enable the 50% full interrupt */
  1198. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1199. if (ret)
  1200. goto error_unlock;
  1201. ret = sca3000_write_reg(st,
  1202. SCA3000_REG_INT_MASK_ADDR,
  1203. st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
  1204. if (ret)
  1205. goto error_unlock;
  1206. mutex_unlock(&st->lock);
  1207. return __sca3000_hw_ring_state_set(indio_dev, 1);
  1208. error_unlock:
  1209. mutex_unlock(&st->lock);
  1210. return ret;
  1211. }
  1212. static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
  1213. {
  1214. int ret;
  1215. struct sca3000_state *st = iio_priv(indio_dev);
  1216. ret = __sca3000_hw_ring_state_set(indio_dev, 0);
  1217. if (ret)
  1218. return ret;
  1219. /* Disable the 50% full interrupt */
  1220. mutex_lock(&st->lock);
  1221. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1222. if (ret)
  1223. goto unlock;
  1224. ret = sca3000_write_reg(st,
  1225. SCA3000_REG_INT_MASK_ADDR,
  1226. st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
  1227. unlock:
  1228. mutex_unlock(&st->lock);
  1229. return ret;
  1230. }
  1231. static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
  1232. .preenable = &sca3000_hw_ring_preenable,
  1233. .postdisable = &sca3000_hw_ring_postdisable,
  1234. };
  1235. /**
  1236. * sca3000_clean_setup() - get the device into a predictable state
  1237. * @st: Device instance specific private data structure
  1238. *
  1239. * Devices use flash memory to store many of the register values
  1240. * and hence can come up in somewhat unpredictable states.
  1241. * Hence reset everything on driver load.
  1242. */
  1243. static int sca3000_clean_setup(struct sca3000_state *st)
  1244. {
  1245. int ret;
  1246. mutex_lock(&st->lock);
  1247. /* Ensure all interrupts have been acknowledged */
  1248. ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
  1249. if (ret)
  1250. goto error_ret;
  1251. /* Turn off all motion detection channels */
  1252. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
  1253. if (ret < 0)
  1254. goto error_ret;
  1255. ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
  1256. ret & SCA3000_MD_CTRL_PROT_MASK);
  1257. if (ret)
  1258. goto error_ret;
  1259. /* Disable ring buffer */
  1260. ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
  1261. if (ret < 0)
  1262. goto error_ret;
  1263. ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
  1264. (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
  1265. | SCA3000_REG_OUT_CTRL_BUF_X_EN
  1266. | SCA3000_REG_OUT_CTRL_BUF_Y_EN
  1267. | SCA3000_REG_OUT_CTRL_BUF_Z_EN
  1268. | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
  1269. if (ret)
  1270. goto error_ret;
  1271. /* Enable interrupts, relevant to mode and set up as active low */
  1272. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1273. if (ret)
  1274. goto error_ret;
  1275. ret = sca3000_write_reg(st,
  1276. SCA3000_REG_INT_MASK_ADDR,
  1277. (ret & SCA3000_REG_INT_MASK_PROT_MASK)
  1278. | SCA3000_REG_INT_MASK_ACTIVE_LOW);
  1279. if (ret)
  1280. goto error_ret;
  1281. /*
  1282. * Select normal measurement mode, free fall off, ring off
  1283. * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
  1284. * as that occurs in one of the example on the datasheet
  1285. */
  1286. ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
  1287. if (ret)
  1288. goto error_ret;
  1289. ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
  1290. (st->rx[0] & SCA3000_MODE_PROT_MASK));
  1291. error_ret:
  1292. mutex_unlock(&st->lock);
  1293. return ret;
  1294. }
  1295. static const struct iio_info sca3000_info = {
  1296. .attrs = &sca3000_attribute_group,
  1297. .read_raw = &sca3000_read_raw,
  1298. .write_raw = &sca3000_write_raw,
  1299. .read_event_value = &sca3000_read_event_value,
  1300. .write_event_value = &sca3000_write_event_value,
  1301. .read_event_config = &sca3000_read_event_config,
  1302. .write_event_config = &sca3000_write_event_config,
  1303. };
  1304. static int sca3000_probe(struct spi_device *spi)
  1305. {
  1306. int ret;
  1307. struct sca3000_state *st;
  1308. struct iio_dev *indio_dev;
  1309. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  1310. if (!indio_dev)
  1311. return -ENOMEM;
  1312. st = iio_priv(indio_dev);
  1313. spi_set_drvdata(spi, indio_dev);
  1314. st->us = spi;
  1315. mutex_init(&st->lock);
  1316. st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
  1317. ->driver_data];
  1318. indio_dev->name = spi_get_device_id(spi)->name;
  1319. indio_dev->info = &sca3000_info;
  1320. if (st->info->temp_output) {
  1321. indio_dev->channels = sca3000_channels_with_temp;
  1322. indio_dev->num_channels =
  1323. ARRAY_SIZE(sca3000_channels_with_temp);
  1324. } else {
  1325. indio_dev->channels = sca3000_channels;
  1326. indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
  1327. }
  1328. indio_dev->modes = INDIO_DIRECT_MODE;
  1329. ret = devm_iio_kfifo_buffer_setup(&spi->dev, indio_dev,
  1330. &sca3000_ring_setup_ops);
  1331. if (ret)
  1332. return ret;
  1333. if (spi->irq) {
  1334. ret = request_threaded_irq(spi->irq,
  1335. NULL,
  1336. &sca3000_event_handler,
  1337. IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1338. "sca3000",
  1339. indio_dev);
  1340. if (ret)
  1341. return ret;
  1342. }
  1343. ret = sca3000_clean_setup(st);
  1344. if (ret)
  1345. goto error_free_irq;
  1346. ret = sca3000_print_rev(indio_dev);
  1347. if (ret)
  1348. goto error_free_irq;
  1349. return iio_device_register(indio_dev);
  1350. error_free_irq:
  1351. if (spi->irq)
  1352. free_irq(spi->irq, indio_dev);
  1353. return ret;
  1354. }
  1355. static int sca3000_stop_all_interrupts(struct sca3000_state *st)
  1356. {
  1357. int ret;
  1358. mutex_lock(&st->lock);
  1359. ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
  1360. if (ret)
  1361. goto error_ret;
  1362. ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
  1363. (st->rx[0] &
  1364. ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
  1365. SCA3000_REG_INT_MASK_RING_HALF |
  1366. SCA3000_REG_INT_MASK_ALL_INTS)));
  1367. error_ret:
  1368. mutex_unlock(&st->lock);
  1369. return ret;
  1370. }
  1371. static void sca3000_remove(struct spi_device *spi)
  1372. {
  1373. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  1374. struct sca3000_state *st = iio_priv(indio_dev);
  1375. iio_device_unregister(indio_dev);
  1376. /* Must ensure no interrupts can be generated after this! */
  1377. sca3000_stop_all_interrupts(st);
  1378. if (spi->irq)
  1379. free_irq(spi->irq, indio_dev);
  1380. }
  1381. static const struct spi_device_id sca3000_id[] = {
  1382. {"sca3000_d01", d01},
  1383. {"sca3000_e02", e02},
  1384. {"sca3000_e04", e04},
  1385. {"sca3000_e05", e05},
  1386. {}
  1387. };
  1388. MODULE_DEVICE_TABLE(spi, sca3000_id);
  1389. static struct spi_driver sca3000_driver = {
  1390. .driver = {
  1391. .name = "sca3000",
  1392. },
  1393. .probe = sca3000_probe,
  1394. .remove = sca3000_remove,
  1395. .id_table = sca3000_id,
  1396. };
  1397. module_spi_driver(sca3000_driver);
  1398. MODULE_AUTHOR("Jonathan Cameron <[email protected]>");
  1399. MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
  1400. MODULE_LICENSE("GPL v2");