adxl367_spi.c 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2021 Analog Devices, Inc.
  4. * Author: Cosmin Tanislav <[email protected]>
  5. */
  6. #include <linux/mod_devicetable.h>
  7. #include <linux/module.h>
  8. #include <linux/regmap.h>
  9. #include <linux/spi/spi.h>
  10. #include <linux/iio/iio.h>
  11. #include "adxl367.h"
  12. #define ADXL367_SPI_WRITE_COMMAND 0x0A
  13. #define ADXL367_SPI_READ_COMMAND 0x0B
  14. #define ADXL367_SPI_FIFO_COMMAND 0x0D
  15. struct adxl367_spi_state {
  16. struct spi_device *spi;
  17. struct spi_message reg_write_msg;
  18. struct spi_transfer reg_write_xfer[2];
  19. struct spi_message reg_read_msg;
  20. struct spi_transfer reg_read_xfer[2];
  21. struct spi_message fifo_msg;
  22. struct spi_transfer fifo_xfer[2];
  23. /*
  24. * DMA (thus cache coherency maintenance) may require the
  25. * transfer buffers live in their own cache lines.
  26. */
  27. u8 reg_write_tx_buf[1] __aligned(IIO_DMA_MINALIGN);
  28. u8 reg_read_tx_buf[2];
  29. u8 fifo_tx_buf[1];
  30. };
  31. static int adxl367_read_fifo(void *context, __be16 *fifo_buf,
  32. unsigned int fifo_entries)
  33. {
  34. struct adxl367_spi_state *st = context;
  35. st->fifo_xfer[1].rx_buf = fifo_buf;
  36. st->fifo_xfer[1].len = fifo_entries * sizeof(*fifo_buf);
  37. return spi_sync(st->spi, &st->fifo_msg);
  38. }
  39. static int adxl367_read(void *context, const void *reg_buf, size_t reg_size,
  40. void *val_buf, size_t val_size)
  41. {
  42. struct adxl367_spi_state *st = context;
  43. u8 reg = ((const u8 *)reg_buf)[0];
  44. st->reg_read_tx_buf[1] = reg;
  45. st->reg_read_xfer[1].rx_buf = val_buf;
  46. st->reg_read_xfer[1].len = val_size;
  47. return spi_sync(st->spi, &st->reg_read_msg);
  48. }
  49. static int adxl367_write(void *context, const void *val_buf, size_t val_size)
  50. {
  51. struct adxl367_spi_state *st = context;
  52. st->reg_write_xfer[1].tx_buf = val_buf;
  53. st->reg_write_xfer[1].len = val_size;
  54. return spi_sync(st->spi, &st->reg_write_msg);
  55. }
  56. static struct regmap_bus adxl367_spi_regmap_bus = {
  57. .read = adxl367_read,
  58. .write = adxl367_write,
  59. };
  60. static const struct regmap_config adxl367_spi_regmap_config = {
  61. .reg_bits = 8,
  62. .val_bits = 8,
  63. };
  64. static const struct adxl367_ops adxl367_spi_ops = {
  65. .read_fifo = adxl367_read_fifo,
  66. };
  67. static int adxl367_spi_probe(struct spi_device *spi)
  68. {
  69. struct adxl367_spi_state *st;
  70. struct regmap *regmap;
  71. st = devm_kzalloc(&spi->dev, sizeof(*st), GFP_KERNEL);
  72. if (!st)
  73. return -ENOMEM;
  74. st->spi = spi;
  75. /*
  76. * Xfer: [XFR1] [ XFR2 ]
  77. * Master: 0x0A ADDR DATA0 DATA1 ... DATAN
  78. * Slave: .... ..........................
  79. */
  80. st->reg_write_tx_buf[0] = ADXL367_SPI_WRITE_COMMAND;
  81. st->reg_write_xfer[0].tx_buf = st->reg_write_tx_buf;
  82. st->reg_write_xfer[0].len = sizeof(st->reg_write_tx_buf);
  83. spi_message_init_with_transfers(&st->reg_write_msg,
  84. st->reg_write_xfer, 2);
  85. /*
  86. * Xfer: [ XFR1 ] [ XFR2 ]
  87. * Master: 0x0B ADDR .....................
  88. * Slave: ......... DATA0 DATA1 ... DATAN
  89. */
  90. st->reg_read_tx_buf[0] = ADXL367_SPI_READ_COMMAND;
  91. st->reg_read_xfer[0].tx_buf = st->reg_read_tx_buf;
  92. st->reg_read_xfer[0].len = sizeof(st->reg_read_tx_buf);
  93. spi_message_init_with_transfers(&st->reg_read_msg,
  94. st->reg_read_xfer, 2);
  95. /*
  96. * Xfer: [XFR1] [ XFR2 ]
  97. * Master: 0x0D .....................
  98. * Slave: .... DATA0 DATA1 ... DATAN
  99. */
  100. st->fifo_tx_buf[0] = ADXL367_SPI_FIFO_COMMAND;
  101. st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
  102. st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
  103. spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, 2);
  104. regmap = devm_regmap_init(&spi->dev, &adxl367_spi_regmap_bus, st,
  105. &adxl367_spi_regmap_config);
  106. if (IS_ERR(regmap))
  107. return PTR_ERR(regmap);
  108. return adxl367_probe(&spi->dev, &adxl367_spi_ops, st, regmap, spi->irq);
  109. }
  110. static const struct spi_device_id adxl367_spi_id[] = {
  111. { "adxl367", 0 },
  112. { },
  113. };
  114. MODULE_DEVICE_TABLE(spi, adxl367_spi_id);
  115. static const struct of_device_id adxl367_of_match[] = {
  116. { .compatible = "adi,adxl367" },
  117. { },
  118. };
  119. MODULE_DEVICE_TABLE(of, adxl367_of_match);
  120. static struct spi_driver adxl367_spi_driver = {
  121. .driver = {
  122. .name = "adxl367_spi",
  123. .of_match_table = adxl367_of_match,
  124. },
  125. .probe = adxl367_spi_probe,
  126. .id_table = adxl367_spi_id,
  127. };
  128. module_spi_driver(adxl367_spi_driver);
  129. MODULE_IMPORT_NS(IIO_ADXL367);
  130. MODULE_AUTHOR("Cosmin Tanislav <[email protected]>");
  131. MODULE_DESCRIPTION("Analog Devices ADXL367 3-axis accelerometer SPI driver");
  132. MODULE_LICENSE("GPL");