i2c-piix4.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Copyright (c) 1998 - 2002 Frodo Looijaard <[email protected]> and
  4. Philip Edelbrock <[email protected]>
  5. */
  6. /*
  7. Supports:
  8. Intel PIIX4, 440MX
  9. Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
  10. ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
  11. AMD Hudson-2, ML, CZ
  12. Hygon CZ
  13. SMSC Victory66
  14. Note: we assume there can only be one device, with one or more
  15. SMBus interfaces.
  16. The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS).
  17. For devices supporting multiple ports the i2c_adapter should provide
  18. an i2c_algorithm to access them.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/moduleparam.h>
  22. #include <linux/pci.h>
  23. #include <linux/kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/stddef.h>
  26. #include <linux/ioport.h>
  27. #include <linux/i2c.h>
  28. #include <linux/slab.h>
  29. #include <linux/dmi.h>
  30. #include <linux/acpi.h>
  31. #include <linux/io.h>
  32. /* PIIX4 SMBus address offsets */
  33. #define SMBHSTSTS (0 + piix4_smba)
  34. #define SMBHSLVSTS (1 + piix4_smba)
  35. #define SMBHSTCNT (2 + piix4_smba)
  36. #define SMBHSTCMD (3 + piix4_smba)
  37. #define SMBHSTADD (4 + piix4_smba)
  38. #define SMBHSTDAT0 (5 + piix4_smba)
  39. #define SMBHSTDAT1 (6 + piix4_smba)
  40. #define SMBBLKDAT (7 + piix4_smba)
  41. #define SMBSLVCNT (8 + piix4_smba)
  42. #define SMBSHDWCMD (9 + piix4_smba)
  43. #define SMBSLVEVT (0xA + piix4_smba)
  44. #define SMBSLVDAT (0xC + piix4_smba)
  45. /* count for request_region */
  46. #define SMBIOSIZE 9
  47. /* PCI Address Constants */
  48. #define SMBBA 0x090
  49. #define SMBHSTCFG 0x0D2
  50. #define SMBSLVC 0x0D3
  51. #define SMBSHDW1 0x0D4
  52. #define SMBSHDW2 0x0D5
  53. #define SMBREV 0x0D6
  54. /* Other settings */
  55. #define MAX_TIMEOUT 500
  56. #define ENABLE_INT9 0
  57. /* PIIX4 constants */
  58. #define PIIX4_QUICK 0x00
  59. #define PIIX4_BYTE 0x04
  60. #define PIIX4_BYTE_DATA 0x08
  61. #define PIIX4_WORD_DATA 0x0C
  62. #define PIIX4_BLOCK_DATA 0x14
  63. /* Multi-port constants */
  64. #define PIIX4_MAX_ADAPTERS 4
  65. #define HUDSON2_MAIN_PORTS 2 /* HUDSON2, KERNCZ reserves ports 3, 4 */
  66. /* SB800 constants */
  67. #define SB800_PIIX4_SMB_IDX 0xcd6
  68. #define SB800_PIIX4_SMB_MAP_SIZE 2
  69. #define KERNCZ_IMC_IDX 0x3e
  70. #define KERNCZ_IMC_DATA 0x3f
  71. /*
  72. * SB800 port is selected by bits 2:1 of the smb_en register (0x2c)
  73. * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f.
  74. * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f.
  75. */
  76. #define SB800_PIIX4_PORT_IDX 0x2c
  77. #define SB800_PIIX4_PORT_IDX_ALT 0x2e
  78. #define SB800_PIIX4_PORT_IDX_SEL 0x2f
  79. #define SB800_PIIX4_PORT_IDX_MASK 0x06
  80. #define SB800_PIIX4_PORT_IDX_SHIFT 1
  81. /* On kerncz and Hudson2, SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */
  82. #define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
  83. #define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
  84. #define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
  85. #define SB800_PIIX4_FCH_PM_ADDR 0xFED80300
  86. #define SB800_PIIX4_FCH_PM_SIZE 8
  87. /* insmod parameters */
  88. /* If force is set to anything different from 0, we forcibly enable the
  89. PIIX4. DANGEROUS! */
  90. static int force;
  91. module_param (force, int, 0);
  92. MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  93. /* If force_addr is set to anything different from 0, we forcibly enable
  94. the PIIX4 at the given address. VERY DANGEROUS! */
  95. static int force_addr;
  96. module_param_hw(force_addr, int, ioport, 0);
  97. MODULE_PARM_DESC(force_addr,
  98. "Forcibly enable the PIIX4 at the given address. "
  99. "EXTREMELY DANGEROUS!");
  100. static int srvrworks_csb5_delay;
  101. static struct pci_driver piix4_driver;
  102. static const struct dmi_system_id piix4_dmi_blacklist[] = {
  103. {
  104. .ident = "Sapphire AM2RD790",
  105. .matches = {
  106. DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
  107. DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
  108. },
  109. },
  110. {
  111. .ident = "DFI Lanparty UT 790FX",
  112. .matches = {
  113. DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
  114. DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
  115. },
  116. },
  117. { }
  118. };
  119. /* The IBM entry is in a separate table because we only check it
  120. on Intel-based systems */
  121. static const struct dmi_system_id piix4_dmi_ibm[] = {
  122. {
  123. .ident = "IBM",
  124. .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
  125. },
  126. { },
  127. };
  128. /*
  129. * SB800 globals
  130. */
  131. static u8 piix4_port_sel_sb800;
  132. static u8 piix4_port_mask_sb800;
  133. static u8 piix4_port_shift_sb800;
  134. static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
  135. " port 0", " port 2", " port 3", " port 4"
  136. };
  137. static const char *piix4_aux_port_name_sb800 = " port 1";
  138. struct sb800_mmio_cfg {
  139. void __iomem *addr;
  140. bool use_mmio;
  141. };
  142. struct i2c_piix4_adapdata {
  143. unsigned short smba;
  144. /* SB800 */
  145. bool sb800_main;
  146. bool notify_imc;
  147. u8 port; /* Port number, shifted */
  148. struct sb800_mmio_cfg mmio_cfg;
  149. };
  150. static int piix4_sb800_region_request(struct device *dev,
  151. struct sb800_mmio_cfg *mmio_cfg)
  152. {
  153. if (mmio_cfg->use_mmio) {
  154. void __iomem *addr;
  155. if (!request_mem_region_muxed(SB800_PIIX4_FCH_PM_ADDR,
  156. SB800_PIIX4_FCH_PM_SIZE,
  157. "sb800_piix4_smb")) {
  158. dev_err(dev,
  159. "SMBus base address memory region 0x%x already in use.\n",
  160. SB800_PIIX4_FCH_PM_ADDR);
  161. return -EBUSY;
  162. }
  163. addr = ioremap(SB800_PIIX4_FCH_PM_ADDR,
  164. SB800_PIIX4_FCH_PM_SIZE);
  165. if (!addr) {
  166. release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
  167. SB800_PIIX4_FCH_PM_SIZE);
  168. dev_err(dev, "SMBus base address mapping failed.\n");
  169. return -ENOMEM;
  170. }
  171. mmio_cfg->addr = addr;
  172. return 0;
  173. }
  174. if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE,
  175. "sb800_piix4_smb")) {
  176. dev_err(dev,
  177. "SMBus base address index region 0x%x already in use.\n",
  178. SB800_PIIX4_SMB_IDX);
  179. return -EBUSY;
  180. }
  181. return 0;
  182. }
  183. static void piix4_sb800_region_release(struct device *dev,
  184. struct sb800_mmio_cfg *mmio_cfg)
  185. {
  186. if (mmio_cfg->use_mmio) {
  187. iounmap(mmio_cfg->addr);
  188. release_mem_region(SB800_PIIX4_FCH_PM_ADDR,
  189. SB800_PIIX4_FCH_PM_SIZE);
  190. return;
  191. }
  192. release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE);
  193. }
  194. static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev)
  195. {
  196. /*
  197. * cd6h/cd7h port I/O accesses can be disabled on AMD processors
  198. * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on
  199. * the same processors and is the recommended access method.
  200. */
  201. return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
  202. PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  203. PIIX4_dev->revision >= 0x51);
  204. }
  205. static int piix4_setup(struct pci_dev *PIIX4_dev,
  206. const struct pci_device_id *id)
  207. {
  208. unsigned char temp;
  209. unsigned short piix4_smba;
  210. if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
  211. (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
  212. srvrworks_csb5_delay = 1;
  213. /* On some motherboards, it was reported that accessing the SMBus
  214. caused severe hardware problems */
  215. if (dmi_check_system(piix4_dmi_blacklist)) {
  216. dev_err(&PIIX4_dev->dev,
  217. "Accessing the SMBus on this system is unsafe!\n");
  218. return -EPERM;
  219. }
  220. /* Don't access SMBus on IBM systems which get corrupted eeproms */
  221. if (dmi_check_system(piix4_dmi_ibm) &&
  222. PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
  223. dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
  224. "may corrupt your serial eeprom! Refusing to load "
  225. "module!\n");
  226. return -EPERM;
  227. }
  228. /* Determine the address of the SMBus areas */
  229. if (force_addr) {
  230. piix4_smba = force_addr & 0xfff0;
  231. force = 0;
  232. } else {
  233. pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
  234. piix4_smba &= 0xfff0;
  235. if(piix4_smba == 0) {
  236. dev_err(&PIIX4_dev->dev, "SMBus base address "
  237. "uninitialized - upgrade BIOS or use "
  238. "force_addr=0xaddr\n");
  239. return -ENODEV;
  240. }
  241. }
  242. if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
  243. return -ENODEV;
  244. if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
  245. dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
  246. piix4_smba);
  247. return -EBUSY;
  248. }
  249. pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
  250. /* If force_addr is set, we program the new address here. Just to make
  251. sure, we disable the PIIX4 first. */
  252. if (force_addr) {
  253. pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
  254. pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
  255. pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
  256. dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
  257. "new address %04x!\n", piix4_smba);
  258. } else if ((temp & 1) == 0) {
  259. if (force) {
  260. /* This should never need to be done, but has been
  261. * noted that many Dell machines have the SMBus
  262. * interface on the PIIX4 disabled!? NOTE: This assumes
  263. * I/O space and other allocations WERE done by the
  264. * Bios! Don't complain if your hardware does weird
  265. * things after enabling this. :') Check for Bios
  266. * updates before resorting to this.
  267. */
  268. pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
  269. temp | 1);
  270. dev_notice(&PIIX4_dev->dev,
  271. "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
  272. } else {
  273. dev_err(&PIIX4_dev->dev,
  274. "SMBus Host Controller not enabled!\n");
  275. release_region(piix4_smba, SMBIOSIZE);
  276. return -ENODEV;
  277. }
  278. }
  279. if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
  280. dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
  281. else if ((temp & 0x0E) == 0)
  282. dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
  283. else
  284. dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
  285. "(or code out of date)!\n");
  286. pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
  287. dev_info(&PIIX4_dev->dev,
  288. "SMBus Host Controller at 0x%x, revision %d\n",
  289. piix4_smba, temp);
  290. return piix4_smba;
  291. }
  292. static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev,
  293. u8 smb_en,
  294. u8 aux,
  295. u8 *smb_en_status,
  296. unsigned short *piix4_smba)
  297. {
  298. struct sb800_mmio_cfg mmio_cfg;
  299. u8 smba_en_lo;
  300. u8 smba_en_hi;
  301. int retval;
  302. mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
  303. retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
  304. if (retval)
  305. return retval;
  306. if (mmio_cfg.use_mmio) {
  307. smba_en_lo = ioread8(mmio_cfg.addr);
  308. smba_en_hi = ioread8(mmio_cfg.addr + 1);
  309. } else {
  310. outb_p(smb_en, SB800_PIIX4_SMB_IDX);
  311. smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
  312. outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
  313. smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
  314. }
  315. piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
  316. if (!smb_en) {
  317. *smb_en_status = smba_en_lo & 0x10;
  318. *piix4_smba = smba_en_hi << 8;
  319. if (aux)
  320. *piix4_smba |= 0x20;
  321. } else {
  322. *smb_en_status = smba_en_lo & 0x01;
  323. *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
  324. }
  325. if (!*smb_en_status) {
  326. dev_err(&PIIX4_dev->dev,
  327. "SMBus Host Controller not enabled!\n");
  328. return -ENODEV;
  329. }
  330. return 0;
  331. }
  332. static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
  333. const struct pci_device_id *id, u8 aux)
  334. {
  335. unsigned short piix4_smba;
  336. u8 smb_en, smb_en_status, port_sel;
  337. u8 i2ccfg, i2ccfg_offset = 0x10;
  338. struct sb800_mmio_cfg mmio_cfg;
  339. int retval;
  340. /* SB800 and later SMBus does not support forcing address */
  341. if (force || force_addr) {
  342. dev_err(&PIIX4_dev->dev, "SMBus does not support "
  343. "forcing address!\n");
  344. return -EINVAL;
  345. }
  346. /* Determine the address of the SMBus areas */
  347. if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
  348. PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  349. PIIX4_dev->revision >= 0x41) ||
  350. (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
  351. PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
  352. PIIX4_dev->revision >= 0x49) ||
  353. (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
  354. PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
  355. smb_en = 0x00;
  356. else
  357. smb_en = (aux) ? 0x28 : 0x2c;
  358. retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, aux, &smb_en_status,
  359. &piix4_smba);
  360. if (retval)
  361. return retval;
  362. if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
  363. return -ENODEV;
  364. if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
  365. dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
  366. piix4_smba);
  367. return -EBUSY;
  368. }
  369. /* Aux SMBus does not support IRQ information */
  370. if (aux) {
  371. dev_info(&PIIX4_dev->dev,
  372. "Auxiliary SMBus Host Controller at 0x%x\n",
  373. piix4_smba);
  374. return piix4_smba;
  375. }
  376. /* Request the SMBus I2C bus config region */
  377. if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
  378. dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
  379. "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
  380. release_region(piix4_smba, SMBIOSIZE);
  381. return -EBUSY;
  382. }
  383. i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
  384. release_region(piix4_smba + i2ccfg_offset, 1);
  385. if (i2ccfg & 1)
  386. dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
  387. else
  388. dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
  389. dev_info(&PIIX4_dev->dev,
  390. "SMBus Host Controller at 0x%x, revision %d\n",
  391. piix4_smba, i2ccfg >> 4);
  392. /* Find which register is used for port selection */
  393. if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
  394. PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
  395. if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
  396. (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  397. PIIX4_dev->revision >= 0x1F)) {
  398. piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
  399. piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
  400. piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
  401. } else {
  402. piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
  403. piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
  404. piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
  405. }
  406. } else {
  407. mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev);
  408. retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg);
  409. if (retval) {
  410. release_region(piix4_smba, SMBIOSIZE);
  411. return retval;
  412. }
  413. outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
  414. port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
  415. piix4_port_sel_sb800 = (port_sel & 0x01) ?
  416. SB800_PIIX4_PORT_IDX_ALT :
  417. SB800_PIIX4_PORT_IDX;
  418. piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
  419. piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
  420. piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg);
  421. }
  422. dev_info(&PIIX4_dev->dev,
  423. "Using register 0x%02x for SMBus port selection\n",
  424. (unsigned int)piix4_port_sel_sb800);
  425. return piix4_smba;
  426. }
  427. static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
  428. const struct pci_device_id *id,
  429. unsigned short base_reg_addr)
  430. {
  431. /* Set up auxiliary SMBus controllers found on some
  432. * AMD chipsets e.g. SP5100 (SB700 derivative) */
  433. unsigned short piix4_smba;
  434. /* Read address of auxiliary SMBus controller */
  435. pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
  436. if ((piix4_smba & 1) == 0) {
  437. dev_dbg(&PIIX4_dev->dev,
  438. "Auxiliary SMBus controller not enabled\n");
  439. return -ENODEV;
  440. }
  441. piix4_smba &= 0xfff0;
  442. if (piix4_smba == 0) {
  443. dev_dbg(&PIIX4_dev->dev,
  444. "Auxiliary SMBus base address uninitialized\n");
  445. return -ENODEV;
  446. }
  447. if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
  448. return -ENODEV;
  449. if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
  450. dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
  451. "already in use!\n", piix4_smba);
  452. return -EBUSY;
  453. }
  454. dev_info(&PIIX4_dev->dev,
  455. "Auxiliary SMBus Host Controller at 0x%x\n",
  456. piix4_smba);
  457. return piix4_smba;
  458. }
  459. static int piix4_transaction(struct i2c_adapter *piix4_adapter)
  460. {
  461. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
  462. unsigned short piix4_smba = adapdata->smba;
  463. int temp;
  464. int result = 0;
  465. int timeout = 0;
  466. dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
  467. "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
  468. inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
  469. inb_p(SMBHSTDAT1));
  470. /* Make sure the SMBus host is ready to start transmitting */
  471. if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
  472. dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
  473. "Resetting...\n", temp);
  474. outb_p(temp, SMBHSTSTS);
  475. if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
  476. dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
  477. return -EBUSY;
  478. } else {
  479. dev_dbg(&piix4_adapter->dev, "Successful!\n");
  480. }
  481. }
  482. /* start the transaction by setting bit 6 */
  483. outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
  484. /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
  485. if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
  486. usleep_range(2000, 2100);
  487. else
  488. usleep_range(250, 500);
  489. while ((++timeout < MAX_TIMEOUT) &&
  490. ((temp = inb_p(SMBHSTSTS)) & 0x01))
  491. usleep_range(250, 500);
  492. /* If the SMBus is still busy, we give up */
  493. if (timeout == MAX_TIMEOUT) {
  494. dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
  495. result = -ETIMEDOUT;
  496. }
  497. if (temp & 0x10) {
  498. result = -EIO;
  499. dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
  500. }
  501. if (temp & 0x08) {
  502. result = -EIO;
  503. dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
  504. "locked until next hard reset. (sorry!)\n");
  505. /* Clock stops and slave is stuck in mid-transmission */
  506. }
  507. if (temp & 0x04) {
  508. result = -ENXIO;
  509. dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
  510. }
  511. if (inb_p(SMBHSTSTS) != 0x00)
  512. outb_p(inb(SMBHSTSTS), SMBHSTSTS);
  513. if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
  514. dev_err(&piix4_adapter->dev, "Failed reset at end of "
  515. "transaction (%02x)\n", temp);
  516. }
  517. dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
  518. "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
  519. inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
  520. inb_p(SMBHSTDAT1));
  521. return result;
  522. }
  523. /* Return negative errno on error. */
  524. static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
  525. unsigned short flags, char read_write,
  526. u8 command, int size, union i2c_smbus_data * data)
  527. {
  528. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
  529. unsigned short piix4_smba = adapdata->smba;
  530. int i, len;
  531. int status;
  532. switch (size) {
  533. case I2C_SMBUS_QUICK:
  534. outb_p((addr << 1) | read_write,
  535. SMBHSTADD);
  536. size = PIIX4_QUICK;
  537. break;
  538. case I2C_SMBUS_BYTE:
  539. outb_p((addr << 1) | read_write,
  540. SMBHSTADD);
  541. if (read_write == I2C_SMBUS_WRITE)
  542. outb_p(command, SMBHSTCMD);
  543. size = PIIX4_BYTE;
  544. break;
  545. case I2C_SMBUS_BYTE_DATA:
  546. outb_p((addr << 1) | read_write,
  547. SMBHSTADD);
  548. outb_p(command, SMBHSTCMD);
  549. if (read_write == I2C_SMBUS_WRITE)
  550. outb_p(data->byte, SMBHSTDAT0);
  551. size = PIIX4_BYTE_DATA;
  552. break;
  553. case I2C_SMBUS_WORD_DATA:
  554. outb_p((addr << 1) | read_write,
  555. SMBHSTADD);
  556. outb_p(command, SMBHSTCMD);
  557. if (read_write == I2C_SMBUS_WRITE) {
  558. outb_p(data->word & 0xff, SMBHSTDAT0);
  559. outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
  560. }
  561. size = PIIX4_WORD_DATA;
  562. break;
  563. case I2C_SMBUS_BLOCK_DATA:
  564. outb_p((addr << 1) | read_write,
  565. SMBHSTADD);
  566. outb_p(command, SMBHSTCMD);
  567. if (read_write == I2C_SMBUS_WRITE) {
  568. len = data->block[0];
  569. if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
  570. return -EINVAL;
  571. outb_p(len, SMBHSTDAT0);
  572. inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
  573. for (i = 1; i <= len; i++)
  574. outb_p(data->block[i], SMBBLKDAT);
  575. }
  576. size = PIIX4_BLOCK_DATA;
  577. break;
  578. default:
  579. dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
  580. return -EOPNOTSUPP;
  581. }
  582. outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
  583. status = piix4_transaction(adap);
  584. if (status)
  585. return status;
  586. if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
  587. return 0;
  588. switch (size) {
  589. case PIIX4_BYTE:
  590. case PIIX4_BYTE_DATA:
  591. data->byte = inb_p(SMBHSTDAT0);
  592. break;
  593. case PIIX4_WORD_DATA:
  594. data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
  595. break;
  596. case PIIX4_BLOCK_DATA:
  597. data->block[0] = inb_p(SMBHSTDAT0);
  598. if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
  599. return -EPROTO;
  600. inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
  601. for (i = 1; i <= data->block[0]; i++)
  602. data->block[i] = inb_p(SMBBLKDAT);
  603. break;
  604. }
  605. return 0;
  606. }
  607. static uint8_t piix4_imc_read(uint8_t idx)
  608. {
  609. outb_p(idx, KERNCZ_IMC_IDX);
  610. return inb_p(KERNCZ_IMC_DATA);
  611. }
  612. static void piix4_imc_write(uint8_t idx, uint8_t value)
  613. {
  614. outb_p(idx, KERNCZ_IMC_IDX);
  615. outb_p(value, KERNCZ_IMC_DATA);
  616. }
  617. static int piix4_imc_sleep(void)
  618. {
  619. int timeout = MAX_TIMEOUT;
  620. if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
  621. return -EBUSY;
  622. /* clear response register */
  623. piix4_imc_write(0x82, 0x00);
  624. /* request ownership flag */
  625. piix4_imc_write(0x83, 0xB4);
  626. /* kick off IMC Mailbox command 96 */
  627. piix4_imc_write(0x80, 0x96);
  628. while (timeout--) {
  629. if (piix4_imc_read(0x82) == 0xfa) {
  630. release_region(KERNCZ_IMC_IDX, 2);
  631. return 0;
  632. }
  633. usleep_range(1000, 2000);
  634. }
  635. release_region(KERNCZ_IMC_IDX, 2);
  636. return -ETIMEDOUT;
  637. }
  638. static void piix4_imc_wakeup(void)
  639. {
  640. int timeout = MAX_TIMEOUT;
  641. if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
  642. return;
  643. /* clear response register */
  644. piix4_imc_write(0x82, 0x00);
  645. /* release ownership flag */
  646. piix4_imc_write(0x83, 0xB5);
  647. /* kick off IMC Mailbox command 96 */
  648. piix4_imc_write(0x80, 0x96);
  649. while (timeout--) {
  650. if (piix4_imc_read(0x82) == 0xfa)
  651. break;
  652. usleep_range(1000, 2000);
  653. }
  654. release_region(KERNCZ_IMC_IDX, 2);
  655. }
  656. static int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg)
  657. {
  658. u8 smba_en_lo, val;
  659. if (mmio_cfg->use_mmio) {
  660. smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800);
  661. val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
  662. if (smba_en_lo != val)
  663. iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800);
  664. return (smba_en_lo & piix4_port_mask_sb800);
  665. }
  666. outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
  667. smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
  668. val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
  669. if (smba_en_lo != val)
  670. outb_p(val, SB800_PIIX4_SMB_IDX + 1);
  671. return (smba_en_lo & piix4_port_mask_sb800);
  672. }
  673. /*
  674. * Handles access to multiple SMBus ports on the SB800.
  675. * The port is selected by bits 2:1 of the smb_en register (0x2c).
  676. * Returns negative errno on error.
  677. *
  678. * Note: The selected port must be returned to the initial selection to avoid
  679. * problems on certain systems.
  680. */
  681. static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
  682. unsigned short flags, char read_write,
  683. u8 command, int size, union i2c_smbus_data *data)
  684. {
  685. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
  686. unsigned short piix4_smba = adapdata->smba;
  687. int retries = MAX_TIMEOUT;
  688. int smbslvcnt;
  689. u8 prev_port;
  690. int retval;
  691. retval = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg);
  692. if (retval)
  693. return retval;
  694. /* Request the SMBUS semaphore, avoid conflicts with the IMC */
  695. smbslvcnt = inb_p(SMBSLVCNT);
  696. do {
  697. outb_p(smbslvcnt | 0x10, SMBSLVCNT);
  698. /* Check the semaphore status */
  699. smbslvcnt = inb_p(SMBSLVCNT);
  700. if (smbslvcnt & 0x10)
  701. break;
  702. usleep_range(1000, 2000);
  703. } while (--retries);
  704. /* SMBus is still owned by the IMC, we give up */
  705. if (!retries) {
  706. retval = -EBUSY;
  707. goto release;
  708. }
  709. /*
  710. * Notify the IMC (Integrated Micro Controller) if required.
  711. * Among other responsibilities, the IMC is in charge of monitoring
  712. * the System fans and temperature sensors, and act accordingly.
  713. * All this is done through SMBus and can/will collide
  714. * with our transactions if they are long (BLOCK_DATA).
  715. * Therefore we need to request the ownership flag during those
  716. * transactions.
  717. */
  718. if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
  719. int ret;
  720. ret = piix4_imc_sleep();
  721. switch (ret) {
  722. case -EBUSY:
  723. dev_warn(&adap->dev,
  724. "IMC base address index region 0x%x already in use.\n",
  725. KERNCZ_IMC_IDX);
  726. break;
  727. case -ETIMEDOUT:
  728. dev_warn(&adap->dev,
  729. "Failed to communicate with the IMC.\n");
  730. break;
  731. default:
  732. break;
  733. }
  734. /* If IMC communication fails do not retry */
  735. if (ret) {
  736. dev_warn(&adap->dev,
  737. "Continuing without IMC notification.\n");
  738. adapdata->notify_imc = false;
  739. }
  740. }
  741. prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg);
  742. retval = piix4_access(adap, addr, flags, read_write,
  743. command, size, data);
  744. piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg);
  745. /* Release the semaphore */
  746. outb_p(smbslvcnt | 0x20, SMBSLVCNT);
  747. if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
  748. piix4_imc_wakeup();
  749. release:
  750. piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg);
  751. return retval;
  752. }
  753. static u32 piix4_func(struct i2c_adapter *adapter)
  754. {
  755. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  756. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  757. I2C_FUNC_SMBUS_BLOCK_DATA;
  758. }
  759. static const struct i2c_algorithm smbus_algorithm = {
  760. .smbus_xfer = piix4_access,
  761. .functionality = piix4_func,
  762. };
  763. static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
  764. .smbus_xfer = piix4_access_sb800,
  765. .functionality = piix4_func,
  766. };
  767. static const struct pci_device_id piix4_ids[] = {
  768. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
  769. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
  770. { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
  771. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
  772. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
  773. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
  774. { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
  775. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
  776. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
  777. { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
  778. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  779. PCI_DEVICE_ID_SERVERWORKS_OSB4) },
  780. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  781. PCI_DEVICE_ID_SERVERWORKS_CSB5) },
  782. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  783. PCI_DEVICE_ID_SERVERWORKS_CSB6) },
  784. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  785. PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
  786. { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
  787. PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
  788. { 0, }
  789. };
  790. MODULE_DEVICE_TABLE (pci, piix4_ids);
  791. static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
  792. static struct i2c_adapter *piix4_aux_adapter;
  793. static int piix4_adapter_count;
  794. static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
  795. bool sb800_main, u8 port, bool notify_imc,
  796. u8 hw_port_nr, const char *name,
  797. struct i2c_adapter **padap)
  798. {
  799. struct i2c_adapter *adap;
  800. struct i2c_piix4_adapdata *adapdata;
  801. int retval;
  802. adap = kzalloc(sizeof(*adap), GFP_KERNEL);
  803. if (adap == NULL) {
  804. release_region(smba, SMBIOSIZE);
  805. return -ENOMEM;
  806. }
  807. adap->owner = THIS_MODULE;
  808. adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  809. adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
  810. : &smbus_algorithm;
  811. adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
  812. if (adapdata == NULL) {
  813. kfree(adap);
  814. release_region(smba, SMBIOSIZE);
  815. return -ENOMEM;
  816. }
  817. adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev);
  818. adapdata->smba = smba;
  819. adapdata->sb800_main = sb800_main;
  820. adapdata->port = port << piix4_port_shift_sb800;
  821. adapdata->notify_imc = notify_imc;
  822. /* set up the sysfs linkage to our parent device */
  823. adap->dev.parent = &dev->dev;
  824. if (has_acpi_companion(&dev->dev)) {
  825. acpi_preset_companion(&adap->dev,
  826. ACPI_COMPANION(&dev->dev),
  827. hw_port_nr);
  828. }
  829. snprintf(adap->name, sizeof(adap->name),
  830. "SMBus PIIX4 adapter%s at %04x", name, smba);
  831. i2c_set_adapdata(adap, adapdata);
  832. retval = i2c_add_adapter(adap);
  833. if (retval) {
  834. kfree(adapdata);
  835. kfree(adap);
  836. release_region(smba, SMBIOSIZE);
  837. return retval;
  838. }
  839. *padap = adap;
  840. return 0;
  841. }
  842. static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
  843. bool notify_imc)
  844. {
  845. struct i2c_piix4_adapdata *adapdata;
  846. int port;
  847. int retval;
  848. if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
  849. (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
  850. dev->revision >= 0x1F)) {
  851. piix4_adapter_count = HUDSON2_MAIN_PORTS;
  852. } else {
  853. piix4_adapter_count = PIIX4_MAX_ADAPTERS;
  854. }
  855. for (port = 0; port < piix4_adapter_count; port++) {
  856. u8 hw_port_nr = port == 0 ? 0 : port + 1;
  857. retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
  858. hw_port_nr,
  859. piix4_main_port_names_sb800[port],
  860. &piix4_main_adapters[port]);
  861. if (retval < 0)
  862. goto error;
  863. }
  864. return retval;
  865. error:
  866. dev_err(&dev->dev,
  867. "Error setting up SB800 adapters. Unregistering!\n");
  868. while (--port >= 0) {
  869. adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
  870. if (adapdata->smba) {
  871. i2c_del_adapter(piix4_main_adapters[port]);
  872. kfree(adapdata);
  873. kfree(piix4_main_adapters[port]);
  874. piix4_main_adapters[port] = NULL;
  875. }
  876. }
  877. return retval;
  878. }
  879. static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
  880. {
  881. int retval;
  882. bool is_sb800 = false;
  883. if ((dev->vendor == PCI_VENDOR_ID_ATI &&
  884. dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
  885. dev->revision >= 0x40) ||
  886. dev->vendor == PCI_VENDOR_ID_AMD ||
  887. dev->vendor == PCI_VENDOR_ID_HYGON) {
  888. bool notify_imc = false;
  889. is_sb800 = true;
  890. if ((dev->vendor == PCI_VENDOR_ID_AMD ||
  891. dev->vendor == PCI_VENDOR_ID_HYGON) &&
  892. dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
  893. u8 imc;
  894. /*
  895. * Detect if IMC is active or not, this method is
  896. * described on coreboot's AMD IMC notes
  897. */
  898. pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
  899. 0x40, &imc);
  900. if (imc & 0x80)
  901. notify_imc = true;
  902. }
  903. /* base address location etc changed in SB800 */
  904. retval = piix4_setup_sb800(dev, id, 0);
  905. if (retval < 0)
  906. return retval;
  907. /*
  908. * Try to register multiplexed main SMBus adapter,
  909. * give up if we can't
  910. */
  911. retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
  912. if (retval < 0)
  913. return retval;
  914. } else {
  915. retval = piix4_setup(dev, id);
  916. if (retval < 0)
  917. return retval;
  918. /* Try to register main SMBus adapter, give up if we can't */
  919. retval = piix4_add_adapter(dev, retval, false, 0, false, 0,
  920. "", &piix4_main_adapters[0]);
  921. if (retval < 0)
  922. return retval;
  923. piix4_adapter_count = 1;
  924. }
  925. /* Check for auxiliary SMBus on some AMD chipsets */
  926. retval = -ENODEV;
  927. if (dev->vendor == PCI_VENDOR_ID_ATI &&
  928. dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
  929. if (dev->revision < 0x40) {
  930. retval = piix4_setup_aux(dev, id, 0x58);
  931. } else {
  932. /* SB800 added aux bus too */
  933. retval = piix4_setup_sb800(dev, id, 1);
  934. }
  935. }
  936. if (dev->vendor == PCI_VENDOR_ID_AMD &&
  937. (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
  938. dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
  939. retval = piix4_setup_sb800(dev, id, 1);
  940. }
  941. if (retval > 0) {
  942. /* Try to add the aux adapter if it exists,
  943. * piix4_add_adapter will clean up if this fails */
  944. piix4_add_adapter(dev, retval, false, 0, false, 1,
  945. is_sb800 ? piix4_aux_port_name_sb800 : "",
  946. &piix4_aux_adapter);
  947. }
  948. return 0;
  949. }
  950. static void piix4_adap_remove(struct i2c_adapter *adap)
  951. {
  952. struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
  953. if (adapdata->smba) {
  954. i2c_del_adapter(adap);
  955. if (adapdata->port == (0 << piix4_port_shift_sb800))
  956. release_region(adapdata->smba, SMBIOSIZE);
  957. kfree(adapdata);
  958. kfree(adap);
  959. }
  960. }
  961. static void piix4_remove(struct pci_dev *dev)
  962. {
  963. int port = piix4_adapter_count;
  964. while (--port >= 0) {
  965. if (piix4_main_adapters[port]) {
  966. piix4_adap_remove(piix4_main_adapters[port]);
  967. piix4_main_adapters[port] = NULL;
  968. }
  969. }
  970. if (piix4_aux_adapter) {
  971. piix4_adap_remove(piix4_aux_adapter);
  972. piix4_aux_adapter = NULL;
  973. }
  974. }
  975. static struct pci_driver piix4_driver = {
  976. .name = "piix4_smbus",
  977. .id_table = piix4_ids,
  978. .probe = piix4_probe,
  979. .remove = piix4_remove,
  980. };
  981. module_pci_driver(piix4_driver);
  982. MODULE_AUTHOR("Frodo Looijaard <[email protected]>");
  983. MODULE_AUTHOR("Philip Edelbrock <[email protected]>");
  984. MODULE_DESCRIPTION("PIIX4 SMBus driver");
  985. MODULE_LICENSE("GPL");