i2c-eg20t.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
  4. */
  5. #include <linux/module.h>
  6. #include <linux/kernel.h>
  7. #include <linux/delay.h>
  8. #include <linux/errno.h>
  9. #include <linux/i2c.h>
  10. #include <linux/fs.h>
  11. #include <linux/io.h>
  12. #include <linux/types.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/jiffies.h>
  15. #include <linux/pci.h>
  16. #include <linux/mutex.h>
  17. #include <linux/ktime.h>
  18. #include <linux/slab.h>
  19. #define PCH_EVENT_SET 0 /* I2C Interrupt Event Set Status */
  20. #define PCH_EVENT_NONE 1 /* I2C Interrupt Event Clear Status */
  21. #define PCH_MAX_CLK 100000 /* Maximum Clock speed in MHz */
  22. #define PCH_BUFFER_MODE_ENABLE 0x0002 /* flag for Buffer mode enable */
  23. #define PCH_EEPROM_SW_RST_MODE_ENABLE 0x0008 /* EEPROM SW RST enable flag */
  24. #define PCH_I2CSADR 0x00 /* I2C slave address register */
  25. #define PCH_I2CCTL 0x04 /* I2C control register */
  26. #define PCH_I2CSR 0x08 /* I2C status register */
  27. #define PCH_I2CDR 0x0C /* I2C data register */
  28. #define PCH_I2CMON 0x10 /* I2C bus monitor register */
  29. #define PCH_I2CBC 0x14 /* I2C bus transfer rate setup counter */
  30. #define PCH_I2CMOD 0x18 /* I2C mode register */
  31. #define PCH_I2CBUFSLV 0x1C /* I2C buffer mode slave address register */
  32. #define PCH_I2CBUFSUB 0x20 /* I2C buffer mode subaddress register */
  33. #define PCH_I2CBUFFOR 0x24 /* I2C buffer mode format register */
  34. #define PCH_I2CBUFCTL 0x28 /* I2C buffer mode control register */
  35. #define PCH_I2CBUFMSK 0x2C /* I2C buffer mode interrupt mask register */
  36. #define PCH_I2CBUFSTA 0x30 /* I2C buffer mode status register */
  37. #define PCH_I2CBUFLEV 0x34 /* I2C buffer mode level register */
  38. #define PCH_I2CESRFOR 0x38 /* EEPROM software reset mode format register */
  39. #define PCH_I2CESRCTL 0x3C /* EEPROM software reset mode ctrl register */
  40. #define PCH_I2CESRMSK 0x40 /* EEPROM software reset mode */
  41. #define PCH_I2CESRSTA 0x44 /* EEPROM software reset mode status register */
  42. #define PCH_I2CTMR 0x48 /* I2C timer register */
  43. #define PCH_I2CSRST 0xFC /* I2C reset register */
  44. #define PCH_I2CNF 0xF8 /* I2C noise filter register */
  45. #define BUS_IDLE_TIMEOUT 20
  46. #define PCH_I2CCTL_I2CMEN 0x0080
  47. #define TEN_BIT_ADDR_DEFAULT 0xF000
  48. #define TEN_BIT_ADDR_MASK 0xF0
  49. #define PCH_START 0x0020
  50. #define PCH_RESTART 0x0004
  51. #define PCH_ESR_START 0x0001
  52. #define PCH_BUFF_START 0x1
  53. #define PCH_REPSTART 0x0004
  54. #define PCH_ACK 0x0008
  55. #define PCH_GETACK 0x0001
  56. #define CLR_REG 0x0
  57. #define I2C_RD 0x1
  58. #define I2CMCF_BIT 0x0080
  59. #define I2CMIF_BIT 0x0002
  60. #define I2CMAL_BIT 0x0010
  61. #define I2CBMFI_BIT 0x0001
  62. #define I2CBMAL_BIT 0x0002
  63. #define I2CBMNA_BIT 0x0004
  64. #define I2CBMTO_BIT 0x0008
  65. #define I2CBMIS_BIT 0x0010
  66. #define I2CESRFI_BIT 0X0001
  67. #define I2CESRTO_BIT 0x0002
  68. #define I2CESRFIIE_BIT 0x1
  69. #define I2CESRTOIE_BIT 0x2
  70. #define I2CBMDZ_BIT 0x0040
  71. #define I2CBMAG_BIT 0x0020
  72. #define I2CMBB_BIT 0x0020
  73. #define BUFFER_MODE_MASK (I2CBMFI_BIT | I2CBMAL_BIT | I2CBMNA_BIT | \
  74. I2CBMTO_BIT | I2CBMIS_BIT)
  75. #define I2C_ADDR_MSK 0xFF
  76. #define I2C_MSB_2B_MSK 0x300
  77. #define FAST_MODE_CLK 400
  78. #define FAST_MODE_EN 0x0001
  79. #define SUB_ADDR_LEN_MAX 4
  80. #define BUF_LEN_MAX 32
  81. #define PCH_BUFFER_MODE 0x1
  82. #define EEPROM_SW_RST_MODE 0x0002
  83. #define NORMAL_INTR_ENBL 0x0300
  84. #define EEPROM_RST_INTR_ENBL (I2CESRFIIE_BIT | I2CESRTOIE_BIT)
  85. #define EEPROM_RST_INTR_DISBL 0x0
  86. #define BUFFER_MODE_INTR_ENBL 0x001F
  87. #define BUFFER_MODE_INTR_DISBL 0x0
  88. #define NORMAL_MODE 0x0
  89. #define BUFFER_MODE 0x1
  90. #define EEPROM_SR_MODE 0x2
  91. #define I2C_TX_MODE 0x0010
  92. #define PCH_BUF_TX 0xFFF7
  93. #define PCH_BUF_RD 0x0008
  94. #define I2C_ERROR_MASK (I2CESRTO_EVENT | I2CBMIS_EVENT | I2CBMTO_EVENT | \
  95. I2CBMNA_EVENT | I2CBMAL_EVENT | I2CMAL_EVENT)
  96. #define I2CMAL_EVENT 0x0001
  97. #define I2CMCF_EVENT 0x0002
  98. #define I2CBMFI_EVENT 0x0004
  99. #define I2CBMAL_EVENT 0x0008
  100. #define I2CBMNA_EVENT 0x0010
  101. #define I2CBMTO_EVENT 0x0020
  102. #define I2CBMIS_EVENT 0x0040
  103. #define I2CESRFI_EVENT 0x0080
  104. #define I2CESRTO_EVENT 0x0100
  105. #define PCI_DEVICE_ID_PCH_I2C 0x8817
  106. #define pch_dbg(adap, fmt, arg...) \
  107. dev_dbg(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
  108. #define pch_err(adap, fmt, arg...) \
  109. dev_err(adap->pch_adapter.dev.parent, "%s :" fmt, __func__, ##arg)
  110. #define pch_pci_err(pdev, fmt, arg...) \
  111. dev_err(&pdev->dev, "%s :" fmt, __func__, ##arg)
  112. #define pch_pci_dbg(pdev, fmt, arg...) \
  113. dev_dbg(&pdev->dev, "%s :" fmt, __func__, ##arg)
  114. /*
  115. Set the number of I2C instance max
  116. Intel EG20T PCH : 1ch
  117. LAPIS Semiconductor ML7213 IOH : 2ch
  118. LAPIS Semiconductor ML7831 IOH : 1ch
  119. */
  120. #define PCH_I2C_MAX_DEV 2
  121. /**
  122. * struct i2c_algo_pch_data - for I2C driver functionalities
  123. * @pch_adapter: stores the reference to i2c_adapter structure
  124. * @p_adapter_info: stores the reference to adapter_info structure
  125. * @pch_base_address: specifies the remapped base address
  126. * @pch_buff_mode_en: specifies if buffer mode is enabled
  127. * @pch_event_flag: specifies occurrence of interrupt events
  128. * @pch_i2c_xfer_in_progress: specifies whether the transfer is completed
  129. */
  130. struct i2c_algo_pch_data {
  131. struct i2c_adapter pch_adapter;
  132. struct adapter_info *p_adapter_info;
  133. void __iomem *pch_base_address;
  134. int pch_buff_mode_en;
  135. u32 pch_event_flag;
  136. bool pch_i2c_xfer_in_progress;
  137. };
  138. /**
  139. * struct adapter_info - This structure holds the adapter information for the
  140. * PCH i2c controller
  141. * @pch_data: stores a list of i2c_algo_pch_data
  142. * @pch_i2c_suspended: specifies whether the system is suspended or not
  143. * perhaps with more lines and words.
  144. * @ch_num: specifies the number of i2c instance
  145. *
  146. * pch_data has as many elements as maximum I2C channels
  147. */
  148. struct adapter_info {
  149. struct i2c_algo_pch_data pch_data[PCH_I2C_MAX_DEV];
  150. bool pch_i2c_suspended;
  151. int ch_num;
  152. };
  153. static int pch_i2c_speed = 100; /* I2C bus speed in Kbps */
  154. static int pch_clk = 50000; /* specifies I2C clock speed in KHz */
  155. static wait_queue_head_t pch_event;
  156. static DEFINE_MUTEX(pch_mutex);
  157. /* Definition for ML7213 by LAPIS Semiconductor */
  158. #define PCI_DEVICE_ID_ML7213_I2C 0x802D
  159. #define PCI_DEVICE_ID_ML7223_I2C 0x8010
  160. #define PCI_DEVICE_ID_ML7831_I2C 0x8817
  161. static const struct pci_device_id pch_pcidev_id[] = {
  162. { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
  163. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
  164. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
  165. { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7831_I2C), 1, },
  166. {0,}
  167. };
  168. MODULE_DEVICE_TABLE(pci, pch_pcidev_id);
  169. static irqreturn_t pch_i2c_handler(int irq, void *pData);
  170. static inline void pch_setbit(void __iomem *addr, u32 offset, u32 bitmask)
  171. {
  172. u32 val;
  173. val = ioread32(addr + offset);
  174. val |= bitmask;
  175. iowrite32(val, addr + offset);
  176. }
  177. static inline void pch_clrbit(void __iomem *addr, u32 offset, u32 bitmask)
  178. {
  179. u32 val;
  180. val = ioread32(addr + offset);
  181. val &= (~bitmask);
  182. iowrite32(val, addr + offset);
  183. }
  184. /**
  185. * pch_i2c_init() - hardware initialization of I2C module
  186. * @adap: Pointer to struct i2c_algo_pch_data.
  187. */
  188. static void pch_i2c_init(struct i2c_algo_pch_data *adap)
  189. {
  190. void __iomem *p = adap->pch_base_address;
  191. u32 pch_i2cbc;
  192. u32 pch_i2ctmr;
  193. u32 reg_value;
  194. /* reset I2C controller */
  195. iowrite32(0x01, p + PCH_I2CSRST);
  196. msleep(20);
  197. iowrite32(0x0, p + PCH_I2CSRST);
  198. /* Initialize I2C registers */
  199. iowrite32(0x21, p + PCH_I2CNF);
  200. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_I2CCTL_I2CMEN);
  201. if (pch_i2c_speed != 400)
  202. pch_i2c_speed = 100;
  203. reg_value = PCH_I2CCTL_I2CMEN;
  204. if (pch_i2c_speed == FAST_MODE_CLK) {
  205. reg_value |= FAST_MODE_EN;
  206. pch_dbg(adap, "Fast mode enabled\n");
  207. }
  208. if (pch_clk > PCH_MAX_CLK)
  209. pch_clk = 62500;
  210. pch_i2cbc = (pch_clk + (pch_i2c_speed * 4)) / (pch_i2c_speed * 8);
  211. /* Set transfer speed in I2CBC */
  212. iowrite32(pch_i2cbc, p + PCH_I2CBC);
  213. pch_i2ctmr = (pch_clk) / 8;
  214. iowrite32(pch_i2ctmr, p + PCH_I2CTMR);
  215. reg_value |= NORMAL_INTR_ENBL; /* Enable interrupts in normal mode */
  216. iowrite32(reg_value, p + PCH_I2CCTL);
  217. pch_dbg(adap,
  218. "I2CCTL=%x pch_i2cbc=%x pch_i2ctmr=%x Enable interrupts\n",
  219. ioread32(p + PCH_I2CCTL), pch_i2cbc, pch_i2ctmr);
  220. init_waitqueue_head(&pch_event);
  221. }
  222. /**
  223. * pch_i2c_wait_for_bus_idle() - check the status of bus.
  224. * @adap: Pointer to struct i2c_algo_pch_data.
  225. * @timeout: waiting time counter (ms).
  226. */
  227. static s32 pch_i2c_wait_for_bus_idle(struct i2c_algo_pch_data *adap,
  228. s32 timeout)
  229. {
  230. void __iomem *p = adap->pch_base_address;
  231. int schedule = 0;
  232. unsigned long end = jiffies + msecs_to_jiffies(timeout);
  233. while (ioread32(p + PCH_I2CSR) & I2CMBB_BIT) {
  234. if (time_after(jiffies, end)) {
  235. pch_dbg(adap, "I2CSR = %x\n", ioread32(p + PCH_I2CSR));
  236. pch_err(adap, "%s: Timeout Error.return%d\n",
  237. __func__, -ETIME);
  238. pch_i2c_init(adap);
  239. return -ETIME;
  240. }
  241. if (!schedule)
  242. /* Retry after some usecs */
  243. udelay(5);
  244. else
  245. /* Wait a bit more without consuming CPU */
  246. usleep_range(20, 1000);
  247. schedule = 1;
  248. }
  249. return 0;
  250. }
  251. /**
  252. * pch_i2c_start() - Generate I2C start condition in normal mode.
  253. * @adap: Pointer to struct i2c_algo_pch_data.
  254. *
  255. * Generate I2C start condition in normal mode by setting I2CCTL.I2CMSTA to 1.
  256. */
  257. static void pch_i2c_start(struct i2c_algo_pch_data *adap)
  258. {
  259. void __iomem *p = adap->pch_base_address;
  260. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  261. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
  262. }
  263. /**
  264. * pch_i2c_stop() - generate stop condition in normal mode.
  265. * @adap: Pointer to struct i2c_algo_pch_data.
  266. */
  267. static void pch_i2c_stop(struct i2c_algo_pch_data *adap)
  268. {
  269. void __iomem *p = adap->pch_base_address;
  270. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  271. /* clear the start bit */
  272. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_START);
  273. }
  274. static int pch_i2c_wait_for_check_xfer(struct i2c_algo_pch_data *adap)
  275. {
  276. long ret;
  277. void __iomem *p = adap->pch_base_address;
  278. ret = wait_event_timeout(pch_event,
  279. (adap->pch_event_flag != 0), msecs_to_jiffies(1000));
  280. if (!ret) {
  281. pch_err(adap, "%s:wait-event timeout\n", __func__);
  282. adap->pch_event_flag = 0;
  283. pch_i2c_stop(adap);
  284. pch_i2c_init(adap);
  285. return -ETIMEDOUT;
  286. }
  287. if (adap->pch_event_flag & I2C_ERROR_MASK) {
  288. pch_err(adap, "Lost Arbitration\n");
  289. adap->pch_event_flag = 0;
  290. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMAL_BIT);
  291. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
  292. pch_i2c_init(adap);
  293. return -EAGAIN;
  294. }
  295. adap->pch_event_flag = 0;
  296. if (ioread32(p + PCH_I2CSR) & PCH_GETACK) {
  297. pch_dbg(adap, "Receive NACK for slave address setting\n");
  298. return -ENXIO;
  299. }
  300. return 0;
  301. }
  302. /**
  303. * pch_i2c_repstart() - generate repeated start condition in normal mode
  304. * @adap: Pointer to struct i2c_algo_pch_data.
  305. */
  306. static void pch_i2c_repstart(struct i2c_algo_pch_data *adap)
  307. {
  308. void __iomem *p = adap->pch_base_address;
  309. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  310. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_REPSTART);
  311. }
  312. /**
  313. * pch_i2c_writebytes() - write data to I2C bus in normal mode
  314. * @i2c_adap: Pointer to the struct i2c_adapter.
  315. * @msgs: Pointer to the i2c message structure.
  316. * @last: specifies whether last message or not.
  317. * In the case of compound mode it will be 1 for last message,
  318. * otherwise 0.
  319. * @first: specifies whether first message or not.
  320. * 1 for first message otherwise 0.
  321. */
  322. static s32 pch_i2c_writebytes(struct i2c_adapter *i2c_adap,
  323. struct i2c_msg *msgs, u32 last, u32 first)
  324. {
  325. struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
  326. u8 *buf;
  327. u32 length;
  328. u32 addr;
  329. u32 addr_2_msb;
  330. u32 addr_8_lsb;
  331. s32 wrcount;
  332. s32 rtn;
  333. void __iomem *p = adap->pch_base_address;
  334. length = msgs->len;
  335. buf = msgs->buf;
  336. addr = msgs->addr;
  337. /* enable master tx */
  338. pch_setbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
  339. pch_dbg(adap, "I2CCTL = %x msgs->len = %d\n", ioread32(p + PCH_I2CCTL),
  340. length);
  341. if (first) {
  342. if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
  343. return -ETIME;
  344. }
  345. if (msgs->flags & I2C_M_TEN) {
  346. addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7) & 0x06;
  347. iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
  348. if (first)
  349. pch_i2c_start(adap);
  350. rtn = pch_i2c_wait_for_check_xfer(adap);
  351. if (rtn)
  352. return rtn;
  353. addr_8_lsb = (addr & I2C_ADDR_MSK);
  354. iowrite32(addr_8_lsb, p + PCH_I2CDR);
  355. } else {
  356. /* set 7 bit slave address and R/W bit as 0 */
  357. iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
  358. if (first)
  359. pch_i2c_start(adap);
  360. }
  361. rtn = pch_i2c_wait_for_check_xfer(adap);
  362. if (rtn)
  363. return rtn;
  364. for (wrcount = 0; wrcount < length; ++wrcount) {
  365. /* write buffer value to I2C data register */
  366. iowrite32(buf[wrcount], p + PCH_I2CDR);
  367. pch_dbg(adap, "writing %x to Data register\n", buf[wrcount]);
  368. rtn = pch_i2c_wait_for_check_xfer(adap);
  369. if (rtn)
  370. return rtn;
  371. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMCF_BIT);
  372. pch_clrbit(adap->pch_base_address, PCH_I2CSR, I2CMIF_BIT);
  373. }
  374. /* check if this is the last message */
  375. if (last)
  376. pch_i2c_stop(adap);
  377. else
  378. pch_i2c_repstart(adap);
  379. pch_dbg(adap, "return=%d\n", wrcount);
  380. return wrcount;
  381. }
  382. /**
  383. * pch_i2c_sendack() - send ACK
  384. * @adap: Pointer to struct i2c_algo_pch_data.
  385. */
  386. static void pch_i2c_sendack(struct i2c_algo_pch_data *adap)
  387. {
  388. void __iomem *p = adap->pch_base_address;
  389. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  390. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
  391. }
  392. /**
  393. * pch_i2c_sendnack() - send NACK
  394. * @adap: Pointer to struct i2c_algo_pch_data.
  395. */
  396. static void pch_i2c_sendnack(struct i2c_algo_pch_data *adap)
  397. {
  398. void __iomem *p = adap->pch_base_address;
  399. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  400. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_ACK);
  401. }
  402. /**
  403. * pch_i2c_restart() - Generate I2C restart condition in normal mode.
  404. * @adap: Pointer to struct i2c_algo_pch_data.
  405. *
  406. * Generate I2C restart condition in normal mode by setting I2CCTL.I2CRSTA.
  407. */
  408. static void pch_i2c_restart(struct i2c_algo_pch_data *adap)
  409. {
  410. void __iomem *p = adap->pch_base_address;
  411. pch_dbg(adap, "I2CCTL = %x\n", ioread32(p + PCH_I2CCTL));
  412. pch_setbit(adap->pch_base_address, PCH_I2CCTL, PCH_RESTART);
  413. }
  414. /**
  415. * pch_i2c_readbytes() - read data from I2C bus in normal mode.
  416. * @i2c_adap: Pointer to the struct i2c_adapter.
  417. * @msgs: Pointer to i2c_msg structure.
  418. * @last: specifies whether last message or not.
  419. * @first: specifies whether first message or not.
  420. */
  421. static s32 pch_i2c_readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
  422. u32 last, u32 first)
  423. {
  424. struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
  425. u8 *buf;
  426. u32 count;
  427. u32 length;
  428. u32 addr;
  429. u32 addr_2_msb;
  430. u32 addr_8_lsb;
  431. void __iomem *p = adap->pch_base_address;
  432. s32 rtn;
  433. length = msgs->len;
  434. buf = msgs->buf;
  435. addr = msgs->addr;
  436. /* enable master reception */
  437. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, I2C_TX_MODE);
  438. if (first) {
  439. if (pch_i2c_wait_for_bus_idle(adap, BUS_IDLE_TIMEOUT) == -ETIME)
  440. return -ETIME;
  441. }
  442. if (msgs->flags & I2C_M_TEN) {
  443. addr_2_msb = ((addr & I2C_MSB_2B_MSK) >> 7);
  444. iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
  445. if (first)
  446. pch_i2c_start(adap);
  447. rtn = pch_i2c_wait_for_check_xfer(adap);
  448. if (rtn)
  449. return rtn;
  450. addr_8_lsb = (addr & I2C_ADDR_MSK);
  451. iowrite32(addr_8_lsb, p + PCH_I2CDR);
  452. pch_i2c_restart(adap);
  453. rtn = pch_i2c_wait_for_check_xfer(adap);
  454. if (rtn)
  455. return rtn;
  456. addr_2_msb |= I2C_RD;
  457. iowrite32(addr_2_msb | TEN_BIT_ADDR_MASK, p + PCH_I2CDR);
  458. } else {
  459. /* 7 address bits + R/W bit */
  460. iowrite32(i2c_8bit_addr_from_msg(msgs), p + PCH_I2CDR);
  461. }
  462. /* check if it is the first message */
  463. if (first)
  464. pch_i2c_start(adap);
  465. rtn = pch_i2c_wait_for_check_xfer(adap);
  466. if (rtn)
  467. return rtn;
  468. if (length == 0) {
  469. pch_i2c_stop(adap);
  470. ioread32(p + PCH_I2CDR); /* Dummy read needs */
  471. count = length;
  472. } else {
  473. int read_index;
  474. int loop;
  475. pch_i2c_sendack(adap);
  476. /* Dummy read */
  477. for (loop = 1, read_index = 0; loop < length; loop++) {
  478. buf[read_index] = ioread32(p + PCH_I2CDR);
  479. if (loop != 1)
  480. read_index++;
  481. rtn = pch_i2c_wait_for_check_xfer(adap);
  482. if (rtn)
  483. return rtn;
  484. } /* end for */
  485. pch_i2c_sendnack(adap);
  486. buf[read_index] = ioread32(p + PCH_I2CDR); /* Read final - 1 */
  487. if (length != 1)
  488. read_index++;
  489. rtn = pch_i2c_wait_for_check_xfer(adap);
  490. if (rtn)
  491. return rtn;
  492. if (last)
  493. pch_i2c_stop(adap);
  494. else
  495. pch_i2c_repstart(adap);
  496. buf[read_index++] = ioread32(p + PCH_I2CDR); /* Read Final */
  497. count = read_index;
  498. }
  499. return count;
  500. }
  501. /**
  502. * pch_i2c_cb() - Interrupt handler Call back function
  503. * @adap: Pointer to struct i2c_algo_pch_data.
  504. */
  505. static void pch_i2c_cb(struct i2c_algo_pch_data *adap)
  506. {
  507. u32 sts;
  508. void __iomem *p = adap->pch_base_address;
  509. sts = ioread32(p + PCH_I2CSR);
  510. sts &= (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT);
  511. if (sts & I2CMAL_BIT)
  512. adap->pch_event_flag |= I2CMAL_EVENT;
  513. if (sts & I2CMCF_BIT)
  514. adap->pch_event_flag |= I2CMCF_EVENT;
  515. /* clear the applicable bits */
  516. pch_clrbit(adap->pch_base_address, PCH_I2CSR, sts);
  517. pch_dbg(adap, "PCH_I2CSR = %x\n", ioread32(p + PCH_I2CSR));
  518. wake_up(&pch_event);
  519. }
  520. /**
  521. * pch_i2c_handler() - interrupt handler for the PCH I2C controller
  522. * @irq: irq number.
  523. * @pData: cookie passed back to the handler function.
  524. */
  525. static irqreturn_t pch_i2c_handler(int irq, void *pData)
  526. {
  527. u32 reg_val;
  528. int flag;
  529. int i;
  530. struct adapter_info *adap_info = pData;
  531. void __iomem *p;
  532. u32 mode;
  533. for (i = 0, flag = 0; i < adap_info->ch_num; i++) {
  534. p = adap_info->pch_data[i].pch_base_address;
  535. mode = ioread32(p + PCH_I2CMOD);
  536. mode &= BUFFER_MODE | EEPROM_SR_MODE;
  537. if (mode != NORMAL_MODE) {
  538. pch_err(adap_info->pch_data,
  539. "I2C-%d mode(%d) is not supported\n", mode, i);
  540. continue;
  541. }
  542. reg_val = ioread32(p + PCH_I2CSR);
  543. if (reg_val & (I2CMAL_BIT | I2CMCF_BIT | I2CMIF_BIT)) {
  544. pch_i2c_cb(&adap_info->pch_data[i]);
  545. flag = 1;
  546. }
  547. }
  548. return flag ? IRQ_HANDLED : IRQ_NONE;
  549. }
  550. /**
  551. * pch_i2c_xfer() - Reading adnd writing data through I2C bus
  552. * @i2c_adap: Pointer to the struct i2c_adapter.
  553. * @msgs: Pointer to i2c_msg structure.
  554. * @num: number of messages.
  555. */
  556. static s32 pch_i2c_xfer(struct i2c_adapter *i2c_adap,
  557. struct i2c_msg *msgs, s32 num)
  558. {
  559. struct i2c_msg *pmsg;
  560. u32 i = 0;
  561. u32 status;
  562. s32 ret;
  563. struct i2c_algo_pch_data *adap = i2c_adap->algo_data;
  564. ret = mutex_lock_interruptible(&pch_mutex);
  565. if (ret)
  566. return ret;
  567. if (adap->p_adapter_info->pch_i2c_suspended) {
  568. mutex_unlock(&pch_mutex);
  569. return -EBUSY;
  570. }
  571. pch_dbg(adap, "adap->p_adapter_info->pch_i2c_suspended is %d\n",
  572. adap->p_adapter_info->pch_i2c_suspended);
  573. /* transfer not completed */
  574. adap->pch_i2c_xfer_in_progress = true;
  575. for (i = 0; i < num && ret >= 0; i++) {
  576. pmsg = &msgs[i];
  577. pmsg->flags |= adap->pch_buff_mode_en;
  578. status = pmsg->flags;
  579. pch_dbg(adap,
  580. "After invoking I2C_MODE_SEL :flag= 0x%x\n", status);
  581. if ((status & (I2C_M_RD)) != false) {
  582. ret = pch_i2c_readbytes(i2c_adap, pmsg, (i + 1 == num),
  583. (i == 0));
  584. } else {
  585. ret = pch_i2c_writebytes(i2c_adap, pmsg, (i + 1 == num),
  586. (i == 0));
  587. }
  588. }
  589. adap->pch_i2c_xfer_in_progress = false; /* transfer completed */
  590. mutex_unlock(&pch_mutex);
  591. return (ret < 0) ? ret : num;
  592. }
  593. /**
  594. * pch_i2c_func() - return the functionality of the I2C driver
  595. * @adap: Pointer to struct i2c_algo_pch_data.
  596. */
  597. static u32 pch_i2c_func(struct i2c_adapter *adap)
  598. {
  599. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
  600. }
  601. static const struct i2c_algorithm pch_algorithm = {
  602. .master_xfer = pch_i2c_xfer,
  603. .functionality = pch_i2c_func
  604. };
  605. /**
  606. * pch_i2c_disbl_int() - Disable PCH I2C interrupts
  607. * @adap: Pointer to struct i2c_algo_pch_data.
  608. */
  609. static void pch_i2c_disbl_int(struct i2c_algo_pch_data *adap)
  610. {
  611. void __iomem *p = adap->pch_base_address;
  612. pch_clrbit(adap->pch_base_address, PCH_I2CCTL, NORMAL_INTR_ENBL);
  613. iowrite32(EEPROM_RST_INTR_DISBL, p + PCH_I2CESRMSK);
  614. iowrite32(BUFFER_MODE_INTR_DISBL, p + PCH_I2CBUFMSK);
  615. }
  616. static int pch_i2c_probe(struct pci_dev *pdev,
  617. const struct pci_device_id *id)
  618. {
  619. void __iomem *base_addr;
  620. int ret;
  621. int i, j;
  622. struct adapter_info *adap_info;
  623. struct i2c_adapter *pch_adap;
  624. pch_pci_dbg(pdev, "Entered.\n");
  625. adap_info = kzalloc((sizeof(struct adapter_info)), GFP_KERNEL);
  626. if (adap_info == NULL)
  627. return -ENOMEM;
  628. ret = pci_enable_device(pdev);
  629. if (ret) {
  630. pch_pci_err(pdev, "pci_enable_device FAILED\n");
  631. goto err_pci_enable;
  632. }
  633. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  634. if (ret) {
  635. pch_pci_err(pdev, "pci_request_regions FAILED\n");
  636. goto err_pci_req;
  637. }
  638. base_addr = pci_iomap(pdev, 1, 0);
  639. if (base_addr == NULL) {
  640. pch_pci_err(pdev, "pci_iomap FAILED\n");
  641. ret = -ENOMEM;
  642. goto err_pci_iomap;
  643. }
  644. /* Set the number of I2C channel instance */
  645. adap_info->ch_num = id->driver_data;
  646. for (i = 0; i < adap_info->ch_num; i++) {
  647. pch_adap = &adap_info->pch_data[i].pch_adapter;
  648. adap_info->pch_i2c_suspended = false;
  649. adap_info->pch_data[i].p_adapter_info = adap_info;
  650. pch_adap->owner = THIS_MODULE;
  651. pch_adap->class = I2C_CLASS_HWMON;
  652. strscpy(pch_adap->name, KBUILD_MODNAME, sizeof(pch_adap->name));
  653. pch_adap->algo = &pch_algorithm;
  654. pch_adap->algo_data = &adap_info->pch_data[i];
  655. /* base_addr + offset; */
  656. adap_info->pch_data[i].pch_base_address = base_addr + 0x100 * i;
  657. pch_adap->dev.of_node = pdev->dev.of_node;
  658. pch_adap->dev.parent = &pdev->dev;
  659. }
  660. ret = request_irq(pdev->irq, pch_i2c_handler, IRQF_SHARED,
  661. KBUILD_MODNAME, adap_info);
  662. if (ret) {
  663. pch_pci_err(pdev, "request_irq FAILED\n");
  664. goto err_request_irq;
  665. }
  666. for (i = 0; i < adap_info->ch_num; i++) {
  667. pch_adap = &adap_info->pch_data[i].pch_adapter;
  668. pch_i2c_init(&adap_info->pch_data[i]);
  669. pch_adap->nr = i;
  670. ret = i2c_add_numbered_adapter(pch_adap);
  671. if (ret) {
  672. pch_pci_err(pdev, "i2c_add_adapter[ch:%d] FAILED\n", i);
  673. goto err_add_adapter;
  674. }
  675. }
  676. pci_set_drvdata(pdev, adap_info);
  677. pch_pci_dbg(pdev, "returns %d.\n", ret);
  678. return 0;
  679. err_add_adapter:
  680. for (j = 0; j < i; j++)
  681. i2c_del_adapter(&adap_info->pch_data[j].pch_adapter);
  682. free_irq(pdev->irq, adap_info);
  683. err_request_irq:
  684. pci_iounmap(pdev, base_addr);
  685. err_pci_iomap:
  686. pci_release_regions(pdev);
  687. err_pci_req:
  688. pci_disable_device(pdev);
  689. err_pci_enable:
  690. kfree(adap_info);
  691. return ret;
  692. }
  693. static void pch_i2c_remove(struct pci_dev *pdev)
  694. {
  695. int i;
  696. struct adapter_info *adap_info = pci_get_drvdata(pdev);
  697. free_irq(pdev->irq, adap_info);
  698. for (i = 0; i < adap_info->ch_num; i++) {
  699. pch_i2c_disbl_int(&adap_info->pch_data[i]);
  700. i2c_del_adapter(&adap_info->pch_data[i].pch_adapter);
  701. }
  702. if (adap_info->pch_data[0].pch_base_address)
  703. pci_iounmap(pdev, adap_info->pch_data[0].pch_base_address);
  704. for (i = 0; i < adap_info->ch_num; i++)
  705. adap_info->pch_data[i].pch_base_address = NULL;
  706. pci_release_regions(pdev);
  707. pci_disable_device(pdev);
  708. kfree(adap_info);
  709. }
  710. static int __maybe_unused pch_i2c_suspend(struct device *dev)
  711. {
  712. int i;
  713. struct pci_dev *pdev = to_pci_dev(dev);
  714. struct adapter_info *adap_info = pci_get_drvdata(pdev);
  715. void __iomem *p = adap_info->pch_data[0].pch_base_address;
  716. adap_info->pch_i2c_suspended = true;
  717. for (i = 0; i < adap_info->ch_num; i++) {
  718. while ((adap_info->pch_data[i].pch_i2c_xfer_in_progress)) {
  719. /* Wait until all channel transfers are completed */
  720. msleep(20);
  721. }
  722. }
  723. /* Disable the i2c interrupts */
  724. for (i = 0; i < adap_info->ch_num; i++)
  725. pch_i2c_disbl_int(&adap_info->pch_data[i]);
  726. pch_pci_dbg(pdev, "I2CSR = %x I2CBUFSTA = %x I2CESRSTA = %x "
  727. "invoked function pch_i2c_disbl_int successfully\n",
  728. ioread32(p + PCH_I2CSR), ioread32(p + PCH_I2CBUFSTA),
  729. ioread32(p + PCH_I2CESRSTA));
  730. return 0;
  731. }
  732. static int __maybe_unused pch_i2c_resume(struct device *dev)
  733. {
  734. int i;
  735. struct adapter_info *adap_info = dev_get_drvdata(dev);
  736. for (i = 0; i < adap_info->ch_num; i++)
  737. pch_i2c_init(&adap_info->pch_data[i]);
  738. adap_info->pch_i2c_suspended = false;
  739. return 0;
  740. }
  741. static SIMPLE_DEV_PM_OPS(pch_i2c_pm_ops, pch_i2c_suspend, pch_i2c_resume);
  742. static struct pci_driver pch_pcidriver = {
  743. .name = KBUILD_MODNAME,
  744. .id_table = pch_pcidev_id,
  745. .probe = pch_i2c_probe,
  746. .remove = pch_i2c_remove,
  747. .driver.pm = &pch_i2c_pm_ops,
  748. };
  749. module_pci_driver(pch_pcidriver);
  750. MODULE_DESCRIPTION("Intel EG20T PCH/LAPIS Semico ML7213/ML7223/ML7831 IOH I2C");
  751. MODULE_LICENSE("GPL");
  752. MODULE_AUTHOR("Tomoya MORINAGA. <[email protected]>");
  753. module_param(pch_i2c_speed, int, (S_IRUSR | S_IWUSR));
  754. module_param(pch_clk, int, (S_IRUSR | S_IWUSR));