i2c-axxia.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * This driver implements I2C master functionality using the LSI API2C
  4. * controller.
  5. *
  6. * NOTE: The controller has a limitation in that it can only do transfers of
  7. * maximum 255 bytes at a time. If a larger transfer is attempted, error code
  8. * (-EINVAL) is returned.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/clkdev.h>
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/i2c.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/module.h>
  18. #include <linux/io.h>
  19. #include <linux/kernel.h>
  20. #include <linux/platform_device.h>
  21. #define SCL_WAIT_TIMEOUT_NS 25000000
  22. #define I2C_XFER_TIMEOUT (msecs_to_jiffies(250))
  23. #define I2C_STOP_TIMEOUT (msecs_to_jiffies(100))
  24. #define FIFO_SIZE 8
  25. #define SEQ_LEN 2
  26. #define GLOBAL_CONTROL 0x00
  27. #define GLOBAL_MST_EN BIT(0)
  28. #define GLOBAL_SLV_EN BIT(1)
  29. #define GLOBAL_IBML_EN BIT(2)
  30. #define INTERRUPT_STATUS 0x04
  31. #define INTERRUPT_ENABLE 0x08
  32. #define INT_SLV BIT(1)
  33. #define INT_MST BIT(0)
  34. #define WAIT_TIMER_CONTROL 0x0c
  35. #define WT_EN BIT(15)
  36. #define WT_VALUE(_x) ((_x) & 0x7fff)
  37. #define IBML_TIMEOUT 0x10
  38. #define IBML_LOW_MEXT 0x14
  39. #define IBML_LOW_SEXT 0x18
  40. #define TIMER_CLOCK_DIV 0x1c
  41. #define I2C_BUS_MONITOR 0x20
  42. #define BM_SDAC BIT(3)
  43. #define BM_SCLC BIT(2)
  44. #define BM_SDAS BIT(1)
  45. #define BM_SCLS BIT(0)
  46. #define SOFT_RESET 0x24
  47. #define MST_COMMAND 0x28
  48. #define CMD_BUSY (1<<3)
  49. #define CMD_MANUAL (0x00 | CMD_BUSY)
  50. #define CMD_AUTO (0x01 | CMD_BUSY)
  51. #define CMD_SEQUENCE (0x02 | CMD_BUSY)
  52. #define MST_RX_XFER 0x2c
  53. #define MST_TX_XFER 0x30
  54. #define MST_ADDR_1 0x34
  55. #define MST_ADDR_2 0x38
  56. #define MST_DATA 0x3c
  57. #define MST_TX_FIFO 0x40
  58. #define MST_RX_FIFO 0x44
  59. #define MST_INT_ENABLE 0x48
  60. #define MST_INT_STATUS 0x4c
  61. #define MST_STATUS_RFL (1 << 13) /* RX FIFO serivce */
  62. #define MST_STATUS_TFL (1 << 12) /* TX FIFO service */
  63. #define MST_STATUS_SNS (1 << 11) /* Manual mode done */
  64. #define MST_STATUS_SS (1 << 10) /* Automatic mode done */
  65. #define MST_STATUS_SCC (1 << 9) /* Stop complete */
  66. #define MST_STATUS_IP (1 << 8) /* Invalid parameter */
  67. #define MST_STATUS_TSS (1 << 7) /* Timeout */
  68. #define MST_STATUS_AL (1 << 6) /* Arbitration lost */
  69. #define MST_STATUS_ND (1 << 5) /* NAK on data phase */
  70. #define MST_STATUS_NA (1 << 4) /* NAK on address phase */
  71. #define MST_STATUS_NAK (MST_STATUS_NA | \
  72. MST_STATUS_ND)
  73. #define MST_STATUS_ERR (MST_STATUS_NAK | \
  74. MST_STATUS_AL | \
  75. MST_STATUS_IP)
  76. #define MST_TX_BYTES_XFRD 0x50
  77. #define MST_RX_BYTES_XFRD 0x54
  78. #define SLV_ADDR_DEC_CTL 0x58
  79. #define SLV_ADDR_DEC_GCE BIT(0) /* ACK to General Call Address from own master (loopback) */
  80. #define SLV_ADDR_DEC_OGCE BIT(1) /* ACK to General Call Address from external masters */
  81. #define SLV_ADDR_DEC_SA1E BIT(2) /* ACK to addr_1 enabled */
  82. #define SLV_ADDR_DEC_SA1M BIT(3) /* 10-bit addressing for addr_1 enabled */
  83. #define SLV_ADDR_DEC_SA2E BIT(4) /* ACK to addr_2 enabled */
  84. #define SLV_ADDR_DEC_SA2M BIT(5) /* 10-bit addressing for addr_2 enabled */
  85. #define SLV_ADDR_1 0x5c
  86. #define SLV_ADDR_2 0x60
  87. #define SLV_RX_CTL 0x64
  88. #define SLV_RX_ACSA1 BIT(0) /* Generate ACK for writes to addr_1 */
  89. #define SLV_RX_ACSA2 BIT(1) /* Generate ACK for writes to addr_2 */
  90. #define SLV_RX_ACGCA BIT(2) /* ACK data phase transfers to General Call Address */
  91. #define SLV_DATA 0x68
  92. #define SLV_RX_FIFO 0x6c
  93. #define SLV_FIFO_DV1 BIT(0) /* Data Valid for addr_1 */
  94. #define SLV_FIFO_DV2 BIT(1) /* Data Valid for addr_2 */
  95. #define SLV_FIFO_AS BIT(2) /* (N)ACK Sent */
  96. #define SLV_FIFO_TNAK BIT(3) /* Timeout NACK */
  97. #define SLV_FIFO_STRC BIT(4) /* First byte after start condition received */
  98. #define SLV_FIFO_RSC BIT(5) /* Repeated Start Condition */
  99. #define SLV_FIFO_STPC BIT(6) /* Stop Condition */
  100. #define SLV_FIFO_DV (SLV_FIFO_DV1 | SLV_FIFO_DV2)
  101. #define SLV_INT_ENABLE 0x70
  102. #define SLV_INT_STATUS 0x74
  103. #define SLV_STATUS_RFH BIT(0) /* FIFO service */
  104. #define SLV_STATUS_WTC BIT(1) /* Write transfer complete */
  105. #define SLV_STATUS_SRS1 BIT(2) /* Slave read from addr 1 */
  106. #define SLV_STATUS_SRRS1 BIT(3) /* Repeated start from addr 1 */
  107. #define SLV_STATUS_SRND1 BIT(4) /* Read request not following start condition */
  108. #define SLV_STATUS_SRC1 BIT(5) /* Read canceled */
  109. #define SLV_STATUS_SRAT1 BIT(6) /* Slave Read timed out */
  110. #define SLV_STATUS_SRDRE1 BIT(7) /* Data written after timed out */
  111. #define SLV_READ_DUMMY 0x78
  112. #define SCL_HIGH_PERIOD 0x80
  113. #define SCL_LOW_PERIOD 0x84
  114. #define SPIKE_FLTR_LEN 0x88
  115. #define SDA_SETUP_TIME 0x8c
  116. #define SDA_HOLD_TIME 0x90
  117. /**
  118. * axxia_i2c_dev - I2C device context
  119. * @base: pointer to register struct
  120. * @msg: pointer to current message
  121. * @msg_r: pointer to current read message (sequence transfer)
  122. * @msg_xfrd: number of bytes transferred in tx_fifo
  123. * @msg_xfrd_r: number of bytes transferred in rx_fifo
  124. * @msg_err: error code for completed message
  125. * @msg_complete: xfer completion object
  126. * @dev: device reference
  127. * @adapter: core i2c abstraction
  128. * @i2c_clk: clock reference for i2c input clock
  129. * @bus_clk_rate: current i2c bus clock rate
  130. * @last: a flag indicating is this is last message in transfer
  131. */
  132. struct axxia_i2c_dev {
  133. void __iomem *base;
  134. struct i2c_msg *msg;
  135. struct i2c_msg *msg_r;
  136. size_t msg_xfrd;
  137. size_t msg_xfrd_r;
  138. int msg_err;
  139. struct completion msg_complete;
  140. struct device *dev;
  141. struct i2c_adapter adapter;
  142. struct clk *i2c_clk;
  143. u32 bus_clk_rate;
  144. bool last;
  145. struct i2c_client *slave;
  146. int irq;
  147. };
  148. static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
  149. {
  150. u32 int_en;
  151. int_en = readl(idev->base + MST_INT_ENABLE);
  152. writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
  153. }
  154. static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
  155. {
  156. u32 int_en;
  157. int_en = readl(idev->base + MST_INT_ENABLE);
  158. writel(int_en | mask, idev->base + MST_INT_ENABLE);
  159. }
  160. /**
  161. * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
  162. */
  163. static u32 ns_to_clk(u64 ns, u32 clk_mhz)
  164. {
  165. return div_u64(ns * clk_mhz, 1000);
  166. }
  167. static int axxia_i2c_init(struct axxia_i2c_dev *idev)
  168. {
  169. u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
  170. u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
  171. u32 t_setup;
  172. u32 t_high, t_low;
  173. u32 tmo_clk;
  174. u32 prescale;
  175. unsigned long timeout;
  176. dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
  177. idev->bus_clk_rate, clk_mhz, divisor);
  178. /* Reset controller */
  179. writel(0x01, idev->base + SOFT_RESET);
  180. timeout = jiffies + msecs_to_jiffies(100);
  181. while (readl(idev->base + SOFT_RESET) & 1) {
  182. if (time_after(jiffies, timeout)) {
  183. dev_warn(idev->dev, "Soft reset failed\n");
  184. break;
  185. }
  186. }
  187. /* Enable Master Mode */
  188. writel(0x1, idev->base + GLOBAL_CONTROL);
  189. if (idev->bus_clk_rate <= I2C_MAX_STANDARD_MODE_FREQ) {
  190. /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
  191. t_high = divisor * 1 / 2;
  192. t_low = divisor * 1 / 2;
  193. t_setup = ns_to_clk(250, clk_mhz);
  194. } else {
  195. /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
  196. t_high = divisor * 1 / 3;
  197. t_low = divisor * 2 / 3;
  198. t_setup = ns_to_clk(100, clk_mhz);
  199. }
  200. /* SCL High Time */
  201. writel(t_high, idev->base + SCL_HIGH_PERIOD);
  202. /* SCL Low Time */
  203. writel(t_low, idev->base + SCL_LOW_PERIOD);
  204. /* SDA Setup Time */
  205. writel(t_setup, idev->base + SDA_SETUP_TIME);
  206. /* SDA Hold Time, 300ns */
  207. writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
  208. /* Filter <50ns spikes */
  209. writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
  210. /* Configure Time-Out Registers */
  211. tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
  212. /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
  213. for (prescale = 0; prescale < 15; ++prescale) {
  214. if (tmo_clk <= 0x7fff)
  215. break;
  216. tmo_clk >>= 1;
  217. }
  218. if (tmo_clk > 0x7fff)
  219. tmo_clk = 0x7fff;
  220. /* Prescale divider (log2) */
  221. writel(prescale, idev->base + TIMER_CLOCK_DIV);
  222. /* Timeout in divided clocks */
  223. writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
  224. /* Mask all master interrupt bits */
  225. i2c_int_disable(idev, ~0);
  226. /* Interrupt enable */
  227. writel(0x01, idev->base + INTERRUPT_ENABLE);
  228. return 0;
  229. }
  230. static int i2c_m_rd(const struct i2c_msg *msg)
  231. {
  232. return (msg->flags & I2C_M_RD) != 0;
  233. }
  234. static int i2c_m_ten(const struct i2c_msg *msg)
  235. {
  236. return (msg->flags & I2C_M_TEN) != 0;
  237. }
  238. static int i2c_m_recv_len(const struct i2c_msg *msg)
  239. {
  240. return (msg->flags & I2C_M_RECV_LEN) != 0;
  241. }
  242. /**
  243. * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
  244. * transfer length if this is the first byte of such a transfer.
  245. */
  246. static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
  247. {
  248. struct i2c_msg *msg = idev->msg_r;
  249. size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
  250. int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd_r);
  251. while (bytes_to_transfer-- > 0) {
  252. int c = readl(idev->base + MST_DATA);
  253. if (idev->msg_xfrd_r == 0 && i2c_m_recv_len(msg)) {
  254. /*
  255. * Check length byte for SMBus block read
  256. */
  257. if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
  258. idev->msg_err = -EPROTO;
  259. i2c_int_disable(idev, ~MST_STATUS_TSS);
  260. complete(&idev->msg_complete);
  261. break;
  262. }
  263. msg->len = 1 + c;
  264. writel(msg->len, idev->base + MST_RX_XFER);
  265. }
  266. msg->buf[idev->msg_xfrd_r++] = c;
  267. }
  268. return 0;
  269. }
  270. /**
  271. * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
  272. * @return: Number of bytes left to transfer.
  273. */
  274. static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
  275. {
  276. struct i2c_msg *msg = idev->msg;
  277. size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
  278. int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
  279. int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
  280. while (bytes_to_transfer-- > 0)
  281. writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
  282. return ret;
  283. }
  284. static void axxia_i2c_slv_fifo_event(struct axxia_i2c_dev *idev)
  285. {
  286. u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
  287. u8 val;
  288. dev_dbg(idev->dev, "slave irq fifo_status=0x%x\n", fifo_status);
  289. if (fifo_status & SLV_FIFO_DV1) {
  290. if (fifo_status & SLV_FIFO_STRC)
  291. i2c_slave_event(idev->slave,
  292. I2C_SLAVE_WRITE_REQUESTED, &val);
  293. val = readl(idev->base + SLV_DATA);
  294. i2c_slave_event(idev->slave, I2C_SLAVE_WRITE_RECEIVED, &val);
  295. }
  296. if (fifo_status & SLV_FIFO_STPC) {
  297. readl(idev->base + SLV_DATA); /* dummy read */
  298. i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
  299. }
  300. if (fifo_status & SLV_FIFO_RSC)
  301. readl(idev->base + SLV_DATA); /* dummy read */
  302. }
  303. static irqreturn_t axxia_i2c_slv_isr(struct axxia_i2c_dev *idev)
  304. {
  305. u32 status = readl(idev->base + SLV_INT_STATUS);
  306. u8 val;
  307. dev_dbg(idev->dev, "slave irq status=0x%x\n", status);
  308. if (status & SLV_STATUS_RFH)
  309. axxia_i2c_slv_fifo_event(idev);
  310. if (status & SLV_STATUS_SRS1) {
  311. i2c_slave_event(idev->slave, I2C_SLAVE_READ_REQUESTED, &val);
  312. writel(val, idev->base + SLV_DATA);
  313. }
  314. if (status & SLV_STATUS_SRND1) {
  315. i2c_slave_event(idev->slave, I2C_SLAVE_READ_PROCESSED, &val);
  316. writel(val, idev->base + SLV_DATA);
  317. }
  318. if (status & SLV_STATUS_SRC1)
  319. i2c_slave_event(idev->slave, I2C_SLAVE_STOP, &val);
  320. writel(INT_SLV, idev->base + INTERRUPT_STATUS);
  321. return IRQ_HANDLED;
  322. }
  323. static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
  324. {
  325. struct axxia_i2c_dev *idev = _dev;
  326. irqreturn_t ret = IRQ_NONE;
  327. u32 status;
  328. status = readl(idev->base + INTERRUPT_STATUS);
  329. if (status & INT_SLV)
  330. ret = axxia_i2c_slv_isr(idev);
  331. if (!(status & INT_MST))
  332. return ret;
  333. /* Read interrupt status bits */
  334. status = readl(idev->base + MST_INT_STATUS);
  335. if (!idev->msg) {
  336. dev_warn(idev->dev, "unexpected interrupt\n");
  337. goto out;
  338. }
  339. /* RX FIFO needs service? */
  340. if (i2c_m_rd(idev->msg_r) && (status & MST_STATUS_RFL))
  341. axxia_i2c_empty_rx_fifo(idev);
  342. /* TX FIFO needs service? */
  343. if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
  344. if (axxia_i2c_fill_tx_fifo(idev) == 0)
  345. i2c_int_disable(idev, MST_STATUS_TFL);
  346. }
  347. if (unlikely(status & MST_STATUS_ERR)) {
  348. /* Transfer error */
  349. i2c_int_disable(idev, ~0);
  350. if (status & MST_STATUS_AL)
  351. idev->msg_err = -EAGAIN;
  352. else if (status & MST_STATUS_NAK)
  353. idev->msg_err = -ENXIO;
  354. else
  355. idev->msg_err = -EIO;
  356. dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
  357. status,
  358. idev->msg->addr,
  359. readl(idev->base + MST_RX_BYTES_XFRD),
  360. readl(idev->base + MST_RX_XFER),
  361. readl(idev->base + MST_TX_BYTES_XFRD),
  362. readl(idev->base + MST_TX_XFER));
  363. complete(&idev->msg_complete);
  364. } else if (status & MST_STATUS_SCC) {
  365. /* Stop completed */
  366. i2c_int_disable(idev, ~MST_STATUS_TSS);
  367. complete(&idev->msg_complete);
  368. } else if (status & (MST_STATUS_SNS | MST_STATUS_SS)) {
  369. /* Transfer done */
  370. int mask = idev->last ? ~0 : ~MST_STATUS_TSS;
  371. i2c_int_disable(idev, mask);
  372. if (i2c_m_rd(idev->msg_r) && idev->msg_xfrd_r < idev->msg_r->len)
  373. axxia_i2c_empty_rx_fifo(idev);
  374. complete(&idev->msg_complete);
  375. } else if (status & MST_STATUS_TSS) {
  376. /* Transfer timeout */
  377. idev->msg_err = -ETIMEDOUT;
  378. i2c_int_disable(idev, ~MST_STATUS_TSS);
  379. complete(&idev->msg_complete);
  380. }
  381. out:
  382. /* Clear interrupt */
  383. writel(INT_MST, idev->base + INTERRUPT_STATUS);
  384. return IRQ_HANDLED;
  385. }
  386. static void axxia_i2c_set_addr(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
  387. {
  388. u32 addr_1, addr_2;
  389. if (i2c_m_ten(msg)) {
  390. /* 10-bit address
  391. * addr_1: 5'b11110 | addr[9:8] | (R/nW)
  392. * addr_2: addr[7:0]
  393. */
  394. addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
  395. if (i2c_m_rd(msg))
  396. addr_1 |= 1; /* Set the R/nW bit of the address */
  397. addr_2 = msg->addr & 0xFF;
  398. } else {
  399. /* 7-bit address
  400. * addr_1: addr[6:0] | (R/nW)
  401. * addr_2: dont care
  402. */
  403. addr_1 = i2c_8bit_addr_from_msg(msg);
  404. addr_2 = 0;
  405. }
  406. writel(addr_1, idev->base + MST_ADDR_1);
  407. writel(addr_2, idev->base + MST_ADDR_2);
  408. }
  409. /* The NAK interrupt will be sent _before_ issuing STOP command
  410. * so the controller might still be busy processing it. No
  411. * interrupt will be sent at the end so we have to poll for it
  412. */
  413. static int axxia_i2c_handle_seq_nak(struct axxia_i2c_dev *idev)
  414. {
  415. unsigned long timeout = jiffies + I2C_XFER_TIMEOUT;
  416. do {
  417. if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
  418. return 0;
  419. usleep_range(1, 100);
  420. } while (time_before(jiffies, timeout));
  421. return -ETIMEDOUT;
  422. }
  423. static int axxia_i2c_xfer_seq(struct axxia_i2c_dev *idev, struct i2c_msg msgs[])
  424. {
  425. u32 int_mask = MST_STATUS_ERR | MST_STATUS_SS | MST_STATUS_RFL;
  426. u32 rlen = i2c_m_recv_len(&msgs[1]) ? I2C_SMBUS_BLOCK_MAX : msgs[1].len;
  427. unsigned long time_left;
  428. axxia_i2c_set_addr(idev, &msgs[0]);
  429. writel(msgs[0].len, idev->base + MST_TX_XFER);
  430. writel(rlen, idev->base + MST_RX_XFER);
  431. idev->msg = &msgs[0];
  432. idev->msg_r = &msgs[1];
  433. idev->msg_xfrd = 0;
  434. idev->msg_xfrd_r = 0;
  435. idev->last = true;
  436. axxia_i2c_fill_tx_fifo(idev);
  437. writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
  438. reinit_completion(&idev->msg_complete);
  439. i2c_int_enable(idev, int_mask);
  440. time_left = wait_for_completion_timeout(&idev->msg_complete,
  441. I2C_XFER_TIMEOUT);
  442. if (idev->msg_err == -ENXIO) {
  443. if (axxia_i2c_handle_seq_nak(idev))
  444. axxia_i2c_init(idev);
  445. } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
  446. dev_warn(idev->dev, "busy after xfer\n");
  447. }
  448. if (time_left == 0) {
  449. idev->msg_err = -ETIMEDOUT;
  450. i2c_recover_bus(&idev->adapter);
  451. axxia_i2c_init(idev);
  452. }
  453. if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
  454. axxia_i2c_init(idev);
  455. return idev->msg_err;
  456. }
  457. static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg,
  458. bool last)
  459. {
  460. u32 int_mask = MST_STATUS_ERR;
  461. u32 rx_xfer, tx_xfer;
  462. unsigned long time_left;
  463. unsigned int wt_value;
  464. idev->msg = msg;
  465. idev->msg_r = msg;
  466. idev->msg_xfrd = 0;
  467. idev->msg_xfrd_r = 0;
  468. idev->last = last;
  469. reinit_completion(&idev->msg_complete);
  470. axxia_i2c_set_addr(idev, msg);
  471. if (i2c_m_rd(msg)) {
  472. /* I2C read transfer */
  473. rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
  474. tx_xfer = 0;
  475. } else {
  476. /* I2C write transfer */
  477. rx_xfer = 0;
  478. tx_xfer = msg->len;
  479. }
  480. writel(rx_xfer, idev->base + MST_RX_XFER);
  481. writel(tx_xfer, idev->base + MST_TX_XFER);
  482. if (i2c_m_rd(msg))
  483. int_mask |= MST_STATUS_RFL;
  484. else if (axxia_i2c_fill_tx_fifo(idev) != 0)
  485. int_mask |= MST_STATUS_TFL;
  486. wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
  487. /* Disable wait timer temporarly */
  488. writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
  489. /* Check if timeout error happened */
  490. if (idev->msg_err)
  491. goto out;
  492. if (!last) {
  493. writel(CMD_MANUAL, idev->base + MST_COMMAND);
  494. int_mask |= MST_STATUS_SNS;
  495. } else {
  496. writel(CMD_AUTO, idev->base + MST_COMMAND);
  497. int_mask |= MST_STATUS_SS;
  498. }
  499. writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
  500. i2c_int_enable(idev, int_mask);
  501. time_left = wait_for_completion_timeout(&idev->msg_complete,
  502. I2C_XFER_TIMEOUT);
  503. i2c_int_disable(idev, int_mask);
  504. if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
  505. dev_warn(idev->dev, "busy after xfer\n");
  506. if (time_left == 0) {
  507. idev->msg_err = -ETIMEDOUT;
  508. i2c_recover_bus(&idev->adapter);
  509. axxia_i2c_init(idev);
  510. }
  511. out:
  512. if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO &&
  513. idev->msg_err != -ETIMEDOUT)
  514. axxia_i2c_init(idev);
  515. return idev->msg_err;
  516. }
  517. /* This function checks if the msgs[] array contains messages compatible with
  518. * Sequence mode of operation. This mode assumes there will be exactly one
  519. * write of non-zero length followed by exactly one read of non-zero length,
  520. * both targeted at the same client device.
  521. */
  522. static bool axxia_i2c_sequence_ok(struct i2c_msg msgs[], int num)
  523. {
  524. return num == SEQ_LEN && !i2c_m_rd(&msgs[0]) && i2c_m_rd(&msgs[1]) &&
  525. msgs[0].len > 0 && msgs[0].len <= FIFO_SIZE &&
  526. msgs[1].len > 0 && msgs[0].addr == msgs[1].addr;
  527. }
  528. static int
  529. axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
  530. {
  531. struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
  532. int i;
  533. int ret = 0;
  534. idev->msg_err = 0;
  535. if (axxia_i2c_sequence_ok(msgs, num)) {
  536. ret = axxia_i2c_xfer_seq(idev, msgs);
  537. return ret ? : SEQ_LEN;
  538. }
  539. i2c_int_enable(idev, MST_STATUS_TSS);
  540. for (i = 0; ret == 0 && i < num; ++i)
  541. ret = axxia_i2c_xfer_msg(idev, &msgs[i], i == (num - 1));
  542. return ret ? : i;
  543. }
  544. static int axxia_i2c_get_scl(struct i2c_adapter *adap)
  545. {
  546. struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
  547. return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
  548. }
  549. static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
  550. {
  551. struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
  552. u32 tmp;
  553. /* Preserve SDA Control */
  554. tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
  555. if (!val)
  556. tmp |= BM_SCLC;
  557. writel(tmp, idev->base + I2C_BUS_MONITOR);
  558. }
  559. static int axxia_i2c_get_sda(struct i2c_adapter *adap)
  560. {
  561. struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
  562. return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
  563. }
  564. static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
  565. .recover_bus = i2c_generic_scl_recovery,
  566. .get_scl = axxia_i2c_get_scl,
  567. .set_scl = axxia_i2c_set_scl,
  568. .get_sda = axxia_i2c_get_sda,
  569. };
  570. static u32 axxia_i2c_func(struct i2c_adapter *adap)
  571. {
  572. u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
  573. I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
  574. return caps;
  575. }
  576. static int axxia_i2c_reg_slave(struct i2c_client *slave)
  577. {
  578. struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
  579. u32 slv_int_mask = SLV_STATUS_RFH;
  580. u32 dec_ctl;
  581. if (idev->slave)
  582. return -EBUSY;
  583. idev->slave = slave;
  584. /* Enable slave mode as well */
  585. writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
  586. writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
  587. /* Set slave address */
  588. dec_ctl = SLV_ADDR_DEC_SA1E;
  589. if (slave->flags & I2C_CLIENT_TEN)
  590. dec_ctl |= SLV_ADDR_DEC_SA1M;
  591. writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
  592. writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
  593. writel(slave->addr, idev->base + SLV_ADDR_1);
  594. /* Enable interrupts */
  595. slv_int_mask |= SLV_STATUS_SRS1 | SLV_STATUS_SRRS1 | SLV_STATUS_SRND1;
  596. slv_int_mask |= SLV_STATUS_SRC1;
  597. writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
  598. return 0;
  599. }
  600. static int axxia_i2c_unreg_slave(struct i2c_client *slave)
  601. {
  602. struct axxia_i2c_dev *idev = i2c_get_adapdata(slave->adapter);
  603. /* Disable slave mode */
  604. writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
  605. writel(INT_MST, idev->base + INTERRUPT_ENABLE);
  606. synchronize_irq(idev->irq);
  607. idev->slave = NULL;
  608. return 0;
  609. }
  610. static const struct i2c_algorithm axxia_i2c_algo = {
  611. .master_xfer = axxia_i2c_xfer,
  612. .functionality = axxia_i2c_func,
  613. .reg_slave = axxia_i2c_reg_slave,
  614. .unreg_slave = axxia_i2c_unreg_slave,
  615. };
  616. static const struct i2c_adapter_quirks axxia_i2c_quirks = {
  617. .max_read_len = 255,
  618. .max_write_len = 255,
  619. };
  620. static int axxia_i2c_probe(struct platform_device *pdev)
  621. {
  622. struct device_node *np = pdev->dev.of_node;
  623. struct axxia_i2c_dev *idev = NULL;
  624. void __iomem *base;
  625. int ret = 0;
  626. idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
  627. if (!idev)
  628. return -ENOMEM;
  629. base = devm_platform_ioremap_resource(pdev, 0);
  630. if (IS_ERR(base))
  631. return PTR_ERR(base);
  632. idev->irq = platform_get_irq(pdev, 0);
  633. if (idev->irq < 0)
  634. return idev->irq;
  635. idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
  636. if (IS_ERR(idev->i2c_clk)) {
  637. dev_err(&pdev->dev, "missing clock\n");
  638. return PTR_ERR(idev->i2c_clk);
  639. }
  640. idev->base = base;
  641. idev->dev = &pdev->dev;
  642. init_completion(&idev->msg_complete);
  643. of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
  644. if (idev->bus_clk_rate == 0)
  645. idev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; /* default clock rate */
  646. ret = clk_prepare_enable(idev->i2c_clk);
  647. if (ret) {
  648. dev_err(&pdev->dev, "failed to enable clock\n");
  649. return ret;
  650. }
  651. ret = axxia_i2c_init(idev);
  652. if (ret) {
  653. dev_err(&pdev->dev, "failed to initialize\n");
  654. goto error_disable_clk;
  655. }
  656. ret = devm_request_irq(&pdev->dev, idev->irq, axxia_i2c_isr, 0,
  657. pdev->name, idev);
  658. if (ret) {
  659. dev_err(&pdev->dev, "failed to claim IRQ%d\n", idev->irq);
  660. goto error_disable_clk;
  661. }
  662. i2c_set_adapdata(&idev->adapter, idev);
  663. strscpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
  664. idev->adapter.owner = THIS_MODULE;
  665. idev->adapter.algo = &axxia_i2c_algo;
  666. idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
  667. idev->adapter.quirks = &axxia_i2c_quirks;
  668. idev->adapter.dev.parent = &pdev->dev;
  669. idev->adapter.dev.of_node = pdev->dev.of_node;
  670. platform_set_drvdata(pdev, idev);
  671. ret = i2c_add_adapter(&idev->adapter);
  672. if (ret)
  673. goto error_disable_clk;
  674. return 0;
  675. error_disable_clk:
  676. clk_disable_unprepare(idev->i2c_clk);
  677. return ret;
  678. }
  679. static int axxia_i2c_remove(struct platform_device *pdev)
  680. {
  681. struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
  682. clk_disable_unprepare(idev->i2c_clk);
  683. i2c_del_adapter(&idev->adapter);
  684. return 0;
  685. }
  686. /* Match table for of_platform binding */
  687. static const struct of_device_id axxia_i2c_of_match[] = {
  688. { .compatible = "lsi,api2c", },
  689. {},
  690. };
  691. MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
  692. static struct platform_driver axxia_i2c_driver = {
  693. .probe = axxia_i2c_probe,
  694. .remove = axxia_i2c_remove,
  695. .driver = {
  696. .name = "axxia-i2c",
  697. .of_match_table = axxia_i2c_of_match,
  698. },
  699. };
  700. module_platform_driver(axxia_i2c_driver);
  701. MODULE_DESCRIPTION("Axxia I2C Bus driver");
  702. MODULE_AUTHOR("Anders Berg <[email protected]>");
  703. MODULE_LICENSE("GPL v2");