i2c-amd756.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. Copyright (c) 1999-2002 Merlin Hughes <[email protected]>
  4. Shamelessly ripped from i2c-piix4.c:
  5. Copyright (c) 1998, 1999 Frodo Looijaard <[email protected]> and
  6. Philip Edelbrock <[email protected]>
  7. */
  8. /*
  9. 2002-04-08: Added nForce support. (Csaba Halasz)
  10. 2002-10-03: Fixed nForce PnP I/O port. (Michael Steil)
  11. 2002-12-28: Rewritten into something that resembles a Linux driver (hch)
  12. 2003-11-29: Added back AMD8111 removed by the previous rewrite.
  13. (Philip Pokorny)
  14. */
  15. /*
  16. Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce
  17. Note: we assume there can only be one device, with one SMBus interface.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/pci.h>
  21. #include <linux/kernel.h>
  22. #include <linux/delay.h>
  23. #include <linux/stddef.h>
  24. #include <linux/ioport.h>
  25. #include <linux/i2c.h>
  26. #include <linux/acpi.h>
  27. #include <linux/io.h>
  28. /* AMD756 SMBus address offsets */
  29. #define SMB_ADDR_OFFSET 0xE0
  30. #define SMB_IOSIZE 16
  31. #define SMB_GLOBAL_STATUS (0x0 + amd756_ioport)
  32. #define SMB_GLOBAL_ENABLE (0x2 + amd756_ioport)
  33. #define SMB_HOST_ADDRESS (0x4 + amd756_ioport)
  34. #define SMB_HOST_DATA (0x6 + amd756_ioport)
  35. #define SMB_HOST_COMMAND (0x8 + amd756_ioport)
  36. #define SMB_HOST_BLOCK_DATA (0x9 + amd756_ioport)
  37. #define SMB_HAS_DATA (0xA + amd756_ioport)
  38. #define SMB_HAS_DEVICE_ADDRESS (0xC + amd756_ioport)
  39. #define SMB_HAS_HOST_ADDRESS (0xE + amd756_ioport)
  40. #define SMB_SNOOP_ADDRESS (0xF + amd756_ioport)
  41. /* PCI Address Constants */
  42. /* address of I/O space */
  43. #define SMBBA 0x058 /* mh */
  44. #define SMBBANFORCE 0x014
  45. /* general configuration */
  46. #define SMBGCFG 0x041 /* mh */
  47. /* silicon revision code */
  48. #define SMBREV 0x008
  49. /* Other settings */
  50. #define MAX_TIMEOUT 500
  51. /* AMD756 constants */
  52. #define AMD756_QUICK 0x00
  53. #define AMD756_BYTE 0x01
  54. #define AMD756_BYTE_DATA 0x02
  55. #define AMD756_WORD_DATA 0x03
  56. #define AMD756_PROCESS_CALL 0x04
  57. #define AMD756_BLOCK_DATA 0x05
  58. static struct pci_driver amd756_driver;
  59. static unsigned short amd756_ioport;
  60. /*
  61. SMBUS event = I/O 28-29 bit 11
  62. see E0 for the status bits and enabled in E2
  63. */
  64. #define GS_ABRT_STS (1 << 0)
  65. #define GS_COL_STS (1 << 1)
  66. #define GS_PRERR_STS (1 << 2)
  67. #define GS_HST_STS (1 << 3)
  68. #define GS_HCYC_STS (1 << 4)
  69. #define GS_TO_STS (1 << 5)
  70. #define GS_SMB_STS (1 << 11)
  71. #define GS_CLEAR_STS (GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \
  72. GS_HCYC_STS | GS_TO_STS )
  73. #define GE_CYC_TYPE_MASK (7)
  74. #define GE_HOST_STC (1 << 3)
  75. #define GE_ABORT (1 << 5)
  76. static int amd756_transaction(struct i2c_adapter *adap)
  77. {
  78. int temp;
  79. int result = 0;
  80. int timeout = 0;
  81. dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
  82. "DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
  83. inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
  84. inb_p(SMB_HOST_DATA));
  85. /* Make sure the SMBus host is ready to start transmitting */
  86. if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) {
  87. dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
  88. do {
  89. msleep(1);
  90. temp = inw_p(SMB_GLOBAL_STATUS);
  91. } while ((temp & (GS_HST_STS | GS_SMB_STS)) &&
  92. (timeout++ < MAX_TIMEOUT));
  93. /* If the SMBus is still busy, we give up */
  94. if (timeout > MAX_TIMEOUT) {
  95. dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
  96. goto abort;
  97. }
  98. timeout = 0;
  99. }
  100. /* start the transaction by setting the start bit */
  101. outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE);
  102. /* We will always wait for a fraction of a second! */
  103. do {
  104. msleep(1);
  105. temp = inw_p(SMB_GLOBAL_STATUS);
  106. } while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));
  107. /* If the SMBus is still busy, we give up */
  108. if (timeout > MAX_TIMEOUT) {
  109. dev_dbg(&adap->dev, "Completion timeout!\n");
  110. goto abort;
  111. }
  112. if (temp & GS_PRERR_STS) {
  113. result = -ENXIO;
  114. dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
  115. }
  116. if (temp & GS_COL_STS) {
  117. result = -EIO;
  118. dev_warn(&adap->dev, "SMBus collision!\n");
  119. }
  120. if (temp & GS_TO_STS) {
  121. result = -ETIMEDOUT;
  122. dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
  123. }
  124. if (temp & GS_HCYC_STS)
  125. dev_dbg(&adap->dev, "SMBus protocol success!\n");
  126. outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
  127. #ifdef DEBUG
  128. if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
  129. dev_dbg(&adap->dev,
  130. "Failed reset at end of transaction (%04x)\n", temp);
  131. }
  132. #endif
  133. dev_dbg(&adap->dev,
  134. "Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
  135. inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
  136. inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));
  137. return result;
  138. abort:
  139. dev_warn(&adap->dev, "Sending abort\n");
  140. outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE);
  141. msleep(100);
  142. outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
  143. return -EIO;
  144. }
  145. /* Return negative errno on error. */
  146. static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
  147. unsigned short flags, char read_write,
  148. u8 command, int size, union i2c_smbus_data * data)
  149. {
  150. int i, len;
  151. int status;
  152. switch (size) {
  153. case I2C_SMBUS_QUICK:
  154. outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
  155. SMB_HOST_ADDRESS);
  156. size = AMD756_QUICK;
  157. break;
  158. case I2C_SMBUS_BYTE:
  159. outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
  160. SMB_HOST_ADDRESS);
  161. if (read_write == I2C_SMBUS_WRITE)
  162. outb_p(command, SMB_HOST_DATA);
  163. size = AMD756_BYTE;
  164. break;
  165. case I2C_SMBUS_BYTE_DATA:
  166. outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
  167. SMB_HOST_ADDRESS);
  168. outb_p(command, SMB_HOST_COMMAND);
  169. if (read_write == I2C_SMBUS_WRITE)
  170. outw_p(data->byte, SMB_HOST_DATA);
  171. size = AMD756_BYTE_DATA;
  172. break;
  173. case I2C_SMBUS_WORD_DATA:
  174. outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
  175. SMB_HOST_ADDRESS);
  176. outb_p(command, SMB_HOST_COMMAND);
  177. if (read_write == I2C_SMBUS_WRITE)
  178. outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */
  179. size = AMD756_WORD_DATA;
  180. break;
  181. case I2C_SMBUS_BLOCK_DATA:
  182. outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
  183. SMB_HOST_ADDRESS);
  184. outb_p(command, SMB_HOST_COMMAND);
  185. if (read_write == I2C_SMBUS_WRITE) {
  186. len = data->block[0];
  187. if (len < 0)
  188. len = 0;
  189. if (len > 32)
  190. len = 32;
  191. outw_p(len, SMB_HOST_DATA);
  192. /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
  193. for (i = 1; i <= len; i++)
  194. outb_p(data->block[i],
  195. SMB_HOST_BLOCK_DATA);
  196. }
  197. size = AMD756_BLOCK_DATA;
  198. break;
  199. default:
  200. dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
  201. return -EOPNOTSUPP;
  202. }
  203. /* How about enabling interrupts... */
  204. outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
  205. status = amd756_transaction(adap);
  206. if (status)
  207. return status;
  208. if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
  209. return 0;
  210. switch (size) {
  211. case AMD756_BYTE:
  212. data->byte = inw_p(SMB_HOST_DATA);
  213. break;
  214. case AMD756_BYTE_DATA:
  215. data->byte = inw_p(SMB_HOST_DATA);
  216. break;
  217. case AMD756_WORD_DATA:
  218. data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */
  219. break;
  220. case AMD756_BLOCK_DATA:
  221. data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
  222. if(data->block[0] > 32)
  223. data->block[0] = 32;
  224. /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
  225. for (i = 1; i <= data->block[0]; i++)
  226. data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
  227. break;
  228. }
  229. return 0;
  230. }
  231. static u32 amd756_func(struct i2c_adapter *adapter)
  232. {
  233. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  234. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  235. I2C_FUNC_SMBUS_BLOCK_DATA;
  236. }
  237. static const struct i2c_algorithm smbus_algorithm = {
  238. .smbus_xfer = amd756_access,
  239. .functionality = amd756_func,
  240. };
  241. struct i2c_adapter amd756_smbus = {
  242. .owner = THIS_MODULE,
  243. .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
  244. .algo = &smbus_algorithm,
  245. };
  246. enum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 };
  247. static const char* chipname[] = {
  248. "AMD756", "AMD766", "AMD768",
  249. "nVidia nForce", "AMD8111",
  250. };
  251. static const struct pci_device_id amd756_ids[] = {
  252. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
  253. .driver_data = AMD756 },
  254. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
  255. .driver_data = AMD766 },
  256. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443),
  257. .driver_data = AMD768 },
  258. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS),
  259. .driver_data = AMD8111 },
  260. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS),
  261. .driver_data = NFORCE },
  262. { 0, }
  263. };
  264. MODULE_DEVICE_TABLE (pci, amd756_ids);
  265. static int amd756_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  266. {
  267. int nforce = (id->driver_data == NFORCE);
  268. int error;
  269. u8 temp;
  270. if (amd756_ioport) {
  271. dev_err(&pdev->dev, "Only one device supported "
  272. "(you have a strange motherboard, btw)\n");
  273. return -ENODEV;
  274. }
  275. if (nforce) {
  276. if (PCI_FUNC(pdev->devfn) != 1)
  277. return -ENODEV;
  278. pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport);
  279. amd756_ioport &= 0xfffc;
  280. } else { /* amd */
  281. if (PCI_FUNC(pdev->devfn) != 3)
  282. return -ENODEV;
  283. pci_read_config_byte(pdev, SMBGCFG, &temp);
  284. if ((temp & 128) == 0) {
  285. dev_err(&pdev->dev,
  286. "Error: SMBus controller I/O not enabled!\n");
  287. return -ENODEV;
  288. }
  289. /* Determine the address of the SMBus areas */
  290. /* Technically it is a dword but... */
  291. pci_read_config_word(pdev, SMBBA, &amd756_ioport);
  292. amd756_ioport &= 0xff00;
  293. amd756_ioport += SMB_ADDR_OFFSET;
  294. }
  295. error = acpi_check_region(amd756_ioport, SMB_IOSIZE,
  296. amd756_driver.name);
  297. if (error)
  298. return -ENODEV;
  299. if (!request_region(amd756_ioport, SMB_IOSIZE, amd756_driver.name)) {
  300. dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
  301. amd756_ioport);
  302. return -ENODEV;
  303. }
  304. pci_read_config_byte(pdev, SMBREV, &temp);
  305. dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
  306. dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport);
  307. /* set up the sysfs linkage to our parent device */
  308. amd756_smbus.dev.parent = &pdev->dev;
  309. snprintf(amd756_smbus.name, sizeof(amd756_smbus.name),
  310. "SMBus %s adapter at %04x", chipname[id->driver_data],
  311. amd756_ioport);
  312. error = i2c_add_adapter(&amd756_smbus);
  313. if (error)
  314. goto out_err;
  315. return 0;
  316. out_err:
  317. release_region(amd756_ioport, SMB_IOSIZE);
  318. return error;
  319. }
  320. static void amd756_remove(struct pci_dev *dev)
  321. {
  322. i2c_del_adapter(&amd756_smbus);
  323. release_region(amd756_ioport, SMB_IOSIZE);
  324. }
  325. static struct pci_driver amd756_driver = {
  326. .name = "amd756_smbus",
  327. .id_table = amd756_ids,
  328. .probe = amd756_probe,
  329. .remove = amd756_remove,
  330. };
  331. module_pci_driver(amd756_driver);
  332. MODULE_AUTHOR("Merlin Hughes <[email protected]>");
  333. MODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver");
  334. MODULE_LICENSE("GPL");
  335. EXPORT_SYMBOL(amd756_smbus);