hisi_ptt.h 6.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Driver for HiSilicon PCIe tune and trace device
  4. *
  5. * Copyright (c) 2022 HiSilicon Technologies Co., Ltd.
  6. * Author: Yicong Yang <[email protected]>
  7. */
  8. #ifndef _HISI_PTT_H
  9. #define _HISI_PTT_H
  10. #include <linux/bits.h>
  11. #include <linux/cpumask.h>
  12. #include <linux/list.h>
  13. #include <linux/mutex.h>
  14. #include <linux/pci.h>
  15. #include <linux/perf_event.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/types.h>
  18. #define DRV_NAME "hisi_ptt"
  19. /*
  20. * The definition of the device registers and register fields.
  21. */
  22. #define HISI_PTT_TUNING_CTRL 0x0000
  23. #define HISI_PTT_TUNING_CTRL_CODE GENMASK(15, 0)
  24. #define HISI_PTT_TUNING_CTRL_SUB GENMASK(23, 16)
  25. #define HISI_PTT_TUNING_DATA 0x0004
  26. #define HISI_PTT_TUNING_DATA_VAL_MASK GENMASK(15, 0)
  27. #define HISI_PTT_TRACE_ADDR_SIZE 0x0800
  28. #define HISI_PTT_TRACE_ADDR_BASE_LO_0 0x0810
  29. #define HISI_PTT_TRACE_ADDR_BASE_HI_0 0x0814
  30. #define HISI_PTT_TRACE_ADDR_STRIDE 0x8
  31. #define HISI_PTT_TRACE_CTRL 0x0850
  32. #define HISI_PTT_TRACE_CTRL_EN BIT(0)
  33. #define HISI_PTT_TRACE_CTRL_RST BIT(1)
  34. #define HISI_PTT_TRACE_CTRL_RXTX_SEL GENMASK(3, 2)
  35. #define HISI_PTT_TRACE_CTRL_TYPE_SEL GENMASK(7, 4)
  36. #define HISI_PTT_TRACE_CTRL_DATA_FORMAT BIT(14)
  37. #define HISI_PTT_TRACE_CTRL_FILTER_MODE BIT(15)
  38. #define HISI_PTT_TRACE_CTRL_TARGET_SEL GENMASK(31, 16)
  39. #define HISI_PTT_TRACE_INT_STAT 0x0890
  40. #define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0)
  41. #define HISI_PTT_TRACE_INT_MASK 0x0894
  42. #define HISI_PTT_TUNING_INT_STAT 0x0898
  43. #define HISI_PTT_TUNING_INT_STAT_MASK BIT(0)
  44. #define HISI_PTT_TRACE_WR_STS 0x08a0
  45. #define HISI_PTT_TRACE_WR_STS_WRITE GENMASK(27, 0)
  46. #define HISI_PTT_TRACE_WR_STS_BUFFER GENMASK(29, 28)
  47. #define HISI_PTT_TRACE_STS 0x08b0
  48. #define HISI_PTT_TRACE_IDLE BIT(0)
  49. #define HISI_PTT_DEVICE_RANGE 0x0fe0
  50. #define HISI_PTT_DEVICE_RANGE_UPPER GENMASK(31, 16)
  51. #define HISI_PTT_DEVICE_RANGE_LOWER GENMASK(15, 0)
  52. #define HISI_PTT_LOCATION 0x0fe8
  53. #define HISI_PTT_CORE_ID GENMASK(15, 0)
  54. #define HISI_PTT_SICL_ID GENMASK(31, 16)
  55. /* Parameters of PTT trace DMA part. */
  56. #define HISI_PTT_TRACE_DMA_IRQ 0
  57. #define HISI_PTT_TRACE_BUF_CNT 4
  58. #define HISI_PTT_TRACE_BUF_SIZE SZ_4M
  59. #define HISI_PTT_TRACE_TOTAL_BUF_SIZE (HISI_PTT_TRACE_BUF_SIZE * \
  60. HISI_PTT_TRACE_BUF_CNT)
  61. /* Wait time for hardware DMA to reset */
  62. #define HISI_PTT_RESET_TIMEOUT_US 10UL
  63. #define HISI_PTT_RESET_POLL_INTERVAL_US 1UL
  64. /* Poll timeout and interval for waiting hardware work to finish */
  65. #define HISI_PTT_WAIT_TUNE_TIMEOUT_US 1000000UL
  66. #define HISI_PTT_WAIT_TRACE_TIMEOUT_US 100UL
  67. #define HISI_PTT_WAIT_POLL_INTERVAL_US 10UL
  68. #define HISI_PCIE_CORE_PORT_ID(devfn) ((PCI_SLOT(devfn) & 0x7) << 1)
  69. /* Definition of the PMU configs */
  70. #define HISI_PTT_PMU_FILTER_IS_PORT BIT(19)
  71. #define HISI_PTT_PMU_FILTER_VAL_MASK GENMASK(15, 0)
  72. #define HISI_PTT_PMU_DIRECTION_MASK GENMASK(23, 20)
  73. #define HISI_PTT_PMU_TYPE_MASK GENMASK(31, 24)
  74. #define HISI_PTT_PMU_FORMAT_MASK GENMASK(35, 32)
  75. /**
  76. * struct hisi_ptt_tune_desc - Describe tune event for PTT tune
  77. * @hisi_ptt: PTT device this tune event belongs to
  78. * @name: name of this event
  79. * @event_code: code of the event
  80. */
  81. struct hisi_ptt_tune_desc {
  82. struct hisi_ptt *hisi_ptt;
  83. const char *name;
  84. u32 event_code;
  85. };
  86. /**
  87. * struct hisi_ptt_dma_buffer - Describe a single trace buffer of PTT trace.
  88. * The detail of the data format is described
  89. * in the documentation of PTT device.
  90. * @dma: DMA address of this buffer visible to the device
  91. * @addr: virtual address of this buffer visible to the cpu
  92. */
  93. struct hisi_ptt_dma_buffer {
  94. dma_addr_t dma;
  95. void *addr;
  96. };
  97. /**
  98. * struct hisi_ptt_trace_ctrl - Control and status of PTT trace
  99. * @trace_buf: array of the trace buffers for holding the trace data.
  100. * the length will be HISI_PTT_TRACE_BUF_CNT.
  101. * @handle: perf output handle of current trace session
  102. * @buf_index: the index of current using trace buffer
  103. * @on_cpu: current tracing cpu
  104. * @started: current trace status, true for started
  105. * @is_port: whether we're tracing root port or not
  106. * @direction: direction of the TLP headers to trace
  107. * @filter: filter value for tracing the TLP headers
  108. * @format: format of the TLP headers to trace
  109. * @type: type of the TLP headers to trace
  110. */
  111. struct hisi_ptt_trace_ctrl {
  112. struct hisi_ptt_dma_buffer *trace_buf;
  113. struct perf_output_handle handle;
  114. u32 buf_index;
  115. int on_cpu;
  116. bool started;
  117. bool is_port;
  118. u32 direction:2;
  119. u32 filter:16;
  120. u32 format:1;
  121. u32 type:4;
  122. };
  123. /**
  124. * struct hisi_ptt_filter_desc - Descriptor of the PTT trace filter
  125. * @list: entry of this descriptor in the filter list
  126. * @is_port: the PCI device of the filter is a Root Port or not
  127. * @devid: the PCI device's devid of the filter
  128. */
  129. struct hisi_ptt_filter_desc {
  130. struct list_head list;
  131. bool is_port;
  132. u16 devid;
  133. };
  134. /**
  135. * struct hisi_ptt_pmu_buf - Descriptor of the AUX buffer of PTT trace
  136. * @length: size of the AUX buffer
  137. * @nr_pages: number of pages of the AUX buffer
  138. * @base: start address of AUX buffer
  139. * @pos: position in the AUX buffer to commit traced data
  140. */
  141. struct hisi_ptt_pmu_buf {
  142. size_t length;
  143. int nr_pages;
  144. void *base;
  145. long pos;
  146. };
  147. /**
  148. * struct hisi_ptt - Per PTT device data
  149. * @trace_ctrl: the control information of PTT trace
  150. * @hotplug_node: node for register cpu hotplug event
  151. * @hisi_ptt_pmu: the pum device of trace
  152. * @iobase: base IO address of the device
  153. * @pdev: pci_dev of this PTT device
  154. * @tune_lock: lock to serialize the tune process
  155. * @pmu_lock: lock to serialize the perf process
  156. * @trace_irq: interrupt number used by trace
  157. * @upper_bdf: the upper BDF range of the PCI devices managed by this PTT device
  158. * @lower_bdf: the lower BDF range of the PCI devices managed by this PTT device
  159. * @port_filters: the filter list of root ports
  160. * @req_filters: the filter list of requester ID
  161. * @port_mask: port mask of the managed root ports
  162. */
  163. struct hisi_ptt {
  164. struct hisi_ptt_trace_ctrl trace_ctrl;
  165. struct hlist_node hotplug_node;
  166. struct pmu hisi_ptt_pmu;
  167. void __iomem *iobase;
  168. struct pci_dev *pdev;
  169. struct mutex tune_lock;
  170. spinlock_t pmu_lock;
  171. int trace_irq;
  172. u32 upper_bdf;
  173. u32 lower_bdf;
  174. /*
  175. * The trace TLP headers can either be filtered by certain
  176. * root port, or by the requester ID. Organize the filters
  177. * by @port_filters and @req_filters here. The mask of all
  178. * the valid ports is also cached for doing sanity check
  179. * of user input.
  180. */
  181. struct list_head port_filters;
  182. struct list_head req_filters;
  183. u16 port_mask;
  184. };
  185. #define to_hisi_ptt(pmu) container_of(pmu, struct hisi_ptt, hisi_ptt_pmu)
  186. #endif /* _HISI_PTT_H */