tps23861.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2020 Sartura Ltd.
  4. *
  5. * Driver for the TI TPS23861 PoE PSE.
  6. *
  7. * Author: Robert Marko <[email protected]>
  8. */
  9. #include <linux/bitfield.h>
  10. #include <linux/debugfs.h>
  11. #include <linux/delay.h>
  12. #include <linux/hwmon-sysfs.h>
  13. #include <linux/hwmon.h>
  14. #include <linux/i2c.h>
  15. #include <linux/module.h>
  16. #include <linux/of_device.h>
  17. #include <linux/regmap.h>
  18. #define TEMPERATURE 0x2c
  19. #define INPUT_VOLTAGE_LSB 0x2e
  20. #define INPUT_VOLTAGE_MSB 0x2f
  21. #define PORT_1_CURRENT_LSB 0x30
  22. #define PORT_1_CURRENT_MSB 0x31
  23. #define PORT_1_VOLTAGE_LSB 0x32
  24. #define PORT_1_VOLTAGE_MSB 0x33
  25. #define PORT_2_CURRENT_LSB 0x34
  26. #define PORT_2_CURRENT_MSB 0x35
  27. #define PORT_2_VOLTAGE_LSB 0x36
  28. #define PORT_2_VOLTAGE_MSB 0x37
  29. #define PORT_3_CURRENT_LSB 0x38
  30. #define PORT_3_CURRENT_MSB 0x39
  31. #define PORT_3_VOLTAGE_LSB 0x3a
  32. #define PORT_3_VOLTAGE_MSB 0x3b
  33. #define PORT_4_CURRENT_LSB 0x3c
  34. #define PORT_4_CURRENT_MSB 0x3d
  35. #define PORT_4_VOLTAGE_LSB 0x3e
  36. #define PORT_4_VOLTAGE_MSB 0x3f
  37. #define PORT_N_CURRENT_LSB_OFFSET 0x04
  38. #define PORT_N_VOLTAGE_LSB_OFFSET 0x04
  39. #define VOLTAGE_CURRENT_MASK GENMASK(13, 0)
  40. #define PORT_1_RESISTANCE_LSB 0x60
  41. #define PORT_1_RESISTANCE_MSB 0x61
  42. #define PORT_2_RESISTANCE_LSB 0x62
  43. #define PORT_2_RESISTANCE_MSB 0x63
  44. #define PORT_3_RESISTANCE_LSB 0x64
  45. #define PORT_3_RESISTANCE_MSB 0x65
  46. #define PORT_4_RESISTANCE_LSB 0x66
  47. #define PORT_4_RESISTANCE_MSB 0x67
  48. #define PORT_N_RESISTANCE_LSB_OFFSET 0x02
  49. #define PORT_RESISTANCE_MASK GENMASK(13, 0)
  50. #define PORT_RESISTANCE_RSN_MASK GENMASK(15, 14)
  51. #define PORT_RESISTANCE_RSN_OTHER 0
  52. #define PORT_RESISTANCE_RSN_LOW 1
  53. #define PORT_RESISTANCE_RSN_OPEN 2
  54. #define PORT_RESISTANCE_RSN_SHORT 3
  55. #define PORT_1_STATUS 0x0c
  56. #define PORT_2_STATUS 0x0d
  57. #define PORT_3_STATUS 0x0e
  58. #define PORT_4_STATUS 0x0f
  59. #define PORT_STATUS_CLASS_MASK GENMASK(7, 4)
  60. #define PORT_STATUS_DETECT_MASK GENMASK(3, 0)
  61. #define PORT_CLASS_UNKNOWN 0
  62. #define PORT_CLASS_1 1
  63. #define PORT_CLASS_2 2
  64. #define PORT_CLASS_3 3
  65. #define PORT_CLASS_4 4
  66. #define PORT_CLASS_RESERVED 5
  67. #define PORT_CLASS_0 6
  68. #define PORT_CLASS_OVERCURRENT 7
  69. #define PORT_CLASS_MISMATCH 8
  70. #define PORT_DETECT_UNKNOWN 0
  71. #define PORT_DETECT_SHORT 1
  72. #define PORT_DETECT_RESERVED 2
  73. #define PORT_DETECT_RESISTANCE_LOW 3
  74. #define PORT_DETECT_RESISTANCE_OK 4
  75. #define PORT_DETECT_RESISTANCE_HIGH 5
  76. #define PORT_DETECT_OPEN_CIRCUIT 6
  77. #define PORT_DETECT_RESERVED_2 7
  78. #define PORT_DETECT_MOSFET_FAULT 8
  79. #define PORT_DETECT_LEGACY 9
  80. /* Measurment beyond clamp voltage */
  81. #define PORT_DETECT_CAPACITANCE_INVALID_BEYOND 10
  82. /* Insufficient voltage delta */
  83. #define PORT_DETECT_CAPACITANCE_INVALID_DELTA 11
  84. #define PORT_DETECT_CAPACITANCE_OUT_OF_RANGE 12
  85. #define POE_PLUS 0x40
  86. #define OPERATING_MODE 0x12
  87. #define OPERATING_MODE_OFF 0
  88. #define OPERATING_MODE_MANUAL 1
  89. #define OPERATING_MODE_SEMI 2
  90. #define OPERATING_MODE_AUTO 3
  91. #define OPERATING_MODE_PORT_1_MASK GENMASK(1, 0)
  92. #define OPERATING_MODE_PORT_2_MASK GENMASK(3, 2)
  93. #define OPERATING_MODE_PORT_3_MASK GENMASK(5, 4)
  94. #define OPERATING_MODE_PORT_4_MASK GENMASK(7, 6)
  95. #define DETECT_CLASS_RESTART 0x18
  96. #define POWER_ENABLE 0x19
  97. #define TPS23861_NUM_PORTS 4
  98. #define TPS23861_GENERAL_MASK_1 0x17
  99. #define TPS23861_CURRENT_SHUNT_MASK BIT(0)
  100. #define TEMPERATURE_LSB 652 /* 0.652 degrees Celsius */
  101. #define VOLTAGE_LSB 3662 /* 3.662 mV */
  102. #define SHUNT_RESISTOR_DEFAULT 255000 /* 255 mOhm */
  103. #define CURRENT_LSB_250 62260 /* 62.260 uA */
  104. #define CURRENT_LSB_255 61039 /* 61.039 uA */
  105. #define RESISTANCE_LSB 110966 /* 11.0966 Ohm*/
  106. #define RESISTANCE_LSB_LOW 157216 /* 15.7216 Ohm*/
  107. struct tps23861_data {
  108. struct regmap *regmap;
  109. u32 shunt_resistor;
  110. struct i2c_client *client;
  111. struct dentry *debugfs_dir;
  112. };
  113. static struct regmap_config tps23861_regmap_config = {
  114. .reg_bits = 8,
  115. .val_bits = 8,
  116. .max_register = 0x6f,
  117. };
  118. static int tps23861_read_temp(struct tps23861_data *data, long *val)
  119. {
  120. unsigned int regval;
  121. int err;
  122. err = regmap_read(data->regmap, TEMPERATURE, &regval);
  123. if (err < 0)
  124. return err;
  125. *val = (regval * TEMPERATURE_LSB) - 20000;
  126. return 0;
  127. }
  128. static int tps23861_read_voltage(struct tps23861_data *data, int channel,
  129. long *val)
  130. {
  131. __le16 regval;
  132. long raw_val;
  133. int err;
  134. if (channel < TPS23861_NUM_PORTS) {
  135. err = regmap_bulk_read(data->regmap,
  136. PORT_1_VOLTAGE_LSB + channel * PORT_N_VOLTAGE_LSB_OFFSET,
  137. &regval, 2);
  138. } else {
  139. err = regmap_bulk_read(data->regmap,
  140. INPUT_VOLTAGE_LSB,
  141. &regval, 2);
  142. }
  143. if (err < 0)
  144. return err;
  145. raw_val = le16_to_cpu(regval);
  146. *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, raw_val) * VOLTAGE_LSB) / 1000;
  147. return 0;
  148. }
  149. static int tps23861_read_current(struct tps23861_data *data, int channel,
  150. long *val)
  151. {
  152. long raw_val, current_lsb;
  153. __le16 regval;
  154. int err;
  155. if (data->shunt_resistor == SHUNT_RESISTOR_DEFAULT)
  156. current_lsb = CURRENT_LSB_255;
  157. else
  158. current_lsb = CURRENT_LSB_250;
  159. err = regmap_bulk_read(data->regmap,
  160. PORT_1_CURRENT_LSB + channel * PORT_N_CURRENT_LSB_OFFSET,
  161. &regval, 2);
  162. if (err < 0)
  163. return err;
  164. raw_val = le16_to_cpu(regval);
  165. *val = (FIELD_GET(VOLTAGE_CURRENT_MASK, raw_val) * current_lsb) / 1000000;
  166. return 0;
  167. }
  168. static int tps23861_port_disable(struct tps23861_data *data, int channel)
  169. {
  170. unsigned int regval = 0;
  171. int err;
  172. regval |= BIT(channel + 4);
  173. err = regmap_write(data->regmap, POWER_ENABLE, regval);
  174. return err;
  175. }
  176. static int tps23861_port_enable(struct tps23861_data *data, int channel)
  177. {
  178. unsigned int regval = 0;
  179. int err;
  180. regval |= BIT(channel);
  181. regval |= BIT(channel + 4);
  182. err = regmap_write(data->regmap, DETECT_CLASS_RESTART, regval);
  183. return err;
  184. }
  185. static umode_t tps23861_is_visible(const void *data, enum hwmon_sensor_types type,
  186. u32 attr, int channel)
  187. {
  188. switch (type) {
  189. case hwmon_temp:
  190. switch (attr) {
  191. case hwmon_temp_input:
  192. case hwmon_temp_label:
  193. return 0444;
  194. default:
  195. return 0;
  196. }
  197. case hwmon_in:
  198. switch (attr) {
  199. case hwmon_in_input:
  200. case hwmon_in_label:
  201. return 0444;
  202. case hwmon_in_enable:
  203. return 0200;
  204. default:
  205. return 0;
  206. }
  207. case hwmon_curr:
  208. switch (attr) {
  209. case hwmon_curr_input:
  210. case hwmon_curr_label:
  211. return 0444;
  212. default:
  213. return 0;
  214. }
  215. default:
  216. return 0;
  217. }
  218. }
  219. static int tps23861_write(struct device *dev, enum hwmon_sensor_types type,
  220. u32 attr, int channel, long val)
  221. {
  222. struct tps23861_data *data = dev_get_drvdata(dev);
  223. int err;
  224. switch (type) {
  225. case hwmon_in:
  226. switch (attr) {
  227. case hwmon_in_enable:
  228. if (val == 0)
  229. err = tps23861_port_disable(data, channel);
  230. else if (val == 1)
  231. err = tps23861_port_enable(data, channel);
  232. else
  233. err = -EINVAL;
  234. break;
  235. default:
  236. return -EOPNOTSUPP;
  237. }
  238. break;
  239. default:
  240. return -EOPNOTSUPP;
  241. }
  242. return err;
  243. }
  244. static int tps23861_read(struct device *dev, enum hwmon_sensor_types type,
  245. u32 attr, int channel, long *val)
  246. {
  247. struct tps23861_data *data = dev_get_drvdata(dev);
  248. int err;
  249. switch (type) {
  250. case hwmon_temp:
  251. switch (attr) {
  252. case hwmon_temp_input:
  253. err = tps23861_read_temp(data, val);
  254. break;
  255. default:
  256. return -EOPNOTSUPP;
  257. }
  258. break;
  259. case hwmon_in:
  260. switch (attr) {
  261. case hwmon_in_input:
  262. err = tps23861_read_voltage(data, channel, val);
  263. break;
  264. default:
  265. return -EOPNOTSUPP;
  266. }
  267. break;
  268. case hwmon_curr:
  269. switch (attr) {
  270. case hwmon_curr_input:
  271. err = tps23861_read_current(data, channel, val);
  272. break;
  273. default:
  274. return -EOPNOTSUPP;
  275. }
  276. break;
  277. default:
  278. return -EOPNOTSUPP;
  279. }
  280. return err;
  281. }
  282. static const char * const tps23861_port_label[] = {
  283. "Port1",
  284. "Port2",
  285. "Port3",
  286. "Port4",
  287. "Input",
  288. };
  289. static int tps23861_read_string(struct device *dev,
  290. enum hwmon_sensor_types type,
  291. u32 attr, int channel, const char **str)
  292. {
  293. switch (type) {
  294. case hwmon_in:
  295. case hwmon_curr:
  296. *str = tps23861_port_label[channel];
  297. break;
  298. case hwmon_temp:
  299. *str = "Die";
  300. break;
  301. default:
  302. return -EOPNOTSUPP;
  303. }
  304. return 0;
  305. }
  306. static const struct hwmon_channel_info *tps23861_info[] = {
  307. HWMON_CHANNEL_INFO(chip,
  308. HWMON_C_REGISTER_TZ),
  309. HWMON_CHANNEL_INFO(temp,
  310. HWMON_T_INPUT | HWMON_T_LABEL),
  311. HWMON_CHANNEL_INFO(in,
  312. HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
  313. HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
  314. HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
  315. HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL,
  316. HWMON_I_INPUT | HWMON_I_LABEL),
  317. HWMON_CHANNEL_INFO(curr,
  318. HWMON_C_INPUT | HWMON_C_LABEL,
  319. HWMON_C_INPUT | HWMON_C_LABEL,
  320. HWMON_C_INPUT | HWMON_C_LABEL,
  321. HWMON_C_INPUT | HWMON_C_LABEL),
  322. NULL
  323. };
  324. static const struct hwmon_ops tps23861_hwmon_ops = {
  325. .is_visible = tps23861_is_visible,
  326. .write = tps23861_write,
  327. .read = tps23861_read,
  328. .read_string = tps23861_read_string,
  329. };
  330. static const struct hwmon_chip_info tps23861_chip_info = {
  331. .ops = &tps23861_hwmon_ops,
  332. .info = tps23861_info,
  333. };
  334. static char *port_operating_mode_string(uint8_t mode_reg, unsigned int port)
  335. {
  336. unsigned int mode = ~0;
  337. if (port < TPS23861_NUM_PORTS)
  338. mode = (mode_reg >> (2 * port)) & OPERATING_MODE_PORT_1_MASK;
  339. switch (mode) {
  340. case OPERATING_MODE_OFF:
  341. return "Off";
  342. case OPERATING_MODE_MANUAL:
  343. return "Manual";
  344. case OPERATING_MODE_SEMI:
  345. return "Semi-Auto";
  346. case OPERATING_MODE_AUTO:
  347. return "Auto";
  348. default:
  349. return "Invalid";
  350. }
  351. }
  352. static char *port_detect_status_string(uint8_t status_reg)
  353. {
  354. switch (FIELD_GET(PORT_STATUS_DETECT_MASK, status_reg)) {
  355. case PORT_DETECT_UNKNOWN:
  356. return "Unknown device";
  357. case PORT_DETECT_SHORT:
  358. return "Short circuit";
  359. case PORT_DETECT_RESISTANCE_LOW:
  360. return "Too low resistance";
  361. case PORT_DETECT_RESISTANCE_OK:
  362. return "Valid resistance";
  363. case PORT_DETECT_RESISTANCE_HIGH:
  364. return "Too high resistance";
  365. case PORT_DETECT_OPEN_CIRCUIT:
  366. return "Open circuit";
  367. case PORT_DETECT_MOSFET_FAULT:
  368. return "MOSFET fault";
  369. case PORT_DETECT_LEGACY:
  370. return "Legacy device";
  371. case PORT_DETECT_CAPACITANCE_INVALID_BEYOND:
  372. return "Invalid capacitance, beyond clamp voltage";
  373. case PORT_DETECT_CAPACITANCE_INVALID_DELTA:
  374. return "Invalid capacitance, insufficient voltage delta";
  375. case PORT_DETECT_CAPACITANCE_OUT_OF_RANGE:
  376. return "Valid capacitance, outside of legacy range";
  377. case PORT_DETECT_RESERVED:
  378. case PORT_DETECT_RESERVED_2:
  379. default:
  380. return "Invalid";
  381. }
  382. }
  383. static char *port_class_status_string(uint8_t status_reg)
  384. {
  385. switch (FIELD_GET(PORT_STATUS_CLASS_MASK, status_reg)) {
  386. case PORT_CLASS_UNKNOWN:
  387. return "Unknown";
  388. case PORT_CLASS_RESERVED:
  389. case PORT_CLASS_0:
  390. return "0";
  391. case PORT_CLASS_1:
  392. return "1";
  393. case PORT_CLASS_2:
  394. return "2";
  395. case PORT_CLASS_3:
  396. return "3";
  397. case PORT_CLASS_4:
  398. return "4";
  399. case PORT_CLASS_OVERCURRENT:
  400. return "Overcurrent";
  401. case PORT_CLASS_MISMATCH:
  402. return "Mismatch";
  403. default:
  404. return "Invalid";
  405. }
  406. }
  407. static char *port_poe_plus_status_string(uint8_t poe_plus, unsigned int port)
  408. {
  409. return (BIT(port + 4) & poe_plus) ? "Yes" : "No";
  410. }
  411. static int tps23861_port_resistance(struct tps23861_data *data, int port)
  412. {
  413. unsigned int raw_val;
  414. __le16 regval;
  415. regmap_bulk_read(data->regmap,
  416. PORT_1_RESISTANCE_LSB + PORT_N_RESISTANCE_LSB_OFFSET * port,
  417. &regval,
  418. 2);
  419. raw_val = le16_to_cpu(regval);
  420. switch (FIELD_GET(PORT_RESISTANCE_RSN_MASK, raw_val)) {
  421. case PORT_RESISTANCE_RSN_OTHER:
  422. return (FIELD_GET(PORT_RESISTANCE_MASK, raw_val) * RESISTANCE_LSB) / 10000;
  423. case PORT_RESISTANCE_RSN_LOW:
  424. return (FIELD_GET(PORT_RESISTANCE_MASK, raw_val) * RESISTANCE_LSB_LOW) / 10000;
  425. case PORT_RESISTANCE_RSN_SHORT:
  426. case PORT_RESISTANCE_RSN_OPEN:
  427. default:
  428. return 0;
  429. }
  430. }
  431. static int tps23861_port_status_show(struct seq_file *s, void *data)
  432. {
  433. struct tps23861_data *priv = s->private;
  434. unsigned int i, mode, poe_plus, status;
  435. regmap_read(priv->regmap, OPERATING_MODE, &mode);
  436. regmap_read(priv->regmap, POE_PLUS, &poe_plus);
  437. for (i = 0; i < TPS23861_NUM_PORTS; i++) {
  438. regmap_read(priv->regmap, PORT_1_STATUS + i, &status);
  439. seq_printf(s, "Port: \t\t%d\n", i + 1);
  440. seq_printf(s, "Operating mode: %s\n", port_operating_mode_string(mode, i));
  441. seq_printf(s, "Detected: \t%s\n", port_detect_status_string(status));
  442. seq_printf(s, "Class: \t\t%s\n", port_class_status_string(status));
  443. seq_printf(s, "PoE Plus: \t%s\n", port_poe_plus_status_string(poe_plus, i));
  444. seq_printf(s, "Resistance: \t%d\n", tps23861_port_resistance(priv, i));
  445. seq_putc(s, '\n');
  446. }
  447. return 0;
  448. }
  449. DEFINE_SHOW_ATTRIBUTE(tps23861_port_status);
  450. static void tps23861_init_debugfs(struct tps23861_data *data,
  451. struct device *hwmon_dev)
  452. {
  453. const char *debugfs_name;
  454. debugfs_name = devm_kasprintf(&data->client->dev, GFP_KERNEL, "%s-%s",
  455. data->client->name, dev_name(hwmon_dev));
  456. if (!debugfs_name)
  457. return;
  458. data->debugfs_dir = debugfs_create_dir(debugfs_name, NULL);
  459. debugfs_create_file("port_status",
  460. 0400,
  461. data->debugfs_dir,
  462. data,
  463. &tps23861_port_status_fops);
  464. }
  465. static int tps23861_probe(struct i2c_client *client)
  466. {
  467. struct device *dev = &client->dev;
  468. struct tps23861_data *data;
  469. struct device *hwmon_dev;
  470. u32 shunt_resistor;
  471. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  472. if (!data)
  473. return -ENOMEM;
  474. data->client = client;
  475. i2c_set_clientdata(client, data);
  476. data->regmap = devm_regmap_init_i2c(client, &tps23861_regmap_config);
  477. if (IS_ERR(data->regmap)) {
  478. dev_err(dev, "failed to allocate register map\n");
  479. return PTR_ERR(data->regmap);
  480. }
  481. if (!of_property_read_u32(dev->of_node, "shunt-resistor-micro-ohms", &shunt_resistor))
  482. data->shunt_resistor = shunt_resistor;
  483. else
  484. data->shunt_resistor = SHUNT_RESISTOR_DEFAULT;
  485. if (data->shunt_resistor == SHUNT_RESISTOR_DEFAULT)
  486. regmap_clear_bits(data->regmap,
  487. TPS23861_GENERAL_MASK_1,
  488. TPS23861_CURRENT_SHUNT_MASK);
  489. else
  490. regmap_set_bits(data->regmap,
  491. TPS23861_GENERAL_MASK_1,
  492. TPS23861_CURRENT_SHUNT_MASK);
  493. hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
  494. data, &tps23861_chip_info,
  495. NULL);
  496. if (IS_ERR(hwmon_dev))
  497. return PTR_ERR(hwmon_dev);
  498. tps23861_init_debugfs(data, hwmon_dev);
  499. return 0;
  500. }
  501. static void tps23861_remove(struct i2c_client *client)
  502. {
  503. struct tps23861_data *data = i2c_get_clientdata(client);
  504. debugfs_remove_recursive(data->debugfs_dir);
  505. }
  506. static const struct of_device_id __maybe_unused tps23861_of_match[] = {
  507. { .compatible = "ti,tps23861", },
  508. { },
  509. };
  510. MODULE_DEVICE_TABLE(of, tps23861_of_match);
  511. static struct i2c_driver tps23861_driver = {
  512. .probe_new = tps23861_probe,
  513. .remove = tps23861_remove,
  514. .driver = {
  515. .name = "tps23861",
  516. .of_match_table = of_match_ptr(tps23861_of_match),
  517. },
  518. };
  519. module_i2c_driver(tps23861_driver);
  520. MODULE_LICENSE("GPL");
  521. MODULE_AUTHOR("Robert Marko <[email protected]>");
  522. MODULE_DESCRIPTION("TI TPS23861 PoE PSE");