tmp401.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /* tmp401.c
  3. *
  4. * Copyright (C) 2007,2008 Hans de Goede <[email protected]>
  5. * Preliminary tmp411 support by:
  6. * Gabriel Konat, Sander Leget, Wouter Willems
  7. * Copyright (C) 2009 Andre Prendel <[email protected]>
  8. *
  9. * Cleanup and support for TMP431 and TMP432 by Guenter Roeck
  10. * Copyright (c) 2013 Guenter Roeck <[email protected]>
  11. */
  12. /*
  13. * Driver for the Texas Instruments TMP401 SMBUS temperature sensor IC.
  14. *
  15. * Note this IC is in some aspect similar to the LM90, but it has quite a
  16. * few differences too, for example the local temp has a higher resolution
  17. * and thus has 16 bits registers for its value and limit instead of 8 bits.
  18. */
  19. #include <linux/bitops.h>
  20. #include <linux/err.h>
  21. #include <linux/i2c.h>
  22. #include <linux/hwmon.h>
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/mutex.h>
  26. #include <linux/regmap.h>
  27. #include <linux/slab.h>
  28. /* Addresses to scan */
  29. static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4c, 0x4d,
  30. 0x4e, 0x4f, I2C_CLIENT_END };
  31. enum chips { tmp401, tmp411, tmp431, tmp432, tmp435 };
  32. /*
  33. * The TMP401 registers, note some registers have different addresses for
  34. * reading and writing
  35. */
  36. #define TMP401_STATUS 0x02
  37. #define TMP401_CONFIG 0x03
  38. #define TMP401_CONVERSION_RATE 0x04
  39. #define TMP4XX_N_FACTOR_REG 0x18
  40. #define TMP43X_BETA_RANGE 0x25
  41. #define TMP401_TEMP_CRIT_HYST 0x21
  42. #define TMP401_MANUFACTURER_ID_REG 0xFE
  43. #define TMP401_DEVICE_ID_REG 0xFF
  44. static const u8 TMP401_TEMP_MSB[7][3] = {
  45. { 0x00, 0x01, 0x23 }, /* temp */
  46. { 0x06, 0x08, 0x16 }, /* low limit */
  47. { 0x05, 0x07, 0x15 }, /* high limit */
  48. { 0x20, 0x19, 0x1a }, /* therm (crit) limit */
  49. { 0x30, 0x34, 0x00 }, /* lowest */
  50. { 0x32, 0xf6, 0x00 }, /* highest */
  51. };
  52. /* [0] = fault, [1] = low, [2] = high, [3] = therm/crit */
  53. static const u8 TMP432_STATUS_REG[] = {
  54. 0x1b, 0x36, 0x35, 0x37 };
  55. /* Flags */
  56. #define TMP401_CONFIG_RANGE BIT(2)
  57. #define TMP401_CONFIG_SHUTDOWN BIT(6)
  58. #define TMP401_STATUS_LOCAL_CRIT BIT(0)
  59. #define TMP401_STATUS_REMOTE_CRIT BIT(1)
  60. #define TMP401_STATUS_REMOTE_OPEN BIT(2)
  61. #define TMP401_STATUS_REMOTE_LOW BIT(3)
  62. #define TMP401_STATUS_REMOTE_HIGH BIT(4)
  63. #define TMP401_STATUS_LOCAL_LOW BIT(5)
  64. #define TMP401_STATUS_LOCAL_HIGH BIT(6)
  65. /* On TMP432, each status has its own register */
  66. #define TMP432_STATUS_LOCAL BIT(0)
  67. #define TMP432_STATUS_REMOTE1 BIT(1)
  68. #define TMP432_STATUS_REMOTE2 BIT(2)
  69. /* Manufacturer / Device ID's */
  70. #define TMP401_MANUFACTURER_ID 0x55
  71. #define TMP401_DEVICE_ID 0x11
  72. #define TMP411A_DEVICE_ID 0x12
  73. #define TMP411B_DEVICE_ID 0x13
  74. #define TMP411C_DEVICE_ID 0x10
  75. #define TMP431_DEVICE_ID 0x31
  76. #define TMP432_DEVICE_ID 0x32
  77. #define TMP435_DEVICE_ID 0x35
  78. /*
  79. * Driver data (common to all clients)
  80. */
  81. static const struct i2c_device_id tmp401_id[] = {
  82. { "tmp401", tmp401 },
  83. { "tmp411", tmp411 },
  84. { "tmp431", tmp431 },
  85. { "tmp432", tmp432 },
  86. { "tmp435", tmp435 },
  87. { }
  88. };
  89. MODULE_DEVICE_TABLE(i2c, tmp401_id);
  90. /*
  91. * Client data (each client gets its own)
  92. */
  93. struct tmp401_data {
  94. struct i2c_client *client;
  95. struct regmap *regmap;
  96. struct mutex update_lock;
  97. enum chips kind;
  98. bool extended_range;
  99. /* hwmon API configuration data */
  100. u32 chip_channel_config[4];
  101. struct hwmon_channel_info chip_info;
  102. u32 temp_channel_config[4];
  103. struct hwmon_channel_info temp_info;
  104. const struct hwmon_channel_info *info[3];
  105. struct hwmon_chip_info chip;
  106. };
  107. /* regmap */
  108. static bool tmp401_regmap_is_volatile(struct device *dev, unsigned int reg)
  109. {
  110. switch (reg) {
  111. case 0: /* local temp msb */
  112. case 1: /* remote temp msb */
  113. case 2: /* status */
  114. case 0x10: /* remote temp lsb */
  115. case 0x15: /* local temp lsb */
  116. case 0x1b: /* status (tmp432) */
  117. case 0x23 ... 0x24: /* remote temp 2 msb / lsb */
  118. case 0x30 ... 0x37: /* lowest/highest temp; status (tmp432) */
  119. return true;
  120. default:
  121. return false;
  122. }
  123. }
  124. static int tmp401_reg_read(void *context, unsigned int reg, unsigned int *val)
  125. {
  126. struct tmp401_data *data = context;
  127. struct i2c_client *client = data->client;
  128. int regval;
  129. switch (reg) {
  130. case 0: /* local temp msb */
  131. case 1: /* remote temp msb */
  132. case 5: /* local temp high limit msb */
  133. case 6: /* local temp low limit msb */
  134. case 7: /* remote temp ligh limit msb */
  135. case 8: /* remote temp low limit msb */
  136. case 0x15: /* remote temp 2 high limit msb */
  137. case 0x16: /* remote temp 2 low limit msb */
  138. case 0x23: /* remote temp 2 msb */
  139. case 0x30: /* local temp minimum, tmp411 */
  140. case 0x32: /* local temp maximum, tmp411 */
  141. case 0x34: /* remote temp minimum, tmp411 */
  142. case 0xf6: /* remote temp maximum, tmp411 (really 0x36) */
  143. /* work around register overlap between TMP411 and TMP432 */
  144. if (reg == 0xf6)
  145. reg = 0x36;
  146. regval = i2c_smbus_read_word_swapped(client, reg);
  147. if (regval < 0)
  148. return regval;
  149. *val = regval;
  150. break;
  151. case 0x19: /* critical limits, 8-bit registers */
  152. case 0x1a:
  153. case 0x20:
  154. regval = i2c_smbus_read_byte_data(client, reg);
  155. if (regval < 0)
  156. return regval;
  157. *val = regval << 8;
  158. break;
  159. case 0x1b:
  160. case 0x35 ... 0x37:
  161. if (data->kind == tmp432) {
  162. regval = i2c_smbus_read_byte_data(client, reg);
  163. if (regval < 0)
  164. return regval;
  165. *val = regval;
  166. break;
  167. }
  168. /* simulate TMP432 status registers */
  169. regval = i2c_smbus_read_byte_data(client, TMP401_STATUS);
  170. if (regval < 0)
  171. return regval;
  172. *val = 0;
  173. switch (reg) {
  174. case 0x1b: /* open / fault */
  175. if (regval & TMP401_STATUS_REMOTE_OPEN)
  176. *val |= BIT(1);
  177. break;
  178. case 0x35: /* high limit */
  179. if (regval & TMP401_STATUS_LOCAL_HIGH)
  180. *val |= BIT(0);
  181. if (regval & TMP401_STATUS_REMOTE_HIGH)
  182. *val |= BIT(1);
  183. break;
  184. case 0x36: /* low limit */
  185. if (regval & TMP401_STATUS_LOCAL_LOW)
  186. *val |= BIT(0);
  187. if (regval & TMP401_STATUS_REMOTE_LOW)
  188. *val |= BIT(1);
  189. break;
  190. case 0x37: /* therm / crit limit */
  191. if (regval & TMP401_STATUS_LOCAL_CRIT)
  192. *val |= BIT(0);
  193. if (regval & TMP401_STATUS_REMOTE_CRIT)
  194. *val |= BIT(1);
  195. break;
  196. }
  197. break;
  198. default:
  199. regval = i2c_smbus_read_byte_data(client, reg);
  200. if (regval < 0)
  201. return regval;
  202. *val = regval;
  203. break;
  204. }
  205. return 0;
  206. }
  207. static int tmp401_reg_write(void *context, unsigned int reg, unsigned int val)
  208. {
  209. struct tmp401_data *data = context;
  210. struct i2c_client *client = data->client;
  211. switch (reg) {
  212. case 0x05: /* local temp high limit msb */
  213. case 0x06: /* local temp low limit msb */
  214. case 0x07: /* remote temp ligh limit msb */
  215. case 0x08: /* remote temp low limit msb */
  216. reg += 6; /* adjust for register write address */
  217. fallthrough;
  218. case 0x15: /* remote temp 2 high limit msb */
  219. case 0x16: /* remote temp 2 low limit msb */
  220. return i2c_smbus_write_word_swapped(client, reg, val);
  221. case 0x19: /* critical limits, 8-bit registers */
  222. case 0x1a:
  223. case 0x20:
  224. return i2c_smbus_write_byte_data(client, reg, val >> 8);
  225. case TMP401_CONVERSION_RATE:
  226. case TMP401_CONFIG:
  227. reg += 6; /* adjust for register write address */
  228. fallthrough;
  229. default:
  230. return i2c_smbus_write_byte_data(client, reg, val);
  231. }
  232. }
  233. static const struct regmap_config tmp401_regmap_config = {
  234. .reg_bits = 8,
  235. .val_bits = 16,
  236. .cache_type = REGCACHE_RBTREE,
  237. .volatile_reg = tmp401_regmap_is_volatile,
  238. .reg_read = tmp401_reg_read,
  239. .reg_write = tmp401_reg_write,
  240. };
  241. /* temperature conversion */
  242. static int tmp401_register_to_temp(u16 reg, bool extended)
  243. {
  244. int temp = reg;
  245. if (extended)
  246. temp -= 64 * 256;
  247. return DIV_ROUND_CLOSEST(temp * 125, 32);
  248. }
  249. static u16 tmp401_temp_to_register(long temp, bool extended, int zbits)
  250. {
  251. if (extended) {
  252. temp = clamp_val(temp, -64000, 191000);
  253. temp += 64000;
  254. } else {
  255. temp = clamp_val(temp, 0, 127000);
  256. }
  257. return DIV_ROUND_CLOSEST(temp * (1 << (8 - zbits)), 1000) << zbits;
  258. }
  259. /* hwmon API functions */
  260. static const u8 tmp401_temp_reg_index[] = {
  261. [hwmon_temp_input] = 0,
  262. [hwmon_temp_min] = 1,
  263. [hwmon_temp_max] = 2,
  264. [hwmon_temp_crit] = 3,
  265. [hwmon_temp_lowest] = 4,
  266. [hwmon_temp_highest] = 5,
  267. };
  268. static const u8 tmp401_status_reg_index[] = {
  269. [hwmon_temp_fault] = 0,
  270. [hwmon_temp_min_alarm] = 1,
  271. [hwmon_temp_max_alarm] = 2,
  272. [hwmon_temp_crit_alarm] = 3,
  273. };
  274. static int tmp401_temp_read(struct device *dev, u32 attr, int channel, long *val)
  275. {
  276. struct tmp401_data *data = dev_get_drvdata(dev);
  277. struct regmap *regmap = data->regmap;
  278. unsigned int regval;
  279. int reg, ret;
  280. switch (attr) {
  281. case hwmon_temp_input:
  282. case hwmon_temp_min:
  283. case hwmon_temp_max:
  284. case hwmon_temp_crit:
  285. case hwmon_temp_lowest:
  286. case hwmon_temp_highest:
  287. reg = TMP401_TEMP_MSB[tmp401_temp_reg_index[attr]][channel];
  288. ret = regmap_read(regmap, reg, &regval);
  289. if (ret < 0)
  290. return ret;
  291. *val = tmp401_register_to_temp(regval, data->extended_range);
  292. break;
  293. case hwmon_temp_crit_hyst:
  294. mutex_lock(&data->update_lock);
  295. reg = TMP401_TEMP_MSB[3][channel];
  296. ret = regmap_read(regmap, reg, &regval);
  297. if (ret < 0)
  298. goto unlock;
  299. *val = tmp401_register_to_temp(regval, data->extended_range);
  300. ret = regmap_read(regmap, TMP401_TEMP_CRIT_HYST, &regval);
  301. if (ret < 0)
  302. goto unlock;
  303. *val -= regval * 1000;
  304. unlock:
  305. mutex_unlock(&data->update_lock);
  306. if (ret < 0)
  307. return ret;
  308. break;
  309. case hwmon_temp_fault:
  310. case hwmon_temp_min_alarm:
  311. case hwmon_temp_max_alarm:
  312. case hwmon_temp_crit_alarm:
  313. reg = TMP432_STATUS_REG[tmp401_status_reg_index[attr]];
  314. ret = regmap_read(regmap, reg, &regval);
  315. if (ret < 0)
  316. return ret;
  317. *val = !!(regval & BIT(channel));
  318. break;
  319. default:
  320. return -EOPNOTSUPP;
  321. }
  322. return 0;
  323. }
  324. static int tmp401_temp_write(struct device *dev, u32 attr, int channel,
  325. long val)
  326. {
  327. struct tmp401_data *data = dev_get_drvdata(dev);
  328. struct regmap *regmap = data->regmap;
  329. unsigned int regval;
  330. int reg, ret, temp;
  331. mutex_lock(&data->update_lock);
  332. switch (attr) {
  333. case hwmon_temp_min:
  334. case hwmon_temp_max:
  335. case hwmon_temp_crit:
  336. reg = TMP401_TEMP_MSB[tmp401_temp_reg_index[attr]][channel];
  337. regval = tmp401_temp_to_register(val, data->extended_range,
  338. attr == hwmon_temp_crit ? 8 : 4);
  339. ret = regmap_write(regmap, reg, regval);
  340. break;
  341. case hwmon_temp_crit_hyst:
  342. if (data->extended_range)
  343. val = clamp_val(val, -64000, 191000);
  344. else
  345. val = clamp_val(val, 0, 127000);
  346. reg = TMP401_TEMP_MSB[3][channel];
  347. ret = regmap_read(regmap, reg, &regval);
  348. if (ret < 0)
  349. break;
  350. temp = tmp401_register_to_temp(regval, data->extended_range);
  351. val = clamp_val(val, temp - 255000, temp);
  352. regval = ((temp - val) + 500) / 1000;
  353. ret = regmap_write(regmap, TMP401_TEMP_CRIT_HYST, regval);
  354. break;
  355. default:
  356. ret = -EOPNOTSUPP;
  357. break;
  358. }
  359. mutex_unlock(&data->update_lock);
  360. return ret;
  361. }
  362. static int tmp401_chip_read(struct device *dev, u32 attr, int channel, long *val)
  363. {
  364. struct tmp401_data *data = dev_get_drvdata(dev);
  365. u32 regval;
  366. int ret;
  367. switch (attr) {
  368. case hwmon_chip_update_interval:
  369. ret = regmap_read(data->regmap, TMP401_CONVERSION_RATE, &regval);
  370. if (ret < 0)
  371. return ret;
  372. *val = (1 << (7 - regval)) * 125;
  373. break;
  374. case hwmon_chip_temp_reset_history:
  375. *val = 0;
  376. break;
  377. default:
  378. return -EOPNOTSUPP;
  379. }
  380. return 0;
  381. }
  382. static int tmp401_set_convrate(struct regmap *regmap, long val)
  383. {
  384. int rate;
  385. /*
  386. * For valid rates, interval can be calculated as
  387. * interval = (1 << (7 - rate)) * 125;
  388. * Rounded rate is therefore
  389. * rate = 7 - __fls(interval * 4 / (125 * 3));
  390. * Use clamp_val() to avoid overflows, and to ensure valid input
  391. * for __fls.
  392. */
  393. val = clamp_val(val, 125, 16000);
  394. rate = 7 - __fls(val * 4 / (125 * 3));
  395. return regmap_write(regmap, TMP401_CONVERSION_RATE, rate);
  396. }
  397. static int tmp401_chip_write(struct device *dev, u32 attr, int channel, long val)
  398. {
  399. struct tmp401_data *data = dev_get_drvdata(dev);
  400. struct regmap *regmap = data->regmap;
  401. int err;
  402. mutex_lock(&data->update_lock);
  403. switch (attr) {
  404. case hwmon_chip_update_interval:
  405. err = tmp401_set_convrate(regmap, val);
  406. break;
  407. case hwmon_chip_temp_reset_history:
  408. if (val != 1) {
  409. err = -EINVAL;
  410. break;
  411. }
  412. /*
  413. * Reset history by writing any value to any of the
  414. * minimum/maximum registers (0x30-0x37).
  415. */
  416. err = regmap_write(regmap, 0x30, 0);
  417. break;
  418. default:
  419. err = -EOPNOTSUPP;
  420. break;
  421. }
  422. mutex_unlock(&data->update_lock);
  423. return err;
  424. }
  425. static int tmp401_read(struct device *dev, enum hwmon_sensor_types type,
  426. u32 attr, int channel, long *val)
  427. {
  428. switch (type) {
  429. case hwmon_chip:
  430. return tmp401_chip_read(dev, attr, channel, val);
  431. case hwmon_temp:
  432. return tmp401_temp_read(dev, attr, channel, val);
  433. default:
  434. return -EOPNOTSUPP;
  435. }
  436. }
  437. static int tmp401_write(struct device *dev, enum hwmon_sensor_types type,
  438. u32 attr, int channel, long val)
  439. {
  440. switch (type) {
  441. case hwmon_chip:
  442. return tmp401_chip_write(dev, attr, channel, val);
  443. case hwmon_temp:
  444. return tmp401_temp_write(dev, attr, channel, val);
  445. default:
  446. return -EOPNOTSUPP;
  447. }
  448. }
  449. static umode_t tmp401_is_visible(const void *data, enum hwmon_sensor_types type,
  450. u32 attr, int channel)
  451. {
  452. switch (type) {
  453. case hwmon_chip:
  454. switch (attr) {
  455. case hwmon_chip_update_interval:
  456. case hwmon_chip_temp_reset_history:
  457. return 0644;
  458. default:
  459. break;
  460. }
  461. break;
  462. case hwmon_temp:
  463. switch (attr) {
  464. case hwmon_temp_input:
  465. case hwmon_temp_min_alarm:
  466. case hwmon_temp_max_alarm:
  467. case hwmon_temp_crit_alarm:
  468. case hwmon_temp_fault:
  469. case hwmon_temp_lowest:
  470. case hwmon_temp_highest:
  471. return 0444;
  472. case hwmon_temp_min:
  473. case hwmon_temp_max:
  474. case hwmon_temp_crit:
  475. case hwmon_temp_crit_hyst:
  476. return 0644;
  477. default:
  478. break;
  479. }
  480. break;
  481. default:
  482. break;
  483. }
  484. return 0;
  485. }
  486. static const struct hwmon_ops tmp401_ops = {
  487. .is_visible = tmp401_is_visible,
  488. .read = tmp401_read,
  489. .write = tmp401_write,
  490. };
  491. /* chip initialization, detect, probe */
  492. static int tmp401_init_client(struct tmp401_data *data)
  493. {
  494. struct regmap *regmap = data->regmap;
  495. u32 config, config_orig;
  496. int ret;
  497. u32 val = 0;
  498. s32 nfactor = 0;
  499. /* Set conversion rate to 2 Hz */
  500. ret = regmap_write(regmap, TMP401_CONVERSION_RATE, 5);
  501. if (ret < 0)
  502. return ret;
  503. /* Start conversions (disable shutdown if necessary) */
  504. ret = regmap_read(regmap, TMP401_CONFIG, &config);
  505. if (ret < 0)
  506. return ret;
  507. config_orig = config;
  508. config &= ~TMP401_CONFIG_SHUTDOWN;
  509. if (of_property_read_bool(data->client->dev.of_node, "ti,extended-range-enable")) {
  510. /* Enable measurement over extended temperature range */
  511. config |= TMP401_CONFIG_RANGE;
  512. }
  513. data->extended_range = !!(config & TMP401_CONFIG_RANGE);
  514. if (config != config_orig) {
  515. ret = regmap_write(regmap, TMP401_CONFIG, config);
  516. if (ret < 0)
  517. return ret;
  518. }
  519. ret = of_property_read_u32(data->client->dev.of_node, "ti,n-factor", &nfactor);
  520. if (!ret) {
  521. if (data->kind == tmp401) {
  522. dev_err(&data->client->dev, "ti,tmp401 does not support n-factor correction\n");
  523. return -EINVAL;
  524. }
  525. if (nfactor < -128 || nfactor > 127) {
  526. dev_err(&data->client->dev, "n-factor is invalid (%d)\n", nfactor);
  527. return -EINVAL;
  528. }
  529. ret = regmap_write(regmap, TMP4XX_N_FACTOR_REG, (unsigned int)nfactor);
  530. if (ret < 0)
  531. return ret;
  532. }
  533. ret = of_property_read_u32(data->client->dev.of_node, "ti,beta-compensation", &val);
  534. if (!ret) {
  535. if (data->kind == tmp401 || data->kind == tmp411) {
  536. dev_err(&data->client->dev, "ti,tmp401 or ti,tmp411 does not support beta compensation\n");
  537. return -EINVAL;
  538. }
  539. if (val > 15) {
  540. dev_err(&data->client->dev, "beta-compensation is invalid (%u)\n", val);
  541. return -EINVAL;
  542. }
  543. ret = regmap_write(regmap, TMP43X_BETA_RANGE, val);
  544. if (ret < 0)
  545. return ret;
  546. }
  547. return 0;
  548. }
  549. static int tmp401_detect(struct i2c_client *client,
  550. struct i2c_board_info *info)
  551. {
  552. enum chips kind;
  553. struct i2c_adapter *adapter = client->adapter;
  554. u8 reg;
  555. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  556. return -ENODEV;
  557. /* Detect and identify the chip */
  558. reg = i2c_smbus_read_byte_data(client, TMP401_MANUFACTURER_ID_REG);
  559. if (reg != TMP401_MANUFACTURER_ID)
  560. return -ENODEV;
  561. reg = i2c_smbus_read_byte_data(client, TMP401_DEVICE_ID_REG);
  562. switch (reg) {
  563. case TMP401_DEVICE_ID:
  564. if (client->addr != 0x4c)
  565. return -ENODEV;
  566. kind = tmp401;
  567. break;
  568. case TMP411A_DEVICE_ID:
  569. if (client->addr != 0x4c)
  570. return -ENODEV;
  571. kind = tmp411;
  572. break;
  573. case TMP411B_DEVICE_ID:
  574. if (client->addr != 0x4d)
  575. return -ENODEV;
  576. kind = tmp411;
  577. break;
  578. case TMP411C_DEVICE_ID:
  579. if (client->addr != 0x4e)
  580. return -ENODEV;
  581. kind = tmp411;
  582. break;
  583. case TMP431_DEVICE_ID:
  584. if (client->addr != 0x4c && client->addr != 0x4d)
  585. return -ENODEV;
  586. kind = tmp431;
  587. break;
  588. case TMP432_DEVICE_ID:
  589. if (client->addr != 0x4c && client->addr != 0x4d)
  590. return -ENODEV;
  591. kind = tmp432;
  592. break;
  593. case TMP435_DEVICE_ID:
  594. kind = tmp435;
  595. break;
  596. default:
  597. return -ENODEV;
  598. }
  599. reg = i2c_smbus_read_byte_data(client, TMP401_CONFIG);
  600. if (reg & 0x1b)
  601. return -ENODEV;
  602. reg = i2c_smbus_read_byte_data(client, TMP401_CONVERSION_RATE);
  603. /* Datasheet says: 0x1-0x6 */
  604. if (reg > 15)
  605. return -ENODEV;
  606. strscpy(info->type, tmp401_id[kind].name, I2C_NAME_SIZE);
  607. return 0;
  608. }
  609. static int tmp401_probe(struct i2c_client *client)
  610. {
  611. static const char * const names[] = {
  612. "TMP401", "TMP411", "TMP431", "TMP432", "TMP435"
  613. };
  614. struct device *dev = &client->dev;
  615. struct hwmon_channel_info *info;
  616. struct device *hwmon_dev;
  617. struct tmp401_data *data;
  618. int status;
  619. data = devm_kzalloc(dev, sizeof(struct tmp401_data), GFP_KERNEL);
  620. if (!data)
  621. return -ENOMEM;
  622. data->client = client;
  623. mutex_init(&data->update_lock);
  624. data->kind = i2c_match_id(tmp401_id, client)->driver_data;
  625. data->regmap = devm_regmap_init(dev, NULL, data, &tmp401_regmap_config);
  626. if (IS_ERR(data->regmap))
  627. return PTR_ERR(data->regmap);
  628. /* initialize configuration data */
  629. data->chip.ops = &tmp401_ops;
  630. data->chip.info = data->info;
  631. data->info[0] = &data->chip_info;
  632. data->info[1] = &data->temp_info;
  633. info = &data->chip_info;
  634. info->type = hwmon_chip;
  635. info->config = data->chip_channel_config;
  636. data->chip_channel_config[0] = HWMON_C_UPDATE_INTERVAL;
  637. info = &data->temp_info;
  638. info->type = hwmon_temp;
  639. info->config = data->temp_channel_config;
  640. data->temp_channel_config[0] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
  641. HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
  642. HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM;
  643. data->temp_channel_config[1] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
  644. HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
  645. HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT;
  646. if (data->kind == tmp411) {
  647. data->temp_channel_config[0] |= HWMON_T_HIGHEST | HWMON_T_LOWEST;
  648. data->temp_channel_config[1] |= HWMON_T_HIGHEST | HWMON_T_LOWEST;
  649. data->chip_channel_config[0] |= HWMON_C_TEMP_RESET_HISTORY;
  650. }
  651. if (data->kind == tmp432) {
  652. data->temp_channel_config[2] = HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
  653. HWMON_T_CRIT | HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
  654. HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM | HWMON_T_FAULT;
  655. }
  656. /* Initialize the TMP401 chip */
  657. status = tmp401_init_client(data);
  658. if (status < 0)
  659. return status;
  660. hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, data,
  661. &data->chip, NULL);
  662. if (IS_ERR(hwmon_dev))
  663. return PTR_ERR(hwmon_dev);
  664. dev_info(dev, "Detected TI %s chip\n", names[data->kind]);
  665. return 0;
  666. }
  667. static const struct of_device_id __maybe_unused tmp4xx_of_match[] = {
  668. { .compatible = "ti,tmp401", },
  669. { .compatible = "ti,tmp411", },
  670. { .compatible = "ti,tmp431", },
  671. { .compatible = "ti,tmp432", },
  672. { .compatible = "ti,tmp435", },
  673. { },
  674. };
  675. MODULE_DEVICE_TABLE(of, tmp4xx_of_match);
  676. static struct i2c_driver tmp401_driver = {
  677. .class = I2C_CLASS_HWMON,
  678. .driver = {
  679. .name = "tmp401",
  680. .of_match_table = of_match_ptr(tmp4xx_of_match),
  681. },
  682. .probe_new = tmp401_probe,
  683. .id_table = tmp401_id,
  684. .detect = tmp401_detect,
  685. .address_list = normal_i2c,
  686. };
  687. module_i2c_driver(tmp401_driver);
  688. MODULE_AUTHOR("Hans de Goede <[email protected]>");
  689. MODULE_DESCRIPTION("Texas Instruments TMP401 temperature sensor driver");
  690. MODULE_LICENSE("GPL");