nct7904.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * nct7904.c - driver for Nuvoton NCT7904D.
  4. *
  5. * Copyright (c) 2015 Kontron
  6. * Author: Vadim V. Vlasov <[email protected]>
  7. *
  8. * Copyright (c) 2019 Advantech
  9. * Author: Amy.Shih <[email protected]>
  10. *
  11. * Copyright (c) 2020 Advantech
  12. * Author: Yuechao Zhao <[email protected]>
  13. *
  14. * Supports the following chips:
  15. *
  16. * Chip #vin #fan #pwm #temp #dts chip ID
  17. * nct7904d 20 12 4 5 8 0xc5
  18. */
  19. #include <linux/module.h>
  20. #include <linux/device.h>
  21. #include <linux/init.h>
  22. #include <linux/i2c.h>
  23. #include <linux/mutex.h>
  24. #include <linux/hwmon.h>
  25. #include <linux/watchdog.h>
  26. #define VENDOR_ID_REG 0x7A /* Any bank */
  27. #define NUVOTON_ID 0x50
  28. #define CHIP_ID_REG 0x7B /* Any bank */
  29. #define NCT7904_ID 0xC5
  30. #define DEVICE_ID_REG 0x7C /* Any bank */
  31. #define BANK_SEL_REG 0xFF
  32. #define BANK_0 0x00
  33. #define BANK_1 0x01
  34. #define BANK_2 0x02
  35. #define BANK_3 0x03
  36. #define BANK_4 0x04
  37. #define BANK_MAX 0x04
  38. #define FANIN_MAX 12 /* Counted from 1 */
  39. #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB,
  40. LTD (not a voltage), VSEN17..19 */
  41. #define FANCTL_MAX 4 /* Counted from 1 */
  42. #define TCPU_MAX 8 /* Counted from 1 */
  43. #define TEMP_MAX 4 /* Counted from 1 */
  44. #define SMI_STS_MAX 10 /* Counted from 1 */
  45. #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */
  46. #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */
  47. #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */
  48. #define FANIN_CTRL0_REG 0x24
  49. #define FANIN_CTRL1_REG 0x25
  50. #define DTS_T_CTRL0_REG 0x26
  51. #define DTS_T_CTRL1_REG 0x27
  52. #define VT_ADC_MD_REG 0x2E
  53. #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
  54. #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
  55. #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
  56. #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
  57. #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */
  58. #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */
  59. #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */
  60. #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */
  61. #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */
  62. #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
  63. #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */
  64. #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */
  65. #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */
  66. #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */
  67. #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */
  68. #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */
  69. #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */
  70. #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */
  71. #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */
  72. #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */
  73. #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */
  74. #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */
  75. #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */
  76. #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */
  77. #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */
  78. #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */
  79. #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */
  80. #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */
  81. #define PRTS_REG 0x03 /* Bank 2 */
  82. #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */
  83. #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */
  84. #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */
  85. #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */
  86. #define WDT_LOCK_REG 0xE0 /* W/O Lock Watchdog Register */
  87. #define WDT_EN_REG 0xE1 /* R/O Watchdog Enable Register */
  88. #define WDT_STS_REG 0xE2 /* R/O Watchdog Status Register */
  89. #define WDT_TIMER_REG 0xE3 /* R/W Watchdog Timer Register */
  90. #define WDT_SOFT_EN 0x55 /* Enable soft watchdog timer */
  91. #define WDT_SOFT_DIS 0xAA /* Disable soft watchdog timer */
  92. #define VOLT_MONITOR_MODE 0x0
  93. #define THERMAL_DIODE_MODE 0x1
  94. #define THERMISTOR_MODE 0x3
  95. #define ENABLE_TSI BIT(1)
  96. #define WATCHDOG_TIMEOUT 1 /* 1 minute default timeout */
  97. /*The timeout range is 1-255 minutes*/
  98. #define MIN_TIMEOUT (1 * 60)
  99. #define MAX_TIMEOUT (255 * 60)
  100. static int timeout;
  101. module_param(timeout, int, 0);
  102. MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes. 1 <= timeout <= 255, default="
  103. __MODULE_STRING(WATCHDOG_TIMEOUT) ".");
  104. static bool nowayout = WATCHDOG_NOWAYOUT;
  105. module_param(nowayout, bool, 0);
  106. MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
  107. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  108. static const unsigned short normal_i2c[] = {
  109. 0x2d, 0x2e, I2C_CLIENT_END
  110. };
  111. struct nct7904_data {
  112. struct i2c_client *client;
  113. struct watchdog_device wdt;
  114. struct mutex bank_lock;
  115. int bank_sel;
  116. u32 fanin_mask;
  117. u32 vsen_mask;
  118. u32 tcpu_mask;
  119. u8 fan_mode[FANCTL_MAX];
  120. u8 enable_dts;
  121. u8 has_dts;
  122. u8 temp_mode; /* 0: TR mode, 1: TD mode */
  123. u8 fan_alarm[2];
  124. u8 vsen_alarm[3];
  125. };
  126. /* Access functions */
  127. static int nct7904_bank_lock(struct nct7904_data *data, unsigned int bank)
  128. {
  129. int ret;
  130. mutex_lock(&data->bank_lock);
  131. if (data->bank_sel == bank)
  132. return 0;
  133. ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank);
  134. if (ret == 0)
  135. data->bank_sel = bank;
  136. else
  137. data->bank_sel = -1;
  138. return ret;
  139. }
  140. static inline void nct7904_bank_release(struct nct7904_data *data)
  141. {
  142. mutex_unlock(&data->bank_lock);
  143. }
  144. /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
  145. static int nct7904_read_reg(struct nct7904_data *data,
  146. unsigned int bank, unsigned int reg)
  147. {
  148. struct i2c_client *client = data->client;
  149. int ret;
  150. ret = nct7904_bank_lock(data, bank);
  151. if (ret == 0)
  152. ret = i2c_smbus_read_byte_data(client, reg);
  153. nct7904_bank_release(data);
  154. return ret;
  155. }
  156. /*
  157. * Read 2-byte register. Returns register in big-endian format or
  158. * -ERRNO on error.
  159. */
  160. static int nct7904_read_reg16(struct nct7904_data *data,
  161. unsigned int bank, unsigned int reg)
  162. {
  163. struct i2c_client *client = data->client;
  164. int ret, hi;
  165. ret = nct7904_bank_lock(data, bank);
  166. if (ret == 0) {
  167. ret = i2c_smbus_read_byte_data(client, reg);
  168. if (ret >= 0) {
  169. hi = ret;
  170. ret = i2c_smbus_read_byte_data(client, reg + 1);
  171. if (ret >= 0)
  172. ret |= hi << 8;
  173. }
  174. }
  175. nct7904_bank_release(data);
  176. return ret;
  177. }
  178. /* Write 1-byte register. Returns 0 or -ERRNO on error. */
  179. static int nct7904_write_reg(struct nct7904_data *data,
  180. unsigned int bank, unsigned int reg, u8 val)
  181. {
  182. struct i2c_client *client = data->client;
  183. int ret;
  184. ret = nct7904_bank_lock(data, bank);
  185. if (ret == 0)
  186. ret = i2c_smbus_write_byte_data(client, reg, val);
  187. nct7904_bank_release(data);
  188. return ret;
  189. }
  190. static int nct7904_read_fan(struct device *dev, u32 attr, int channel,
  191. long *val)
  192. {
  193. struct nct7904_data *data = dev_get_drvdata(dev);
  194. unsigned int cnt, rpm;
  195. int ret;
  196. switch (attr) {
  197. case hwmon_fan_input:
  198. ret = nct7904_read_reg16(data, BANK_0,
  199. FANIN1_HV_REG + channel * 2);
  200. if (ret < 0)
  201. return ret;
  202. cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
  203. if (cnt == 0 || cnt == 0x1fff)
  204. rpm = 0;
  205. else
  206. rpm = 1350000 / cnt;
  207. *val = rpm;
  208. return 0;
  209. case hwmon_fan_min:
  210. ret = nct7904_read_reg16(data, BANK_1,
  211. FANIN1_HV_HL_REG + channel * 2);
  212. if (ret < 0)
  213. return ret;
  214. cnt = ((ret & 0xff00) >> 3) | (ret & 0x1f);
  215. if (cnt == 0 || cnt == 0x1fff)
  216. rpm = 0;
  217. else
  218. rpm = 1350000 / cnt;
  219. *val = rpm;
  220. return 0;
  221. case hwmon_fan_alarm:
  222. ret = nct7904_read_reg(data, BANK_0,
  223. SMI_STS5_REG + (channel >> 3));
  224. if (ret < 0)
  225. return ret;
  226. if (!data->fan_alarm[channel >> 3])
  227. data->fan_alarm[channel >> 3] = ret & 0xff;
  228. else
  229. /* If there is new alarm showing up */
  230. data->fan_alarm[channel >> 3] |= (ret & 0xff);
  231. *val = (data->fan_alarm[channel >> 3] >> (channel & 0x07)) & 1;
  232. /* Needs to clean the alarm if alarm existing */
  233. if (*val)
  234. data->fan_alarm[channel >> 3] ^= 1 << (channel & 0x07);
  235. return 0;
  236. default:
  237. return -EOPNOTSUPP;
  238. }
  239. }
  240. static umode_t nct7904_fan_is_visible(const void *_data, u32 attr, int channel)
  241. {
  242. const struct nct7904_data *data = _data;
  243. switch (attr) {
  244. case hwmon_fan_input:
  245. case hwmon_fan_alarm:
  246. if (data->fanin_mask & (1 << channel))
  247. return 0444;
  248. break;
  249. case hwmon_fan_min:
  250. if (data->fanin_mask & (1 << channel))
  251. return 0644;
  252. break;
  253. default:
  254. break;
  255. }
  256. return 0;
  257. }
  258. static u8 nct7904_chan_to_index[] = {
  259. 0, /* Not used */
  260. 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
  261. 18, 19, 20, 16
  262. };
  263. static int nct7904_read_in(struct device *dev, u32 attr, int channel,
  264. long *val)
  265. {
  266. struct nct7904_data *data = dev_get_drvdata(dev);
  267. int ret, volt, index;
  268. index = nct7904_chan_to_index[channel];
  269. switch (attr) {
  270. case hwmon_in_input:
  271. ret = nct7904_read_reg16(data, BANK_0,
  272. VSEN1_HV_REG + index * 2);
  273. if (ret < 0)
  274. return ret;
  275. volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
  276. if (index < 14)
  277. volt *= 2; /* 0.002V scale */
  278. else
  279. volt *= 6; /* 0.006V scale */
  280. *val = volt;
  281. return 0;
  282. case hwmon_in_min:
  283. ret = nct7904_read_reg16(data, BANK_1,
  284. VSEN1_HV_LL_REG + index * 4);
  285. if (ret < 0)
  286. return ret;
  287. volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
  288. if (index < 14)
  289. volt *= 2; /* 0.002V scale */
  290. else
  291. volt *= 6; /* 0.006V scale */
  292. *val = volt;
  293. return 0;
  294. case hwmon_in_max:
  295. ret = nct7904_read_reg16(data, BANK_1,
  296. VSEN1_HV_HL_REG + index * 4);
  297. if (ret < 0)
  298. return ret;
  299. volt = ((ret & 0xff00) >> 5) | (ret & 0x7);
  300. if (index < 14)
  301. volt *= 2; /* 0.002V scale */
  302. else
  303. volt *= 6; /* 0.006V scale */
  304. *val = volt;
  305. return 0;
  306. case hwmon_in_alarm:
  307. ret = nct7904_read_reg(data, BANK_0,
  308. SMI_STS1_REG + (index >> 3));
  309. if (ret < 0)
  310. return ret;
  311. if (!data->vsen_alarm[index >> 3])
  312. data->vsen_alarm[index >> 3] = ret & 0xff;
  313. else
  314. /* If there is new alarm showing up */
  315. data->vsen_alarm[index >> 3] |= (ret & 0xff);
  316. *val = (data->vsen_alarm[index >> 3] >> (index & 0x07)) & 1;
  317. /* Needs to clean the alarm if alarm existing */
  318. if (*val)
  319. data->vsen_alarm[index >> 3] ^= 1 << (index & 0x07);
  320. return 0;
  321. default:
  322. return -EOPNOTSUPP;
  323. }
  324. }
  325. static umode_t nct7904_in_is_visible(const void *_data, u32 attr, int channel)
  326. {
  327. const struct nct7904_data *data = _data;
  328. int index = nct7904_chan_to_index[channel];
  329. switch (attr) {
  330. case hwmon_in_input:
  331. case hwmon_in_alarm:
  332. if (channel > 0 && (data->vsen_mask & BIT(index)))
  333. return 0444;
  334. break;
  335. case hwmon_in_min:
  336. case hwmon_in_max:
  337. if (channel > 0 && (data->vsen_mask & BIT(index)))
  338. return 0644;
  339. break;
  340. default:
  341. break;
  342. }
  343. return 0;
  344. }
  345. static int nct7904_read_temp(struct device *dev, u32 attr, int channel,
  346. long *val)
  347. {
  348. struct nct7904_data *data = dev_get_drvdata(dev);
  349. int ret, temp;
  350. unsigned int reg1, reg2, reg3;
  351. s8 temps;
  352. switch (attr) {
  353. case hwmon_temp_input:
  354. if (channel == 4)
  355. ret = nct7904_read_reg16(data, BANK_0, LTD_HV_REG);
  356. else if (channel < 5)
  357. ret = nct7904_read_reg16(data, BANK_0,
  358. TEMP_CH1_HV_REG + channel * 4);
  359. else
  360. ret = nct7904_read_reg16(data, BANK_0,
  361. T_CPU1_HV_REG + (channel - 5)
  362. * 2);
  363. if (ret < 0)
  364. return ret;
  365. temp = ((ret & 0xff00) >> 5) | (ret & 0x7);
  366. *val = sign_extend32(temp, 10) * 125;
  367. return 0;
  368. case hwmon_temp_alarm:
  369. if (channel == 4) {
  370. ret = nct7904_read_reg(data, BANK_0,
  371. SMI_STS3_REG);
  372. if (ret < 0)
  373. return ret;
  374. *val = (ret >> 1) & 1;
  375. } else if (channel < 4) {
  376. ret = nct7904_read_reg(data, BANK_0,
  377. SMI_STS1_REG);
  378. if (ret < 0)
  379. return ret;
  380. *val = (ret >> (((channel * 2) + 1) & 0x07)) & 1;
  381. } else {
  382. if ((channel - 5) < 4) {
  383. ret = nct7904_read_reg(data, BANK_0,
  384. SMI_STS7_REG +
  385. ((channel - 5) >> 3));
  386. if (ret < 0)
  387. return ret;
  388. *val = (ret >> ((channel - 5) & 0x07)) & 1;
  389. } else {
  390. ret = nct7904_read_reg(data, BANK_0,
  391. SMI_STS8_REG +
  392. ((channel - 5) >> 3));
  393. if (ret < 0)
  394. return ret;
  395. *val = (ret >> (((channel - 5) & 0x07) - 4))
  396. & 1;
  397. }
  398. }
  399. return 0;
  400. case hwmon_temp_type:
  401. if (channel < 5) {
  402. if ((data->tcpu_mask >> channel) & 0x01) {
  403. if ((data->temp_mode >> channel) & 0x01)
  404. *val = 3; /* TD */
  405. else
  406. *val = 4; /* TR */
  407. } else {
  408. *val = 0;
  409. }
  410. } else {
  411. if ((data->has_dts >> (channel - 5)) & 0x01) {
  412. if (data->enable_dts & ENABLE_TSI)
  413. *val = 5; /* TSI */
  414. else
  415. *val = 6; /* PECI */
  416. } else {
  417. *val = 0;
  418. }
  419. }
  420. return 0;
  421. case hwmon_temp_max:
  422. reg1 = LTD_HV_LL_REG;
  423. reg2 = TEMP_CH1_W_REG;
  424. reg3 = DTS_T_CPU1_W_REG;
  425. break;
  426. case hwmon_temp_max_hyst:
  427. reg1 = LTD_LV_LL_REG;
  428. reg2 = TEMP_CH1_WH_REG;
  429. reg3 = DTS_T_CPU1_WH_REG;
  430. break;
  431. case hwmon_temp_crit:
  432. reg1 = LTD_HV_HL_REG;
  433. reg2 = TEMP_CH1_C_REG;
  434. reg3 = DTS_T_CPU1_C_REG;
  435. break;
  436. case hwmon_temp_crit_hyst:
  437. reg1 = LTD_LV_HL_REG;
  438. reg2 = TEMP_CH1_CH_REG;
  439. reg3 = DTS_T_CPU1_CH_REG;
  440. break;
  441. default:
  442. return -EOPNOTSUPP;
  443. }
  444. if (channel == 4)
  445. ret = nct7904_read_reg(data, BANK_1, reg1);
  446. else if (channel < 5)
  447. ret = nct7904_read_reg(data, BANK_1,
  448. reg2 + channel * 8);
  449. else
  450. ret = nct7904_read_reg(data, BANK_1,
  451. reg3 + (channel - 5) * 4);
  452. if (ret < 0)
  453. return ret;
  454. temps = ret;
  455. *val = temps * 1000;
  456. return 0;
  457. }
  458. static umode_t nct7904_temp_is_visible(const void *_data, u32 attr, int channel)
  459. {
  460. const struct nct7904_data *data = _data;
  461. switch (attr) {
  462. case hwmon_temp_input:
  463. case hwmon_temp_alarm:
  464. case hwmon_temp_type:
  465. if (channel < 5) {
  466. if (data->tcpu_mask & BIT(channel))
  467. return 0444;
  468. } else {
  469. if (data->has_dts & BIT(channel - 5))
  470. return 0444;
  471. }
  472. break;
  473. case hwmon_temp_max:
  474. case hwmon_temp_max_hyst:
  475. case hwmon_temp_crit:
  476. case hwmon_temp_crit_hyst:
  477. if (channel < 5) {
  478. if (data->tcpu_mask & BIT(channel))
  479. return 0644;
  480. } else {
  481. if (data->has_dts & BIT(channel - 5))
  482. return 0644;
  483. }
  484. break;
  485. default:
  486. break;
  487. }
  488. return 0;
  489. }
  490. static int nct7904_read_pwm(struct device *dev, u32 attr, int channel,
  491. long *val)
  492. {
  493. struct nct7904_data *data = dev_get_drvdata(dev);
  494. int ret;
  495. switch (attr) {
  496. case hwmon_pwm_input:
  497. ret = nct7904_read_reg(data, BANK_3, FANCTL1_OUT_REG + channel);
  498. if (ret < 0)
  499. return ret;
  500. *val = ret;
  501. return 0;
  502. case hwmon_pwm_enable:
  503. ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + channel);
  504. if (ret < 0)
  505. return ret;
  506. *val = ret ? 2 : 1;
  507. return 0;
  508. default:
  509. return -EOPNOTSUPP;
  510. }
  511. }
  512. static int nct7904_write_temp(struct device *dev, u32 attr, int channel,
  513. long val)
  514. {
  515. struct nct7904_data *data = dev_get_drvdata(dev);
  516. int ret;
  517. unsigned int reg1, reg2, reg3;
  518. val = clamp_val(val / 1000, -128, 127);
  519. switch (attr) {
  520. case hwmon_temp_max:
  521. reg1 = LTD_HV_LL_REG;
  522. reg2 = TEMP_CH1_W_REG;
  523. reg3 = DTS_T_CPU1_W_REG;
  524. break;
  525. case hwmon_temp_max_hyst:
  526. reg1 = LTD_LV_LL_REG;
  527. reg2 = TEMP_CH1_WH_REG;
  528. reg3 = DTS_T_CPU1_WH_REG;
  529. break;
  530. case hwmon_temp_crit:
  531. reg1 = LTD_HV_HL_REG;
  532. reg2 = TEMP_CH1_C_REG;
  533. reg3 = DTS_T_CPU1_C_REG;
  534. break;
  535. case hwmon_temp_crit_hyst:
  536. reg1 = LTD_LV_HL_REG;
  537. reg2 = TEMP_CH1_CH_REG;
  538. reg3 = DTS_T_CPU1_CH_REG;
  539. break;
  540. default:
  541. return -EOPNOTSUPP;
  542. }
  543. if (channel == 4)
  544. ret = nct7904_write_reg(data, BANK_1, reg1, val);
  545. else if (channel < 5)
  546. ret = nct7904_write_reg(data, BANK_1,
  547. reg2 + channel * 8, val);
  548. else
  549. ret = nct7904_write_reg(data, BANK_1,
  550. reg3 + (channel - 5) * 4, val);
  551. return ret;
  552. }
  553. static int nct7904_write_fan(struct device *dev, u32 attr, int channel,
  554. long val)
  555. {
  556. struct nct7904_data *data = dev_get_drvdata(dev);
  557. int ret;
  558. u8 tmp;
  559. switch (attr) {
  560. case hwmon_fan_min:
  561. if (val <= 0)
  562. return -EINVAL;
  563. val = clamp_val(DIV_ROUND_CLOSEST(1350000, val), 1, 0x1fff);
  564. tmp = (val >> 5) & 0xff;
  565. ret = nct7904_write_reg(data, BANK_1,
  566. FANIN1_HV_HL_REG + channel * 2, tmp);
  567. if (ret < 0)
  568. return ret;
  569. tmp = val & 0x1f;
  570. ret = nct7904_write_reg(data, BANK_1,
  571. FANIN1_LV_HL_REG + channel * 2, tmp);
  572. return ret;
  573. default:
  574. return -EOPNOTSUPP;
  575. }
  576. }
  577. static int nct7904_write_in(struct device *dev, u32 attr, int channel,
  578. long val)
  579. {
  580. struct nct7904_data *data = dev_get_drvdata(dev);
  581. int ret, index, tmp;
  582. index = nct7904_chan_to_index[channel];
  583. if (index < 14)
  584. val = val / 2; /* 0.002V scale */
  585. else
  586. val = val / 6; /* 0.006V scale */
  587. val = clamp_val(val, 0, 0x7ff);
  588. switch (attr) {
  589. case hwmon_in_min:
  590. tmp = nct7904_read_reg(data, BANK_1,
  591. VSEN1_LV_LL_REG + index * 4);
  592. if (tmp < 0)
  593. return tmp;
  594. tmp &= ~0x7;
  595. tmp |= val & 0x7;
  596. ret = nct7904_write_reg(data, BANK_1,
  597. VSEN1_LV_LL_REG + index * 4, tmp);
  598. if (ret < 0)
  599. return ret;
  600. tmp = nct7904_read_reg(data, BANK_1,
  601. VSEN1_HV_LL_REG + index * 4);
  602. if (tmp < 0)
  603. return tmp;
  604. tmp = (val >> 3) & 0xff;
  605. ret = nct7904_write_reg(data, BANK_1,
  606. VSEN1_HV_LL_REG + index * 4, tmp);
  607. return ret;
  608. case hwmon_in_max:
  609. tmp = nct7904_read_reg(data, BANK_1,
  610. VSEN1_LV_HL_REG + index * 4);
  611. if (tmp < 0)
  612. return tmp;
  613. tmp &= ~0x7;
  614. tmp |= val & 0x7;
  615. ret = nct7904_write_reg(data, BANK_1,
  616. VSEN1_LV_HL_REG + index * 4, tmp);
  617. if (ret < 0)
  618. return ret;
  619. tmp = nct7904_read_reg(data, BANK_1,
  620. VSEN1_HV_HL_REG + index * 4);
  621. if (tmp < 0)
  622. return tmp;
  623. tmp = (val >> 3) & 0xff;
  624. ret = nct7904_write_reg(data, BANK_1,
  625. VSEN1_HV_HL_REG + index * 4, tmp);
  626. return ret;
  627. default:
  628. return -EOPNOTSUPP;
  629. }
  630. }
  631. static int nct7904_write_pwm(struct device *dev, u32 attr, int channel,
  632. long val)
  633. {
  634. struct nct7904_data *data = dev_get_drvdata(dev);
  635. int ret;
  636. switch (attr) {
  637. case hwmon_pwm_input:
  638. if (val < 0 || val > 255)
  639. return -EINVAL;
  640. ret = nct7904_write_reg(data, BANK_3, FANCTL1_OUT_REG + channel,
  641. val);
  642. return ret;
  643. case hwmon_pwm_enable:
  644. if (val < 1 || val > 2 ||
  645. (val == 2 && !data->fan_mode[channel]))
  646. return -EINVAL;
  647. ret = nct7904_write_reg(data, BANK_3, FANCTL1_FMR_REG + channel,
  648. val == 2 ? data->fan_mode[channel] : 0);
  649. return ret;
  650. default:
  651. return -EOPNOTSUPP;
  652. }
  653. }
  654. static umode_t nct7904_pwm_is_visible(const void *_data, u32 attr, int channel)
  655. {
  656. switch (attr) {
  657. case hwmon_pwm_input:
  658. case hwmon_pwm_enable:
  659. return 0644;
  660. default:
  661. return 0;
  662. }
  663. }
  664. static int nct7904_read(struct device *dev, enum hwmon_sensor_types type,
  665. u32 attr, int channel, long *val)
  666. {
  667. switch (type) {
  668. case hwmon_in:
  669. return nct7904_read_in(dev, attr, channel, val);
  670. case hwmon_fan:
  671. return nct7904_read_fan(dev, attr, channel, val);
  672. case hwmon_pwm:
  673. return nct7904_read_pwm(dev, attr, channel, val);
  674. case hwmon_temp:
  675. return nct7904_read_temp(dev, attr, channel, val);
  676. default:
  677. return -EOPNOTSUPP;
  678. }
  679. }
  680. static int nct7904_write(struct device *dev, enum hwmon_sensor_types type,
  681. u32 attr, int channel, long val)
  682. {
  683. switch (type) {
  684. case hwmon_in:
  685. return nct7904_write_in(dev, attr, channel, val);
  686. case hwmon_fan:
  687. return nct7904_write_fan(dev, attr, channel, val);
  688. case hwmon_pwm:
  689. return nct7904_write_pwm(dev, attr, channel, val);
  690. case hwmon_temp:
  691. return nct7904_write_temp(dev, attr, channel, val);
  692. default:
  693. return -EOPNOTSUPP;
  694. }
  695. }
  696. static umode_t nct7904_is_visible(const void *data,
  697. enum hwmon_sensor_types type,
  698. u32 attr, int channel)
  699. {
  700. switch (type) {
  701. case hwmon_in:
  702. return nct7904_in_is_visible(data, attr, channel);
  703. case hwmon_fan:
  704. return nct7904_fan_is_visible(data, attr, channel);
  705. case hwmon_pwm:
  706. return nct7904_pwm_is_visible(data, attr, channel);
  707. case hwmon_temp:
  708. return nct7904_temp_is_visible(data, attr, channel);
  709. default:
  710. return 0;
  711. }
  712. }
  713. /* Return 0 if detection is successful, -ENODEV otherwise */
  714. static int nct7904_detect(struct i2c_client *client,
  715. struct i2c_board_info *info)
  716. {
  717. struct i2c_adapter *adapter = client->adapter;
  718. if (!i2c_check_functionality(adapter,
  719. I2C_FUNC_SMBUS_READ_BYTE |
  720. I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
  721. return -ENODEV;
  722. /* Determine the chip type. */
  723. if (i2c_smbus_read_byte_data(client, VENDOR_ID_REG) != NUVOTON_ID ||
  724. i2c_smbus_read_byte_data(client, CHIP_ID_REG) != NCT7904_ID ||
  725. (i2c_smbus_read_byte_data(client, DEVICE_ID_REG) & 0xf0) != 0x50 ||
  726. (i2c_smbus_read_byte_data(client, BANK_SEL_REG) & 0xf8) != 0x00)
  727. return -ENODEV;
  728. strscpy(info->type, "nct7904", I2C_NAME_SIZE);
  729. return 0;
  730. }
  731. static const struct hwmon_channel_info *nct7904_info[] = {
  732. HWMON_CHANNEL_INFO(in,
  733. /* dummy, skipped in is_visible */
  734. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  735. HWMON_I_ALARM,
  736. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  737. HWMON_I_ALARM,
  738. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  739. HWMON_I_ALARM,
  740. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  741. HWMON_I_ALARM,
  742. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  743. HWMON_I_ALARM,
  744. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  745. HWMON_I_ALARM,
  746. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  747. HWMON_I_ALARM,
  748. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  749. HWMON_I_ALARM,
  750. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  751. HWMON_I_ALARM,
  752. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  753. HWMON_I_ALARM,
  754. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  755. HWMON_I_ALARM,
  756. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  757. HWMON_I_ALARM,
  758. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  759. HWMON_I_ALARM,
  760. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  761. HWMON_I_ALARM,
  762. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  763. HWMON_I_ALARM,
  764. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  765. HWMON_I_ALARM,
  766. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  767. HWMON_I_ALARM,
  768. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  769. HWMON_I_ALARM,
  770. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  771. HWMON_I_ALARM,
  772. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  773. HWMON_I_ALARM,
  774. HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
  775. HWMON_I_ALARM),
  776. HWMON_CHANNEL_INFO(fan,
  777. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  778. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  779. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  780. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  781. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  782. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  783. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  784. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  785. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  786. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  787. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM,
  788. HWMON_F_INPUT | HWMON_F_MIN | HWMON_F_ALARM),
  789. HWMON_CHANNEL_INFO(pwm,
  790. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  791. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  792. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  793. HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
  794. HWMON_CHANNEL_INFO(temp,
  795. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  796. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  797. HWMON_T_CRIT_HYST,
  798. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  799. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  800. HWMON_T_CRIT_HYST,
  801. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  802. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  803. HWMON_T_CRIT_HYST,
  804. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  805. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  806. HWMON_T_CRIT_HYST,
  807. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  808. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  809. HWMON_T_CRIT_HYST,
  810. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  811. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  812. HWMON_T_CRIT_HYST,
  813. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  814. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  815. HWMON_T_CRIT_HYST,
  816. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  817. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  818. HWMON_T_CRIT_HYST,
  819. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  820. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  821. HWMON_T_CRIT_HYST,
  822. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  823. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  824. HWMON_T_CRIT_HYST,
  825. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  826. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  827. HWMON_T_CRIT_HYST,
  828. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  829. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  830. HWMON_T_CRIT_HYST,
  831. HWMON_T_INPUT | HWMON_T_ALARM | HWMON_T_MAX |
  832. HWMON_T_MAX_HYST | HWMON_T_TYPE | HWMON_T_CRIT |
  833. HWMON_T_CRIT_HYST),
  834. NULL
  835. };
  836. static const struct hwmon_ops nct7904_hwmon_ops = {
  837. .is_visible = nct7904_is_visible,
  838. .read = nct7904_read,
  839. .write = nct7904_write,
  840. };
  841. static const struct hwmon_chip_info nct7904_chip_info = {
  842. .ops = &nct7904_hwmon_ops,
  843. .info = nct7904_info,
  844. };
  845. /*
  846. * Watchdog Function
  847. */
  848. static int nct7904_wdt_start(struct watchdog_device *wdt)
  849. {
  850. struct nct7904_data *data = watchdog_get_drvdata(wdt);
  851. /* Enable soft watchdog timer */
  852. return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
  853. }
  854. static int nct7904_wdt_stop(struct watchdog_device *wdt)
  855. {
  856. struct nct7904_data *data = watchdog_get_drvdata(wdt);
  857. return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
  858. }
  859. static int nct7904_wdt_set_timeout(struct watchdog_device *wdt,
  860. unsigned int timeout)
  861. {
  862. struct nct7904_data *data = watchdog_get_drvdata(wdt);
  863. /*
  864. * The NCT7904 is very special in watchdog function.
  865. * Its minimum unit is minutes. And wdt->timeout needs
  866. * to match the actual timeout selected. So, this needs
  867. * to be: wdt->timeout = timeout / 60 * 60.
  868. * For example, if the user configures a timeout of
  869. * 119 seconds, the actual timeout will be 60 seconds.
  870. * So, wdt->timeout must then be set to 60 seconds.
  871. */
  872. wdt->timeout = timeout / 60 * 60;
  873. return nct7904_write_reg(data, BANK_0, WDT_TIMER_REG,
  874. wdt->timeout / 60);
  875. }
  876. static int nct7904_wdt_ping(struct watchdog_device *wdt)
  877. {
  878. /*
  879. * Note:
  880. * NCT7904 does not support refreshing WDT_TIMER_REG register when
  881. * the watchdog is active. Please disable watchdog before feeding
  882. * the watchdog and enable it again.
  883. */
  884. struct nct7904_data *data = watchdog_get_drvdata(wdt);
  885. int ret;
  886. /* Disable soft watchdog timer */
  887. ret = nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_DIS);
  888. if (ret < 0)
  889. return ret;
  890. /* feed watchdog */
  891. ret = nct7904_write_reg(data, BANK_0, WDT_TIMER_REG, wdt->timeout / 60);
  892. if (ret < 0)
  893. return ret;
  894. /* Enable soft watchdog timer */
  895. return nct7904_write_reg(data, BANK_0, WDT_LOCK_REG, WDT_SOFT_EN);
  896. }
  897. static unsigned int nct7904_wdt_get_timeleft(struct watchdog_device *wdt)
  898. {
  899. struct nct7904_data *data = watchdog_get_drvdata(wdt);
  900. int ret;
  901. ret = nct7904_read_reg(data, BANK_0, WDT_TIMER_REG);
  902. if (ret < 0)
  903. return 0;
  904. return ret * 60;
  905. }
  906. static const struct watchdog_info nct7904_wdt_info = {
  907. .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
  908. WDIOF_MAGICCLOSE,
  909. .identity = "nct7904 watchdog",
  910. };
  911. static const struct watchdog_ops nct7904_wdt_ops = {
  912. .owner = THIS_MODULE,
  913. .start = nct7904_wdt_start,
  914. .stop = nct7904_wdt_stop,
  915. .ping = nct7904_wdt_ping,
  916. .set_timeout = nct7904_wdt_set_timeout,
  917. .get_timeleft = nct7904_wdt_get_timeleft,
  918. };
  919. static int nct7904_probe(struct i2c_client *client)
  920. {
  921. struct nct7904_data *data;
  922. struct device *hwmon_dev;
  923. struct device *dev = &client->dev;
  924. int ret, i;
  925. u32 mask;
  926. u8 val, bit;
  927. data = devm_kzalloc(dev, sizeof(struct nct7904_data), GFP_KERNEL);
  928. if (!data)
  929. return -ENOMEM;
  930. data->client = client;
  931. mutex_init(&data->bank_lock);
  932. data->bank_sel = -1;
  933. /* Setup sensor groups. */
  934. /* FANIN attributes */
  935. ret = nct7904_read_reg16(data, BANK_0, FANIN_CTRL0_REG);
  936. if (ret < 0)
  937. return ret;
  938. data->fanin_mask = (ret >> 8) | ((ret & 0xff) << 8);
  939. /*
  940. * VSEN attributes
  941. *
  942. * Note: voltage sensors overlap with external temperature
  943. * sensors. So, if we ever decide to support the latter
  944. * we will have to adjust 'vsen_mask' accordingly.
  945. */
  946. mask = 0;
  947. ret = nct7904_read_reg16(data, BANK_0, VT_ADC_CTRL0_REG);
  948. if (ret >= 0)
  949. mask = (ret >> 8) | ((ret & 0xff) << 8);
  950. ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
  951. if (ret >= 0)
  952. mask |= (ret << 16);
  953. data->vsen_mask = mask;
  954. /* CPU_TEMP attributes */
  955. ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL0_REG);
  956. if (ret < 0)
  957. return ret;
  958. if ((ret & 0x6) == 0x6)
  959. data->tcpu_mask |= 1; /* TR1 */
  960. if ((ret & 0x18) == 0x18)
  961. data->tcpu_mask |= 2; /* TR2 */
  962. if ((ret & 0x20) == 0x20)
  963. data->tcpu_mask |= 4; /* TR3 */
  964. if ((ret & 0x80) == 0x80)
  965. data->tcpu_mask |= 8; /* TR4 */
  966. /* LTD */
  967. ret = nct7904_read_reg(data, BANK_0, VT_ADC_CTRL2_REG);
  968. if (ret < 0)
  969. return ret;
  970. if ((ret & 0x02) == 0x02)
  971. data->tcpu_mask |= 0x10;
  972. /* Multi-Function detecting for Volt and TR/TD */
  973. ret = nct7904_read_reg(data, BANK_0, VT_ADC_MD_REG);
  974. if (ret < 0)
  975. return ret;
  976. data->temp_mode = 0;
  977. for (i = 0; i < 4; i++) {
  978. val = (ret >> (i * 2)) & 0x03;
  979. bit = (1 << i);
  980. if (val == VOLT_MONITOR_MODE) {
  981. data->tcpu_mask &= ~bit;
  982. } else if (val == THERMAL_DIODE_MODE && i < 2) {
  983. data->temp_mode |= bit;
  984. data->vsen_mask &= ~(0x06 << (i * 2));
  985. } else if (val == THERMISTOR_MODE) {
  986. data->vsen_mask &= ~(0x02 << (i * 2));
  987. } else {
  988. /* Reserved */
  989. data->tcpu_mask &= ~bit;
  990. data->vsen_mask &= ~(0x06 << (i * 2));
  991. }
  992. }
  993. /* PECI */
  994. ret = nct7904_read_reg(data, BANK_2, PFE_REG);
  995. if (ret < 0)
  996. return ret;
  997. if (ret & 0x80) {
  998. data->enable_dts = 1; /* Enable DTS & PECI */
  999. } else {
  1000. ret = nct7904_read_reg(data, BANK_2, TSI_CTRL_REG);
  1001. if (ret < 0)
  1002. return ret;
  1003. if (ret & 0x80)
  1004. data->enable_dts = 0x3; /* Enable DTS & TSI */
  1005. }
  1006. /* Check DTS enable status */
  1007. if (data->enable_dts) {
  1008. ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL0_REG);
  1009. if (ret < 0)
  1010. return ret;
  1011. data->has_dts = ret & 0xF;
  1012. if (data->enable_dts & ENABLE_TSI) {
  1013. ret = nct7904_read_reg(data, BANK_0, DTS_T_CTRL1_REG);
  1014. if (ret < 0)
  1015. return ret;
  1016. data->has_dts |= (ret & 0xF) << 4;
  1017. }
  1018. }
  1019. for (i = 0; i < FANCTL_MAX; i++) {
  1020. ret = nct7904_read_reg(data, BANK_3, FANCTL1_FMR_REG + i);
  1021. if (ret < 0)
  1022. return ret;
  1023. data->fan_mode[i] = ret;
  1024. }
  1025. /* Read all of SMI status register to clear alarms */
  1026. for (i = 0; i < SMI_STS_MAX; i++) {
  1027. ret = nct7904_read_reg(data, BANK_0, SMI_STS1_REG + i);
  1028. if (ret < 0)
  1029. return ret;
  1030. }
  1031. hwmon_dev =
  1032. devm_hwmon_device_register_with_info(dev, client->name, data,
  1033. &nct7904_chip_info, NULL);
  1034. ret = PTR_ERR_OR_ZERO(hwmon_dev);
  1035. if (ret)
  1036. return ret;
  1037. /* Watchdog initialization */
  1038. data->wdt.ops = &nct7904_wdt_ops;
  1039. data->wdt.info = &nct7904_wdt_info;
  1040. data->wdt.timeout = WATCHDOG_TIMEOUT * 60; /* Set default timeout */
  1041. data->wdt.min_timeout = MIN_TIMEOUT;
  1042. data->wdt.max_timeout = MAX_TIMEOUT;
  1043. data->wdt.parent = &client->dev;
  1044. watchdog_init_timeout(&data->wdt, timeout * 60, &client->dev);
  1045. watchdog_set_nowayout(&data->wdt, nowayout);
  1046. watchdog_set_drvdata(&data->wdt, data);
  1047. watchdog_stop_on_unregister(&data->wdt);
  1048. return devm_watchdog_register_device(dev, &data->wdt);
  1049. }
  1050. static const struct i2c_device_id nct7904_id[] = {
  1051. {"nct7904", 0},
  1052. {}
  1053. };
  1054. MODULE_DEVICE_TABLE(i2c, nct7904_id);
  1055. static struct i2c_driver nct7904_driver = {
  1056. .class = I2C_CLASS_HWMON,
  1057. .driver = {
  1058. .name = "nct7904",
  1059. },
  1060. .probe_new = nct7904_probe,
  1061. .id_table = nct7904_id,
  1062. .detect = nct7904_detect,
  1063. .address_list = normal_i2c,
  1064. };
  1065. module_i2c_driver(nct7904_driver);
  1066. MODULE_AUTHOR("Vadim V. Vlasov <[email protected]>");
  1067. MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
  1068. MODULE_LICENSE("GPL");