mr75203.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MaxLinear, Inc.
  4. *
  5. * This driver is a hardware monitoring driver for PVT controller
  6. * (MR75203) which is used to configure & control Moortec embedded
  7. * analog IP to enable multiple embedded temperature sensor(TS),
  8. * voltage monitor(VM) & process detector(PD) modules.
  9. */
  10. #include <linux/bits.h>
  11. #include <linux/clk.h>
  12. #include <linux/debugfs.h>
  13. #include <linux/hwmon.h>
  14. #include <linux/module.h>
  15. #include <linux/mod_devicetable.h>
  16. #include <linux/mutex.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/property.h>
  19. #include <linux/regmap.h>
  20. #include <linux/reset.h>
  21. #include <linux/slab.h>
  22. #include <linux/units.h>
  23. /* PVT Common register */
  24. #define PVT_IP_CONFIG 0x04
  25. #define TS_NUM_MSK GENMASK(4, 0)
  26. #define TS_NUM_SFT 0
  27. #define PD_NUM_MSK GENMASK(12, 8)
  28. #define PD_NUM_SFT 8
  29. #define VM_NUM_MSK GENMASK(20, 16)
  30. #define VM_NUM_SFT 16
  31. #define CH_NUM_MSK GENMASK(31, 24)
  32. #define CH_NUM_SFT 24
  33. #define VM_NUM_MAX (VM_NUM_MSK >> VM_NUM_SFT)
  34. /* Macro Common Register */
  35. #define CLK_SYNTH 0x00
  36. #define CLK_SYNTH_LO_SFT 0
  37. #define CLK_SYNTH_HI_SFT 8
  38. #define CLK_SYNTH_HOLD_SFT 16
  39. #define CLK_SYNTH_EN BIT(24)
  40. #define CLK_SYS_CYCLES_MAX 514
  41. #define CLK_SYS_CYCLES_MIN 2
  42. #define SDIF_DISABLE 0x04
  43. #define SDIF_STAT 0x08
  44. #define SDIF_BUSY BIT(0)
  45. #define SDIF_LOCK BIT(1)
  46. #define SDIF_W 0x0c
  47. #define SDIF_PROG BIT(31)
  48. #define SDIF_WRN_W BIT(27)
  49. #define SDIF_WRN_R 0x00
  50. #define SDIF_ADDR_SFT 24
  51. #define SDIF_HALT 0x10
  52. #define SDIF_CTRL 0x14
  53. #define SDIF_SMPL_CTRL 0x20
  54. /* TS & PD Individual Macro Register */
  55. #define COM_REG_SIZE 0x40
  56. #define SDIF_DONE(n) (COM_REG_SIZE + 0x14 + 0x40 * (n))
  57. #define SDIF_SMPL_DONE BIT(0)
  58. #define SDIF_DATA(n) (COM_REG_SIZE + 0x18 + 0x40 * (n))
  59. #define SAMPLE_DATA_MSK GENMASK(15, 0)
  60. #define HILO_RESET(n) (COM_REG_SIZE + 0x2c + 0x40 * (n))
  61. /* VM Individual Macro Register */
  62. #define VM_COM_REG_SIZE 0x200
  63. #define VM_SDIF_DONE(vm) (VM_COM_REG_SIZE + 0x34 + 0x200 * (vm))
  64. #define VM_SDIF_DATA(vm, ch) \
  65. (VM_COM_REG_SIZE + 0x40 + 0x200 * (vm) + 0x4 * (ch))
  66. /* SDA Slave Register */
  67. #define IP_CTRL 0x00
  68. #define IP_RST_REL BIT(1)
  69. #define IP_RUN_CONT BIT(3)
  70. #define IP_AUTO BIT(8)
  71. #define IP_VM_MODE BIT(10)
  72. #define IP_CFG 0x01
  73. #define CFG0_MODE_2 BIT(0)
  74. #define CFG0_PARALLEL_OUT 0
  75. #define CFG0_12_BIT 0
  76. #define CFG1_VOL_MEAS_MODE 0
  77. #define CFG1_PARALLEL_OUT 0
  78. #define CFG1_14_BIT 0
  79. #define IP_DATA 0x03
  80. #define IP_POLL 0x04
  81. #define VM_CH_INIT BIT(20)
  82. #define VM_CH_REQ BIT(21)
  83. #define IP_TMR 0x05
  84. #define POWER_DELAY_CYCLE_256 0x100
  85. #define POWER_DELAY_CYCLE_64 0x40
  86. #define PVT_POLL_DELAY_US 20
  87. #define PVT_POLL_TIMEOUT_US 20000
  88. #define PVT_CONV_BITS 10
  89. #define PVT_N_CONST 90
  90. #define PVT_R_CONST 245805
  91. #define PVT_TEMP_MIN_mC -40000
  92. #define PVT_TEMP_MAX_mC 125000
  93. /* Temperature coefficients for series 5 */
  94. #define PVT_SERIES5_H_CONST 200000
  95. #define PVT_SERIES5_G_CONST 60000
  96. #define PVT_SERIES5_J_CONST -100
  97. #define PVT_SERIES5_CAL5_CONST 4094
  98. /* Temperature coefficients for series 6 */
  99. #define PVT_SERIES6_H_CONST 249400
  100. #define PVT_SERIES6_G_CONST 57400
  101. #define PVT_SERIES6_J_CONST 0
  102. #define PVT_SERIES6_CAL5_CONST 4096
  103. #define TEMPERATURE_SENSOR_SERIES_5 5
  104. #define TEMPERATURE_SENSOR_SERIES_6 6
  105. #define PRE_SCALER_X1 1
  106. #define PRE_SCALER_X2 2
  107. /**
  108. * struct voltage_device - VM single input parameters.
  109. * @vm_map: Map channel number to VM index.
  110. * @ch_map: Map channel number to channel index.
  111. * @pre_scaler: Pre scaler value (1 or 2) used to normalize the voltage output
  112. * result.
  113. *
  114. * The structure provides mapping between channel-number (0..N-1) to VM-index
  115. * (0..num_vm-1) and channel-index (0..ch_num-1) where N = num_vm * ch_num.
  116. * It also provides normalization factor for the VM equation.
  117. */
  118. struct voltage_device {
  119. u32 vm_map;
  120. u32 ch_map;
  121. u32 pre_scaler;
  122. };
  123. /**
  124. * struct voltage_channels - VM channel count.
  125. * @total: Total number of channels in all VMs.
  126. * @max: Maximum number of channels among all VMs.
  127. *
  128. * The structure provides channel count information across all VMs.
  129. */
  130. struct voltage_channels {
  131. u32 total;
  132. u8 max;
  133. };
  134. struct temp_coeff {
  135. u32 h;
  136. u32 g;
  137. u32 cal5;
  138. s32 j;
  139. };
  140. struct pvt_device {
  141. struct regmap *c_map;
  142. struct regmap *t_map;
  143. struct regmap *p_map;
  144. struct regmap *v_map;
  145. struct clk *clk;
  146. struct reset_control *rst;
  147. struct dentry *dbgfs_dir;
  148. struct voltage_device *vd;
  149. struct voltage_channels vm_channels;
  150. struct temp_coeff ts_coeff;
  151. u32 t_num;
  152. u32 p_num;
  153. u32 v_num;
  154. u32 ip_freq;
  155. };
  156. static ssize_t pvt_ts_coeff_j_read(struct file *file, char __user *user_buf,
  157. size_t count, loff_t *ppos)
  158. {
  159. struct pvt_device *pvt = file->private_data;
  160. unsigned int len;
  161. char buf[13];
  162. len = scnprintf(buf, sizeof(buf), "%d\n", pvt->ts_coeff.j);
  163. return simple_read_from_buffer(user_buf, count, ppos, buf, len);
  164. }
  165. static ssize_t pvt_ts_coeff_j_write(struct file *file,
  166. const char __user *user_buf,
  167. size_t count, loff_t *ppos)
  168. {
  169. struct pvt_device *pvt = file->private_data;
  170. int ret;
  171. ret = kstrtos32_from_user(user_buf, count, 0, &pvt->ts_coeff.j);
  172. if (ret)
  173. return ret;
  174. return count;
  175. }
  176. static const struct file_operations pvt_ts_coeff_j_fops = {
  177. .read = pvt_ts_coeff_j_read,
  178. .write = pvt_ts_coeff_j_write,
  179. .open = simple_open,
  180. .owner = THIS_MODULE,
  181. .llseek = default_llseek,
  182. };
  183. static void devm_pvt_ts_dbgfs_remove(void *data)
  184. {
  185. struct pvt_device *pvt = (struct pvt_device *)data;
  186. debugfs_remove_recursive(pvt->dbgfs_dir);
  187. pvt->dbgfs_dir = NULL;
  188. }
  189. static int pvt_ts_dbgfs_create(struct pvt_device *pvt, struct device *dev)
  190. {
  191. pvt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
  192. debugfs_create_u32("ts_coeff_h", 0644, pvt->dbgfs_dir,
  193. &pvt->ts_coeff.h);
  194. debugfs_create_u32("ts_coeff_g", 0644, pvt->dbgfs_dir,
  195. &pvt->ts_coeff.g);
  196. debugfs_create_u32("ts_coeff_cal5", 0644, pvt->dbgfs_dir,
  197. &pvt->ts_coeff.cal5);
  198. debugfs_create_file("ts_coeff_j", 0644, pvt->dbgfs_dir, pvt,
  199. &pvt_ts_coeff_j_fops);
  200. return devm_add_action_or_reset(dev, devm_pvt_ts_dbgfs_remove, pvt);
  201. }
  202. static umode_t pvt_is_visible(const void *data, enum hwmon_sensor_types type,
  203. u32 attr, int channel)
  204. {
  205. switch (type) {
  206. case hwmon_temp:
  207. if (attr == hwmon_temp_input)
  208. return 0444;
  209. break;
  210. case hwmon_in:
  211. if (attr == hwmon_in_input)
  212. return 0444;
  213. break;
  214. default:
  215. break;
  216. }
  217. return 0;
  218. }
  219. static long pvt_calc_temp(struct pvt_device *pvt, u32 nbs)
  220. {
  221. /*
  222. * Convert the register value to degrees centigrade temperature:
  223. * T = G + H * (n / cal5 - 0.5) + J * F
  224. */
  225. struct temp_coeff *ts_coeff = &pvt->ts_coeff;
  226. s64 tmp = ts_coeff->g +
  227. div_s64(ts_coeff->h * (s64)nbs, ts_coeff->cal5) -
  228. ts_coeff->h / 2 +
  229. div_s64(ts_coeff->j * (s64)pvt->ip_freq, HZ_PER_MHZ);
  230. return clamp_val(tmp, PVT_TEMP_MIN_mC, PVT_TEMP_MAX_mC);
  231. }
  232. static int pvt_read_temp(struct device *dev, u32 attr, int channel, long *val)
  233. {
  234. struct pvt_device *pvt = dev_get_drvdata(dev);
  235. struct regmap *t_map = pvt->t_map;
  236. u32 stat, nbs;
  237. int ret;
  238. switch (attr) {
  239. case hwmon_temp_input:
  240. ret = regmap_read_poll_timeout(t_map, SDIF_DONE(channel),
  241. stat, stat & SDIF_SMPL_DONE,
  242. PVT_POLL_DELAY_US,
  243. PVT_POLL_TIMEOUT_US);
  244. if (ret)
  245. return ret;
  246. ret = regmap_read(t_map, SDIF_DATA(channel), &nbs);
  247. if (ret < 0)
  248. return ret;
  249. nbs &= SAMPLE_DATA_MSK;
  250. /*
  251. * Convert the register value to
  252. * degrees centigrade temperature
  253. */
  254. *val = pvt_calc_temp(pvt, nbs);
  255. return 0;
  256. default:
  257. return -EOPNOTSUPP;
  258. }
  259. }
  260. static int pvt_read_in(struct device *dev, u32 attr, int channel, long *val)
  261. {
  262. struct pvt_device *pvt = dev_get_drvdata(dev);
  263. struct regmap *v_map = pvt->v_map;
  264. u32 n, stat, pre_scaler;
  265. u8 vm_idx, ch_idx;
  266. int ret;
  267. if (channel >= pvt->vm_channels.total)
  268. return -EINVAL;
  269. vm_idx = pvt->vd[channel].vm_map;
  270. ch_idx = pvt->vd[channel].ch_map;
  271. switch (attr) {
  272. case hwmon_in_input:
  273. ret = regmap_read_poll_timeout(v_map, VM_SDIF_DONE(vm_idx),
  274. stat, stat & SDIF_SMPL_DONE,
  275. PVT_POLL_DELAY_US,
  276. PVT_POLL_TIMEOUT_US);
  277. if (ret)
  278. return ret;
  279. ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx, ch_idx), &n);
  280. if (ret < 0)
  281. return ret;
  282. n &= SAMPLE_DATA_MSK;
  283. pre_scaler = pvt->vd[channel].pre_scaler;
  284. /*
  285. * Convert the N bitstream count into voltage.
  286. * To support negative voltage calculation for 64bit machines
  287. * n must be cast to long, since n and *val differ both in
  288. * signedness and in size.
  289. * Division is used instead of right shift, because for signed
  290. * numbers, the sign bit is used to fill the vacated bit
  291. * positions, and if the number is negative, 1 is used.
  292. * BIT(x) may not be used instead of (1 << x) because it's
  293. * unsigned.
  294. */
  295. *val = pre_scaler * (PVT_N_CONST * (long)n - PVT_R_CONST) /
  296. (1 << PVT_CONV_BITS);
  297. return 0;
  298. default:
  299. return -EOPNOTSUPP;
  300. }
  301. }
  302. static int pvt_read(struct device *dev, enum hwmon_sensor_types type,
  303. u32 attr, int channel, long *val)
  304. {
  305. switch (type) {
  306. case hwmon_temp:
  307. return pvt_read_temp(dev, attr, channel, val);
  308. case hwmon_in:
  309. return pvt_read_in(dev, attr, channel, val);
  310. default:
  311. return -EOPNOTSUPP;
  312. }
  313. }
  314. static struct hwmon_channel_info pvt_temp = {
  315. .type = hwmon_temp,
  316. };
  317. static struct hwmon_channel_info pvt_in = {
  318. .type = hwmon_in,
  319. };
  320. static const struct hwmon_ops pvt_hwmon_ops = {
  321. .is_visible = pvt_is_visible,
  322. .read = pvt_read,
  323. };
  324. static struct hwmon_chip_info pvt_chip_info = {
  325. .ops = &pvt_hwmon_ops,
  326. };
  327. static int pvt_init(struct pvt_device *pvt)
  328. {
  329. u16 sys_freq, key, middle, low = 4, high = 8;
  330. struct regmap *t_map = pvt->t_map;
  331. struct regmap *p_map = pvt->p_map;
  332. struct regmap *v_map = pvt->v_map;
  333. u32 t_num = pvt->t_num;
  334. u32 p_num = pvt->p_num;
  335. u32 v_num = pvt->v_num;
  336. u32 clk_synth, val;
  337. int ret;
  338. sys_freq = clk_get_rate(pvt->clk) / HZ_PER_MHZ;
  339. while (high >= low) {
  340. middle = (low + high + 1) / 2;
  341. key = DIV_ROUND_CLOSEST(sys_freq, middle);
  342. if (key > CLK_SYS_CYCLES_MAX) {
  343. low = middle + 1;
  344. continue;
  345. } else if (key < CLK_SYS_CYCLES_MIN) {
  346. high = middle - 1;
  347. continue;
  348. } else {
  349. break;
  350. }
  351. }
  352. /*
  353. * The system supports 'clk_sys' to 'clk_ip' frequency ratios
  354. * from 2:1 to 512:1
  355. */
  356. key = clamp_val(key, CLK_SYS_CYCLES_MIN, CLK_SYS_CYCLES_MAX) - 2;
  357. clk_synth = ((key + 1) >> 1) << CLK_SYNTH_LO_SFT |
  358. (key >> 1) << CLK_SYNTH_HI_SFT |
  359. (key >> 1) << CLK_SYNTH_HOLD_SFT | CLK_SYNTH_EN;
  360. pvt->ip_freq = clk_get_rate(pvt->clk) / (key + 2);
  361. if (t_num) {
  362. ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0);
  363. if (ret < 0)
  364. return ret;
  365. ret = regmap_write(t_map, SDIF_HALT, 0x0);
  366. if (ret < 0)
  367. return ret;
  368. ret = regmap_write(t_map, CLK_SYNTH, clk_synth);
  369. if (ret < 0)
  370. return ret;
  371. ret = regmap_write(t_map, SDIF_DISABLE, 0x0);
  372. if (ret < 0)
  373. return ret;
  374. ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
  375. val, !(val & SDIF_BUSY),
  376. PVT_POLL_DELAY_US,
  377. PVT_POLL_TIMEOUT_US);
  378. if (ret)
  379. return ret;
  380. val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
  381. IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
  382. ret = regmap_write(t_map, SDIF_W, val);
  383. if (ret < 0)
  384. return ret;
  385. ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
  386. val, !(val & SDIF_BUSY),
  387. PVT_POLL_DELAY_US,
  388. PVT_POLL_TIMEOUT_US);
  389. if (ret)
  390. return ret;
  391. val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
  392. SDIF_WRN_W | SDIF_PROG;
  393. ret = regmap_write(t_map, SDIF_W, val);
  394. if (ret < 0)
  395. return ret;
  396. ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
  397. val, !(val & SDIF_BUSY),
  398. PVT_POLL_DELAY_US,
  399. PVT_POLL_TIMEOUT_US);
  400. if (ret)
  401. return ret;
  402. val = IP_RST_REL | IP_RUN_CONT | IP_AUTO |
  403. IP_CTRL << SDIF_ADDR_SFT |
  404. SDIF_WRN_W | SDIF_PROG;
  405. ret = regmap_write(t_map, SDIF_W, val);
  406. if (ret < 0)
  407. return ret;
  408. }
  409. if (p_num) {
  410. ret = regmap_write(p_map, SDIF_HALT, 0x0);
  411. if (ret < 0)
  412. return ret;
  413. ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1);
  414. if (ret < 0)
  415. return ret;
  416. ret = regmap_write(p_map, CLK_SYNTH, clk_synth);
  417. if (ret < 0)
  418. return ret;
  419. }
  420. if (v_num) {
  421. ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0);
  422. if (ret < 0)
  423. return ret;
  424. ret = regmap_write(v_map, SDIF_HALT, 0x0);
  425. if (ret < 0)
  426. return ret;
  427. ret = regmap_write(v_map, CLK_SYNTH, clk_synth);
  428. if (ret < 0)
  429. return ret;
  430. ret = regmap_write(v_map, SDIF_DISABLE, 0x0);
  431. if (ret < 0)
  432. return ret;
  433. ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
  434. val, !(val & SDIF_BUSY),
  435. PVT_POLL_DELAY_US,
  436. PVT_POLL_TIMEOUT_US);
  437. if (ret)
  438. return ret;
  439. val = (BIT(pvt->vm_channels.max) - 1) | VM_CH_INIT |
  440. IP_POLL << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
  441. ret = regmap_write(v_map, SDIF_W, val);
  442. if (ret < 0)
  443. return ret;
  444. ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
  445. val, !(val & SDIF_BUSY),
  446. PVT_POLL_DELAY_US,
  447. PVT_POLL_TIMEOUT_US);
  448. if (ret)
  449. return ret;
  450. val = CFG1_VOL_MEAS_MODE | CFG1_PARALLEL_OUT |
  451. CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT |
  452. SDIF_WRN_W | SDIF_PROG;
  453. ret = regmap_write(v_map, SDIF_W, val);
  454. if (ret < 0)
  455. return ret;
  456. ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
  457. val, !(val & SDIF_BUSY),
  458. PVT_POLL_DELAY_US,
  459. PVT_POLL_TIMEOUT_US);
  460. if (ret)
  461. return ret;
  462. val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
  463. SDIF_WRN_W | SDIF_PROG;
  464. ret = regmap_write(v_map, SDIF_W, val);
  465. if (ret < 0)
  466. return ret;
  467. ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
  468. val, !(val & SDIF_BUSY),
  469. PVT_POLL_DELAY_US,
  470. PVT_POLL_TIMEOUT_US);
  471. if (ret)
  472. return ret;
  473. val = IP_RST_REL | IP_RUN_CONT | IP_AUTO | IP_VM_MODE |
  474. IP_CTRL << SDIF_ADDR_SFT |
  475. SDIF_WRN_W | SDIF_PROG;
  476. ret = regmap_write(v_map, SDIF_W, val);
  477. if (ret < 0)
  478. return ret;
  479. }
  480. return 0;
  481. }
  482. static struct regmap_config pvt_regmap_config = {
  483. .reg_bits = 32,
  484. .reg_stride = 4,
  485. .val_bits = 32,
  486. };
  487. static int pvt_get_regmap(struct platform_device *pdev, char *reg_name,
  488. struct pvt_device *pvt)
  489. {
  490. struct device *dev = &pdev->dev;
  491. struct regmap **reg_map;
  492. void __iomem *io_base;
  493. if (!strcmp(reg_name, "common"))
  494. reg_map = &pvt->c_map;
  495. else if (!strcmp(reg_name, "ts"))
  496. reg_map = &pvt->t_map;
  497. else if (!strcmp(reg_name, "pd"))
  498. reg_map = &pvt->p_map;
  499. else if (!strcmp(reg_name, "vm"))
  500. reg_map = &pvt->v_map;
  501. else
  502. return -EINVAL;
  503. io_base = devm_platform_ioremap_resource_byname(pdev, reg_name);
  504. if (IS_ERR(io_base))
  505. return PTR_ERR(io_base);
  506. pvt_regmap_config.name = reg_name;
  507. *reg_map = devm_regmap_init_mmio(dev, io_base, &pvt_regmap_config);
  508. if (IS_ERR(*reg_map)) {
  509. dev_err(dev, "failed to init register map\n");
  510. return PTR_ERR(*reg_map);
  511. }
  512. return 0;
  513. }
  514. static void pvt_reset_control_assert(void *data)
  515. {
  516. struct pvt_device *pvt = data;
  517. reset_control_assert(pvt->rst);
  518. }
  519. static int pvt_reset_control_deassert(struct device *dev, struct pvt_device *pvt)
  520. {
  521. int ret;
  522. ret = reset_control_deassert(pvt->rst);
  523. if (ret)
  524. return ret;
  525. return devm_add_action_or_reset(dev, pvt_reset_control_assert, pvt);
  526. }
  527. static int pvt_get_active_channel(struct device *dev, struct pvt_device *pvt,
  528. u32 vm_num, u32 ch_num, u8 *vm_idx)
  529. {
  530. u8 vm_active_ch[VM_NUM_MAX];
  531. int ret, i, j, k;
  532. ret = device_property_read_u8_array(dev, "moortec,vm-active-channels",
  533. vm_active_ch, vm_num);
  534. if (ret) {
  535. /*
  536. * Incase "moortec,vm-active-channels" property is not defined,
  537. * we assume each VM sensor has all of its channels active.
  538. */
  539. memset(vm_active_ch, ch_num, vm_num);
  540. pvt->vm_channels.max = ch_num;
  541. pvt->vm_channels.total = ch_num * vm_num;
  542. } else {
  543. for (i = 0; i < vm_num; i++) {
  544. if (vm_active_ch[i] > ch_num) {
  545. dev_err(dev, "invalid active channels: %u\n",
  546. vm_active_ch[i]);
  547. return -EINVAL;
  548. }
  549. pvt->vm_channels.total += vm_active_ch[i];
  550. if (vm_active_ch[i] > pvt->vm_channels.max)
  551. pvt->vm_channels.max = vm_active_ch[i];
  552. }
  553. }
  554. /*
  555. * Map between the channel-number to VM-index and channel-index.
  556. * Example - 3 VMs, "moortec,vm_active_ch" = <5 2 4>:
  557. * vm_map = [0 0 0 0 0 1 1 2 2 2 2]
  558. * ch_map = [0 1 2 3 4 0 1 0 1 2 3]
  559. */
  560. pvt->vd = devm_kcalloc(dev, pvt->vm_channels.total, sizeof(*pvt->vd),
  561. GFP_KERNEL);
  562. if (!pvt->vd)
  563. return -ENOMEM;
  564. k = 0;
  565. for (i = 0; i < vm_num; i++) {
  566. for (j = 0; j < vm_active_ch[i]; j++) {
  567. pvt->vd[k].vm_map = vm_idx[i];
  568. pvt->vd[k].ch_map = j;
  569. k++;
  570. }
  571. }
  572. return 0;
  573. }
  574. static int pvt_get_pre_scaler(struct device *dev, struct pvt_device *pvt)
  575. {
  576. u8 *pre_scaler_ch_list;
  577. int i, ret, num_ch;
  578. u32 channel;
  579. /* Set default pre-scaler value to be 1. */
  580. for (i = 0; i < pvt->vm_channels.total; i++)
  581. pvt->vd[i].pre_scaler = PRE_SCALER_X1;
  582. /* Get number of channels configured in "moortec,vm-pre-scaler-x2". */
  583. num_ch = device_property_count_u8(dev, "moortec,vm-pre-scaler-x2");
  584. if (num_ch <= 0)
  585. return 0;
  586. pre_scaler_ch_list = kcalloc(num_ch, sizeof(*pre_scaler_ch_list),
  587. GFP_KERNEL);
  588. if (!pre_scaler_ch_list)
  589. return -ENOMEM;
  590. /* Get list of all channels that have pre-scaler of 2. */
  591. ret = device_property_read_u8_array(dev, "moortec,vm-pre-scaler-x2",
  592. pre_scaler_ch_list, num_ch);
  593. if (ret)
  594. goto out;
  595. for (i = 0; i < num_ch; i++) {
  596. channel = pre_scaler_ch_list[i];
  597. pvt->vd[channel].pre_scaler = PRE_SCALER_X2;
  598. }
  599. out:
  600. kfree(pre_scaler_ch_list);
  601. return ret;
  602. }
  603. static int pvt_set_temp_coeff(struct device *dev, struct pvt_device *pvt)
  604. {
  605. struct temp_coeff *ts_coeff = &pvt->ts_coeff;
  606. u32 series;
  607. int ret;
  608. /* Incase ts-series property is not defined, use default 5. */
  609. ret = device_property_read_u32(dev, "moortec,ts-series", &series);
  610. if (ret)
  611. series = TEMPERATURE_SENSOR_SERIES_5;
  612. switch (series) {
  613. case TEMPERATURE_SENSOR_SERIES_5:
  614. ts_coeff->h = PVT_SERIES5_H_CONST;
  615. ts_coeff->g = PVT_SERIES5_G_CONST;
  616. ts_coeff->j = PVT_SERIES5_J_CONST;
  617. ts_coeff->cal5 = PVT_SERIES5_CAL5_CONST;
  618. break;
  619. case TEMPERATURE_SENSOR_SERIES_6:
  620. ts_coeff->h = PVT_SERIES6_H_CONST;
  621. ts_coeff->g = PVT_SERIES6_G_CONST;
  622. ts_coeff->j = PVT_SERIES6_J_CONST;
  623. ts_coeff->cal5 = PVT_SERIES6_CAL5_CONST;
  624. break;
  625. default:
  626. dev_err(dev, "invalid temperature sensor series (%u)\n",
  627. series);
  628. return -EINVAL;
  629. }
  630. dev_dbg(dev, "temperature sensor series = %u\n", series);
  631. /* Override ts-coeff-h/g/j/cal5 if they are defined. */
  632. device_property_read_u32(dev, "moortec,ts-coeff-h", &ts_coeff->h);
  633. device_property_read_u32(dev, "moortec,ts-coeff-g", &ts_coeff->g);
  634. device_property_read_u32(dev, "moortec,ts-coeff-j", &ts_coeff->j);
  635. device_property_read_u32(dev, "moortec,ts-coeff-cal5", &ts_coeff->cal5);
  636. dev_dbg(dev, "ts-coeff: h = %u, g = %u, j = %d, cal5 = %u\n",
  637. ts_coeff->h, ts_coeff->g, ts_coeff->j, ts_coeff->cal5);
  638. return 0;
  639. }
  640. static int mr75203_probe(struct platform_device *pdev)
  641. {
  642. u32 ts_num, vm_num, pd_num, ch_num, val, index, i;
  643. const struct hwmon_channel_info **pvt_info;
  644. struct device *dev = &pdev->dev;
  645. u32 *temp_config, *in_config;
  646. struct device *hwmon_dev;
  647. struct pvt_device *pvt;
  648. int ret;
  649. pvt = devm_kzalloc(dev, sizeof(*pvt), GFP_KERNEL);
  650. if (!pvt)
  651. return -ENOMEM;
  652. ret = pvt_get_regmap(pdev, "common", pvt);
  653. if (ret)
  654. return ret;
  655. pvt->clk = devm_clk_get_enabled(dev, NULL);
  656. if (IS_ERR(pvt->clk))
  657. return dev_err_probe(dev, PTR_ERR(pvt->clk), "failed to get clock\n");
  658. pvt->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
  659. if (IS_ERR(pvt->rst))
  660. return dev_err_probe(dev, PTR_ERR(pvt->rst),
  661. "failed to get reset control\n");
  662. if (pvt->rst) {
  663. ret = pvt_reset_control_deassert(dev, pvt);
  664. if (ret)
  665. return dev_err_probe(dev, ret,
  666. "cannot deassert reset control\n");
  667. }
  668. ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
  669. if (ret < 0)
  670. return ret;
  671. ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;
  672. pd_num = (val & PD_NUM_MSK) >> PD_NUM_SFT;
  673. vm_num = (val & VM_NUM_MSK) >> VM_NUM_SFT;
  674. ch_num = (val & CH_NUM_MSK) >> CH_NUM_SFT;
  675. pvt->t_num = ts_num;
  676. pvt->p_num = pd_num;
  677. pvt->v_num = vm_num;
  678. val = 0;
  679. if (ts_num)
  680. val++;
  681. if (vm_num)
  682. val++;
  683. if (!val)
  684. return -ENODEV;
  685. pvt_info = devm_kcalloc(dev, val + 2, sizeof(*pvt_info), GFP_KERNEL);
  686. if (!pvt_info)
  687. return -ENOMEM;
  688. pvt_info[0] = HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ);
  689. index = 1;
  690. if (ts_num) {
  691. ret = pvt_get_regmap(pdev, "ts", pvt);
  692. if (ret)
  693. return ret;
  694. ret = pvt_set_temp_coeff(dev, pvt);
  695. if (ret)
  696. return ret;
  697. temp_config = devm_kcalloc(dev, ts_num + 1,
  698. sizeof(*temp_config), GFP_KERNEL);
  699. if (!temp_config)
  700. return -ENOMEM;
  701. memset32(temp_config, HWMON_T_INPUT, ts_num);
  702. pvt_temp.config = temp_config;
  703. pvt_info[index++] = &pvt_temp;
  704. pvt_ts_dbgfs_create(pvt, dev);
  705. }
  706. if (pd_num) {
  707. ret = pvt_get_regmap(pdev, "pd", pvt);
  708. if (ret)
  709. return ret;
  710. }
  711. if (vm_num) {
  712. u8 vm_idx[VM_NUM_MAX];
  713. ret = pvt_get_regmap(pdev, "vm", pvt);
  714. if (ret)
  715. return ret;
  716. ret = device_property_read_u8_array(dev, "intel,vm-map", vm_idx,
  717. vm_num);
  718. if (ret) {
  719. /*
  720. * Incase intel,vm-map property is not defined, we
  721. * assume incremental channel numbers.
  722. */
  723. for (i = 0; i < vm_num; i++)
  724. vm_idx[i] = i;
  725. } else {
  726. for (i = 0; i < vm_num; i++)
  727. if (vm_idx[i] >= vm_num || vm_idx[i] == 0xff) {
  728. pvt->v_num = i;
  729. vm_num = i;
  730. break;
  731. }
  732. }
  733. ret = pvt_get_active_channel(dev, pvt, vm_num, ch_num, vm_idx);
  734. if (ret)
  735. return ret;
  736. ret = pvt_get_pre_scaler(dev, pvt);
  737. if (ret)
  738. return ret;
  739. in_config = devm_kcalloc(dev, pvt->vm_channels.total + 1,
  740. sizeof(*in_config), GFP_KERNEL);
  741. if (!in_config)
  742. return -ENOMEM;
  743. memset32(in_config, HWMON_I_INPUT, pvt->vm_channels.total);
  744. in_config[pvt->vm_channels.total] = 0;
  745. pvt_in.config = in_config;
  746. pvt_info[index++] = &pvt_in;
  747. }
  748. ret = pvt_init(pvt);
  749. if (ret) {
  750. dev_err(dev, "failed to init pvt: %d\n", ret);
  751. return ret;
  752. }
  753. pvt_chip_info.info = pvt_info;
  754. hwmon_dev = devm_hwmon_device_register_with_info(dev, "pvt",
  755. pvt,
  756. &pvt_chip_info,
  757. NULL);
  758. return PTR_ERR_OR_ZERO(hwmon_dev);
  759. }
  760. static const struct of_device_id moortec_pvt_of_match[] = {
  761. { .compatible = "moortec,mr75203" },
  762. { }
  763. };
  764. MODULE_DEVICE_TABLE(of, moortec_pvt_of_match);
  765. static struct platform_driver moortec_pvt_driver = {
  766. .driver = {
  767. .name = "moortec-pvt",
  768. .of_match_table = moortec_pvt_of_match,
  769. },
  770. .probe = mr75203_probe,
  771. };
  772. module_platform_driver(moortec_pvt_driver);
  773. MODULE_LICENSE("GPL v2");