max6621.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Hardware monitoring driver for Maxim MAX6621
  4. *
  5. * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
  6. * Copyright (c) 2017 Vadim Pasternak <[email protected]>
  7. */
  8. #include <linux/bitops.h>
  9. #include <linux/hwmon.h>
  10. #include <linux/hwmon-sysfs.h>
  11. #include <linux/i2c.h>
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/of_device.h>
  15. #include <linux/regmap.h>
  16. #define MAX6621_DRV_NAME "max6621"
  17. #define MAX6621_TEMP_INPUT_REG_NUM 9
  18. #define MAX6621_TEMP_INPUT_MIN -127000
  19. #define MAX6621_TEMP_INPUT_MAX 128000
  20. #define MAX6621_TEMP_ALERT_CHAN_SHIFT 1
  21. #define MAX6621_TEMP_S0D0_REG 0x00
  22. #define MAX6621_TEMP_S0D1_REG 0x01
  23. #define MAX6621_TEMP_S1D0_REG 0x02
  24. #define MAX6621_TEMP_S1D1_REG 0x03
  25. #define MAX6621_TEMP_S2D0_REG 0x04
  26. #define MAX6621_TEMP_S2D1_REG 0x05
  27. #define MAX6621_TEMP_S3D0_REG 0x06
  28. #define MAX6621_TEMP_S3D1_REG 0x07
  29. #define MAX6621_TEMP_MAX_REG 0x08
  30. #define MAX6621_TEMP_MAX_ADDR_REG 0x0a
  31. #define MAX6621_TEMP_ALERT_CAUSE_REG 0x0b
  32. #define MAX6621_CONFIG0_REG 0x0c
  33. #define MAX6621_CONFIG1_REG 0x0d
  34. #define MAX6621_CONFIG2_REG 0x0e
  35. #define MAX6621_CONFIG3_REG 0x0f
  36. #define MAX6621_TEMP_S0_ALERT_REG 0x10
  37. #define MAX6621_TEMP_S1_ALERT_REG 0x11
  38. #define MAX6621_TEMP_S2_ALERT_REG 0x12
  39. #define MAX6621_TEMP_S3_ALERT_REG 0x13
  40. #define MAX6621_CLEAR_ALERT_REG 0x15
  41. #define MAX6621_REG_MAX (MAX6621_CLEAR_ALERT_REG + 1)
  42. #define MAX6621_REG_TEMP_SHIFT 0x06
  43. #define MAX6621_ENABLE_TEMP_ALERTS_BIT 4
  44. #define MAX6621_ENABLE_I2C_CRC_BIT 5
  45. #define MAX6621_ENABLE_ALTERNATE_DATA 6
  46. #define MAX6621_ENABLE_LOCKUP_TO 7
  47. #define MAX6621_ENABLE_S0D0_BIT 8
  48. #define MAX6621_ENABLE_S3D1_BIT 15
  49. #define MAX6621_ENABLE_TEMP_ALL GENMASK(MAX6621_ENABLE_S3D1_BIT, \
  50. MAX6621_ENABLE_S0D0_BIT)
  51. #define MAX6621_POLL_DELAY_MASK 0x5
  52. #define MAX6621_CONFIG0_INIT (MAX6621_ENABLE_TEMP_ALL | \
  53. BIT(MAX6621_ENABLE_LOCKUP_TO) | \
  54. BIT(MAX6621_ENABLE_I2C_CRC_BIT) | \
  55. MAX6621_POLL_DELAY_MASK)
  56. #define MAX6621_PECI_BIT_TIME 0x2
  57. #define MAX6621_PECI_RETRY_NUM 0x3
  58. #define MAX6621_CONFIG1_INIT ((MAX6621_PECI_BIT_TIME << 8) | \
  59. MAX6621_PECI_RETRY_NUM)
  60. /* Error codes */
  61. #define MAX6621_TRAN_FAILED 0x8100 /*
  62. * PECI transaction failed for more
  63. * than the configured number of
  64. * consecutive retries.
  65. */
  66. #define MAX6621_POOL_DIS 0x8101 /*
  67. * Polling disabled for requested
  68. * socket/domain.
  69. */
  70. #define MAX6621_POOL_UNCOMPLETE 0x8102 /*
  71. * First poll not yet completed for
  72. * requested socket/domain (on
  73. * startup).
  74. */
  75. #define MAX6621_SD_DIS 0x8103 /*
  76. * Read maximum temperature requested,
  77. * but no sockets/domains enabled or
  78. * all enabled sockets/domains have
  79. * errors; or read maximum temperature
  80. * address requested, but read maximum
  81. * temperature was not called.
  82. */
  83. #define MAX6621_ALERT_DIS 0x8104 /*
  84. * Get alert socket/domain requested,
  85. * but no alert active.
  86. */
  87. #define MAX6621_PECI_ERR_MIN 0x8000 /* Intel spec PECI error min value. */
  88. #define MAX6621_PECI_ERR_MAX 0x80ff /* Intel spec PECI error max value. */
  89. static const u32 max6621_temp_regs[] = {
  90. MAX6621_TEMP_MAX_REG, MAX6621_TEMP_S0D0_REG, MAX6621_TEMP_S1D0_REG,
  91. MAX6621_TEMP_S2D0_REG, MAX6621_TEMP_S3D0_REG, MAX6621_TEMP_S0D1_REG,
  92. MAX6621_TEMP_S1D1_REG, MAX6621_TEMP_S2D1_REG, MAX6621_TEMP_S3D1_REG,
  93. };
  94. static const char *const max6621_temp_labels[] = {
  95. "maximum",
  96. "socket0_0",
  97. "socket1_0",
  98. "socket2_0",
  99. "socket3_0",
  100. "socket0_1",
  101. "socket1_1",
  102. "socket2_1",
  103. "socket3_1",
  104. };
  105. static const int max6621_temp_alert_chan2reg[] = {
  106. MAX6621_TEMP_S0_ALERT_REG,
  107. MAX6621_TEMP_S1_ALERT_REG,
  108. MAX6621_TEMP_S2_ALERT_REG,
  109. MAX6621_TEMP_S3_ALERT_REG,
  110. };
  111. /**
  112. * struct max6621_data - private data:
  113. *
  114. * @client: I2C client;
  115. * @regmap: register map handle;
  116. * @input_chan2reg: mapping from channel to register;
  117. */
  118. struct max6621_data {
  119. struct i2c_client *client;
  120. struct regmap *regmap;
  121. int input_chan2reg[MAX6621_TEMP_INPUT_REG_NUM + 1];
  122. };
  123. static long max6621_temp_mc2reg(long val)
  124. {
  125. return (val / 1000L) << MAX6621_REG_TEMP_SHIFT;
  126. }
  127. static umode_t
  128. max6621_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
  129. int channel)
  130. {
  131. /* Skip channels which are not physically conncted. */
  132. if (((struct max6621_data *)data)->input_chan2reg[channel] < 0)
  133. return 0;
  134. switch (type) {
  135. case hwmon_temp:
  136. switch (attr) {
  137. case hwmon_temp_input:
  138. case hwmon_temp_label:
  139. case hwmon_temp_crit_alarm:
  140. return 0444;
  141. case hwmon_temp_offset:
  142. case hwmon_temp_crit:
  143. return 0644;
  144. default:
  145. break;
  146. }
  147. break;
  148. default:
  149. break;
  150. }
  151. return 0;
  152. }
  153. static int max6621_verify_reg_data(struct device *dev, int regval)
  154. {
  155. if (regval >= MAX6621_PECI_ERR_MIN &&
  156. regval <= MAX6621_PECI_ERR_MAX) {
  157. dev_dbg(dev, "PECI error code - err 0x%04x.\n",
  158. regval);
  159. return -EIO;
  160. }
  161. switch (regval) {
  162. case MAX6621_TRAN_FAILED:
  163. dev_dbg(dev, "PECI transaction failed - err 0x%04x.\n",
  164. regval);
  165. return -EIO;
  166. case MAX6621_POOL_DIS:
  167. dev_dbg(dev, "Polling disabled - err 0x%04x.\n", regval);
  168. return -EOPNOTSUPP;
  169. case MAX6621_POOL_UNCOMPLETE:
  170. dev_dbg(dev, "First poll not completed on startup - err 0x%04x.\n",
  171. regval);
  172. return -EIO;
  173. case MAX6621_SD_DIS:
  174. dev_dbg(dev, "Resource is disabled - err 0x%04x.\n", regval);
  175. return -EOPNOTSUPP;
  176. case MAX6621_ALERT_DIS:
  177. dev_dbg(dev, "No alert active - err 0x%04x.\n", regval);
  178. return -EOPNOTSUPP;
  179. default:
  180. return 0;
  181. }
  182. }
  183. static int
  184. max6621_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
  185. int channel, long *val)
  186. {
  187. struct max6621_data *data = dev_get_drvdata(dev);
  188. u32 regval;
  189. int reg;
  190. s8 temp;
  191. int ret;
  192. switch (type) {
  193. case hwmon_temp:
  194. switch (attr) {
  195. case hwmon_temp_input:
  196. reg = data->input_chan2reg[channel];
  197. ret = regmap_read(data->regmap, reg, &regval);
  198. if (ret)
  199. return ret;
  200. ret = max6621_verify_reg_data(dev, regval);
  201. if (ret)
  202. return ret;
  203. /*
  204. * Bit MAX6621_REG_TEMP_SHIFT represents 1 degree step.
  205. * The temperature is given in two's complement and 8
  206. * bits is used for the register conversion.
  207. */
  208. temp = (regval >> MAX6621_REG_TEMP_SHIFT);
  209. *val = temp * 1000L;
  210. break;
  211. case hwmon_temp_offset:
  212. ret = regmap_read(data->regmap, MAX6621_CONFIG2_REG,
  213. &regval);
  214. if (ret)
  215. return ret;
  216. ret = max6621_verify_reg_data(dev, regval);
  217. if (ret)
  218. return ret;
  219. *val = (regval >> MAX6621_REG_TEMP_SHIFT) *
  220. 1000L;
  221. break;
  222. case hwmon_temp_crit:
  223. channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
  224. reg = max6621_temp_alert_chan2reg[channel];
  225. ret = regmap_read(data->regmap, reg, &regval);
  226. if (ret)
  227. return ret;
  228. ret = max6621_verify_reg_data(dev, regval);
  229. if (ret)
  230. return ret;
  231. *val = regval * 1000L;
  232. break;
  233. case hwmon_temp_crit_alarm:
  234. /*
  235. * Set val to zero to recover the case, when reading
  236. * MAX6621_TEMP_ALERT_CAUSE_REG results in for example
  237. * MAX6621_ALERT_DIS. Reading will return with error,
  238. * but in such case alarm should be returned as 0.
  239. */
  240. *val = 0;
  241. ret = regmap_read(data->regmap,
  242. MAX6621_TEMP_ALERT_CAUSE_REG,
  243. &regval);
  244. if (ret)
  245. return ret;
  246. ret = max6621_verify_reg_data(dev, regval);
  247. if (ret) {
  248. /* Do not report error if alert is disabled. */
  249. if (regval == MAX6621_ALERT_DIS)
  250. return 0;
  251. else
  252. return ret;
  253. }
  254. /*
  255. * Clear the alert automatically, using send-byte
  256. * smbus protocol for clearing alert.
  257. */
  258. if (regval) {
  259. ret = i2c_smbus_write_byte(data->client,
  260. MAX6621_CLEAR_ALERT_REG);
  261. if (ret)
  262. return ret;
  263. }
  264. *val = !!regval;
  265. break;
  266. default:
  267. return -EOPNOTSUPP;
  268. }
  269. break;
  270. default:
  271. return -EOPNOTSUPP;
  272. }
  273. return 0;
  274. }
  275. static int
  276. max6621_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
  277. int channel, long val)
  278. {
  279. struct max6621_data *data = dev_get_drvdata(dev);
  280. u32 reg;
  281. switch (type) {
  282. case hwmon_temp:
  283. switch (attr) {
  284. case hwmon_temp_offset:
  285. /* Clamp to allowed range to prevent overflow. */
  286. val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
  287. MAX6621_TEMP_INPUT_MAX);
  288. val = max6621_temp_mc2reg(val);
  289. return regmap_write(data->regmap,
  290. MAX6621_CONFIG2_REG, val);
  291. case hwmon_temp_crit:
  292. channel -= MAX6621_TEMP_ALERT_CHAN_SHIFT;
  293. reg = max6621_temp_alert_chan2reg[channel];
  294. /* Clamp to allowed range to prevent overflow. */
  295. val = clamp_val(val, MAX6621_TEMP_INPUT_MIN,
  296. MAX6621_TEMP_INPUT_MAX);
  297. val = val / 1000L;
  298. return regmap_write(data->regmap, reg, val);
  299. default:
  300. return -EOPNOTSUPP;
  301. }
  302. break;
  303. default:
  304. return -EOPNOTSUPP;
  305. }
  306. return -EOPNOTSUPP;
  307. }
  308. static int
  309. max6621_read_string(struct device *dev, enum hwmon_sensor_types type, u32 attr,
  310. int channel, const char **str)
  311. {
  312. switch (type) {
  313. case hwmon_temp:
  314. switch (attr) {
  315. case hwmon_temp_label:
  316. *str = max6621_temp_labels[channel];
  317. return 0;
  318. default:
  319. return -EOPNOTSUPP;
  320. }
  321. break;
  322. default:
  323. return -EOPNOTSUPP;
  324. }
  325. return -EOPNOTSUPP;
  326. }
  327. static bool max6621_writeable_reg(struct device *dev, unsigned int reg)
  328. {
  329. switch (reg) {
  330. case MAX6621_CONFIG0_REG:
  331. case MAX6621_CONFIG1_REG:
  332. case MAX6621_CONFIG2_REG:
  333. case MAX6621_CONFIG3_REG:
  334. case MAX6621_TEMP_S0_ALERT_REG:
  335. case MAX6621_TEMP_S1_ALERT_REG:
  336. case MAX6621_TEMP_S2_ALERT_REG:
  337. case MAX6621_TEMP_S3_ALERT_REG:
  338. case MAX6621_TEMP_ALERT_CAUSE_REG:
  339. return true;
  340. }
  341. return false;
  342. }
  343. static bool max6621_readable_reg(struct device *dev, unsigned int reg)
  344. {
  345. switch (reg) {
  346. case MAX6621_TEMP_S0D0_REG:
  347. case MAX6621_TEMP_S0D1_REG:
  348. case MAX6621_TEMP_S1D0_REG:
  349. case MAX6621_TEMP_S1D1_REG:
  350. case MAX6621_TEMP_S2D0_REG:
  351. case MAX6621_TEMP_S2D1_REG:
  352. case MAX6621_TEMP_S3D0_REG:
  353. case MAX6621_TEMP_S3D1_REG:
  354. case MAX6621_TEMP_MAX_REG:
  355. case MAX6621_TEMP_MAX_ADDR_REG:
  356. case MAX6621_CONFIG0_REG:
  357. case MAX6621_CONFIG1_REG:
  358. case MAX6621_CONFIG2_REG:
  359. case MAX6621_CONFIG3_REG:
  360. case MAX6621_TEMP_S0_ALERT_REG:
  361. case MAX6621_TEMP_S1_ALERT_REG:
  362. case MAX6621_TEMP_S2_ALERT_REG:
  363. case MAX6621_TEMP_S3_ALERT_REG:
  364. return true;
  365. }
  366. return false;
  367. }
  368. static bool max6621_volatile_reg(struct device *dev, unsigned int reg)
  369. {
  370. switch (reg) {
  371. case MAX6621_TEMP_S0D0_REG:
  372. case MAX6621_TEMP_S0D1_REG:
  373. case MAX6621_TEMP_S1D0_REG:
  374. case MAX6621_TEMP_S1D1_REG:
  375. case MAX6621_TEMP_S2D0_REG:
  376. case MAX6621_TEMP_S2D1_REG:
  377. case MAX6621_TEMP_S3D0_REG:
  378. case MAX6621_TEMP_S3D1_REG:
  379. case MAX6621_TEMP_MAX_REG:
  380. case MAX6621_TEMP_S0_ALERT_REG:
  381. case MAX6621_TEMP_S1_ALERT_REG:
  382. case MAX6621_TEMP_S2_ALERT_REG:
  383. case MAX6621_TEMP_S3_ALERT_REG:
  384. case MAX6621_TEMP_ALERT_CAUSE_REG:
  385. return true;
  386. }
  387. return false;
  388. }
  389. static const struct reg_default max6621_regmap_default[] = {
  390. { MAX6621_CONFIG0_REG, MAX6621_CONFIG0_INIT },
  391. { MAX6621_CONFIG1_REG, MAX6621_CONFIG1_INIT },
  392. };
  393. static const struct regmap_config max6621_regmap_config = {
  394. .reg_bits = 8,
  395. .val_bits = 16,
  396. .max_register = MAX6621_REG_MAX,
  397. .val_format_endian = REGMAP_ENDIAN_LITTLE,
  398. .cache_type = REGCACHE_FLAT,
  399. .writeable_reg = max6621_writeable_reg,
  400. .readable_reg = max6621_readable_reg,
  401. .volatile_reg = max6621_volatile_reg,
  402. .reg_defaults = max6621_regmap_default,
  403. .num_reg_defaults = ARRAY_SIZE(max6621_regmap_default),
  404. };
  405. static const struct hwmon_channel_info *max6621_info[] = {
  406. HWMON_CHANNEL_INFO(chip,
  407. HWMON_C_REGISTER_TZ),
  408. HWMON_CHANNEL_INFO(temp,
  409. HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_OFFSET,
  410. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  411. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  412. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  413. HWMON_T_INPUT | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | HWMON_T_LABEL,
  414. HWMON_T_INPUT | HWMON_T_LABEL,
  415. HWMON_T_INPUT | HWMON_T_LABEL,
  416. HWMON_T_INPUT | HWMON_T_LABEL,
  417. HWMON_T_INPUT | HWMON_T_LABEL),
  418. NULL
  419. };
  420. static const struct hwmon_ops max6621_hwmon_ops = {
  421. .read = max6621_read,
  422. .write = max6621_write,
  423. .read_string = max6621_read_string,
  424. .is_visible = max6621_is_visible,
  425. };
  426. static const struct hwmon_chip_info max6621_chip_info = {
  427. .ops = &max6621_hwmon_ops,
  428. .info = max6621_info,
  429. };
  430. static int max6621_probe(struct i2c_client *client)
  431. {
  432. struct device *dev = &client->dev;
  433. struct max6621_data *data;
  434. struct device *hwmon_dev;
  435. int i;
  436. int ret;
  437. data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
  438. if (!data)
  439. return -ENOMEM;
  440. data->regmap = devm_regmap_init_i2c(client, &max6621_regmap_config);
  441. if (IS_ERR(data->regmap))
  442. return PTR_ERR(data->regmap);
  443. i2c_set_clientdata(client, data);
  444. data->client = client;
  445. /* Set CONFIG0 register masking temperature alerts and PEC. */
  446. ret = regmap_write(data->regmap, MAX6621_CONFIG0_REG,
  447. MAX6621_CONFIG0_INIT);
  448. if (ret)
  449. return ret;
  450. /* Set CONFIG1 register for PEC access retry number. */
  451. ret = regmap_write(data->regmap, MAX6621_CONFIG1_REG,
  452. MAX6621_CONFIG1_INIT);
  453. if (ret)
  454. return ret;
  455. /* Sync registers with hardware. */
  456. regcache_mark_dirty(data->regmap);
  457. ret = regcache_sync(data->regmap);
  458. if (ret)
  459. return ret;
  460. /* Verify which temperature input registers are enabled. */
  461. for (i = 0; i < MAX6621_TEMP_INPUT_REG_NUM; i++) {
  462. ret = i2c_smbus_read_word_data(client, max6621_temp_regs[i]);
  463. if (ret < 0)
  464. return ret;
  465. ret = max6621_verify_reg_data(dev, ret);
  466. if (ret) {
  467. data->input_chan2reg[i] = -1;
  468. continue;
  469. }
  470. data->input_chan2reg[i] = max6621_temp_regs[i];
  471. }
  472. hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
  473. data,
  474. &max6621_chip_info,
  475. NULL);
  476. return PTR_ERR_OR_ZERO(hwmon_dev);
  477. }
  478. static const struct i2c_device_id max6621_id[] = {
  479. { MAX6621_DRV_NAME, 0 },
  480. { }
  481. };
  482. MODULE_DEVICE_TABLE(i2c, max6621_id);
  483. static const struct of_device_id __maybe_unused max6621_of_match[] = {
  484. { .compatible = "maxim,max6621" },
  485. { }
  486. };
  487. MODULE_DEVICE_TABLE(of, max6621_of_match);
  488. static struct i2c_driver max6621_driver = {
  489. .class = I2C_CLASS_HWMON,
  490. .driver = {
  491. .name = MAX6621_DRV_NAME,
  492. .of_match_table = of_match_ptr(max6621_of_match),
  493. },
  494. .probe_new = max6621_probe,
  495. .id_table = max6621_id,
  496. };
  497. module_i2c_driver(max6621_driver);
  498. MODULE_AUTHOR("Vadim Pasternak <[email protected]>");
  499. MODULE_DESCRIPTION("Driver for Maxim MAX6621");
  500. MODULE_LICENSE("GPL");