max31790.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * max31790.c - Part of lm_sensors, Linux kernel modules for hardware
  4. * monitoring.
  5. *
  6. * (C) 2015 by Il Han <[email protected]>
  7. */
  8. #include <linux/err.h>
  9. #include <linux/hwmon.h>
  10. #include <linux/i2c.h>
  11. #include <linux/init.h>
  12. #include <linux/jiffies.h>
  13. #include <linux/module.h>
  14. #include <linux/slab.h>
  15. /* MAX31790 registers */
  16. #define MAX31790_REG_GLOBAL_CONFIG 0x00
  17. #define MAX31790_REG_FAN_CONFIG(ch) (0x02 + (ch))
  18. #define MAX31790_REG_FAN_DYNAMICS(ch) (0x08 + (ch))
  19. #define MAX31790_REG_FAN_FAULT_STATUS2 0x10
  20. #define MAX31790_REG_FAN_FAULT_STATUS1 0x11
  21. #define MAX31790_REG_TACH_COUNT(ch) (0x18 + (ch) * 2)
  22. #define MAX31790_REG_PWM_DUTY_CYCLE(ch) (0x30 + (ch) * 2)
  23. #define MAX31790_REG_PWMOUT(ch) (0x40 + (ch) * 2)
  24. #define MAX31790_REG_TARGET_COUNT(ch) (0x50 + (ch) * 2)
  25. /* Fan Config register bits */
  26. #define MAX31790_FAN_CFG_RPM_MODE 0x80
  27. #define MAX31790_FAN_CFG_CTRL_MON 0x10
  28. #define MAX31790_FAN_CFG_TACH_INPUT_EN 0x08
  29. #define MAX31790_FAN_CFG_TACH_INPUT 0x01
  30. /* Fan Dynamics register bits */
  31. #define MAX31790_FAN_DYN_SR_SHIFT 5
  32. #define MAX31790_FAN_DYN_SR_MASK 0xE0
  33. #define SR_FROM_REG(reg) (((reg) & MAX31790_FAN_DYN_SR_MASK) \
  34. >> MAX31790_FAN_DYN_SR_SHIFT)
  35. #define FAN_RPM_MIN 120
  36. #define FAN_RPM_MAX 7864320
  37. #define FAN_COUNT_REG_MAX 0xffe0
  38. #define RPM_FROM_REG(reg, sr) (((reg) >> 4) ? \
  39. ((60 * (sr) * 8192) / ((reg) >> 4)) : \
  40. FAN_RPM_MAX)
  41. #define RPM_TO_REG(rpm, sr) ((60 * (sr) * 8192) / ((rpm) * 2))
  42. #define NR_CHANNEL 6
  43. /*
  44. * Client data (each client gets its own)
  45. */
  46. struct max31790_data {
  47. struct i2c_client *client;
  48. struct mutex update_lock;
  49. bool valid; /* zero until following fields are valid */
  50. unsigned long last_updated; /* in jiffies */
  51. /* register values */
  52. u8 fan_config[NR_CHANNEL];
  53. u8 fan_dynamics[NR_CHANNEL];
  54. u16 fault_status;
  55. u16 tach[NR_CHANNEL * 2];
  56. u16 pwm[NR_CHANNEL];
  57. u16 target_count[NR_CHANNEL];
  58. };
  59. static struct max31790_data *max31790_update_device(struct device *dev)
  60. {
  61. struct max31790_data *data = dev_get_drvdata(dev);
  62. struct i2c_client *client = data->client;
  63. struct max31790_data *ret = data;
  64. int i;
  65. int rv;
  66. mutex_lock(&data->update_lock);
  67. if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
  68. rv = i2c_smbus_read_byte_data(client,
  69. MAX31790_REG_FAN_FAULT_STATUS1);
  70. if (rv < 0)
  71. goto abort;
  72. data->fault_status |= rv & 0x3F;
  73. rv = i2c_smbus_read_byte_data(client,
  74. MAX31790_REG_FAN_FAULT_STATUS2);
  75. if (rv < 0)
  76. goto abort;
  77. data->fault_status |= (rv & 0x3F) << 6;
  78. for (i = 0; i < NR_CHANNEL; i++) {
  79. rv = i2c_smbus_read_word_swapped(client,
  80. MAX31790_REG_TACH_COUNT(i));
  81. if (rv < 0)
  82. goto abort;
  83. data->tach[i] = rv;
  84. if (data->fan_config[i]
  85. & MAX31790_FAN_CFG_TACH_INPUT) {
  86. rv = i2c_smbus_read_word_swapped(client,
  87. MAX31790_REG_TACH_COUNT(NR_CHANNEL
  88. + i));
  89. if (rv < 0)
  90. goto abort;
  91. data->tach[NR_CHANNEL + i] = rv;
  92. } else {
  93. rv = i2c_smbus_read_word_swapped(client,
  94. MAX31790_REG_PWM_DUTY_CYCLE(i));
  95. if (rv < 0)
  96. goto abort;
  97. data->pwm[i] = rv;
  98. rv = i2c_smbus_read_word_swapped(client,
  99. MAX31790_REG_TARGET_COUNT(i));
  100. if (rv < 0)
  101. goto abort;
  102. data->target_count[i] = rv;
  103. }
  104. }
  105. data->last_updated = jiffies;
  106. data->valid = true;
  107. }
  108. goto done;
  109. abort:
  110. data->valid = false;
  111. ret = ERR_PTR(rv);
  112. done:
  113. mutex_unlock(&data->update_lock);
  114. return ret;
  115. }
  116. static const u8 tach_period[8] = { 1, 2, 4, 8, 16, 32, 32, 32 };
  117. static u8 get_tach_period(u8 fan_dynamics)
  118. {
  119. return tach_period[SR_FROM_REG(fan_dynamics)];
  120. }
  121. static u8 bits_for_tach_period(int rpm)
  122. {
  123. u8 bits;
  124. if (rpm < 500)
  125. bits = 0x0;
  126. else if (rpm < 1000)
  127. bits = 0x1;
  128. else if (rpm < 2000)
  129. bits = 0x2;
  130. else if (rpm < 4000)
  131. bits = 0x3;
  132. else if (rpm < 8000)
  133. bits = 0x4;
  134. else
  135. bits = 0x5;
  136. return bits;
  137. }
  138. static int max31790_read_fan(struct device *dev, u32 attr, int channel,
  139. long *val)
  140. {
  141. struct max31790_data *data = max31790_update_device(dev);
  142. int sr, rpm;
  143. if (IS_ERR(data))
  144. return PTR_ERR(data);
  145. switch (attr) {
  146. case hwmon_fan_input:
  147. sr = get_tach_period(data->fan_dynamics[channel % NR_CHANNEL]);
  148. if (data->tach[channel] == FAN_COUNT_REG_MAX)
  149. rpm = 0;
  150. else
  151. rpm = RPM_FROM_REG(data->tach[channel], sr);
  152. *val = rpm;
  153. return 0;
  154. case hwmon_fan_target:
  155. sr = get_tach_period(data->fan_dynamics[channel]);
  156. rpm = RPM_FROM_REG(data->target_count[channel], sr);
  157. *val = rpm;
  158. return 0;
  159. case hwmon_fan_fault:
  160. mutex_lock(&data->update_lock);
  161. *val = !!(data->fault_status & (1 << channel));
  162. data->fault_status &= ~(1 << channel);
  163. /*
  164. * If a fault bit is set, we need to write into one of the fan
  165. * configuration registers to clear it. Note that this also
  166. * clears the fault for the companion channel if enabled.
  167. */
  168. if (*val) {
  169. int reg = MAX31790_REG_TARGET_COUNT(channel % NR_CHANNEL);
  170. i2c_smbus_write_byte_data(data->client, reg,
  171. data->target_count[channel % NR_CHANNEL] >> 8);
  172. }
  173. mutex_unlock(&data->update_lock);
  174. return 0;
  175. case hwmon_fan_enable:
  176. *val = !!(data->fan_config[channel] & MAX31790_FAN_CFG_TACH_INPUT_EN);
  177. return 0;
  178. default:
  179. return -EOPNOTSUPP;
  180. }
  181. }
  182. static int max31790_write_fan(struct device *dev, u32 attr, int channel,
  183. long val)
  184. {
  185. struct max31790_data *data = dev_get_drvdata(dev);
  186. struct i2c_client *client = data->client;
  187. int target_count;
  188. int err = 0;
  189. u8 bits, fan_config;
  190. int sr;
  191. mutex_lock(&data->update_lock);
  192. switch (attr) {
  193. case hwmon_fan_target:
  194. val = clamp_val(val, FAN_RPM_MIN, FAN_RPM_MAX);
  195. bits = bits_for_tach_period(val);
  196. data->fan_dynamics[channel] =
  197. ((data->fan_dynamics[channel] &
  198. ~MAX31790_FAN_DYN_SR_MASK) |
  199. (bits << MAX31790_FAN_DYN_SR_SHIFT));
  200. err = i2c_smbus_write_byte_data(client,
  201. MAX31790_REG_FAN_DYNAMICS(channel),
  202. data->fan_dynamics[channel]);
  203. if (err < 0)
  204. break;
  205. sr = get_tach_period(data->fan_dynamics[channel]);
  206. target_count = RPM_TO_REG(val, sr);
  207. target_count = clamp_val(target_count, 0x1, 0x7FF);
  208. data->target_count[channel] = target_count << 5;
  209. err = i2c_smbus_write_word_swapped(client,
  210. MAX31790_REG_TARGET_COUNT(channel),
  211. data->target_count[channel]);
  212. break;
  213. case hwmon_fan_enable:
  214. fan_config = data->fan_config[channel];
  215. if (val == 0) {
  216. fan_config &= ~MAX31790_FAN_CFG_TACH_INPUT_EN;
  217. } else if (val == 1) {
  218. fan_config |= MAX31790_FAN_CFG_TACH_INPUT_EN;
  219. } else {
  220. err = -EINVAL;
  221. break;
  222. }
  223. if (fan_config != data->fan_config[channel]) {
  224. err = i2c_smbus_write_byte_data(client, MAX31790_REG_FAN_CONFIG(channel),
  225. fan_config);
  226. if (!err)
  227. data->fan_config[channel] = fan_config;
  228. }
  229. break;
  230. default:
  231. err = -EOPNOTSUPP;
  232. break;
  233. }
  234. mutex_unlock(&data->update_lock);
  235. return err;
  236. }
  237. static umode_t max31790_fan_is_visible(const void *_data, u32 attr, int channel)
  238. {
  239. const struct max31790_data *data = _data;
  240. u8 fan_config = data->fan_config[channel % NR_CHANNEL];
  241. switch (attr) {
  242. case hwmon_fan_input:
  243. case hwmon_fan_fault:
  244. if (channel < NR_CHANNEL ||
  245. (fan_config & MAX31790_FAN_CFG_TACH_INPUT))
  246. return 0444;
  247. return 0;
  248. case hwmon_fan_target:
  249. if (channel < NR_CHANNEL &&
  250. !(fan_config & MAX31790_FAN_CFG_TACH_INPUT))
  251. return 0644;
  252. return 0;
  253. case hwmon_fan_enable:
  254. if (channel < NR_CHANNEL)
  255. return 0644;
  256. return 0;
  257. default:
  258. return 0;
  259. }
  260. }
  261. static int max31790_read_pwm(struct device *dev, u32 attr, int channel,
  262. long *val)
  263. {
  264. struct max31790_data *data = max31790_update_device(dev);
  265. u8 fan_config;
  266. if (IS_ERR(data))
  267. return PTR_ERR(data);
  268. fan_config = data->fan_config[channel];
  269. switch (attr) {
  270. case hwmon_pwm_input:
  271. *val = data->pwm[channel] >> 8;
  272. return 0;
  273. case hwmon_pwm_enable:
  274. if (fan_config & MAX31790_FAN_CFG_CTRL_MON)
  275. *val = 0;
  276. else if (fan_config & MAX31790_FAN_CFG_RPM_MODE)
  277. *val = 2;
  278. else
  279. *val = 1;
  280. return 0;
  281. default:
  282. return -EOPNOTSUPP;
  283. }
  284. }
  285. static int max31790_write_pwm(struct device *dev, u32 attr, int channel,
  286. long val)
  287. {
  288. struct max31790_data *data = dev_get_drvdata(dev);
  289. struct i2c_client *client = data->client;
  290. u8 fan_config;
  291. int err = 0;
  292. mutex_lock(&data->update_lock);
  293. switch (attr) {
  294. case hwmon_pwm_input:
  295. if (val < 0 || val > 255) {
  296. err = -EINVAL;
  297. break;
  298. }
  299. data->valid = false;
  300. err = i2c_smbus_write_word_swapped(client,
  301. MAX31790_REG_PWMOUT(channel),
  302. val << 8);
  303. break;
  304. case hwmon_pwm_enable:
  305. fan_config = data->fan_config[channel];
  306. if (val == 0) {
  307. fan_config |= MAX31790_FAN_CFG_CTRL_MON;
  308. /*
  309. * Disable RPM mode; otherwise disabling fan speed
  310. * monitoring is not possible.
  311. */
  312. fan_config &= ~MAX31790_FAN_CFG_RPM_MODE;
  313. } else if (val == 1) {
  314. fan_config &= ~(MAX31790_FAN_CFG_CTRL_MON | MAX31790_FAN_CFG_RPM_MODE);
  315. } else if (val == 2) {
  316. fan_config &= ~MAX31790_FAN_CFG_CTRL_MON;
  317. /*
  318. * The chip sets MAX31790_FAN_CFG_TACH_INPUT_EN on its
  319. * own if MAX31790_FAN_CFG_RPM_MODE is set.
  320. * Do it here as well to reflect the actual register
  321. * value in the cache.
  322. */
  323. fan_config |= (MAX31790_FAN_CFG_RPM_MODE | MAX31790_FAN_CFG_TACH_INPUT_EN);
  324. } else {
  325. err = -EINVAL;
  326. break;
  327. }
  328. if (fan_config != data->fan_config[channel]) {
  329. err = i2c_smbus_write_byte_data(client, MAX31790_REG_FAN_CONFIG(channel),
  330. fan_config);
  331. if (!err)
  332. data->fan_config[channel] = fan_config;
  333. }
  334. break;
  335. default:
  336. err = -EOPNOTSUPP;
  337. break;
  338. }
  339. mutex_unlock(&data->update_lock);
  340. return err;
  341. }
  342. static umode_t max31790_pwm_is_visible(const void *_data, u32 attr, int channel)
  343. {
  344. const struct max31790_data *data = _data;
  345. u8 fan_config = data->fan_config[channel];
  346. switch (attr) {
  347. case hwmon_pwm_input:
  348. case hwmon_pwm_enable:
  349. if (!(fan_config & MAX31790_FAN_CFG_TACH_INPUT))
  350. return 0644;
  351. return 0;
  352. default:
  353. return 0;
  354. }
  355. }
  356. static int max31790_read(struct device *dev, enum hwmon_sensor_types type,
  357. u32 attr, int channel, long *val)
  358. {
  359. switch (type) {
  360. case hwmon_fan:
  361. return max31790_read_fan(dev, attr, channel, val);
  362. case hwmon_pwm:
  363. return max31790_read_pwm(dev, attr, channel, val);
  364. default:
  365. return -EOPNOTSUPP;
  366. }
  367. }
  368. static int max31790_write(struct device *dev, enum hwmon_sensor_types type,
  369. u32 attr, int channel, long val)
  370. {
  371. switch (type) {
  372. case hwmon_fan:
  373. return max31790_write_fan(dev, attr, channel, val);
  374. case hwmon_pwm:
  375. return max31790_write_pwm(dev, attr, channel, val);
  376. default:
  377. return -EOPNOTSUPP;
  378. }
  379. }
  380. static umode_t max31790_is_visible(const void *data,
  381. enum hwmon_sensor_types type,
  382. u32 attr, int channel)
  383. {
  384. switch (type) {
  385. case hwmon_fan:
  386. return max31790_fan_is_visible(data, attr, channel);
  387. case hwmon_pwm:
  388. return max31790_pwm_is_visible(data, attr, channel);
  389. default:
  390. return 0;
  391. }
  392. }
  393. static const struct hwmon_channel_info *max31790_info[] = {
  394. HWMON_CHANNEL_INFO(fan,
  395. HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_FAULT | HWMON_F_ENABLE,
  396. HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_FAULT | HWMON_F_ENABLE,
  397. HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_FAULT | HWMON_F_ENABLE,
  398. HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_FAULT | HWMON_F_ENABLE,
  399. HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_FAULT | HWMON_F_ENABLE,
  400. HWMON_F_INPUT | HWMON_F_TARGET | HWMON_F_FAULT | HWMON_F_ENABLE,
  401. HWMON_F_INPUT | HWMON_F_FAULT,
  402. HWMON_F_INPUT | HWMON_F_FAULT,
  403. HWMON_F_INPUT | HWMON_F_FAULT,
  404. HWMON_F_INPUT | HWMON_F_FAULT,
  405. HWMON_F_INPUT | HWMON_F_FAULT,
  406. HWMON_F_INPUT | HWMON_F_FAULT),
  407. HWMON_CHANNEL_INFO(pwm,
  408. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  409. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  410. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  411. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  412. HWMON_PWM_INPUT | HWMON_PWM_ENABLE,
  413. HWMON_PWM_INPUT | HWMON_PWM_ENABLE),
  414. NULL
  415. };
  416. static const struct hwmon_ops max31790_hwmon_ops = {
  417. .is_visible = max31790_is_visible,
  418. .read = max31790_read,
  419. .write = max31790_write,
  420. };
  421. static const struct hwmon_chip_info max31790_chip_info = {
  422. .ops = &max31790_hwmon_ops,
  423. .info = max31790_info,
  424. };
  425. static int max31790_init_client(struct i2c_client *client,
  426. struct max31790_data *data)
  427. {
  428. int i, rv;
  429. for (i = 0; i < NR_CHANNEL; i++) {
  430. rv = i2c_smbus_read_byte_data(client,
  431. MAX31790_REG_FAN_CONFIG(i));
  432. if (rv < 0)
  433. return rv;
  434. data->fan_config[i] = rv;
  435. rv = i2c_smbus_read_byte_data(client,
  436. MAX31790_REG_FAN_DYNAMICS(i));
  437. if (rv < 0)
  438. return rv;
  439. data->fan_dynamics[i] = rv;
  440. }
  441. return 0;
  442. }
  443. static int max31790_probe(struct i2c_client *client)
  444. {
  445. struct i2c_adapter *adapter = client->adapter;
  446. struct device *dev = &client->dev;
  447. struct max31790_data *data;
  448. struct device *hwmon_dev;
  449. int err;
  450. if (!i2c_check_functionality(adapter,
  451. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA))
  452. return -ENODEV;
  453. data = devm_kzalloc(dev, sizeof(struct max31790_data), GFP_KERNEL);
  454. if (!data)
  455. return -ENOMEM;
  456. data->client = client;
  457. mutex_init(&data->update_lock);
  458. /*
  459. * Initialize the max31790 chip
  460. */
  461. err = max31790_init_client(client, data);
  462. if (err)
  463. return err;
  464. hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name,
  465. data,
  466. &max31790_chip_info,
  467. NULL);
  468. return PTR_ERR_OR_ZERO(hwmon_dev);
  469. }
  470. static const struct i2c_device_id max31790_id[] = {
  471. { "max31790", 0 },
  472. { }
  473. };
  474. MODULE_DEVICE_TABLE(i2c, max31790_id);
  475. static struct i2c_driver max31790_driver = {
  476. .class = I2C_CLASS_HWMON,
  477. .probe_new = max31790_probe,
  478. .driver = {
  479. .name = "max31790",
  480. },
  481. .id_table = max31790_id,
  482. };
  483. module_i2c_driver(max31790_driver);
  484. MODULE_AUTHOR("Il Han <[email protected]>");
  485. MODULE_DESCRIPTION("MAX31790 sensor driver");
  486. MODULE_LICENSE("GPL");