ltc2992.c 24 KB

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  1. // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2. /*
  3. * LTC2992 - Dual Wide Range Power Monitor
  4. *
  5. * Copyright 2020 Analog Devices Inc.
  6. */
  7. #include <linux/bitfield.h>
  8. #include <linux/bitops.h>
  9. #include <linux/err.h>
  10. #include <linux/gpio/driver.h>
  11. #include <linux/hwmon.h>
  12. #include <linux/i2c.h>
  13. #include <linux/kernel.h>
  14. #include <linux/module.h>
  15. #include <linux/property.h>
  16. #include <linux/regmap.h>
  17. #define LTC2992_CTRLB 0x01
  18. #define LTC2992_FAULT1 0x03
  19. #define LTC2992_POWER1 0x05
  20. #define LTC2992_POWER1_MAX 0x08
  21. #define LTC2992_POWER1_MIN 0x0B
  22. #define LTC2992_POWER1_MAX_THRESH 0x0E
  23. #define LTC2992_POWER1_MIN_THRESH 0x11
  24. #define LTC2992_DSENSE1 0x14
  25. #define LTC2992_DSENSE1_MAX 0x16
  26. #define LTC2992_DSENSE1_MIN 0x18
  27. #define LTC2992_DSENSE1_MAX_THRESH 0x1A
  28. #define LTC2992_DSENSE1_MIN_THRESH 0x1C
  29. #define LTC2992_SENSE1 0x1E
  30. #define LTC2992_SENSE1_MAX 0x20
  31. #define LTC2992_SENSE1_MIN 0x22
  32. #define LTC2992_SENSE1_MAX_THRESH 0x24
  33. #define LTC2992_SENSE1_MIN_THRESH 0x26
  34. #define LTC2992_G1 0x28
  35. #define LTC2992_G1_MAX 0x2A
  36. #define LTC2992_G1_MIN 0x2C
  37. #define LTC2992_G1_MAX_THRESH 0x2E
  38. #define LTC2992_G1_MIN_THRESH 0x30
  39. #define LTC2992_FAULT2 0x35
  40. #define LTC2992_G2 0x5A
  41. #define LTC2992_G2_MAX 0x5C
  42. #define LTC2992_G2_MIN 0x5E
  43. #define LTC2992_G2_MAX_THRESH 0x60
  44. #define LTC2992_G2_MIN_THRESH 0x62
  45. #define LTC2992_G3 0x64
  46. #define LTC2992_G3_MAX 0x66
  47. #define LTC2992_G3_MIN 0x68
  48. #define LTC2992_G3_MAX_THRESH 0x6A
  49. #define LTC2992_G3_MIN_THRESH 0x6C
  50. #define LTC2992_G4 0x6E
  51. #define LTC2992_G4_MAX 0x70
  52. #define LTC2992_G4_MIN 0x72
  53. #define LTC2992_G4_MAX_THRESH 0x74
  54. #define LTC2992_G4_MIN_THRESH 0x76
  55. #define LTC2992_FAULT3 0x92
  56. #define LTC2992_GPIO_STATUS 0x95
  57. #define LTC2992_GPIO_IO_CTRL 0x96
  58. #define LTC2992_GPIO_CTRL 0x97
  59. #define LTC2992_POWER(x) (LTC2992_POWER1 + ((x) * 0x32))
  60. #define LTC2992_POWER_MAX(x) (LTC2992_POWER1_MAX + ((x) * 0x32))
  61. #define LTC2992_POWER_MIN(x) (LTC2992_POWER1_MIN + ((x) * 0x32))
  62. #define LTC2992_POWER_MAX_THRESH(x) (LTC2992_POWER1_MAX_THRESH + ((x) * 0x32))
  63. #define LTC2992_POWER_MIN_THRESH(x) (LTC2992_POWER1_MIN_THRESH + ((x) * 0x32))
  64. #define LTC2992_DSENSE(x) (LTC2992_DSENSE1 + ((x) * 0x32))
  65. #define LTC2992_DSENSE_MAX(x) (LTC2992_DSENSE1_MAX + ((x) * 0x32))
  66. #define LTC2992_DSENSE_MIN(x) (LTC2992_DSENSE1_MIN + ((x) * 0x32))
  67. #define LTC2992_DSENSE_MAX_THRESH(x) (LTC2992_DSENSE1_MAX_THRESH + ((x) * 0x32))
  68. #define LTC2992_DSENSE_MIN_THRESH(x) (LTC2992_DSENSE1_MIN_THRESH + ((x) * 0x32))
  69. #define LTC2992_SENSE(x) (LTC2992_SENSE1 + ((x) * 0x32))
  70. #define LTC2992_SENSE_MAX(x) (LTC2992_SENSE1_MAX + ((x) * 0x32))
  71. #define LTC2992_SENSE_MIN(x) (LTC2992_SENSE1_MIN + ((x) * 0x32))
  72. #define LTC2992_SENSE_MAX_THRESH(x) (LTC2992_SENSE1_MAX_THRESH + ((x) * 0x32))
  73. #define LTC2992_SENSE_MIN_THRESH(x) (LTC2992_SENSE1_MIN_THRESH + ((x) * 0x32))
  74. #define LTC2992_POWER_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
  75. #define LTC2992_SENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
  76. #define LTC2992_DSENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
  77. /* CTRLB register bitfields */
  78. #define LTC2992_RESET_HISTORY BIT(3)
  79. /* FAULT1 FAULT2 registers common bitfields */
  80. #define LTC2992_POWER_FAULT_MSK(x) (BIT(6) << (x))
  81. #define LTC2992_DSENSE_FAULT_MSK(x) (BIT(4) << (x))
  82. #define LTC2992_SENSE_FAULT_MSK(x) (BIT(2) << (x))
  83. /* FAULT1 bitfields */
  84. #define LTC2992_GPIO1_FAULT_MSK(x) (BIT(0) << (x))
  85. /* FAULT2 bitfields */
  86. #define LTC2992_GPIO2_FAULT_MSK(x) (BIT(0) << (x))
  87. /* FAULT3 bitfields */
  88. #define LTC2992_GPIO3_FAULT_MSK(x) (BIT(6) << (x))
  89. #define LTC2992_GPIO4_FAULT_MSK(x) (BIT(4) << (x))
  90. #define LTC2992_IADC_NANOV_LSB 12500
  91. #define LTC2992_VADC_UV_LSB 25000
  92. #define LTC2992_VADC_GPIO_UV_LSB 500
  93. #define LTC2992_GPIO_NR 4
  94. #define LTC2992_GPIO1_BIT 7
  95. #define LTC2992_GPIO2_BIT 6
  96. #define LTC2992_GPIO3_BIT 0
  97. #define LTC2992_GPIO4_BIT 6
  98. #define LTC2992_GPIO_BIT(x) (LTC2992_GPIO_NR - (x) - 1)
  99. struct ltc2992_state {
  100. struct i2c_client *client;
  101. struct gpio_chip gc;
  102. struct mutex gpio_mutex; /* lock for gpio access */
  103. const char *gpio_names[LTC2992_GPIO_NR];
  104. struct regmap *regmap;
  105. u32 r_sense_uohm[2];
  106. };
  107. struct ltc2992_gpio_regs {
  108. u8 data;
  109. u8 max;
  110. u8 min;
  111. u8 max_thresh;
  112. u8 min_thresh;
  113. u8 alarm;
  114. u8 min_alarm_msk;
  115. u8 max_alarm_msk;
  116. u8 ctrl;
  117. u8 ctrl_bit;
  118. };
  119. static const struct ltc2992_gpio_regs ltc2992_gpio_addr_map[] = {
  120. {
  121. .data = LTC2992_G1,
  122. .max = LTC2992_G1_MAX,
  123. .min = LTC2992_G1_MIN,
  124. .max_thresh = LTC2992_G1_MAX_THRESH,
  125. .min_thresh = LTC2992_G1_MIN_THRESH,
  126. .alarm = LTC2992_FAULT1,
  127. .min_alarm_msk = LTC2992_GPIO1_FAULT_MSK(0),
  128. .max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
  129. .ctrl = LTC2992_GPIO_IO_CTRL,
  130. .ctrl_bit = LTC2992_GPIO1_BIT,
  131. },
  132. {
  133. .data = LTC2992_G2,
  134. .max = LTC2992_G2_MAX,
  135. .min = LTC2992_G2_MIN,
  136. .max_thresh = LTC2992_G2_MAX_THRESH,
  137. .min_thresh = LTC2992_G2_MIN_THRESH,
  138. .alarm = LTC2992_FAULT2,
  139. .min_alarm_msk = LTC2992_GPIO2_FAULT_MSK(0),
  140. .max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
  141. .ctrl = LTC2992_GPIO_IO_CTRL,
  142. .ctrl_bit = LTC2992_GPIO2_BIT,
  143. },
  144. {
  145. .data = LTC2992_G3,
  146. .max = LTC2992_G3_MAX,
  147. .min = LTC2992_G3_MIN,
  148. .max_thresh = LTC2992_G3_MAX_THRESH,
  149. .min_thresh = LTC2992_G3_MIN_THRESH,
  150. .alarm = LTC2992_FAULT3,
  151. .min_alarm_msk = LTC2992_GPIO3_FAULT_MSK(0),
  152. .max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
  153. .ctrl = LTC2992_GPIO_IO_CTRL,
  154. .ctrl_bit = LTC2992_GPIO3_BIT,
  155. },
  156. {
  157. .data = LTC2992_G4,
  158. .max = LTC2992_G4_MAX,
  159. .min = LTC2992_G4_MIN,
  160. .max_thresh = LTC2992_G4_MAX_THRESH,
  161. .min_thresh = LTC2992_G4_MIN_THRESH,
  162. .alarm = LTC2992_FAULT3,
  163. .min_alarm_msk = LTC2992_GPIO4_FAULT_MSK(0),
  164. .max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
  165. .ctrl = LTC2992_GPIO_CTRL,
  166. .ctrl_bit = LTC2992_GPIO4_BIT,
  167. },
  168. };
  169. static const char *ltc2992_gpio_names[LTC2992_GPIO_NR] = {
  170. "GPIO1", "GPIO2", "GPIO3", "GPIO4",
  171. };
  172. static int ltc2992_read_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len)
  173. {
  174. u8 regvals[4];
  175. int val;
  176. int ret;
  177. int i;
  178. ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len);
  179. if (ret < 0)
  180. return ret;
  181. val = 0;
  182. for (i = 0; i < reg_len; i++)
  183. val |= regvals[reg_len - i - 1] << (i * 8);
  184. return val;
  185. }
  186. static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
  187. {
  188. u8 regvals[4];
  189. int i;
  190. for (i = 0; i < reg_len; i++)
  191. regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF;
  192. return regmap_bulk_write(st->regmap, addr, regvals, reg_len);
  193. }
  194. static int ltc2992_gpio_get(struct gpio_chip *chip, unsigned int offset)
  195. {
  196. struct ltc2992_state *st = gpiochip_get_data(chip);
  197. unsigned long gpio_status;
  198. int reg;
  199. mutex_lock(&st->gpio_mutex);
  200. reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
  201. mutex_unlock(&st->gpio_mutex);
  202. if (reg < 0)
  203. return reg;
  204. gpio_status = reg;
  205. return !test_bit(LTC2992_GPIO_BIT(offset), &gpio_status);
  206. }
  207. static int ltc2992_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
  208. unsigned long *bits)
  209. {
  210. struct ltc2992_state *st = gpiochip_get_data(chip);
  211. unsigned long gpio_status;
  212. unsigned int gpio_nr;
  213. int reg;
  214. mutex_lock(&st->gpio_mutex);
  215. reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
  216. mutex_unlock(&st->gpio_mutex);
  217. if (reg < 0)
  218. return reg;
  219. gpio_status = reg;
  220. for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
  221. if (test_bit(LTC2992_GPIO_BIT(gpio_nr), &gpio_status))
  222. set_bit(gpio_nr, bits);
  223. }
  224. return 0;
  225. }
  226. static void ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
  227. {
  228. struct ltc2992_state *st = gpiochip_get_data(chip);
  229. unsigned long gpio_ctrl;
  230. int reg;
  231. mutex_lock(&st->gpio_mutex);
  232. reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1);
  233. if (reg < 0) {
  234. mutex_unlock(&st->gpio_mutex);
  235. return;
  236. }
  237. gpio_ctrl = reg;
  238. assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value);
  239. ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1, gpio_ctrl);
  240. mutex_unlock(&st->gpio_mutex);
  241. }
  242. static void ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
  243. unsigned long *bits)
  244. {
  245. struct ltc2992_state *st = gpiochip_get_data(chip);
  246. unsigned long gpio_ctrl_io = 0;
  247. unsigned long gpio_ctrl = 0;
  248. unsigned int gpio_nr;
  249. for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
  250. if (gpio_nr < 3)
  251. assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true);
  252. if (gpio_nr == 3)
  253. assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true);
  254. }
  255. mutex_lock(&st->gpio_mutex);
  256. ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io);
  257. ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl);
  258. mutex_unlock(&st->gpio_mutex);
  259. }
  260. static int ltc2992_config_gpio(struct ltc2992_state *st)
  261. {
  262. const char *name = dev_name(&st->client->dev);
  263. char *gpio_name;
  264. int ret;
  265. int i;
  266. ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, 0);
  267. if (ret < 0)
  268. return ret;
  269. mutex_init(&st->gpio_mutex);
  270. for (i = 0; i < ARRAY_SIZE(st->gpio_names); i++) {
  271. gpio_name = devm_kasprintf(&st->client->dev, GFP_KERNEL, "ltc2992-%x-%s",
  272. st->client->addr, ltc2992_gpio_names[i]);
  273. if (!gpio_name)
  274. return -ENOMEM;
  275. st->gpio_names[i] = gpio_name;
  276. }
  277. st->gc.label = name;
  278. st->gc.parent = &st->client->dev;
  279. st->gc.owner = THIS_MODULE;
  280. st->gc.can_sleep = true;
  281. st->gc.base = -1;
  282. st->gc.names = st->gpio_names;
  283. st->gc.ngpio = ARRAY_SIZE(st->gpio_names);
  284. st->gc.get = ltc2992_gpio_get;
  285. st->gc.get_multiple = ltc2992_gpio_get_multiple;
  286. st->gc.set = ltc2992_gpio_set;
  287. st->gc.set_multiple = ltc2992_gpio_set_multiple;
  288. ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st);
  289. if (ret)
  290. dev_err(&st->client->dev, "GPIO registering failed (%d)\n", ret);
  291. return ret;
  292. }
  293. static umode_t ltc2992_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
  294. int channel)
  295. {
  296. const struct ltc2992_state *st = data;
  297. switch (type) {
  298. case hwmon_chip:
  299. switch (attr) {
  300. case hwmon_chip_in_reset_history:
  301. return 0200;
  302. }
  303. break;
  304. case hwmon_in:
  305. switch (attr) {
  306. case hwmon_in_input:
  307. case hwmon_in_lowest:
  308. case hwmon_in_highest:
  309. case hwmon_in_min_alarm:
  310. case hwmon_in_max_alarm:
  311. return 0444;
  312. case hwmon_in_min:
  313. case hwmon_in_max:
  314. return 0644;
  315. }
  316. break;
  317. case hwmon_curr:
  318. switch (attr) {
  319. case hwmon_curr_input:
  320. case hwmon_curr_lowest:
  321. case hwmon_curr_highest:
  322. case hwmon_curr_min_alarm:
  323. case hwmon_curr_max_alarm:
  324. if (st->r_sense_uohm[channel])
  325. return 0444;
  326. break;
  327. case hwmon_curr_min:
  328. case hwmon_curr_max:
  329. if (st->r_sense_uohm[channel])
  330. return 0644;
  331. break;
  332. }
  333. break;
  334. case hwmon_power:
  335. switch (attr) {
  336. case hwmon_power_input:
  337. case hwmon_power_input_lowest:
  338. case hwmon_power_input_highest:
  339. case hwmon_power_min_alarm:
  340. case hwmon_power_max_alarm:
  341. if (st->r_sense_uohm[channel])
  342. return 0444;
  343. break;
  344. case hwmon_power_min:
  345. case hwmon_power_max:
  346. if (st->r_sense_uohm[channel])
  347. return 0644;
  348. break;
  349. }
  350. break;
  351. default:
  352. break;
  353. }
  354. return 0;
  355. }
  356. static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
  357. {
  358. int reg_val;
  359. reg_val = ltc2992_read_reg(st, reg, 2);
  360. if (reg_val < 0)
  361. return reg_val;
  362. reg_val = reg_val >> 4;
  363. *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);
  364. return 0;
  365. }
  366. static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
  367. {
  368. val = DIV_ROUND_CLOSEST(val * 1000, scale);
  369. val = val << 4;
  370. return ltc2992_write_reg(st, reg, 2, val);
  371. }
  372. static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
  373. {
  374. int reg_val;
  375. u32 mask;
  376. if (attr == hwmon_in_max_alarm)
  377. mask = ltc2992_gpio_addr_map[nr_gpio].max_alarm_msk;
  378. else
  379. mask = ltc2992_gpio_addr_map[nr_gpio].min_alarm_msk;
  380. reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);
  381. if (reg_val < 0)
  382. return reg_val;
  383. *val = !!(reg_val & mask);
  384. reg_val &= ~mask;
  385. return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);
  386. }
  387. static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
  388. {
  389. struct ltc2992_state *st = dev_get_drvdata(dev);
  390. u32 reg;
  391. switch (attr) {
  392. case hwmon_in_input:
  393. reg = ltc2992_gpio_addr_map[nr_gpio].data;
  394. break;
  395. case hwmon_in_lowest:
  396. reg = ltc2992_gpio_addr_map[nr_gpio].min;
  397. break;
  398. case hwmon_in_highest:
  399. reg = ltc2992_gpio_addr_map[nr_gpio].max;
  400. break;
  401. case hwmon_in_min:
  402. reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
  403. break;
  404. case hwmon_in_max:
  405. reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
  406. break;
  407. case hwmon_in_min_alarm:
  408. case hwmon_in_max_alarm:
  409. return ltc2992_read_gpio_alarm(st, nr_gpio, attr, val);
  410. default:
  411. return -EOPNOTSUPP;
  412. }
  413. return ltc2992_get_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
  414. }
  415. static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
  416. {
  417. int reg_val;
  418. u32 mask;
  419. if (attr == hwmon_in_max_alarm)
  420. mask = LTC2992_SENSE_FAULT_MSK(1);
  421. else
  422. mask = LTC2992_SENSE_FAULT_MSK(0);
  423. reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);
  424. if (reg_val < 0)
  425. return reg_val;
  426. *val = !!(reg_val & mask);
  427. reg_val &= ~mask;
  428. return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);
  429. }
  430. static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
  431. {
  432. struct ltc2992_state *st = dev_get_drvdata(dev);
  433. u32 reg;
  434. if (channel > 1)
  435. return ltc2992_read_gpios_in(dev, attr, channel - 2, val);
  436. switch (attr) {
  437. case hwmon_in_input:
  438. reg = LTC2992_SENSE(channel);
  439. break;
  440. case hwmon_in_lowest:
  441. reg = LTC2992_SENSE_MIN(channel);
  442. break;
  443. case hwmon_in_highest:
  444. reg = LTC2992_SENSE_MAX(channel);
  445. break;
  446. case hwmon_in_min:
  447. reg = LTC2992_SENSE_MIN_THRESH(channel);
  448. break;
  449. case hwmon_in_max:
  450. reg = LTC2992_SENSE_MAX_THRESH(channel);
  451. break;
  452. case hwmon_in_min_alarm:
  453. case hwmon_in_max_alarm:
  454. return ltc2992_read_in_alarm(st, channel, val, attr);
  455. default:
  456. return -EOPNOTSUPP;
  457. }
  458. return ltc2992_get_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
  459. }
  460. static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
  461. {
  462. int reg_val;
  463. reg_val = ltc2992_read_reg(st, reg, 2);
  464. if (reg_val < 0)
  465. return reg_val;
  466. reg_val = reg_val >> 4;
  467. *val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);
  468. return 0;
  469. }
  470. static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
  471. {
  472. u32 reg_val;
  473. reg_val = DIV_ROUND_CLOSEST(val * st->r_sense_uohm[channel], LTC2992_IADC_NANOV_LSB);
  474. reg_val = reg_val << 4;
  475. return ltc2992_write_reg(st, reg, 2, reg_val);
  476. }
  477. static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
  478. {
  479. int reg_val;
  480. u32 mask;
  481. if (attr == hwmon_curr_max_alarm)
  482. mask = LTC2992_DSENSE_FAULT_MSK(1);
  483. else
  484. mask = LTC2992_DSENSE_FAULT_MSK(0);
  485. reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);
  486. if (reg_val < 0)
  487. return reg_val;
  488. *val = !!(reg_val & mask);
  489. reg_val &= ~mask;
  490. return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);
  491. }
  492. static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
  493. {
  494. struct ltc2992_state *st = dev_get_drvdata(dev);
  495. u32 reg;
  496. switch (attr) {
  497. case hwmon_curr_input:
  498. reg = LTC2992_DSENSE(channel);
  499. break;
  500. case hwmon_curr_lowest:
  501. reg = LTC2992_DSENSE_MIN(channel);
  502. break;
  503. case hwmon_curr_highest:
  504. reg = LTC2992_DSENSE_MAX(channel);
  505. break;
  506. case hwmon_curr_min:
  507. reg = LTC2992_DSENSE_MIN_THRESH(channel);
  508. break;
  509. case hwmon_curr_max:
  510. reg = LTC2992_DSENSE_MAX_THRESH(channel);
  511. break;
  512. case hwmon_curr_min_alarm:
  513. case hwmon_curr_max_alarm:
  514. return ltc2992_read_curr_alarm(st, channel, val, attr);
  515. default:
  516. return -EOPNOTSUPP;
  517. }
  518. return ltc2992_get_current(st, reg, channel, val);
  519. }
  520. static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
  521. {
  522. int reg_val;
  523. reg_val = ltc2992_read_reg(st, reg, 3);
  524. if (reg_val < 0)
  525. return reg_val;
  526. *val = mul_u64_u32_div(reg_val, LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB,
  527. st->r_sense_uohm[channel] * 1000);
  528. return 0;
  529. }
  530. static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
  531. {
  532. u32 reg_val;
  533. reg_val = mul_u64_u32_div(val, st->r_sense_uohm[channel] * 1000,
  534. LTC2992_VADC_UV_LSB * LTC2992_IADC_NANOV_LSB);
  535. return ltc2992_write_reg(st, reg, 3, reg_val);
  536. }
  537. static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
  538. {
  539. int reg_val;
  540. u32 mask;
  541. if (attr == hwmon_power_max_alarm)
  542. mask = LTC2992_POWER_FAULT_MSK(1);
  543. else
  544. mask = LTC2992_POWER_FAULT_MSK(0);
  545. reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);
  546. if (reg_val < 0)
  547. return reg_val;
  548. *val = !!(reg_val & mask);
  549. reg_val &= ~mask;
  550. return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);
  551. }
  552. static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
  553. {
  554. struct ltc2992_state *st = dev_get_drvdata(dev);
  555. u32 reg;
  556. switch (attr) {
  557. case hwmon_power_input:
  558. reg = LTC2992_POWER(channel);
  559. break;
  560. case hwmon_power_input_lowest:
  561. reg = LTC2992_POWER_MIN(channel);
  562. break;
  563. case hwmon_power_input_highest:
  564. reg = LTC2992_POWER_MAX(channel);
  565. break;
  566. case hwmon_power_min:
  567. reg = LTC2992_POWER_MIN_THRESH(channel);
  568. break;
  569. case hwmon_power_max:
  570. reg = LTC2992_POWER_MAX_THRESH(channel);
  571. break;
  572. case hwmon_power_min_alarm:
  573. case hwmon_power_max_alarm:
  574. return ltc2992_read_power_alarm(st, channel, val, attr);
  575. default:
  576. return -EOPNOTSUPP;
  577. }
  578. return ltc2992_get_power(st, reg, channel, val);
  579. }
  580. static int ltc2992_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
  581. long *val)
  582. {
  583. switch (type) {
  584. case hwmon_in:
  585. return ltc2992_read_in(dev, attr, channel, val);
  586. case hwmon_curr:
  587. return ltc2992_read_curr(dev, attr, channel, val);
  588. case hwmon_power:
  589. return ltc2992_read_power(dev, attr, channel, val);
  590. default:
  591. return -EOPNOTSUPP;
  592. }
  593. }
  594. static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
  595. {
  596. struct ltc2992_state *st = dev_get_drvdata(dev);
  597. u32 reg;
  598. switch (attr) {
  599. case hwmon_curr_min:
  600. reg = LTC2992_DSENSE_MIN_THRESH(channel);
  601. break;
  602. case hwmon_curr_max:
  603. reg = LTC2992_DSENSE_MAX_THRESH(channel);
  604. break;
  605. default:
  606. return -EOPNOTSUPP;
  607. }
  608. return ltc2992_set_current(st, reg, channel, val);
  609. }
  610. static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
  611. {
  612. struct ltc2992_state *st = dev_get_drvdata(dev);
  613. u32 reg;
  614. switch (attr) {
  615. case hwmon_in_min:
  616. reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
  617. break;
  618. case hwmon_in_max:
  619. reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
  620. break;
  621. default:
  622. return -EOPNOTSUPP;
  623. }
  624. return ltc2992_set_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
  625. }
  626. static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
  627. {
  628. struct ltc2992_state *st = dev_get_drvdata(dev);
  629. u32 reg;
  630. if (channel > 1)
  631. return ltc2992_write_gpios_in(dev, attr, channel - 2, val);
  632. switch (attr) {
  633. case hwmon_in_min:
  634. reg = LTC2992_SENSE_MIN_THRESH(channel);
  635. break;
  636. case hwmon_in_max:
  637. reg = LTC2992_SENSE_MAX_THRESH(channel);
  638. break;
  639. default:
  640. return -EOPNOTSUPP;
  641. }
  642. return ltc2992_set_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
  643. }
  644. static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
  645. {
  646. struct ltc2992_state *st = dev_get_drvdata(dev);
  647. u32 reg;
  648. switch (attr) {
  649. case hwmon_power_min:
  650. reg = LTC2992_POWER_MIN_THRESH(channel);
  651. break;
  652. case hwmon_power_max:
  653. reg = LTC2992_POWER_MAX_THRESH(channel);
  654. break;
  655. default:
  656. return -EOPNOTSUPP;
  657. }
  658. return ltc2992_set_power(st, reg, channel, val);
  659. }
  660. static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
  661. {
  662. struct ltc2992_state *st = dev_get_drvdata(dev);
  663. switch (attr) {
  664. case hwmon_chip_in_reset_history:
  665. return regmap_update_bits(st->regmap, LTC2992_CTRLB, LTC2992_RESET_HISTORY,
  666. LTC2992_RESET_HISTORY);
  667. default:
  668. return -EOPNOTSUPP;
  669. }
  670. }
  671. static int ltc2992_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
  672. long val)
  673. {
  674. switch (type) {
  675. case hwmon_chip:
  676. return ltc2992_write_chip(dev, attr, channel, val);
  677. case hwmon_in:
  678. return ltc2992_write_in(dev, attr, channel, val);
  679. case hwmon_curr:
  680. return ltc2992_write_curr(dev, attr, channel, val);
  681. case hwmon_power:
  682. return ltc2992_write_power(dev, attr, channel, val);
  683. default:
  684. return -EOPNOTSUPP;
  685. }
  686. }
  687. static const struct hwmon_ops ltc2992_hwmon_ops = {
  688. .is_visible = ltc2992_is_visible,
  689. .read = ltc2992_read,
  690. .write = ltc2992_write,
  691. };
  692. static const struct hwmon_channel_info *ltc2992_info[] = {
  693. HWMON_CHANNEL_INFO(chip,
  694. HWMON_C_IN_RESET_HISTORY),
  695. HWMON_CHANNEL_INFO(in,
  696. HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
  697. HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
  698. HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
  699. HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
  700. HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
  701. HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
  702. HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
  703. HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
  704. HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
  705. HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
  706. HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
  707. HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM),
  708. HWMON_CHANNEL_INFO(curr,
  709. HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
  710. HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
  711. HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
  712. HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM),
  713. HWMON_CHANNEL_INFO(power,
  714. HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
  715. HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
  716. HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
  717. HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM),
  718. NULL
  719. };
  720. static const struct hwmon_chip_info ltc2992_chip_info = {
  721. .ops = &ltc2992_hwmon_ops,
  722. .info = ltc2992_info,
  723. };
  724. static const struct regmap_config ltc2992_regmap_config = {
  725. .reg_bits = 8,
  726. .val_bits = 8,
  727. .max_register = 0xE8,
  728. };
  729. static int ltc2992_parse_dt(struct ltc2992_state *st)
  730. {
  731. struct fwnode_handle *fwnode;
  732. struct fwnode_handle *child;
  733. u32 addr;
  734. u32 val;
  735. int ret;
  736. fwnode = dev_fwnode(&st->client->dev);
  737. fwnode_for_each_available_child_node(fwnode, child) {
  738. ret = fwnode_property_read_u32(child, "reg", &addr);
  739. if (ret < 0) {
  740. fwnode_handle_put(child);
  741. return ret;
  742. }
  743. if (addr > 1) {
  744. fwnode_handle_put(child);
  745. return -EINVAL;
  746. }
  747. ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
  748. if (!ret)
  749. st->r_sense_uohm[addr] = val;
  750. }
  751. return 0;
  752. }
  753. static int ltc2992_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
  754. {
  755. struct device *hwmon_dev;
  756. struct ltc2992_state *st;
  757. int ret;
  758. st = devm_kzalloc(&client->dev, sizeof(*st), GFP_KERNEL);
  759. if (!st)
  760. return -ENOMEM;
  761. st->client = client;
  762. st->regmap = devm_regmap_init_i2c(client, &ltc2992_regmap_config);
  763. if (IS_ERR(st->regmap))
  764. return PTR_ERR(st->regmap);
  765. ret = ltc2992_parse_dt(st);
  766. if (ret < 0)
  767. return ret;
  768. ret = ltc2992_config_gpio(st);
  769. if (ret < 0)
  770. return ret;
  771. hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, client->name, st,
  772. &ltc2992_chip_info, NULL);
  773. return PTR_ERR_OR_ZERO(hwmon_dev);
  774. }
  775. static const struct of_device_id ltc2992_of_match[] = {
  776. { .compatible = "adi,ltc2992" },
  777. { }
  778. };
  779. MODULE_DEVICE_TABLE(of, ltc2992_of_match);
  780. static const struct i2c_device_id ltc2992_i2c_id[] = {
  781. {"ltc2992", 0},
  782. {}
  783. };
  784. MODULE_DEVICE_TABLE(i2c, ltc2992_i2c_id);
  785. static struct i2c_driver ltc2992_i2c_driver = {
  786. .driver = {
  787. .name = "ltc2992",
  788. .of_match_table = ltc2992_of_match,
  789. },
  790. .probe = ltc2992_i2c_probe,
  791. .id_table = ltc2992_i2c_id,
  792. };
  793. module_i2c_driver(ltc2992_i2c_driver);
  794. MODULE_AUTHOR("Alexandru Tachici <[email protected]>");
  795. MODULE_DESCRIPTION("Hwmon driver for Linear Technology 2992");
  796. MODULE_LICENSE("Dual BSD/GPL");