virtgpu_ioctl.c 22 KB

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  1. /*
  2. * Copyright (C) 2015 Red Hat, Inc.
  3. * All Rights Reserved.
  4. *
  5. * Authors:
  6. * Dave Airlie
  7. * Alon Levy
  8. *
  9. * Permission is hereby granted, free of charge, to any person obtaining a
  10. * copy of this software and associated documentation files (the "Software"),
  11. * to deal in the Software without restriction, including without limitation
  12. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13. * and/or sell copies of the Software, and to permit persons to whom the
  14. * Software is furnished to do so, subject to the following conditions:
  15. *
  16. * The above copyright notice and this permission notice shall be included in
  17. * all copies or substantial portions of the Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25. * OTHER DEALINGS IN THE SOFTWARE.
  26. */
  27. #include <linux/file.h>
  28. #include <linux/sync_file.h>
  29. #include <linux/uaccess.h>
  30. #include <drm/drm_file.h>
  31. #include <drm/virtgpu_drm.h>
  32. #include "virtgpu_drv.h"
  33. #define VIRTGPU_BLOB_FLAG_USE_MASK (VIRTGPU_BLOB_FLAG_USE_MAPPABLE | \
  34. VIRTGPU_BLOB_FLAG_USE_SHAREABLE | \
  35. VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE)
  36. static int virtio_gpu_fence_event_create(struct drm_device *dev,
  37. struct drm_file *file,
  38. struct virtio_gpu_fence *fence,
  39. uint32_t ring_idx)
  40. {
  41. struct virtio_gpu_fence_event *e = NULL;
  42. int ret;
  43. e = kzalloc(sizeof(*e), GFP_KERNEL);
  44. if (!e)
  45. return -ENOMEM;
  46. e->event.type = VIRTGPU_EVENT_FENCE_SIGNALED;
  47. e->event.length = sizeof(e->event);
  48. ret = drm_event_reserve_init(dev, file, &e->base, &e->event);
  49. if (ret)
  50. goto free;
  51. fence->e = e;
  52. return 0;
  53. free:
  54. kfree(e);
  55. return ret;
  56. }
  57. /* Must be called with &virtio_gpu_fpriv.struct_mutex held. */
  58. static void virtio_gpu_create_context_locked(struct virtio_gpu_device *vgdev,
  59. struct virtio_gpu_fpriv *vfpriv)
  60. {
  61. char dbgname[TASK_COMM_LEN];
  62. get_task_comm(dbgname, current);
  63. virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id,
  64. vfpriv->context_init, strlen(dbgname),
  65. dbgname);
  66. vfpriv->context_created = true;
  67. }
  68. void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file)
  69. {
  70. struct virtio_gpu_device *vgdev = dev->dev_private;
  71. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  72. mutex_lock(&vfpriv->context_lock);
  73. if (vfpriv->context_created)
  74. goto out_unlock;
  75. virtio_gpu_create_context_locked(vgdev, vfpriv);
  76. out_unlock:
  77. mutex_unlock(&vfpriv->context_lock);
  78. }
  79. static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data,
  80. struct drm_file *file)
  81. {
  82. struct virtio_gpu_device *vgdev = dev->dev_private;
  83. struct drm_virtgpu_map *virtio_gpu_map = data;
  84. return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev,
  85. virtio_gpu_map->handle,
  86. &virtio_gpu_map->offset);
  87. }
  88. /*
  89. * Usage of execbuffer:
  90. * Relocations need to take into account the full VIRTIO_GPUDrawable size.
  91. * However, the command as passed from user space must *not* contain the initial
  92. * VIRTIO_GPUReleaseInfo struct (first XXX bytes)
  93. */
  94. static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
  95. struct drm_file *file)
  96. {
  97. struct drm_virtgpu_execbuffer *exbuf = data;
  98. struct virtio_gpu_device *vgdev = dev->dev_private;
  99. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  100. struct virtio_gpu_fence *out_fence;
  101. bool drm_fence_event;
  102. int ret;
  103. uint32_t *bo_handles = NULL;
  104. void __user *user_bo_handles = NULL;
  105. struct virtio_gpu_object_array *buflist = NULL;
  106. struct sync_file *sync_file;
  107. int out_fence_fd = -1;
  108. void *buf;
  109. uint64_t fence_ctx;
  110. uint32_t ring_idx;
  111. fence_ctx = vgdev->fence_drv.context;
  112. ring_idx = 0;
  113. if (vgdev->has_virgl_3d == false)
  114. return -ENOSYS;
  115. if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS))
  116. return -EINVAL;
  117. if ((exbuf->flags & VIRTGPU_EXECBUF_RING_IDX)) {
  118. if (exbuf->ring_idx >= vfpriv->num_rings)
  119. return -EINVAL;
  120. if (!vfpriv->base_fence_ctx)
  121. return -EINVAL;
  122. fence_ctx = vfpriv->base_fence_ctx;
  123. ring_idx = exbuf->ring_idx;
  124. }
  125. virtio_gpu_create_context(dev, file);
  126. if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) {
  127. struct dma_fence *in_fence;
  128. in_fence = sync_file_get_fence(exbuf->fence_fd);
  129. if (!in_fence)
  130. return -EINVAL;
  131. /*
  132. * Wait if the fence is from a foreign context, or if the fence
  133. * array contains any fence from a foreign context.
  134. */
  135. ret = 0;
  136. if (!dma_fence_match_context(in_fence, fence_ctx + ring_idx))
  137. ret = dma_fence_wait(in_fence, true);
  138. dma_fence_put(in_fence);
  139. if (ret)
  140. return ret;
  141. }
  142. if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) {
  143. out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
  144. if (out_fence_fd < 0)
  145. return out_fence_fd;
  146. }
  147. if (exbuf->num_bo_handles) {
  148. bo_handles = kvmalloc_array(exbuf->num_bo_handles,
  149. sizeof(uint32_t), GFP_KERNEL);
  150. if (!bo_handles) {
  151. ret = -ENOMEM;
  152. goto out_unused_fd;
  153. }
  154. user_bo_handles = u64_to_user_ptr(exbuf->bo_handles);
  155. if (copy_from_user(bo_handles, user_bo_handles,
  156. exbuf->num_bo_handles * sizeof(uint32_t))) {
  157. ret = -EFAULT;
  158. goto out_unused_fd;
  159. }
  160. buflist = virtio_gpu_array_from_handles(file, bo_handles,
  161. exbuf->num_bo_handles);
  162. if (!buflist) {
  163. ret = -ENOENT;
  164. goto out_unused_fd;
  165. }
  166. kvfree(bo_handles);
  167. bo_handles = NULL;
  168. }
  169. buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size);
  170. if (IS_ERR(buf)) {
  171. ret = PTR_ERR(buf);
  172. goto out_unused_fd;
  173. }
  174. if (buflist) {
  175. ret = virtio_gpu_array_lock_resv(buflist);
  176. if (ret)
  177. goto out_memdup;
  178. }
  179. if ((exbuf->flags & VIRTGPU_EXECBUF_RING_IDX) &&
  180. (vfpriv->ring_idx_mask & BIT_ULL(ring_idx)))
  181. drm_fence_event = true;
  182. else
  183. drm_fence_event = false;
  184. if ((exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) ||
  185. exbuf->num_bo_handles ||
  186. drm_fence_event)
  187. out_fence = virtio_gpu_fence_alloc(vgdev, fence_ctx, ring_idx);
  188. else
  189. out_fence = NULL;
  190. if (drm_fence_event) {
  191. ret = virtio_gpu_fence_event_create(dev, file, out_fence, ring_idx);
  192. if (ret)
  193. goto out_unresv;
  194. }
  195. if (out_fence_fd >= 0) {
  196. sync_file = sync_file_create(&out_fence->f);
  197. if (!sync_file) {
  198. dma_fence_put(&out_fence->f);
  199. ret = -ENOMEM;
  200. goto out_unresv;
  201. }
  202. exbuf->fence_fd = out_fence_fd;
  203. fd_install(out_fence_fd, sync_file->file);
  204. }
  205. virtio_gpu_cmd_submit(vgdev, buf, exbuf->size,
  206. vfpriv->ctx_id, buflist, out_fence);
  207. dma_fence_put(&out_fence->f);
  208. virtio_gpu_notify(vgdev);
  209. return 0;
  210. out_unresv:
  211. if (buflist)
  212. virtio_gpu_array_unlock_resv(buflist);
  213. out_memdup:
  214. kvfree(buf);
  215. out_unused_fd:
  216. kvfree(bo_handles);
  217. if (buflist)
  218. virtio_gpu_array_put_free(buflist);
  219. if (out_fence_fd >= 0)
  220. put_unused_fd(out_fence_fd);
  221. return ret;
  222. }
  223. static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data,
  224. struct drm_file *file)
  225. {
  226. struct virtio_gpu_device *vgdev = dev->dev_private;
  227. struct drm_virtgpu_getparam *param = data;
  228. int value;
  229. switch (param->param) {
  230. case VIRTGPU_PARAM_3D_FEATURES:
  231. value = vgdev->has_virgl_3d ? 1 : 0;
  232. break;
  233. case VIRTGPU_PARAM_CAPSET_QUERY_FIX:
  234. value = 1;
  235. break;
  236. case VIRTGPU_PARAM_RESOURCE_BLOB:
  237. value = vgdev->has_resource_blob ? 1 : 0;
  238. break;
  239. case VIRTGPU_PARAM_HOST_VISIBLE:
  240. value = vgdev->has_host_visible ? 1 : 0;
  241. break;
  242. case VIRTGPU_PARAM_CROSS_DEVICE:
  243. value = vgdev->has_resource_assign_uuid ? 1 : 0;
  244. break;
  245. case VIRTGPU_PARAM_CONTEXT_INIT:
  246. value = vgdev->has_context_init ? 1 : 0;
  247. break;
  248. case VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs:
  249. value = vgdev->capset_id_mask;
  250. break;
  251. default:
  252. return -EINVAL;
  253. }
  254. if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int)))
  255. return -EFAULT;
  256. return 0;
  257. }
  258. static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data,
  259. struct drm_file *file)
  260. {
  261. struct virtio_gpu_device *vgdev = dev->dev_private;
  262. struct drm_virtgpu_resource_create *rc = data;
  263. struct virtio_gpu_fence *fence;
  264. int ret;
  265. struct virtio_gpu_object *qobj;
  266. struct drm_gem_object *obj;
  267. uint32_t handle = 0;
  268. struct virtio_gpu_object_params params = { 0 };
  269. if (vgdev->has_virgl_3d) {
  270. virtio_gpu_create_context(dev, file);
  271. params.virgl = true;
  272. params.target = rc->target;
  273. params.bind = rc->bind;
  274. params.depth = rc->depth;
  275. params.array_size = rc->array_size;
  276. params.last_level = rc->last_level;
  277. params.nr_samples = rc->nr_samples;
  278. params.flags = rc->flags;
  279. } else {
  280. if (rc->depth > 1)
  281. return -EINVAL;
  282. if (rc->nr_samples > 1)
  283. return -EINVAL;
  284. if (rc->last_level > 1)
  285. return -EINVAL;
  286. if (rc->target != 2)
  287. return -EINVAL;
  288. if (rc->array_size > 1)
  289. return -EINVAL;
  290. }
  291. params.format = rc->format;
  292. params.width = rc->width;
  293. params.height = rc->height;
  294. params.size = rc->size;
  295. /* allocate a single page size object */
  296. if (params.size == 0)
  297. params.size = PAGE_SIZE;
  298. fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0);
  299. if (!fence)
  300. return -ENOMEM;
  301. ret = virtio_gpu_object_create(vgdev, &params, &qobj, fence);
  302. dma_fence_put(&fence->f);
  303. if (ret < 0)
  304. return ret;
  305. obj = &qobj->base.base;
  306. ret = drm_gem_handle_create(file, obj, &handle);
  307. if (ret) {
  308. drm_gem_object_release(obj);
  309. return ret;
  310. }
  311. rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */
  312. rc->bo_handle = handle;
  313. /*
  314. * The handle owns the reference now. But we must drop our
  315. * remaining reference *after* we no longer need to dereference
  316. * the obj. Otherwise userspace could guess the handle and
  317. * race closing it from another thread.
  318. */
  319. drm_gem_object_put(obj);
  320. return 0;
  321. }
  322. static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data,
  323. struct drm_file *file)
  324. {
  325. struct drm_virtgpu_resource_info *ri = data;
  326. struct drm_gem_object *gobj = NULL;
  327. struct virtio_gpu_object *qobj = NULL;
  328. gobj = drm_gem_object_lookup(file, ri->bo_handle);
  329. if (gobj == NULL)
  330. return -ENOENT;
  331. qobj = gem_to_virtio_gpu_obj(gobj);
  332. ri->size = qobj->base.base.size;
  333. ri->res_handle = qobj->hw_res_handle;
  334. if (qobj->host3d_blob || qobj->guest_blob)
  335. ri->blob_mem = qobj->blob_mem;
  336. drm_gem_object_put(gobj);
  337. return 0;
  338. }
  339. static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev,
  340. void *data,
  341. struct drm_file *file)
  342. {
  343. struct virtio_gpu_device *vgdev = dev->dev_private;
  344. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  345. struct drm_virtgpu_3d_transfer_from_host *args = data;
  346. struct virtio_gpu_object *bo;
  347. struct virtio_gpu_object_array *objs;
  348. struct virtio_gpu_fence *fence;
  349. int ret;
  350. u32 offset = args->offset;
  351. if (vgdev->has_virgl_3d == false)
  352. return -ENOSYS;
  353. virtio_gpu_create_context(dev, file);
  354. objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
  355. if (objs == NULL)
  356. return -ENOENT;
  357. bo = gem_to_virtio_gpu_obj(objs->objs[0]);
  358. if (bo->guest_blob && !bo->host3d_blob) {
  359. ret = -EINVAL;
  360. goto err_put_free;
  361. }
  362. if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
  363. ret = -EINVAL;
  364. goto err_put_free;
  365. }
  366. ret = virtio_gpu_array_lock_resv(objs);
  367. if (ret != 0)
  368. goto err_put_free;
  369. fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context, 0);
  370. if (!fence) {
  371. ret = -ENOMEM;
  372. goto err_unlock;
  373. }
  374. virtio_gpu_cmd_transfer_from_host_3d
  375. (vgdev, vfpriv->ctx_id, offset, args->level, args->stride,
  376. args->layer_stride, &args->box, objs, fence);
  377. dma_fence_put(&fence->f);
  378. virtio_gpu_notify(vgdev);
  379. return 0;
  380. err_unlock:
  381. virtio_gpu_array_unlock_resv(objs);
  382. err_put_free:
  383. virtio_gpu_array_put_free(objs);
  384. return ret;
  385. }
  386. static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data,
  387. struct drm_file *file)
  388. {
  389. struct virtio_gpu_device *vgdev = dev->dev_private;
  390. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  391. struct drm_virtgpu_3d_transfer_to_host *args = data;
  392. struct virtio_gpu_object *bo;
  393. struct virtio_gpu_object_array *objs;
  394. struct virtio_gpu_fence *fence;
  395. int ret;
  396. u32 offset = args->offset;
  397. objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1);
  398. if (objs == NULL)
  399. return -ENOENT;
  400. bo = gem_to_virtio_gpu_obj(objs->objs[0]);
  401. if (bo->guest_blob && !bo->host3d_blob) {
  402. ret = -EINVAL;
  403. goto err_put_free;
  404. }
  405. if (!vgdev->has_virgl_3d) {
  406. virtio_gpu_cmd_transfer_to_host_2d
  407. (vgdev, offset,
  408. args->box.w, args->box.h, args->box.x, args->box.y,
  409. objs, NULL);
  410. } else {
  411. virtio_gpu_create_context(dev, file);
  412. if (!bo->host3d_blob && (args->stride || args->layer_stride)) {
  413. ret = -EINVAL;
  414. goto err_put_free;
  415. }
  416. ret = virtio_gpu_array_lock_resv(objs);
  417. if (ret != 0)
  418. goto err_put_free;
  419. ret = -ENOMEM;
  420. fence = virtio_gpu_fence_alloc(vgdev, vgdev->fence_drv.context,
  421. 0);
  422. if (!fence)
  423. goto err_unlock;
  424. virtio_gpu_cmd_transfer_to_host_3d
  425. (vgdev,
  426. vfpriv ? vfpriv->ctx_id : 0, offset, args->level,
  427. args->stride, args->layer_stride, &args->box, objs,
  428. fence);
  429. dma_fence_put(&fence->f);
  430. }
  431. virtio_gpu_notify(vgdev);
  432. return 0;
  433. err_unlock:
  434. virtio_gpu_array_unlock_resv(objs);
  435. err_put_free:
  436. virtio_gpu_array_put_free(objs);
  437. return ret;
  438. }
  439. static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data,
  440. struct drm_file *file)
  441. {
  442. struct drm_virtgpu_3d_wait *args = data;
  443. struct drm_gem_object *obj;
  444. long timeout = 15 * HZ;
  445. int ret;
  446. obj = drm_gem_object_lookup(file, args->handle);
  447. if (obj == NULL)
  448. return -ENOENT;
  449. if (args->flags & VIRTGPU_WAIT_NOWAIT) {
  450. ret = dma_resv_test_signaled(obj->resv, DMA_RESV_USAGE_READ);
  451. } else {
  452. ret = dma_resv_wait_timeout(obj->resv, DMA_RESV_USAGE_READ,
  453. true, timeout);
  454. }
  455. if (ret == 0)
  456. ret = -EBUSY;
  457. else if (ret > 0)
  458. ret = 0;
  459. drm_gem_object_put(obj);
  460. return ret;
  461. }
  462. static int virtio_gpu_get_caps_ioctl(struct drm_device *dev,
  463. void *data, struct drm_file *file)
  464. {
  465. struct virtio_gpu_device *vgdev = dev->dev_private;
  466. struct drm_virtgpu_get_caps *args = data;
  467. unsigned size, host_caps_size;
  468. int i;
  469. int found_valid = -1;
  470. int ret;
  471. struct virtio_gpu_drv_cap_cache *cache_ent;
  472. void *ptr;
  473. if (vgdev->num_capsets == 0)
  474. return -ENOSYS;
  475. /* don't allow userspace to pass 0 */
  476. if (args->size == 0)
  477. return -EINVAL;
  478. spin_lock(&vgdev->display_info_lock);
  479. for (i = 0; i < vgdev->num_capsets; i++) {
  480. if (vgdev->capsets[i].id == args->cap_set_id) {
  481. if (vgdev->capsets[i].max_version >= args->cap_set_ver) {
  482. found_valid = i;
  483. break;
  484. }
  485. }
  486. }
  487. if (found_valid == -1) {
  488. spin_unlock(&vgdev->display_info_lock);
  489. return -EINVAL;
  490. }
  491. host_caps_size = vgdev->capsets[found_valid].max_size;
  492. /* only copy to user the minimum of the host caps size or the guest caps size */
  493. size = min(args->size, host_caps_size);
  494. list_for_each_entry(cache_ent, &vgdev->cap_cache, head) {
  495. if (cache_ent->id == args->cap_set_id &&
  496. cache_ent->version == args->cap_set_ver) {
  497. spin_unlock(&vgdev->display_info_lock);
  498. goto copy_exit;
  499. }
  500. }
  501. spin_unlock(&vgdev->display_info_lock);
  502. /* not in cache - need to talk to hw */
  503. ret = virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver,
  504. &cache_ent);
  505. if (ret)
  506. return ret;
  507. virtio_gpu_notify(vgdev);
  508. copy_exit:
  509. ret = wait_event_timeout(vgdev->resp_wq,
  510. atomic_read(&cache_ent->is_valid), 5 * HZ);
  511. if (!ret)
  512. return -EBUSY;
  513. /* is_valid check must proceed before copy of the cache entry. */
  514. smp_rmb();
  515. ptr = cache_ent->caps_cache;
  516. if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size))
  517. return -EFAULT;
  518. return 0;
  519. }
  520. static int verify_blob(struct virtio_gpu_device *vgdev,
  521. struct virtio_gpu_fpriv *vfpriv,
  522. struct virtio_gpu_object_params *params,
  523. struct drm_virtgpu_resource_create_blob *rc_blob,
  524. bool *guest_blob, bool *host3d_blob)
  525. {
  526. if (!vgdev->has_resource_blob)
  527. return -EINVAL;
  528. if (rc_blob->blob_flags & ~VIRTGPU_BLOB_FLAG_USE_MASK)
  529. return -EINVAL;
  530. if (rc_blob->blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
  531. if (!vgdev->has_resource_assign_uuid)
  532. return -EINVAL;
  533. }
  534. switch (rc_blob->blob_mem) {
  535. case VIRTGPU_BLOB_MEM_GUEST:
  536. *guest_blob = true;
  537. break;
  538. case VIRTGPU_BLOB_MEM_HOST3D_GUEST:
  539. *guest_blob = true;
  540. fallthrough;
  541. case VIRTGPU_BLOB_MEM_HOST3D:
  542. *host3d_blob = true;
  543. break;
  544. default:
  545. return -EINVAL;
  546. }
  547. if (*host3d_blob) {
  548. if (!vgdev->has_virgl_3d)
  549. return -EINVAL;
  550. /* Must be dword aligned. */
  551. if (rc_blob->cmd_size % 4 != 0)
  552. return -EINVAL;
  553. params->ctx_id = vfpriv->ctx_id;
  554. params->blob_id = rc_blob->blob_id;
  555. } else {
  556. if (rc_blob->blob_id != 0)
  557. return -EINVAL;
  558. if (rc_blob->cmd_size != 0)
  559. return -EINVAL;
  560. }
  561. params->blob_mem = rc_blob->blob_mem;
  562. params->size = rc_blob->size;
  563. params->blob = true;
  564. params->blob_flags = rc_blob->blob_flags;
  565. return 0;
  566. }
  567. static int virtio_gpu_resource_create_blob_ioctl(struct drm_device *dev,
  568. void *data,
  569. struct drm_file *file)
  570. {
  571. int ret = 0;
  572. uint32_t handle = 0;
  573. bool guest_blob = false;
  574. bool host3d_blob = false;
  575. struct drm_gem_object *obj;
  576. struct virtio_gpu_object *bo;
  577. struct virtio_gpu_object_params params = { 0 };
  578. struct virtio_gpu_device *vgdev = dev->dev_private;
  579. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  580. struct drm_virtgpu_resource_create_blob *rc_blob = data;
  581. if (verify_blob(vgdev, vfpriv, &params, rc_blob,
  582. &guest_blob, &host3d_blob))
  583. return -EINVAL;
  584. if (vgdev->has_virgl_3d)
  585. virtio_gpu_create_context(dev, file);
  586. if (rc_blob->cmd_size) {
  587. void *buf;
  588. buf = memdup_user(u64_to_user_ptr(rc_blob->cmd),
  589. rc_blob->cmd_size);
  590. if (IS_ERR(buf))
  591. return PTR_ERR(buf);
  592. virtio_gpu_cmd_submit(vgdev, buf, rc_blob->cmd_size,
  593. vfpriv->ctx_id, NULL, NULL);
  594. }
  595. if (guest_blob)
  596. ret = virtio_gpu_object_create(vgdev, &params, &bo, NULL);
  597. else if (!guest_blob && host3d_blob)
  598. ret = virtio_gpu_vram_create(vgdev, &params, &bo);
  599. else
  600. return -EINVAL;
  601. if (ret < 0)
  602. return ret;
  603. bo->guest_blob = guest_blob;
  604. bo->host3d_blob = host3d_blob;
  605. bo->blob_mem = rc_blob->blob_mem;
  606. bo->blob_flags = rc_blob->blob_flags;
  607. obj = &bo->base.base;
  608. if (params.blob_flags & VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE) {
  609. ret = virtio_gpu_resource_assign_uuid(vgdev, bo);
  610. if (ret) {
  611. drm_gem_object_release(obj);
  612. return ret;
  613. }
  614. }
  615. ret = drm_gem_handle_create(file, obj, &handle);
  616. if (ret) {
  617. drm_gem_object_release(obj);
  618. return ret;
  619. }
  620. rc_blob->res_handle = bo->hw_res_handle;
  621. rc_blob->bo_handle = handle;
  622. /*
  623. * The handle owns the reference now. But we must drop our
  624. * remaining reference *after* we no longer need to dereference
  625. * the obj. Otherwise userspace could guess the handle and
  626. * race closing it from another thread.
  627. */
  628. drm_gem_object_put(obj);
  629. return 0;
  630. }
  631. static int virtio_gpu_context_init_ioctl(struct drm_device *dev,
  632. void *data, struct drm_file *file)
  633. {
  634. int ret = 0;
  635. uint32_t num_params, i, param, value;
  636. uint64_t valid_ring_mask;
  637. size_t len;
  638. struct drm_virtgpu_context_set_param *ctx_set_params = NULL;
  639. struct virtio_gpu_device *vgdev = dev->dev_private;
  640. struct virtio_gpu_fpriv *vfpriv = file->driver_priv;
  641. struct drm_virtgpu_context_init *args = data;
  642. num_params = args->num_params;
  643. len = num_params * sizeof(struct drm_virtgpu_context_set_param);
  644. if (!vgdev->has_context_init || !vgdev->has_virgl_3d)
  645. return -EINVAL;
  646. /* Number of unique parameters supported at this time. */
  647. if (num_params > 3)
  648. return -EINVAL;
  649. ctx_set_params = memdup_user(u64_to_user_ptr(args->ctx_set_params),
  650. len);
  651. if (IS_ERR(ctx_set_params))
  652. return PTR_ERR(ctx_set_params);
  653. mutex_lock(&vfpriv->context_lock);
  654. if (vfpriv->context_created) {
  655. ret = -EEXIST;
  656. goto out_unlock;
  657. }
  658. for (i = 0; i < num_params; i++) {
  659. param = ctx_set_params[i].param;
  660. value = ctx_set_params[i].value;
  661. switch (param) {
  662. case VIRTGPU_CONTEXT_PARAM_CAPSET_ID:
  663. if (value > MAX_CAPSET_ID) {
  664. ret = -EINVAL;
  665. goto out_unlock;
  666. }
  667. if ((vgdev->capset_id_mask & (1ULL << value)) == 0) {
  668. ret = -EINVAL;
  669. goto out_unlock;
  670. }
  671. /* Context capset ID already set */
  672. if (vfpriv->context_init &
  673. VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK) {
  674. ret = -EINVAL;
  675. goto out_unlock;
  676. }
  677. vfpriv->context_init |= value;
  678. break;
  679. case VIRTGPU_CONTEXT_PARAM_NUM_RINGS:
  680. if (vfpriv->base_fence_ctx) {
  681. ret = -EINVAL;
  682. goto out_unlock;
  683. }
  684. if (value > MAX_RINGS) {
  685. ret = -EINVAL;
  686. goto out_unlock;
  687. }
  688. vfpriv->base_fence_ctx = dma_fence_context_alloc(value);
  689. vfpriv->num_rings = value;
  690. break;
  691. case VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK:
  692. if (vfpriv->ring_idx_mask) {
  693. ret = -EINVAL;
  694. goto out_unlock;
  695. }
  696. vfpriv->ring_idx_mask = value;
  697. break;
  698. default:
  699. ret = -EINVAL;
  700. goto out_unlock;
  701. }
  702. }
  703. if (vfpriv->ring_idx_mask) {
  704. valid_ring_mask = 0;
  705. for (i = 0; i < vfpriv->num_rings; i++)
  706. valid_ring_mask |= 1ULL << i;
  707. if (~valid_ring_mask & vfpriv->ring_idx_mask) {
  708. ret = -EINVAL;
  709. goto out_unlock;
  710. }
  711. }
  712. virtio_gpu_create_context_locked(vgdev, vfpriv);
  713. virtio_gpu_notify(vgdev);
  714. out_unlock:
  715. mutex_unlock(&vfpriv->context_lock);
  716. kfree(ctx_set_params);
  717. return ret;
  718. }
  719. struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = {
  720. DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl,
  721. DRM_RENDER_ALLOW),
  722. DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl,
  723. DRM_RENDER_ALLOW),
  724. DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl,
  725. DRM_RENDER_ALLOW),
  726. DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE,
  727. virtio_gpu_resource_create_ioctl,
  728. DRM_RENDER_ALLOW),
  729. DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl,
  730. DRM_RENDER_ALLOW),
  731. /* make transfer async to the main ring? - no sure, can we
  732. * thread these in the underlying GL
  733. */
  734. DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST,
  735. virtio_gpu_transfer_from_host_ioctl,
  736. DRM_RENDER_ALLOW),
  737. DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST,
  738. virtio_gpu_transfer_to_host_ioctl,
  739. DRM_RENDER_ALLOW),
  740. DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl,
  741. DRM_RENDER_ALLOW),
  742. DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl,
  743. DRM_RENDER_ALLOW),
  744. DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE_BLOB,
  745. virtio_gpu_resource_create_blob_ioctl,
  746. DRM_RENDER_ALLOW),
  747. DRM_IOCTL_DEF_DRV(VIRTGPU_CONTEXT_INIT, virtio_gpu_context_init_ioctl,
  748. DRM_RENDER_ALLOW),
  749. };