vc4_txp.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright © 2018 Broadcom
  4. *
  5. * Authors:
  6. * Eric Anholt <[email protected]>
  7. * Boris Brezillon <[email protected]>
  8. */
  9. #include <linux/clk.h>
  10. #include <linux/component.h>
  11. #include <linux/of_graph.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/pm_runtime.h>
  14. #include <drm/drm_atomic.h>
  15. #include <drm/drm_atomic_helper.h>
  16. #include <drm/drm_drv.h>
  17. #include <drm/drm_edid.h>
  18. #include <drm/drm_fb_dma_helper.h>
  19. #include <drm/drm_fourcc.h>
  20. #include <drm/drm_framebuffer.h>
  21. #include <drm/drm_panel.h>
  22. #include <drm/drm_probe_helper.h>
  23. #include <drm/drm_vblank.h>
  24. #include <drm/drm_writeback.h>
  25. #include "vc4_drv.h"
  26. #include "vc4_regs.h"
  27. /* Base address of the output. Raster formats must be 4-byte aligned,
  28. * T and LT must be 16-byte aligned or maybe utile-aligned (docs are
  29. * inconsistent, but probably utile).
  30. */
  31. #define TXP_DST_PTR 0x00
  32. /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's
  33. * the width in tiles.
  34. */
  35. #define TXP_DST_PITCH 0x04
  36. /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
  37. * shifted up.
  38. */
  39. # define TXP_T_TILE_WIDTH_SHIFT 7
  40. /* For LT-tiled images, DST_PITCH should be the number of utiles wide,
  41. * shifted up.
  42. */
  43. # define TXP_LT_TILE_WIDTH_SHIFT 4
  44. /* Pre-rotation width/height of the image. Must match HVS config.
  45. *
  46. * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
  47. * and width/height must be tile or utile-aligned as appropriate. If
  48. * transposing (rotating), width is limited to 1920.
  49. *
  50. * Height is limited to various numbers between 4088 and 4095. I'd
  51. * just use 4088 to be safe.
  52. */
  53. #define TXP_DIM 0x08
  54. # define TXP_HEIGHT_SHIFT 16
  55. # define TXP_HEIGHT_MASK GENMASK(31, 16)
  56. # define TXP_WIDTH_SHIFT 0
  57. # define TXP_WIDTH_MASK GENMASK(15, 0)
  58. #define TXP_DST_CTRL 0x0c
  59. /* These bits are set to 0x54 */
  60. #define TXP_PILOT_SHIFT 24
  61. #define TXP_PILOT_MASK GENMASK(31, 24)
  62. /* Bits 22-23 are set to 0x01 */
  63. #define TXP_VERSION_SHIFT 22
  64. #define TXP_VERSION_MASK GENMASK(23, 22)
  65. /* Powers down the internal memory. */
  66. # define TXP_POWERDOWN BIT(21)
  67. /* Enables storing the alpha component in 8888/4444, instead of
  68. * filling with ~ALPHA_INVERT.
  69. */
  70. # define TXP_ALPHA_ENABLE BIT(20)
  71. /* 4 bits, each enables stores for a channel in each set of 4 bytes.
  72. * Set to 0xf for normal operation.
  73. */
  74. # define TXP_BYTE_ENABLE_SHIFT 16
  75. # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)
  76. /* Debug: Generate VSTART again at EOF. */
  77. # define TXP_VSTART_AT_EOF BIT(15)
  78. /* Debug: Terminate the current frame immediately. Stops AXI
  79. * writes.
  80. */
  81. # define TXP_ABORT BIT(14)
  82. # define TXP_DITHER BIT(13)
  83. /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
  84. * !TXP_ALPHA_ENABLE.
  85. */
  86. # define TXP_ALPHA_INVERT BIT(12)
  87. /* Note: I've listed the channels here in high bit (in byte 3/2/1) to
  88. * low bit (in byte 0) order.
  89. */
  90. # define TXP_FORMAT_SHIFT 8
  91. # define TXP_FORMAT_MASK GENMASK(11, 8)
  92. # define TXP_FORMAT_ABGR4444 0
  93. # define TXP_FORMAT_ARGB4444 1
  94. # define TXP_FORMAT_BGRA4444 2
  95. # define TXP_FORMAT_RGBA4444 3
  96. # define TXP_FORMAT_BGR565 6
  97. # define TXP_FORMAT_RGB565 7
  98. /* 888s are non-rotated, raster-only */
  99. # define TXP_FORMAT_BGR888 8
  100. # define TXP_FORMAT_RGB888 9
  101. # define TXP_FORMAT_ABGR8888 12
  102. # define TXP_FORMAT_ARGB8888 13
  103. # define TXP_FORMAT_BGRA8888 14
  104. # define TXP_FORMAT_RGBA8888 15
  105. /* If TFORMAT is set, generates LT instead of T format. */
  106. # define TXP_LINEAR_UTILE BIT(7)
  107. /* Rotate output by 90 degrees. */
  108. # define TXP_TRANSPOSE BIT(6)
  109. /* Generate a tiled format for V3D. */
  110. # define TXP_TFORMAT BIT(5)
  111. /* Generates some undefined test mode output. */
  112. # define TXP_TEST_MODE BIT(4)
  113. /* Request odd field from HVS. */
  114. # define TXP_FIELD BIT(3)
  115. /* Raise interrupt when idle. */
  116. # define TXP_EI BIT(2)
  117. /* Set when generating a frame, clears when idle. */
  118. # define TXP_BUSY BIT(1)
  119. /* Starts a frame. Self-clearing. */
  120. # define TXP_GO BIT(0)
  121. /* Number of lines received and committed to memory. */
  122. #define TXP_PROGRESS 0x10
  123. #define TXP_READ(offset) readl(txp->regs + (offset))
  124. #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
  125. struct vc4_txp {
  126. struct vc4_crtc base;
  127. struct platform_device *pdev;
  128. struct drm_writeback_connector connector;
  129. void __iomem *regs;
  130. };
  131. static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
  132. {
  133. return container_of(encoder, struct vc4_txp, connector.encoder);
  134. }
  135. static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
  136. {
  137. return container_of(conn, struct vc4_txp, connector.base);
  138. }
  139. static const struct debugfs_reg32 txp_regs[] = {
  140. VC4_REG32(TXP_DST_PTR),
  141. VC4_REG32(TXP_DST_PITCH),
  142. VC4_REG32(TXP_DIM),
  143. VC4_REG32(TXP_DST_CTRL),
  144. VC4_REG32(TXP_PROGRESS),
  145. };
  146. static int vc4_txp_connector_get_modes(struct drm_connector *connector)
  147. {
  148. struct drm_device *dev = connector->dev;
  149. return drm_add_modes_noedid(connector, dev->mode_config.max_width,
  150. dev->mode_config.max_height);
  151. }
  152. static enum drm_mode_status
  153. vc4_txp_connector_mode_valid(struct drm_connector *connector,
  154. struct drm_display_mode *mode)
  155. {
  156. struct drm_device *dev = connector->dev;
  157. struct drm_mode_config *mode_config = &dev->mode_config;
  158. int w = mode->hdisplay, h = mode->vdisplay;
  159. if (w < mode_config->min_width || w > mode_config->max_width)
  160. return MODE_BAD_HVALUE;
  161. if (h < mode_config->min_height || h > mode_config->max_height)
  162. return MODE_BAD_VVALUE;
  163. return MODE_OK;
  164. }
  165. static const u32 drm_fmts[] = {
  166. DRM_FORMAT_RGB888,
  167. DRM_FORMAT_BGR888,
  168. DRM_FORMAT_XRGB8888,
  169. DRM_FORMAT_XBGR8888,
  170. DRM_FORMAT_ARGB8888,
  171. DRM_FORMAT_ABGR8888,
  172. DRM_FORMAT_RGBX8888,
  173. DRM_FORMAT_BGRX8888,
  174. DRM_FORMAT_RGBA8888,
  175. DRM_FORMAT_BGRA8888,
  176. };
  177. static const u32 txp_fmts[] = {
  178. TXP_FORMAT_RGB888,
  179. TXP_FORMAT_BGR888,
  180. TXP_FORMAT_ARGB8888,
  181. TXP_FORMAT_ABGR8888,
  182. TXP_FORMAT_ARGB8888,
  183. TXP_FORMAT_ABGR8888,
  184. TXP_FORMAT_RGBA8888,
  185. TXP_FORMAT_BGRA8888,
  186. TXP_FORMAT_RGBA8888,
  187. TXP_FORMAT_BGRA8888,
  188. };
  189. static void vc4_txp_armed(struct drm_crtc_state *state)
  190. {
  191. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
  192. vc4_state->txp_armed = true;
  193. }
  194. static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
  195. struct drm_atomic_state *state)
  196. {
  197. struct drm_connector_state *conn_state;
  198. struct drm_crtc_state *crtc_state;
  199. struct drm_framebuffer *fb;
  200. int i;
  201. conn_state = drm_atomic_get_new_connector_state(state, conn);
  202. if (!conn_state->writeback_job)
  203. return 0;
  204. crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
  205. fb = conn_state->writeback_job->fb;
  206. if (fb->width != crtc_state->mode.hdisplay ||
  207. fb->height != crtc_state->mode.vdisplay) {
  208. DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
  209. fb->width, fb->height);
  210. return -EINVAL;
  211. }
  212. for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
  213. if (fb->format->format == drm_fmts[i])
  214. break;
  215. }
  216. if (i == ARRAY_SIZE(drm_fmts))
  217. return -EINVAL;
  218. /* Pitch must be aligned on 16 bytes. */
  219. if (fb->pitches[0] & GENMASK(3, 0))
  220. return -EINVAL;
  221. vc4_txp_armed(crtc_state);
  222. return 0;
  223. }
  224. static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
  225. struct drm_atomic_state *state)
  226. {
  227. struct drm_device *drm = conn->dev;
  228. struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state,
  229. conn);
  230. struct vc4_txp *txp = connector_to_vc4_txp(conn);
  231. struct drm_gem_dma_object *gem;
  232. struct drm_display_mode *mode;
  233. struct drm_framebuffer *fb;
  234. u32 ctrl;
  235. int idx;
  236. int i;
  237. if (WARN_ON(!conn_state->writeback_job))
  238. return;
  239. mode = &conn_state->crtc->state->adjusted_mode;
  240. fb = conn_state->writeback_job->fb;
  241. for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
  242. if (fb->format->format == drm_fmts[i])
  243. break;
  244. }
  245. if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
  246. return;
  247. ctrl = TXP_GO | TXP_EI |
  248. VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
  249. VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
  250. if (fb->format->has_alpha)
  251. ctrl |= TXP_ALPHA_ENABLE;
  252. else
  253. /*
  254. * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the
  255. * hardware will force the output padding to be 0xff.
  256. */
  257. ctrl |= TXP_ALPHA_INVERT;
  258. if (!drm_dev_enter(drm, &idx))
  259. return;
  260. gem = drm_fb_dma_get_gem_obj(fb, 0);
  261. TXP_WRITE(TXP_DST_PTR, gem->dma_addr + fb->offsets[0]);
  262. TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
  263. TXP_WRITE(TXP_DIM,
  264. VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
  265. VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
  266. TXP_WRITE(TXP_DST_CTRL, ctrl);
  267. drm_writeback_queue_job(&txp->connector, conn_state);
  268. drm_dev_exit(idx);
  269. }
  270. static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
  271. .get_modes = vc4_txp_connector_get_modes,
  272. .mode_valid = vc4_txp_connector_mode_valid,
  273. .atomic_check = vc4_txp_connector_atomic_check,
  274. .atomic_commit = vc4_txp_connector_atomic_commit,
  275. };
  276. static enum drm_connector_status
  277. vc4_txp_connector_detect(struct drm_connector *connector, bool force)
  278. {
  279. return connector_status_connected;
  280. }
  281. static const struct drm_connector_funcs vc4_txp_connector_funcs = {
  282. .detect = vc4_txp_connector_detect,
  283. .fill_modes = drm_helper_probe_single_connector_modes,
  284. .destroy = drm_connector_cleanup,
  285. .reset = drm_atomic_helper_connector_reset,
  286. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  287. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  288. };
  289. static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
  290. {
  291. struct drm_device *drm = encoder->dev;
  292. struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
  293. int idx;
  294. if (!drm_dev_enter(drm, &idx))
  295. return;
  296. if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
  297. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  298. TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
  299. while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
  300. time_before(jiffies, timeout))
  301. ;
  302. WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
  303. }
  304. TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
  305. drm_dev_exit(idx);
  306. }
  307. static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
  308. .disable = vc4_txp_encoder_disable,
  309. };
  310. static int vc4_txp_enable_vblank(struct drm_crtc *crtc)
  311. {
  312. return 0;
  313. }
  314. static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {}
  315. static const struct drm_crtc_funcs vc4_txp_crtc_funcs = {
  316. .set_config = drm_atomic_helper_set_config,
  317. .page_flip = vc4_page_flip,
  318. .reset = vc4_crtc_reset,
  319. .atomic_duplicate_state = vc4_crtc_duplicate_state,
  320. .atomic_destroy_state = vc4_crtc_destroy_state,
  321. .enable_vblank = vc4_txp_enable_vblank,
  322. .disable_vblank = vc4_txp_disable_vblank,
  323. .late_register = vc4_crtc_late_register,
  324. };
  325. static int vc4_txp_atomic_check(struct drm_crtc *crtc,
  326. struct drm_atomic_state *state)
  327. {
  328. struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
  329. crtc);
  330. int ret;
  331. ret = vc4_hvs_atomic_check(crtc, state);
  332. if (ret)
  333. return ret;
  334. crtc_state->no_vblank = true;
  335. return 0;
  336. }
  337. static void vc4_txp_atomic_enable(struct drm_crtc *crtc,
  338. struct drm_atomic_state *state)
  339. {
  340. drm_crtc_vblank_on(crtc);
  341. vc4_hvs_atomic_enable(crtc, state);
  342. }
  343. static void vc4_txp_atomic_disable(struct drm_crtc *crtc,
  344. struct drm_atomic_state *state)
  345. {
  346. struct drm_device *dev = crtc->dev;
  347. /* Disable vblank irq handling before crtc is disabled. */
  348. drm_crtc_vblank_off(crtc);
  349. vc4_hvs_atomic_disable(crtc, state);
  350. /*
  351. * Make sure we issue a vblank event after disabling the CRTC if
  352. * someone was waiting it.
  353. */
  354. if (crtc->state->event) {
  355. unsigned long flags;
  356. spin_lock_irqsave(&dev->event_lock, flags);
  357. drm_crtc_send_vblank_event(crtc, crtc->state->event);
  358. crtc->state->event = NULL;
  359. spin_unlock_irqrestore(&dev->event_lock, flags);
  360. }
  361. }
  362. static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = {
  363. .atomic_check = vc4_txp_atomic_check,
  364. .atomic_begin = vc4_hvs_atomic_begin,
  365. .atomic_flush = vc4_hvs_atomic_flush,
  366. .atomic_enable = vc4_txp_atomic_enable,
  367. .atomic_disable = vc4_txp_atomic_disable,
  368. };
  369. static irqreturn_t vc4_txp_interrupt(int irq, void *data)
  370. {
  371. struct vc4_txp *txp = data;
  372. struct vc4_crtc *vc4_crtc = &txp->base;
  373. /*
  374. * We don't need to protect the register access using
  375. * drm_dev_enter() there because the interrupt handler lifetime
  376. * is tied to the device itself, and not to the DRM device.
  377. *
  378. * So when the device will be gone, one of the first thing we
  379. * will be doing will be to unregister the interrupt handler,
  380. * and then unregister the DRM device. drm_dev_enter() would
  381. * thus always succeed if we are here.
  382. */
  383. TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
  384. vc4_crtc_handle_vblank(vc4_crtc);
  385. drm_writeback_signal_completion(&txp->connector, 0);
  386. return IRQ_HANDLED;
  387. }
  388. static const struct vc4_crtc_data vc4_txp_crtc_data = {
  389. .debugfs_name = "txp_regs",
  390. .hvs_available_channels = BIT(2),
  391. .hvs_output = 2,
  392. };
  393. static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
  394. {
  395. struct platform_device *pdev = to_platform_device(dev);
  396. struct drm_device *drm = dev_get_drvdata(master);
  397. struct vc4_crtc *vc4_crtc;
  398. struct vc4_txp *txp;
  399. struct drm_crtc *crtc;
  400. struct drm_encoder *encoder;
  401. int ret, irq;
  402. irq = platform_get_irq(pdev, 0);
  403. if (irq < 0)
  404. return irq;
  405. txp = drmm_kzalloc(drm, sizeof(*txp), GFP_KERNEL);
  406. if (!txp)
  407. return -ENOMEM;
  408. vc4_crtc = &txp->base;
  409. crtc = &vc4_crtc->base;
  410. vc4_crtc->pdev = pdev;
  411. vc4_crtc->data = &vc4_txp_crtc_data;
  412. vc4_crtc->feeds_txp = true;
  413. txp->pdev = pdev;
  414. txp->regs = vc4_ioremap_regs(pdev, 0);
  415. if (IS_ERR(txp->regs))
  416. return PTR_ERR(txp->regs);
  417. vc4_crtc->regset.base = txp->regs;
  418. vc4_crtc->regset.regs = txp_regs;
  419. vc4_crtc->regset.nregs = ARRAY_SIZE(txp_regs);
  420. drm_connector_helper_add(&txp->connector.base,
  421. &vc4_txp_connector_helper_funcs);
  422. ret = drm_writeback_connector_init(drm, &txp->connector,
  423. &vc4_txp_connector_funcs,
  424. &vc4_txp_encoder_helper_funcs,
  425. drm_fmts, ARRAY_SIZE(drm_fmts),
  426. 0);
  427. if (ret)
  428. return ret;
  429. ret = vc4_crtc_init(drm, vc4_crtc,
  430. &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs);
  431. if (ret)
  432. return ret;
  433. encoder = &txp->connector.encoder;
  434. encoder->possible_crtcs = drm_crtc_mask(crtc);
  435. ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
  436. dev_name(dev), txp);
  437. if (ret)
  438. return ret;
  439. dev_set_drvdata(dev, txp);
  440. return 0;
  441. }
  442. static void vc4_txp_unbind(struct device *dev, struct device *master,
  443. void *data)
  444. {
  445. struct vc4_txp *txp = dev_get_drvdata(dev);
  446. drm_connector_cleanup(&txp->connector.base);
  447. }
  448. static const struct component_ops vc4_txp_ops = {
  449. .bind = vc4_txp_bind,
  450. .unbind = vc4_txp_unbind,
  451. };
  452. static int vc4_txp_probe(struct platform_device *pdev)
  453. {
  454. return component_add(&pdev->dev, &vc4_txp_ops);
  455. }
  456. static int vc4_txp_remove(struct platform_device *pdev)
  457. {
  458. component_del(&pdev->dev, &vc4_txp_ops);
  459. return 0;
  460. }
  461. static const struct of_device_id vc4_txp_dt_match[] = {
  462. { .compatible = "brcm,bcm2835-txp" },
  463. { /* sentinel */ },
  464. };
  465. struct platform_driver vc4_txp_driver = {
  466. .probe = vc4_txp_probe,
  467. .remove = vc4_txp_remove,
  468. .driver = {
  469. .name = "vc4_txp",
  470. .of_match_table = vc4_txp_dt_match,
  471. },
  472. };