vc4_kms.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2015 Broadcom
  4. */
  5. /**
  6. * DOC: VC4 KMS
  7. *
  8. * This is the general code for implementing KMS mode setting that
  9. * doesn't clearly associate with any of the other objects (plane,
  10. * crtc, HDMI encoder).
  11. */
  12. #include <linux/clk.h>
  13. #include <drm/drm_atomic.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_crtc.h>
  16. #include <drm/drm_fourcc.h>
  17. #include <drm/drm_gem_framebuffer_helper.h>
  18. #include <drm/drm_probe_helper.h>
  19. #include <drm/drm_vblank.h>
  20. #include "vc4_drv.h"
  21. #include "vc4_regs.h"
  22. #define HVS_NUM_CHANNELS 3
  23. struct vc4_ctm_state {
  24. struct drm_private_state base;
  25. struct drm_color_ctm *ctm;
  26. int fifo;
  27. };
  28. static struct vc4_ctm_state *
  29. to_vc4_ctm_state(const struct drm_private_state *priv)
  30. {
  31. return container_of(priv, struct vc4_ctm_state, base);
  32. }
  33. struct vc4_hvs_state {
  34. struct drm_private_state base;
  35. unsigned long core_clock_rate;
  36. struct {
  37. unsigned in_use: 1;
  38. unsigned long fifo_load;
  39. struct drm_crtc_commit *pending_commit;
  40. } fifo_state[HVS_NUM_CHANNELS];
  41. };
  42. static struct vc4_hvs_state *
  43. to_vc4_hvs_state(const struct drm_private_state *priv)
  44. {
  45. return container_of(priv, struct vc4_hvs_state, base);
  46. }
  47. struct vc4_load_tracker_state {
  48. struct drm_private_state base;
  49. u64 hvs_load;
  50. u64 membus_load;
  51. };
  52. static struct vc4_load_tracker_state *
  53. to_vc4_load_tracker_state(const struct drm_private_state *priv)
  54. {
  55. return container_of(priv, struct vc4_load_tracker_state, base);
  56. }
  57. static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state,
  58. struct drm_private_obj *manager)
  59. {
  60. struct drm_device *dev = state->dev;
  61. struct vc4_dev *vc4 = to_vc4_dev(dev);
  62. struct drm_private_state *priv_state;
  63. int ret;
  64. ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx);
  65. if (ret)
  66. return ERR_PTR(ret);
  67. priv_state = drm_atomic_get_private_obj_state(state, manager);
  68. if (IS_ERR(priv_state))
  69. return ERR_CAST(priv_state);
  70. return to_vc4_ctm_state(priv_state);
  71. }
  72. static struct drm_private_state *
  73. vc4_ctm_duplicate_state(struct drm_private_obj *obj)
  74. {
  75. struct vc4_ctm_state *state;
  76. state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  77. if (!state)
  78. return NULL;
  79. __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  80. return &state->base;
  81. }
  82. static void vc4_ctm_destroy_state(struct drm_private_obj *obj,
  83. struct drm_private_state *state)
  84. {
  85. struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state);
  86. kfree(ctm_state);
  87. }
  88. static const struct drm_private_state_funcs vc4_ctm_state_funcs = {
  89. .atomic_duplicate_state = vc4_ctm_duplicate_state,
  90. .atomic_destroy_state = vc4_ctm_destroy_state,
  91. };
  92. static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused)
  93. {
  94. struct vc4_dev *vc4 = to_vc4_dev(dev);
  95. drm_atomic_private_obj_fini(&vc4->ctm_manager);
  96. }
  97. static int vc4_ctm_obj_init(struct vc4_dev *vc4)
  98. {
  99. struct vc4_ctm_state *ctm_state;
  100. drm_modeset_lock_init(&vc4->ctm_state_lock);
  101. ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL);
  102. if (!ctm_state)
  103. return -ENOMEM;
  104. drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base,
  105. &vc4_ctm_state_funcs);
  106. return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL);
  107. }
  108. /* Converts a DRM S31.32 value to the HW S0.9 format. */
  109. static u16 vc4_ctm_s31_32_to_s0_9(u64 in)
  110. {
  111. u16 r;
  112. /* Sign bit. */
  113. r = in & BIT_ULL(63) ? BIT(9) : 0;
  114. if ((in & GENMASK_ULL(62, 32)) > 0) {
  115. /* We have zero integer bits so we can only saturate here. */
  116. r |= GENMASK(8, 0);
  117. } else {
  118. /* Otherwise take the 9 most important fractional bits. */
  119. r |= (in >> 23) & GENMASK(8, 0);
  120. }
  121. return r;
  122. }
  123. static void
  124. vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
  125. {
  126. struct vc4_hvs *hvs = vc4->hvs;
  127. struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state);
  128. struct drm_color_ctm *ctm = ctm_state->ctm;
  129. if (ctm_state->fifo) {
  130. HVS_WRITE(SCALER_OLEDCOEF2,
  131. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
  132. SCALER_OLEDCOEF2_R_TO_R) |
  133. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]),
  134. SCALER_OLEDCOEF2_R_TO_G) |
  135. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]),
  136. SCALER_OLEDCOEF2_R_TO_B));
  137. HVS_WRITE(SCALER_OLEDCOEF1,
  138. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]),
  139. SCALER_OLEDCOEF1_G_TO_R) |
  140. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]),
  141. SCALER_OLEDCOEF1_G_TO_G) |
  142. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]),
  143. SCALER_OLEDCOEF1_G_TO_B));
  144. HVS_WRITE(SCALER_OLEDCOEF0,
  145. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]),
  146. SCALER_OLEDCOEF0_B_TO_R) |
  147. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]),
  148. SCALER_OLEDCOEF0_B_TO_G) |
  149. VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]),
  150. SCALER_OLEDCOEF0_B_TO_B));
  151. }
  152. HVS_WRITE(SCALER_OLEDOFFS,
  153. VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO));
  154. }
  155. static struct vc4_hvs_state *
  156. vc4_hvs_get_new_global_state(struct drm_atomic_state *state)
  157. {
  158. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  159. struct drm_private_state *priv_state;
  160. priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels);
  161. if (!priv_state)
  162. return ERR_PTR(-EINVAL);
  163. return to_vc4_hvs_state(priv_state);
  164. }
  165. static struct vc4_hvs_state *
  166. vc4_hvs_get_old_global_state(struct drm_atomic_state *state)
  167. {
  168. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  169. struct drm_private_state *priv_state;
  170. priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels);
  171. if (!priv_state)
  172. return ERR_PTR(-EINVAL);
  173. return to_vc4_hvs_state(priv_state);
  174. }
  175. static struct vc4_hvs_state *
  176. vc4_hvs_get_global_state(struct drm_atomic_state *state)
  177. {
  178. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  179. struct drm_private_state *priv_state;
  180. priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels);
  181. if (IS_ERR(priv_state))
  182. return ERR_CAST(priv_state);
  183. return to_vc4_hvs_state(priv_state);
  184. }
  185. static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
  186. struct drm_atomic_state *state)
  187. {
  188. struct vc4_hvs *hvs = vc4->hvs;
  189. struct drm_crtc_state *crtc_state;
  190. struct drm_crtc *crtc;
  191. unsigned int i;
  192. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  193. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  194. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
  195. u32 dispctrl;
  196. u32 dsp3_mux;
  197. if (!crtc_state->active)
  198. continue;
  199. if (vc4_state->assigned_channel != 2)
  200. continue;
  201. /*
  202. * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to
  203. * FIFO X'.
  204. * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'.
  205. *
  206. * DSP3 is connected to FIFO2 unless the transposer is
  207. * enabled. In this case, FIFO 2 is directly accessed by the
  208. * TXP IP, and we need to disable the FIFO2 -> pixelvalve1
  209. * route.
  210. */
  211. if (vc4_crtc->feeds_txp)
  212. dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX);
  213. else
  214. dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);
  215. dispctrl = HVS_READ(SCALER_DISPCTRL) &
  216. ~SCALER_DISPCTRL_DSP3_MUX_MASK;
  217. HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux);
  218. }
  219. }
  220. static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
  221. struct drm_atomic_state *state)
  222. {
  223. struct vc4_hvs *hvs = vc4->hvs;
  224. struct drm_crtc_state *crtc_state;
  225. struct drm_crtc *crtc;
  226. unsigned char mux;
  227. unsigned int i;
  228. u32 reg;
  229. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  230. struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
  231. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  232. unsigned int channel = vc4_state->assigned_channel;
  233. if (!vc4_state->update_muxing)
  234. continue;
  235. switch (vc4_crtc->data->hvs_output) {
  236. case 2:
  237. drm_WARN_ON(&vc4->base,
  238. VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL),
  239. SCALER_DISPCTRL_DSP3_MUX) == channel);
  240. mux = (channel == 2) ? 0 : 1;
  241. reg = HVS_READ(SCALER_DISPECTRL);
  242. HVS_WRITE(SCALER_DISPECTRL,
  243. (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) |
  244. VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX));
  245. break;
  246. case 3:
  247. if (channel == VC4_HVS_CHANNEL_DISABLED)
  248. mux = 3;
  249. else
  250. mux = channel;
  251. reg = HVS_READ(SCALER_DISPCTRL);
  252. HVS_WRITE(SCALER_DISPCTRL,
  253. (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) |
  254. VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX));
  255. break;
  256. case 4:
  257. if (channel == VC4_HVS_CHANNEL_DISABLED)
  258. mux = 3;
  259. else
  260. mux = channel;
  261. reg = HVS_READ(SCALER_DISPEOLN);
  262. HVS_WRITE(SCALER_DISPEOLN,
  263. (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) |
  264. VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX));
  265. break;
  266. case 5:
  267. if (channel == VC4_HVS_CHANNEL_DISABLED)
  268. mux = 3;
  269. else
  270. mux = channel;
  271. reg = HVS_READ(SCALER_DISPDITHER);
  272. HVS_WRITE(SCALER_DISPDITHER,
  273. (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) |
  274. VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX));
  275. break;
  276. default:
  277. break;
  278. }
  279. }
  280. }
  281. static void vc4_atomic_commit_tail(struct drm_atomic_state *state)
  282. {
  283. struct drm_device *dev = state->dev;
  284. struct vc4_dev *vc4 = to_vc4_dev(dev);
  285. struct vc4_hvs *hvs = vc4->hvs;
  286. struct drm_crtc_state *new_crtc_state;
  287. struct vc4_hvs_state *new_hvs_state;
  288. struct drm_crtc *crtc;
  289. struct vc4_hvs_state *old_hvs_state;
  290. unsigned int channel;
  291. int i;
  292. old_hvs_state = vc4_hvs_get_old_global_state(state);
  293. if (WARN_ON(IS_ERR(old_hvs_state)))
  294. return;
  295. new_hvs_state = vc4_hvs_get_new_global_state(state);
  296. if (WARN_ON(IS_ERR(new_hvs_state)))
  297. return;
  298. for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
  299. struct vc4_crtc_state *vc4_crtc_state;
  300. if (!new_crtc_state->commit)
  301. continue;
  302. vc4_crtc_state = to_vc4_crtc_state(new_crtc_state);
  303. vc4_hvs_mask_underrun(hvs, vc4_crtc_state->assigned_channel);
  304. }
  305. for (channel = 0; channel < HVS_NUM_CHANNELS; channel++) {
  306. struct drm_crtc_commit *commit;
  307. int ret;
  308. if (!old_hvs_state->fifo_state[channel].in_use)
  309. continue;
  310. commit = old_hvs_state->fifo_state[channel].pending_commit;
  311. if (!commit)
  312. continue;
  313. ret = drm_crtc_commit_wait(commit);
  314. if (ret)
  315. drm_err(dev, "Timed out waiting for commit\n");
  316. drm_crtc_commit_put(commit);
  317. old_hvs_state->fifo_state[channel].pending_commit = NULL;
  318. }
  319. if (vc4->is_vc5) {
  320. unsigned long state_rate = max(old_hvs_state->core_clock_rate,
  321. new_hvs_state->core_clock_rate);
  322. unsigned long core_rate = max_t(unsigned long,
  323. 500000000, state_rate);
  324. drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate);
  325. /*
  326. * Do a temporary request on the core clock during the
  327. * modeset.
  328. */
  329. WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
  330. }
  331. drm_atomic_helper_commit_modeset_disables(dev, state);
  332. vc4_ctm_commit(vc4, state);
  333. if (vc4->is_vc5)
  334. vc5_hvs_pv_muxing_commit(vc4, state);
  335. else
  336. vc4_hvs_pv_muxing_commit(vc4, state);
  337. drm_atomic_helper_commit_planes(dev, state,
  338. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  339. drm_atomic_helper_commit_modeset_enables(dev, state);
  340. drm_atomic_helper_fake_vblank(state);
  341. drm_atomic_helper_commit_hw_done(state);
  342. drm_atomic_helper_wait_for_flip_done(dev, state);
  343. drm_atomic_helper_cleanup_planes(dev, state);
  344. if (vc4->is_vc5) {
  345. drm_dbg(dev, "Running the core clock at %lu Hz\n",
  346. new_hvs_state->core_clock_rate);
  347. /*
  348. * Request a clock rate based on the current HVS
  349. * requirements.
  350. */
  351. WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
  352. drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
  353. clk_get_rate(hvs->core_clk));
  354. }
  355. }
  356. static int vc4_atomic_commit_setup(struct drm_atomic_state *state)
  357. {
  358. struct drm_crtc_state *crtc_state;
  359. struct vc4_hvs_state *hvs_state;
  360. struct drm_crtc *crtc;
  361. unsigned int i;
  362. hvs_state = vc4_hvs_get_new_global_state(state);
  363. if (WARN_ON(IS_ERR(hvs_state)))
  364. return PTR_ERR(hvs_state);
  365. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  366. struct vc4_crtc_state *vc4_crtc_state =
  367. to_vc4_crtc_state(crtc_state);
  368. unsigned int channel =
  369. vc4_crtc_state->assigned_channel;
  370. if (channel == VC4_HVS_CHANNEL_DISABLED)
  371. continue;
  372. if (!hvs_state->fifo_state[channel].in_use)
  373. continue;
  374. hvs_state->fifo_state[channel].pending_commit =
  375. drm_crtc_commit_get(crtc_state->commit);
  376. }
  377. return 0;
  378. }
  379. static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev,
  380. struct drm_file *file_priv,
  381. const struct drm_mode_fb_cmd2 *mode_cmd)
  382. {
  383. struct vc4_dev *vc4 = to_vc4_dev(dev);
  384. struct drm_mode_fb_cmd2 mode_cmd_local;
  385. if (WARN_ON_ONCE(vc4->is_vc5))
  386. return ERR_PTR(-ENODEV);
  387. /* If the user didn't specify a modifier, use the
  388. * vc4_set_tiling_ioctl() state for the BO.
  389. */
  390. if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
  391. struct drm_gem_object *gem_obj;
  392. struct vc4_bo *bo;
  393. gem_obj = drm_gem_object_lookup(file_priv,
  394. mode_cmd->handles[0]);
  395. if (!gem_obj) {
  396. DRM_DEBUG("Failed to look up GEM BO %d\n",
  397. mode_cmd->handles[0]);
  398. return ERR_PTR(-ENOENT);
  399. }
  400. bo = to_vc4_bo(gem_obj);
  401. mode_cmd_local = *mode_cmd;
  402. if (bo->t_format) {
  403. mode_cmd_local.modifier[0] =
  404. DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
  405. } else {
  406. mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE;
  407. }
  408. drm_gem_object_put(gem_obj);
  409. mode_cmd = &mode_cmd_local;
  410. }
  411. return drm_gem_fb_create(dev, file_priv, mode_cmd);
  412. }
  413. /* Our CTM has some peculiar limitations: we can only enable it for one CRTC
  414. * at a time and the HW only supports S0.9 scalars. To account for the latter,
  415. * we don't allow userland to set a CTM that we have no hope of approximating.
  416. */
  417. static int
  418. vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
  419. {
  420. struct vc4_dev *vc4 = to_vc4_dev(dev);
  421. struct vc4_ctm_state *ctm_state = NULL;
  422. struct drm_crtc *crtc;
  423. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  424. struct drm_color_ctm *ctm;
  425. int i;
  426. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  427. /* CTM is being disabled. */
  428. if (!new_crtc_state->ctm && old_crtc_state->ctm) {
  429. ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
  430. if (IS_ERR(ctm_state))
  431. return PTR_ERR(ctm_state);
  432. ctm_state->fifo = 0;
  433. }
  434. }
  435. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  436. if (new_crtc_state->ctm == old_crtc_state->ctm)
  437. continue;
  438. if (!ctm_state) {
  439. ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager);
  440. if (IS_ERR(ctm_state))
  441. return PTR_ERR(ctm_state);
  442. }
  443. /* CTM is being enabled or the matrix changed. */
  444. if (new_crtc_state->ctm) {
  445. struct vc4_crtc_state *vc4_crtc_state =
  446. to_vc4_crtc_state(new_crtc_state);
  447. /* fifo is 1-based since 0 disables CTM. */
  448. int fifo = vc4_crtc_state->assigned_channel + 1;
  449. /* Check userland isn't trying to turn on CTM for more
  450. * than one CRTC at a time.
  451. */
  452. if (ctm_state->fifo && ctm_state->fifo != fifo) {
  453. DRM_DEBUG_DRIVER("Too many CTM configured\n");
  454. return -EINVAL;
  455. }
  456. /* Check we can approximate the specified CTM.
  457. * We disallow scalars |c| > 1.0 since the HW has
  458. * no integer bits.
  459. */
  460. ctm = new_crtc_state->ctm->data;
  461. for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) {
  462. u64 val = ctm->matrix[i];
  463. val &= ~BIT_ULL(63);
  464. if (val > BIT_ULL(32))
  465. return -EINVAL;
  466. }
  467. ctm_state->fifo = fifo;
  468. ctm_state->ctm = ctm;
  469. }
  470. }
  471. return 0;
  472. }
  473. static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state)
  474. {
  475. struct drm_plane_state *old_plane_state, *new_plane_state;
  476. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  477. struct vc4_load_tracker_state *load_state;
  478. struct drm_private_state *priv_state;
  479. struct drm_plane *plane;
  480. int i;
  481. priv_state = drm_atomic_get_private_obj_state(state,
  482. &vc4->load_tracker);
  483. if (IS_ERR(priv_state))
  484. return PTR_ERR(priv_state);
  485. load_state = to_vc4_load_tracker_state(priv_state);
  486. for_each_oldnew_plane_in_state(state, plane, old_plane_state,
  487. new_plane_state, i) {
  488. struct vc4_plane_state *vc4_plane_state;
  489. if (old_plane_state->fb && old_plane_state->crtc) {
  490. vc4_plane_state = to_vc4_plane_state(old_plane_state);
  491. load_state->membus_load -= vc4_plane_state->membus_load;
  492. load_state->hvs_load -= vc4_plane_state->hvs_load;
  493. }
  494. if (new_plane_state->fb && new_plane_state->crtc) {
  495. vc4_plane_state = to_vc4_plane_state(new_plane_state);
  496. load_state->membus_load += vc4_plane_state->membus_load;
  497. load_state->hvs_load += vc4_plane_state->hvs_load;
  498. }
  499. }
  500. /* Don't check the load when the tracker is disabled. */
  501. if (!vc4->load_tracker_enabled)
  502. return 0;
  503. /* The absolute limit is 2Gbyte/sec, but let's take a margin to let
  504. * the system work when other blocks are accessing the memory.
  505. */
  506. if (load_state->membus_load > SZ_1G + SZ_512M)
  507. return -ENOSPC;
  508. /* HVS clock is supposed to run @ 250Mhz, let's take a margin and
  509. * consider the maximum number of cycles is 240M.
  510. */
  511. if (load_state->hvs_load > 240000000ULL)
  512. return -ENOSPC;
  513. return 0;
  514. }
  515. static struct drm_private_state *
  516. vc4_load_tracker_duplicate_state(struct drm_private_obj *obj)
  517. {
  518. struct vc4_load_tracker_state *state;
  519. state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
  520. if (!state)
  521. return NULL;
  522. __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  523. return &state->base;
  524. }
  525. static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj,
  526. struct drm_private_state *state)
  527. {
  528. struct vc4_load_tracker_state *load_state;
  529. load_state = to_vc4_load_tracker_state(state);
  530. kfree(load_state);
  531. }
  532. static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = {
  533. .atomic_duplicate_state = vc4_load_tracker_duplicate_state,
  534. .atomic_destroy_state = vc4_load_tracker_destroy_state,
  535. };
  536. static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused)
  537. {
  538. struct vc4_dev *vc4 = to_vc4_dev(dev);
  539. drm_atomic_private_obj_fini(&vc4->load_tracker);
  540. }
  541. static int vc4_load_tracker_obj_init(struct vc4_dev *vc4)
  542. {
  543. struct vc4_load_tracker_state *load_state;
  544. load_state = kzalloc(sizeof(*load_state), GFP_KERNEL);
  545. if (!load_state)
  546. return -ENOMEM;
  547. drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker,
  548. &load_state->base,
  549. &vc4_load_tracker_state_funcs);
  550. return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL);
  551. }
  552. static struct drm_private_state *
  553. vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj)
  554. {
  555. struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state);
  556. struct vc4_hvs_state *state;
  557. unsigned int i;
  558. state = kzalloc(sizeof(*state), GFP_KERNEL);
  559. if (!state)
  560. return NULL;
  561. __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
  562. for (i = 0; i < HVS_NUM_CHANNELS; i++) {
  563. state->fifo_state[i].in_use = old_state->fifo_state[i].in_use;
  564. state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load;
  565. }
  566. state->core_clock_rate = old_state->core_clock_rate;
  567. return &state->base;
  568. }
  569. static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj,
  570. struct drm_private_state *state)
  571. {
  572. struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
  573. unsigned int i;
  574. for (i = 0; i < HVS_NUM_CHANNELS; i++) {
  575. if (!hvs_state->fifo_state[i].pending_commit)
  576. continue;
  577. drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit);
  578. }
  579. kfree(hvs_state);
  580. }
  581. static void vc4_hvs_channels_print_state(struct drm_printer *p,
  582. const struct drm_private_state *state)
  583. {
  584. struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state);
  585. unsigned int i;
  586. drm_printf(p, "HVS State\n");
  587. drm_printf(p, "\tCore Clock Rate: %lu\n", hvs_state->core_clock_rate);
  588. for (i = 0; i < HVS_NUM_CHANNELS; i++) {
  589. drm_printf(p, "\tChannel %d\n", i);
  590. drm_printf(p, "\t\tin use=%d\n", hvs_state->fifo_state[i].in_use);
  591. drm_printf(p, "\t\tload=%lu\n", hvs_state->fifo_state[i].fifo_load);
  592. }
  593. }
  594. static const struct drm_private_state_funcs vc4_hvs_state_funcs = {
  595. .atomic_duplicate_state = vc4_hvs_channels_duplicate_state,
  596. .atomic_destroy_state = vc4_hvs_channels_destroy_state,
  597. .atomic_print_state = vc4_hvs_channels_print_state,
  598. };
  599. static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused)
  600. {
  601. struct vc4_dev *vc4 = to_vc4_dev(dev);
  602. drm_atomic_private_obj_fini(&vc4->hvs_channels);
  603. }
  604. static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4)
  605. {
  606. struct vc4_hvs_state *state;
  607. state = kzalloc(sizeof(*state), GFP_KERNEL);
  608. if (!state)
  609. return -ENOMEM;
  610. drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels,
  611. &state->base,
  612. &vc4_hvs_state_funcs);
  613. return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL);
  614. }
  615. /*
  616. * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and
  617. * the TXP (and therefore all the CRTCs found on that platform).
  618. *
  619. * The naive (and our initial) implementation would just iterate over
  620. * all the active CRTCs, try to find a suitable FIFO, and then remove it
  621. * from the pool of available FIFOs. However, there are a few corner
  622. * cases that need to be considered:
  623. *
  624. * - When running in a dual-display setup (so with two CRTCs involved),
  625. * we can update the state of a single CRTC (for example by changing
  626. * its mode using xrandr under X11) without affecting the other. In
  627. * this case, the other CRTC wouldn't be in the state at all, so we
  628. * need to consider all the running CRTCs in the DRM device to assign
  629. * a FIFO, not just the one in the state.
  630. *
  631. * - To fix the above, we can't use drm_atomic_get_crtc_state on all
  632. * enabled CRTCs to pull their CRTC state into the global state, since
  633. * a page flip would start considering their vblank to complete. Since
  634. * we don't have a guarantee that they are actually active, that
  635. * vblank might never happen, and shouldn't even be considered if we
  636. * want to do a page flip on a single CRTC. That can be tested by
  637. * doing a modetest -v first on HDMI1 and then on HDMI0.
  638. *
  639. * - Since we need the pixelvalve to be disabled and enabled back when
  640. * the FIFO is changed, we should keep the FIFO assigned for as long
  641. * as the CRTC is enabled, only considering it free again once that
  642. * CRTC has been disabled. This can be tested by booting X11 on a
  643. * single display, and changing the resolution down and then back up.
  644. */
  645. static int vc4_pv_muxing_atomic_check(struct drm_device *dev,
  646. struct drm_atomic_state *state)
  647. {
  648. struct vc4_hvs_state *hvs_new_state;
  649. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  650. struct drm_crtc *crtc;
  651. unsigned int unassigned_channels = 0;
  652. unsigned int i;
  653. hvs_new_state = vc4_hvs_get_global_state(state);
  654. if (IS_ERR(hvs_new_state))
  655. return PTR_ERR(hvs_new_state);
  656. for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++)
  657. if (!hvs_new_state->fifo_state[i].in_use)
  658. unassigned_channels |= BIT(i);
  659. for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
  660. struct vc4_crtc_state *old_vc4_crtc_state =
  661. to_vc4_crtc_state(old_crtc_state);
  662. struct vc4_crtc_state *new_vc4_crtc_state =
  663. to_vc4_crtc_state(new_crtc_state);
  664. struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  665. unsigned int matching_channels;
  666. unsigned int channel;
  667. drm_dbg(dev, "%s: Trying to find a channel.\n", crtc->name);
  668. /* Nothing to do here, let's skip it */
  669. if (old_crtc_state->enable == new_crtc_state->enable) {
  670. if (new_crtc_state->enable)
  671. drm_dbg(dev, "%s: Already enabled, reusing channel %d.\n",
  672. crtc->name, new_vc4_crtc_state->assigned_channel);
  673. else
  674. drm_dbg(dev, "%s: Disabled, ignoring.\n", crtc->name);
  675. continue;
  676. }
  677. /* Muxing will need to be modified, mark it as such */
  678. new_vc4_crtc_state->update_muxing = true;
  679. /* If we're disabling our CRTC, we put back our channel */
  680. if (!new_crtc_state->enable) {
  681. channel = old_vc4_crtc_state->assigned_channel;
  682. drm_dbg(dev, "%s: Disabling, Freeing channel %d\n",
  683. crtc->name, channel);
  684. hvs_new_state->fifo_state[channel].in_use = false;
  685. new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
  686. continue;
  687. }
  688. /*
  689. * The problem we have to solve here is that we have
  690. * up to 7 encoders, connected to up to 6 CRTCs.
  691. *
  692. * Those CRTCs, depending on the instance, can be
  693. * routed to 1, 2 or 3 HVS FIFOs, and we need to set
  694. * the change the muxing between FIFOs and outputs in
  695. * the HVS accordingly.
  696. *
  697. * It would be pretty hard to come up with an
  698. * algorithm that would generically solve
  699. * this. However, the current routing trees we support
  700. * allow us to simplify a bit the problem.
  701. *
  702. * Indeed, with the current supported layouts, if we
  703. * try to assign in the ascending crtc index order the
  704. * FIFOs, we can't fall into the situation where an
  705. * earlier CRTC that had multiple routes is assigned
  706. * one that was the only option for a later CRTC.
  707. *
  708. * If the layout changes and doesn't give us that in
  709. * the future, we will need to have something smarter,
  710. * but it works so far.
  711. */
  712. matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels;
  713. if (!matching_channels)
  714. return -EINVAL;
  715. channel = ffs(matching_channels) - 1;
  716. drm_dbg(dev, "Assigned HVS channel %d to CRTC %s\n", channel, crtc->name);
  717. new_vc4_crtc_state->assigned_channel = channel;
  718. unassigned_channels &= ~BIT(channel);
  719. hvs_new_state->fifo_state[channel].in_use = true;
  720. }
  721. return 0;
  722. }
  723. static int
  724. vc4_core_clock_atomic_check(struct drm_atomic_state *state)
  725. {
  726. struct vc4_dev *vc4 = to_vc4_dev(state->dev);
  727. struct drm_private_state *priv_state;
  728. struct vc4_hvs_state *hvs_new_state;
  729. struct vc4_load_tracker_state *load_state;
  730. struct drm_crtc_state *old_crtc_state, *new_crtc_state;
  731. struct drm_crtc *crtc;
  732. unsigned int num_outputs;
  733. unsigned long pixel_rate;
  734. unsigned long cob_rate;
  735. unsigned int i;
  736. priv_state = drm_atomic_get_private_obj_state(state,
  737. &vc4->load_tracker);
  738. if (IS_ERR(priv_state))
  739. return PTR_ERR(priv_state);
  740. load_state = to_vc4_load_tracker_state(priv_state);
  741. hvs_new_state = vc4_hvs_get_global_state(state);
  742. if (IS_ERR(hvs_new_state))
  743. return PTR_ERR(hvs_new_state);
  744. for_each_oldnew_crtc_in_state(state, crtc,
  745. old_crtc_state,
  746. new_crtc_state,
  747. i) {
  748. if (old_crtc_state->active) {
  749. struct vc4_crtc_state *old_vc4_state =
  750. to_vc4_crtc_state(old_crtc_state);
  751. unsigned int channel = old_vc4_state->assigned_channel;
  752. hvs_new_state->fifo_state[channel].fifo_load = 0;
  753. }
  754. if (new_crtc_state->active) {
  755. struct vc4_crtc_state *new_vc4_state =
  756. to_vc4_crtc_state(new_crtc_state);
  757. unsigned int channel = new_vc4_state->assigned_channel;
  758. hvs_new_state->fifo_state[channel].fifo_load =
  759. new_vc4_state->hvs_load;
  760. }
  761. }
  762. cob_rate = 0;
  763. num_outputs = 0;
  764. for (i = 0; i < HVS_NUM_CHANNELS; i++) {
  765. if (!hvs_new_state->fifo_state[i].in_use)
  766. continue;
  767. num_outputs++;
  768. cob_rate = max_t(unsigned long,
  769. hvs_new_state->fifo_state[i].fifo_load,
  770. cob_rate);
  771. }
  772. pixel_rate = load_state->hvs_load;
  773. if (num_outputs > 1) {
  774. pixel_rate = (pixel_rate * 40) / 100;
  775. } else {
  776. pixel_rate = (pixel_rate * 60) / 100;
  777. }
  778. hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate);
  779. return 0;
  780. }
  781. static int
  782. vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
  783. {
  784. int ret;
  785. ret = vc4_pv_muxing_atomic_check(dev, state);
  786. if (ret)
  787. return ret;
  788. ret = vc4_ctm_atomic_check(dev, state);
  789. if (ret < 0)
  790. return ret;
  791. ret = drm_atomic_helper_check(dev, state);
  792. if (ret)
  793. return ret;
  794. ret = vc4_load_tracker_atomic_check(state);
  795. if (ret)
  796. return ret;
  797. return vc4_core_clock_atomic_check(state);
  798. }
  799. static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = {
  800. .atomic_commit_setup = vc4_atomic_commit_setup,
  801. .atomic_commit_tail = vc4_atomic_commit_tail,
  802. };
  803. static const struct drm_mode_config_funcs vc4_mode_funcs = {
  804. .atomic_check = vc4_atomic_check,
  805. .atomic_commit = drm_atomic_helper_commit,
  806. .fb_create = vc4_fb_create,
  807. };
  808. static const struct drm_mode_config_funcs vc5_mode_funcs = {
  809. .atomic_check = vc4_atomic_check,
  810. .atomic_commit = drm_atomic_helper_commit,
  811. .fb_create = drm_gem_fb_create,
  812. };
  813. int vc4_kms_load(struct drm_device *dev)
  814. {
  815. struct vc4_dev *vc4 = to_vc4_dev(dev);
  816. int ret;
  817. /*
  818. * The limits enforced by the load tracker aren't relevant for
  819. * the BCM2711, but the load tracker computations are used for
  820. * the core clock rate calculation.
  821. */
  822. if (!vc4->is_vc5) {
  823. /* Start with the load tracker enabled. Can be
  824. * disabled through the debugfs load_tracker file.
  825. */
  826. vc4->load_tracker_enabled = true;
  827. }
  828. /* Set support for vblank irq fast disable, before drm_vblank_init() */
  829. dev->vblank_disable_immediate = true;
  830. ret = drm_vblank_init(dev, dev->mode_config.num_crtc);
  831. if (ret < 0) {
  832. dev_err(dev->dev, "failed to initialize vblank\n");
  833. return ret;
  834. }
  835. if (vc4->is_vc5) {
  836. dev->mode_config.max_width = 7680;
  837. dev->mode_config.max_height = 7680;
  838. } else {
  839. dev->mode_config.max_width = 2048;
  840. dev->mode_config.max_height = 2048;
  841. }
  842. dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs;
  843. dev->mode_config.helper_private = &vc4_mode_config_helpers;
  844. dev->mode_config.preferred_depth = 24;
  845. dev->mode_config.async_page_flip = true;
  846. ret = vc4_ctm_obj_init(vc4);
  847. if (ret)
  848. return ret;
  849. ret = vc4_load_tracker_obj_init(vc4);
  850. if (ret)
  851. return ret;
  852. ret = vc4_hvs_channels_obj_init(vc4);
  853. if (ret)
  854. return ret;
  855. drm_mode_config_reset(dev);
  856. drm_kms_helper_poll_init(dev);
  857. return 0;
  858. }