sti_vtg.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2014
  4. * Authors: Benjamin Gaignard <[email protected]>
  5. * Fabien Dessenne <[email protected]>
  6. * Vincent Abriou <[email protected]>
  7. * for STMicroelectronics.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/io.h>
  11. #include <linux/notifier.h>
  12. #include <linux/of_platform.h>
  13. #include <linux/platform_device.h>
  14. #include <drm/drm_modes.h>
  15. #include <drm/drm_print.h>
  16. #include "sti_drv.h"
  17. #include "sti_vtg.h"
  18. #define VTG_MODE_MASTER 0
  19. /* registers offset */
  20. #define VTG_MODE 0x0000
  21. #define VTG_CLKLN 0x0008
  22. #define VTG_HLFLN 0x000C
  23. #define VTG_DRST_AUTOC 0x0010
  24. #define VTG_VID_TFO 0x0040
  25. #define VTG_VID_TFS 0x0044
  26. #define VTG_VID_BFO 0x0048
  27. #define VTG_VID_BFS 0x004C
  28. #define VTG_HOST_ITS 0x0078
  29. #define VTG_HOST_ITS_BCLR 0x007C
  30. #define VTG_HOST_ITM_BCLR 0x0088
  31. #define VTG_HOST_ITM_BSET 0x008C
  32. #define VTG_H_HD_1 0x00C0
  33. #define VTG_TOP_V_VD_1 0x00C4
  34. #define VTG_BOT_V_VD_1 0x00C8
  35. #define VTG_TOP_V_HD_1 0x00CC
  36. #define VTG_BOT_V_HD_1 0x00D0
  37. #define VTG_H_HD_2 0x00E0
  38. #define VTG_TOP_V_VD_2 0x00E4
  39. #define VTG_BOT_V_VD_2 0x00E8
  40. #define VTG_TOP_V_HD_2 0x00EC
  41. #define VTG_BOT_V_HD_2 0x00F0
  42. #define VTG_H_HD_3 0x0100
  43. #define VTG_TOP_V_VD_3 0x0104
  44. #define VTG_BOT_V_VD_3 0x0108
  45. #define VTG_TOP_V_HD_3 0x010C
  46. #define VTG_BOT_V_HD_3 0x0110
  47. #define VTG_H_HD_4 0x0120
  48. #define VTG_TOP_V_VD_4 0x0124
  49. #define VTG_BOT_V_VD_4 0x0128
  50. #define VTG_TOP_V_HD_4 0x012c
  51. #define VTG_BOT_V_HD_4 0x0130
  52. #define VTG_IRQ_BOTTOM BIT(0)
  53. #define VTG_IRQ_TOP BIT(1)
  54. #define VTG_IRQ_MASK (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
  55. /* Delay introduced by the HDMI in nb of pixel */
  56. #define HDMI_DELAY (5)
  57. /* Delay introduced by the DVO in nb of pixel */
  58. #define DVO_DELAY (7)
  59. /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
  60. #define AWG_DELAY_HD (-9)
  61. #define AWG_DELAY_ED (-8)
  62. #define AWG_DELAY_SD (-7)
  63. /*
  64. * STI VTG register offset structure
  65. *
  66. *@h_hd: stores the VTG_H_HD_x register offset
  67. *@top_v_vd: stores the VTG_TOP_V_VD_x register offset
  68. *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
  69. *@top_v_hd: stores the VTG_TOP_V_HD_x register offset
  70. *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset
  71. */
  72. struct sti_vtg_regs_offs {
  73. u32 h_hd;
  74. u32 top_v_vd;
  75. u32 bot_v_vd;
  76. u32 top_v_hd;
  77. u32 bot_v_hd;
  78. };
  79. #define VTG_MAX_SYNC_OUTPUT 4
  80. static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = {
  81. { VTG_H_HD_1,
  82. VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 },
  83. { VTG_H_HD_2,
  84. VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 },
  85. { VTG_H_HD_3,
  86. VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 },
  87. { VTG_H_HD_4,
  88. VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }
  89. };
  90. /*
  91. * STI VTG synchronisation parameters structure
  92. *
  93. *@hsync: sample number falling and rising edge
  94. *@vsync_line_top: vertical top field line number falling and rising edge
  95. *@vsync_line_bot: vertical bottom field line number falling and rising edge
  96. *@vsync_off_top: vertical top field sample number rising and falling edge
  97. *@vsync_off_bot: vertical bottom field sample number rising and falling edge
  98. */
  99. struct sti_vtg_sync_params {
  100. u32 hsync;
  101. u32 vsync_line_top;
  102. u32 vsync_line_bot;
  103. u32 vsync_off_top;
  104. u32 vsync_off_bot;
  105. };
  106. /*
  107. * STI VTG structure
  108. *
  109. * @regs: register mapping
  110. * @sync_params: synchronisation parameters used to generate timings
  111. * @irq: VTG irq
  112. * @irq_status: store the IRQ status value
  113. * @notifier_list: notifier callback
  114. * @crtc: the CRTC for vblank event
  115. */
  116. struct sti_vtg {
  117. void __iomem *regs;
  118. struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT];
  119. int irq;
  120. u32 irq_status;
  121. struct raw_notifier_head notifier_list;
  122. struct drm_crtc *crtc;
  123. };
  124. struct sti_vtg *of_vtg_find(struct device_node *np)
  125. {
  126. struct platform_device *pdev;
  127. pdev = of_find_device_by_node(np);
  128. if (!pdev)
  129. return NULL;
  130. return (struct sti_vtg *)platform_get_drvdata(pdev);
  131. }
  132. static void vtg_reset(struct sti_vtg *vtg)
  133. {
  134. writel(1, vtg->regs + VTG_DRST_AUTOC);
  135. }
  136. static void vtg_set_output_window(void __iomem *regs,
  137. const struct drm_display_mode *mode)
  138. {
  139. u32 video_top_field_start;
  140. u32 video_top_field_stop;
  141. u32 video_bottom_field_start;
  142. u32 video_bottom_field_stop;
  143. u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
  144. u32 ystart = sti_vtg_get_line_number(*mode, 0);
  145. u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
  146. u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
  147. /* Set output window to fit the display mode selected */
  148. video_top_field_start = (ystart << 16) | xstart;
  149. video_top_field_stop = (ystop << 16) | xstop;
  150. /* Only progressive supported for now */
  151. video_bottom_field_start = video_top_field_start;
  152. video_bottom_field_stop = video_top_field_stop;
  153. writel(video_top_field_start, regs + VTG_VID_TFO);
  154. writel(video_top_field_stop, regs + VTG_VID_TFS);
  155. writel(video_bottom_field_start, regs + VTG_VID_BFO);
  156. writel(video_bottom_field_stop, regs + VTG_VID_BFS);
  157. }
  158. static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync,
  159. int delay,
  160. const struct drm_display_mode *mode)
  161. {
  162. long clocksperline, start, stop;
  163. u32 risesync_top, fallsync_top;
  164. u32 risesync_offs_top, fallsync_offs_top;
  165. clocksperline = mode->htotal;
  166. /* Get the hsync position */
  167. start = 0;
  168. stop = mode->hsync_end - mode->hsync_start;
  169. start += delay;
  170. stop += delay;
  171. if (start < 0)
  172. start += clocksperline;
  173. else if (start >= clocksperline)
  174. start -= clocksperline;
  175. if (stop < 0)
  176. stop += clocksperline;
  177. else if (stop >= clocksperline)
  178. stop -= clocksperline;
  179. sync->hsync = (stop << 16) | start;
  180. /* Get the vsync position */
  181. if (delay >= 0) {
  182. risesync_top = 1;
  183. fallsync_top = risesync_top;
  184. fallsync_top += mode->vsync_end - mode->vsync_start;
  185. fallsync_offs_top = (u32)delay;
  186. risesync_offs_top = (u32)delay;
  187. } else {
  188. risesync_top = mode->vtotal;
  189. fallsync_top = mode->vsync_end - mode->vsync_start;
  190. fallsync_offs_top = clocksperline + delay;
  191. risesync_offs_top = clocksperline + delay;
  192. }
  193. sync->vsync_line_top = (fallsync_top << 16) | risesync_top;
  194. sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top;
  195. /* Only progressive supported for now */
  196. sync->vsync_line_bot = sync->vsync_line_top;
  197. sync->vsync_off_bot = sync->vsync_off_top;
  198. }
  199. static void vtg_set_mode(struct sti_vtg *vtg,
  200. int type,
  201. struct sti_vtg_sync_params *sync,
  202. const struct drm_display_mode *mode)
  203. {
  204. unsigned int i;
  205. /* Set the number of clock cycles per line */
  206. writel(mode->htotal, vtg->regs + VTG_CLKLN);
  207. /* Set Half Line Per Field (only progressive supported for now) */
  208. writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
  209. /* Program output window */
  210. vtg_set_output_window(vtg->regs, mode);
  211. /* Set hsync and vsync position for HDMI */
  212. vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode);
  213. /* Set hsync and vsync position for HD DCS */
  214. vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode);
  215. /* Set hsync and vsync position for HDF */
  216. vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode);
  217. /* Set hsync and vsync position for DVO */
  218. vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode);
  219. /* Progam the syncs outputs */
  220. for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) {
  221. writel(sync[i].hsync,
  222. vtg->regs + vtg_regs_offs[i].h_hd);
  223. writel(sync[i].vsync_line_top,
  224. vtg->regs + vtg_regs_offs[i].top_v_vd);
  225. writel(sync[i].vsync_line_bot,
  226. vtg->regs + vtg_regs_offs[i].bot_v_vd);
  227. writel(sync[i].vsync_off_top,
  228. vtg->regs + vtg_regs_offs[i].top_v_hd);
  229. writel(sync[i].vsync_off_bot,
  230. vtg->regs + vtg_regs_offs[i].bot_v_hd);
  231. }
  232. /* mode */
  233. writel(type, vtg->regs + VTG_MODE);
  234. }
  235. static void vtg_enable_irq(struct sti_vtg *vtg)
  236. {
  237. /* clear interrupt status and mask */
  238. writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
  239. writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
  240. writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
  241. }
  242. void sti_vtg_set_config(struct sti_vtg *vtg,
  243. const struct drm_display_mode *mode)
  244. {
  245. /* write configuration */
  246. vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode);
  247. vtg_reset(vtg);
  248. vtg_enable_irq(vtg);
  249. }
  250. /**
  251. * sti_vtg_get_line_number
  252. *
  253. * @mode: display mode to be used
  254. * @y: line
  255. *
  256. * Return the line number according to the display mode taking
  257. * into account the Sync and Back Porch information.
  258. * Video frame line numbers start at 1, y starts at 0.
  259. * In interlaced modes the start line is the field line number of the odd
  260. * field, but y is still defined as a progressive frame.
  261. */
  262. u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y)
  263. {
  264. u32 start_line = mode.vtotal - mode.vsync_start + 1;
  265. if (mode.flags & DRM_MODE_FLAG_INTERLACE)
  266. start_line *= 2;
  267. return start_line + y;
  268. }
  269. /**
  270. * sti_vtg_get_pixel_number
  271. *
  272. * @mode: display mode to be used
  273. * @x: row
  274. *
  275. * Return the pixel number according to the display mode taking
  276. * into account the Sync and Back Porch information.
  277. * Pixels are counted from 0.
  278. */
  279. u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x)
  280. {
  281. return mode.htotal - mode.hsync_start + x;
  282. }
  283. int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb,
  284. struct drm_crtc *crtc)
  285. {
  286. vtg->crtc = crtc;
  287. return raw_notifier_chain_register(&vtg->notifier_list, nb);
  288. }
  289. int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb)
  290. {
  291. return raw_notifier_chain_unregister(&vtg->notifier_list, nb);
  292. }
  293. static irqreturn_t vtg_irq_thread(int irq, void *arg)
  294. {
  295. struct sti_vtg *vtg = arg;
  296. u32 event;
  297. event = (vtg->irq_status & VTG_IRQ_TOP) ?
  298. VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT;
  299. raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc);
  300. return IRQ_HANDLED;
  301. }
  302. static irqreturn_t vtg_irq(int irq, void *arg)
  303. {
  304. struct sti_vtg *vtg = arg;
  305. vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS);
  306. writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
  307. /* force sync bus write */
  308. readl(vtg->regs + VTG_HOST_ITS);
  309. return IRQ_WAKE_THREAD;
  310. }
  311. static int vtg_probe(struct platform_device *pdev)
  312. {
  313. struct device *dev = &pdev->dev;
  314. struct sti_vtg *vtg;
  315. struct resource *res;
  316. int ret;
  317. vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL);
  318. if (!vtg)
  319. return -ENOMEM;
  320. /* Get Memory ressources */
  321. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  322. if (!res) {
  323. DRM_ERROR("Get memory resource failed\n");
  324. return -ENOMEM;
  325. }
  326. vtg->regs = devm_ioremap(dev, res->start, resource_size(res));
  327. if (!vtg->regs) {
  328. DRM_ERROR("failed to remap I/O memory\n");
  329. return -ENOMEM;
  330. }
  331. vtg->irq = platform_get_irq(pdev, 0);
  332. if (vtg->irq < 0) {
  333. DRM_ERROR("Failed to get VTG interrupt\n");
  334. return vtg->irq;
  335. }
  336. RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list);
  337. ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq,
  338. vtg_irq_thread, IRQF_ONESHOT,
  339. dev_name(dev), vtg);
  340. if (ret < 0) {
  341. DRM_ERROR("Failed to register VTG interrupt\n");
  342. return ret;
  343. }
  344. platform_set_drvdata(pdev, vtg);
  345. DRM_INFO("%s %s\n", __func__, dev_name(dev));
  346. return 0;
  347. }
  348. static const struct of_device_id vtg_of_match[] = {
  349. { .compatible = "st,vtg", },
  350. { /* sentinel */ }
  351. };
  352. MODULE_DEVICE_TABLE(of, vtg_of_match);
  353. struct platform_driver sti_vtg_driver = {
  354. .driver = {
  355. .name = "sti-vtg",
  356. .owner = THIS_MODULE,
  357. .of_match_table = vtg_of_match,
  358. },
  359. .probe = vtg_probe,
  360. };
  361. MODULE_AUTHOR("Benjamin Gaignard <[email protected]>");
  362. MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
  363. MODULE_LICENSE("GPL");