sti_gdp.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) STMicroelectronics SA 2014
  4. * Authors: Benjamin Gaignard <[email protected]>
  5. * Fabien Dessenne <[email protected]>
  6. * for STMicroelectronics.
  7. */
  8. #include <linux/dma-mapping.h>
  9. #include <linux/of.h>
  10. #include <linux/seq_file.h>
  11. #include <drm/drm_atomic.h>
  12. #include <drm/drm_device.h>
  13. #include <drm/drm_fb_dma_helper.h>
  14. #include <drm/drm_fourcc.h>
  15. #include <drm/drm_framebuffer.h>
  16. #include <drm/drm_gem_dma_helper.h>
  17. #include "sti_compositor.h"
  18. #include "sti_gdp.h"
  19. #include "sti_plane.h"
  20. #include "sti_vtg.h"
  21. #define ALPHASWITCH BIT(6)
  22. #define ENA_COLOR_FILL BIT(8)
  23. #define BIGNOTLITTLE BIT(23)
  24. #define WAIT_NEXT_VSYNC BIT(31)
  25. /* GDP color formats */
  26. #define GDP_RGB565 0x00
  27. #define GDP_RGB888 0x01
  28. #define GDP_RGB888_32 0x02
  29. #define GDP_XBGR8888 (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
  30. #define GDP_ARGB8565 0x04
  31. #define GDP_ARGB8888 0x05
  32. #define GDP_ABGR8888 (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
  33. #define GDP_ARGB1555 0x06
  34. #define GDP_ARGB4444 0x07
  35. #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
  36. static struct gdp_format_to_str {
  37. int format;
  38. char name[20];
  39. } gdp_format_to_str[] = {
  40. GDP2STR(RGB565),
  41. GDP2STR(RGB888),
  42. GDP2STR(RGB888_32),
  43. GDP2STR(XBGR8888),
  44. GDP2STR(ARGB8565),
  45. GDP2STR(ARGB8888),
  46. GDP2STR(ABGR8888),
  47. GDP2STR(ARGB1555),
  48. GDP2STR(ARGB4444)
  49. };
  50. #define GAM_GDP_CTL_OFFSET 0x00
  51. #define GAM_GDP_AGC_OFFSET 0x04
  52. #define GAM_GDP_VPO_OFFSET 0x0C
  53. #define GAM_GDP_VPS_OFFSET 0x10
  54. #define GAM_GDP_PML_OFFSET 0x14
  55. #define GAM_GDP_PMP_OFFSET 0x18
  56. #define GAM_GDP_SIZE_OFFSET 0x1C
  57. #define GAM_GDP_NVN_OFFSET 0x24
  58. #define GAM_GDP_KEY1_OFFSET 0x28
  59. #define GAM_GDP_KEY2_OFFSET 0x2C
  60. #define GAM_GDP_PPT_OFFSET 0x34
  61. #define GAM_GDP_CML_OFFSET 0x3C
  62. #define GAM_GDP_MST_OFFSET 0x68
  63. #define GAM_GDP_ALPHARANGE_255 BIT(5)
  64. #define GAM_GDP_AGC_FULL_RANGE 0x00808080
  65. #define GAM_GDP_PPT_IGNORE (BIT(1) | BIT(0))
  66. #define GAM_GDP_SIZE_MAX_WIDTH 3840
  67. #define GAM_GDP_SIZE_MAX_HEIGHT 2160
  68. #define GDP_NODE_NB_BANK 2
  69. #define GDP_NODE_PER_FIELD 2
  70. struct sti_gdp_node {
  71. u32 gam_gdp_ctl;
  72. u32 gam_gdp_agc;
  73. u32 reserved1;
  74. u32 gam_gdp_vpo;
  75. u32 gam_gdp_vps;
  76. u32 gam_gdp_pml;
  77. u32 gam_gdp_pmp;
  78. u32 gam_gdp_size;
  79. u32 reserved2;
  80. u32 gam_gdp_nvn;
  81. u32 gam_gdp_key1;
  82. u32 gam_gdp_key2;
  83. u32 reserved3;
  84. u32 gam_gdp_ppt;
  85. u32 reserved4;
  86. u32 gam_gdp_cml;
  87. };
  88. struct sti_gdp_node_list {
  89. struct sti_gdp_node *top_field;
  90. dma_addr_t top_field_paddr;
  91. struct sti_gdp_node *btm_field;
  92. dma_addr_t btm_field_paddr;
  93. };
  94. /*
  95. * STI GDP structure
  96. *
  97. * @sti_plane: sti_plane structure
  98. * @dev: driver device
  99. * @regs: gdp registers
  100. * @clk_pix: pixel clock for the current gdp
  101. * @clk_main_parent: gdp parent clock if main path used
  102. * @clk_aux_parent: gdp parent clock if aux path used
  103. * @vtg_field_nb: callback for VTG FIELD (top or bottom) notification
  104. * @is_curr_top: true if the current node processed is the top field
  105. * @node_list: array of node list
  106. * @vtg: registered vtg
  107. */
  108. struct sti_gdp {
  109. struct sti_plane plane;
  110. struct device *dev;
  111. void __iomem *regs;
  112. struct clk *clk_pix;
  113. struct clk *clk_main_parent;
  114. struct clk *clk_aux_parent;
  115. struct notifier_block vtg_field_nb;
  116. bool is_curr_top;
  117. struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
  118. struct sti_vtg *vtg;
  119. };
  120. #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
  121. static const uint32_t gdp_supported_formats[] = {
  122. DRM_FORMAT_XRGB8888,
  123. DRM_FORMAT_XBGR8888,
  124. DRM_FORMAT_ARGB8888,
  125. DRM_FORMAT_ABGR8888,
  126. DRM_FORMAT_ARGB4444,
  127. DRM_FORMAT_ARGB1555,
  128. DRM_FORMAT_RGB565,
  129. DRM_FORMAT_RGB888,
  130. };
  131. #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
  132. readl(gdp->regs + reg ## _OFFSET))
  133. static void gdp_dbg_ctl(struct seq_file *s, int val)
  134. {
  135. int i;
  136. seq_puts(s, "\tColor:");
  137. for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
  138. if (gdp_format_to_str[i].format == (val & 0x1F)) {
  139. seq_puts(s, gdp_format_to_str[i].name);
  140. break;
  141. }
  142. }
  143. if (i == ARRAY_SIZE(gdp_format_to_str))
  144. seq_puts(s, "<UNKNOWN>");
  145. seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
  146. }
  147. static void gdp_dbg_vpo(struct seq_file *s, int val)
  148. {
  149. seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
  150. }
  151. static void gdp_dbg_vps(struct seq_file *s, int val)
  152. {
  153. seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
  154. }
  155. static void gdp_dbg_size(struct seq_file *s, int val)
  156. {
  157. seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
  158. }
  159. static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
  160. {
  161. void *base = NULL;
  162. unsigned int i;
  163. for (i = 0; i < GDP_NODE_NB_BANK; i++) {
  164. if (gdp->node_list[i].top_field_paddr == val) {
  165. base = gdp->node_list[i].top_field;
  166. break;
  167. }
  168. if (gdp->node_list[i].btm_field_paddr == val) {
  169. base = gdp->node_list[i].btm_field;
  170. break;
  171. }
  172. }
  173. if (base)
  174. seq_printf(s, "\tVirt @: %p", base);
  175. }
  176. static void gdp_dbg_ppt(struct seq_file *s, int val)
  177. {
  178. if (val & GAM_GDP_PPT_IGNORE)
  179. seq_puts(s, "\tNot displayed on mixer!");
  180. }
  181. static void gdp_dbg_mst(struct seq_file *s, int val)
  182. {
  183. if (val & 1)
  184. seq_puts(s, "\tBUFFER UNDERFLOW!");
  185. }
  186. static int gdp_dbg_show(struct seq_file *s, void *data)
  187. {
  188. struct drm_info_node *node = s->private;
  189. struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
  190. struct drm_plane *drm_plane = &gdp->plane.drm_plane;
  191. struct drm_crtc *crtc;
  192. drm_modeset_lock(&drm_plane->mutex, NULL);
  193. crtc = drm_plane->state->crtc;
  194. drm_modeset_unlock(&drm_plane->mutex);
  195. seq_printf(s, "%s: (vaddr = 0x%p)",
  196. sti_plane_to_str(&gdp->plane), gdp->regs);
  197. DBGFS_DUMP(GAM_GDP_CTL);
  198. gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
  199. DBGFS_DUMP(GAM_GDP_AGC);
  200. DBGFS_DUMP(GAM_GDP_VPO);
  201. gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
  202. DBGFS_DUMP(GAM_GDP_VPS);
  203. gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
  204. DBGFS_DUMP(GAM_GDP_PML);
  205. DBGFS_DUMP(GAM_GDP_PMP);
  206. DBGFS_DUMP(GAM_GDP_SIZE);
  207. gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
  208. DBGFS_DUMP(GAM_GDP_NVN);
  209. gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
  210. DBGFS_DUMP(GAM_GDP_KEY1);
  211. DBGFS_DUMP(GAM_GDP_KEY2);
  212. DBGFS_DUMP(GAM_GDP_PPT);
  213. gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
  214. DBGFS_DUMP(GAM_GDP_CML);
  215. DBGFS_DUMP(GAM_GDP_MST);
  216. gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
  217. seq_puts(s, "\n\n");
  218. if (!crtc)
  219. seq_puts(s, " Not connected to any DRM CRTC\n");
  220. else
  221. seq_printf(s, " Connected to DRM CRTC #%d (%s)\n",
  222. crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
  223. return 0;
  224. }
  225. static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
  226. {
  227. seq_printf(s, "\t@:0x%p", node);
  228. seq_printf(s, "\n\tCTL 0x%08X", node->gam_gdp_ctl);
  229. gdp_dbg_ctl(s, node->gam_gdp_ctl);
  230. seq_printf(s, "\n\tAGC 0x%08X", node->gam_gdp_agc);
  231. seq_printf(s, "\n\tVPO 0x%08X", node->gam_gdp_vpo);
  232. gdp_dbg_vpo(s, node->gam_gdp_vpo);
  233. seq_printf(s, "\n\tVPS 0x%08X", node->gam_gdp_vps);
  234. gdp_dbg_vps(s, node->gam_gdp_vps);
  235. seq_printf(s, "\n\tPML 0x%08X", node->gam_gdp_pml);
  236. seq_printf(s, "\n\tPMP 0x%08X", node->gam_gdp_pmp);
  237. seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
  238. gdp_dbg_size(s, node->gam_gdp_size);
  239. seq_printf(s, "\n\tNVN 0x%08X", node->gam_gdp_nvn);
  240. seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
  241. seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
  242. seq_printf(s, "\n\tPPT 0x%08X", node->gam_gdp_ppt);
  243. gdp_dbg_ppt(s, node->gam_gdp_ppt);
  244. seq_printf(s, "\n\tCML 0x%08X\n", node->gam_gdp_cml);
  245. }
  246. static int gdp_node_dbg_show(struct seq_file *s, void *arg)
  247. {
  248. struct drm_info_node *node = s->private;
  249. struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
  250. unsigned int b;
  251. for (b = 0; b < GDP_NODE_NB_BANK; b++) {
  252. seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
  253. gdp_node_dump_node(s, gdp->node_list[b].top_field);
  254. seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
  255. gdp_node_dump_node(s, gdp->node_list[b].btm_field);
  256. }
  257. return 0;
  258. }
  259. static struct drm_info_list gdp0_debugfs_files[] = {
  260. { "gdp0", gdp_dbg_show, 0, NULL },
  261. { "gdp0_node", gdp_node_dbg_show, 0, NULL },
  262. };
  263. static struct drm_info_list gdp1_debugfs_files[] = {
  264. { "gdp1", gdp_dbg_show, 0, NULL },
  265. { "gdp1_node", gdp_node_dbg_show, 0, NULL },
  266. };
  267. static struct drm_info_list gdp2_debugfs_files[] = {
  268. { "gdp2", gdp_dbg_show, 0, NULL },
  269. { "gdp2_node", gdp_node_dbg_show, 0, NULL },
  270. };
  271. static struct drm_info_list gdp3_debugfs_files[] = {
  272. { "gdp3", gdp_dbg_show, 0, NULL },
  273. { "gdp3_node", gdp_node_dbg_show, 0, NULL },
  274. };
  275. static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
  276. {
  277. unsigned int i;
  278. struct drm_info_list *gdp_debugfs_files;
  279. int nb_files;
  280. switch (gdp->plane.desc) {
  281. case STI_GDP_0:
  282. gdp_debugfs_files = gdp0_debugfs_files;
  283. nb_files = ARRAY_SIZE(gdp0_debugfs_files);
  284. break;
  285. case STI_GDP_1:
  286. gdp_debugfs_files = gdp1_debugfs_files;
  287. nb_files = ARRAY_SIZE(gdp1_debugfs_files);
  288. break;
  289. case STI_GDP_2:
  290. gdp_debugfs_files = gdp2_debugfs_files;
  291. nb_files = ARRAY_SIZE(gdp2_debugfs_files);
  292. break;
  293. case STI_GDP_3:
  294. gdp_debugfs_files = gdp3_debugfs_files;
  295. nb_files = ARRAY_SIZE(gdp3_debugfs_files);
  296. break;
  297. default:
  298. return -EINVAL;
  299. }
  300. for (i = 0; i < nb_files; i++)
  301. gdp_debugfs_files[i].data = gdp;
  302. drm_debugfs_create_files(gdp_debugfs_files,
  303. nb_files,
  304. minor->debugfs_root, minor);
  305. return 0;
  306. }
  307. static int sti_gdp_fourcc2format(int fourcc)
  308. {
  309. switch (fourcc) {
  310. case DRM_FORMAT_XRGB8888:
  311. return GDP_RGB888_32;
  312. case DRM_FORMAT_XBGR8888:
  313. return GDP_XBGR8888;
  314. case DRM_FORMAT_ARGB8888:
  315. return GDP_ARGB8888;
  316. case DRM_FORMAT_ABGR8888:
  317. return GDP_ABGR8888;
  318. case DRM_FORMAT_ARGB4444:
  319. return GDP_ARGB4444;
  320. case DRM_FORMAT_ARGB1555:
  321. return GDP_ARGB1555;
  322. case DRM_FORMAT_RGB565:
  323. return GDP_RGB565;
  324. case DRM_FORMAT_RGB888:
  325. return GDP_RGB888;
  326. }
  327. return -1;
  328. }
  329. static int sti_gdp_get_alpharange(int format)
  330. {
  331. switch (format) {
  332. case GDP_ARGB8565:
  333. case GDP_ARGB8888:
  334. case GDP_ABGR8888:
  335. return GAM_GDP_ALPHARANGE_255;
  336. }
  337. return 0;
  338. }
  339. /**
  340. * sti_gdp_get_free_nodes
  341. * @gdp: gdp pointer
  342. *
  343. * Look for a GDP node list that is not currently read by the HW.
  344. *
  345. * RETURNS:
  346. * Pointer to the free GDP node list
  347. */
  348. static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
  349. {
  350. int hw_nvn;
  351. unsigned int i;
  352. hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
  353. if (!hw_nvn)
  354. goto end;
  355. for (i = 0; i < GDP_NODE_NB_BANK; i++)
  356. if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
  357. (hw_nvn != gdp->node_list[i].top_field_paddr))
  358. return &gdp->node_list[i];
  359. /* in hazardous cases restart with the first node */
  360. DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
  361. sti_plane_to_str(&gdp->plane), hw_nvn);
  362. end:
  363. return &gdp->node_list[0];
  364. }
  365. /**
  366. * sti_gdp_get_current_nodes
  367. * @gdp: gdp pointer
  368. *
  369. * Look for GDP nodes that are currently read by the HW.
  370. *
  371. * RETURNS:
  372. * Pointer to the current GDP node list
  373. */
  374. static
  375. struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
  376. {
  377. int hw_nvn;
  378. unsigned int i;
  379. hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
  380. if (!hw_nvn)
  381. goto end;
  382. for (i = 0; i < GDP_NODE_NB_BANK; i++)
  383. if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
  384. (hw_nvn == gdp->node_list[i].top_field_paddr))
  385. return &gdp->node_list[i];
  386. end:
  387. DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
  388. hw_nvn, sti_plane_to_str(&gdp->plane));
  389. return NULL;
  390. }
  391. /**
  392. * sti_gdp_disable
  393. * @gdp: gdp pointer
  394. *
  395. * Disable a GDP.
  396. */
  397. static void sti_gdp_disable(struct sti_gdp *gdp)
  398. {
  399. unsigned int i;
  400. DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
  401. /* Set the nodes as 'to be ignored on mixer' */
  402. for (i = 0; i < GDP_NODE_NB_BANK; i++) {
  403. gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
  404. gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
  405. }
  406. if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
  407. DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
  408. if (gdp->clk_pix)
  409. clk_disable_unprepare(gdp->clk_pix);
  410. gdp->plane.status = STI_PLANE_DISABLED;
  411. gdp->vtg = NULL;
  412. }
  413. /**
  414. * sti_gdp_field_cb
  415. * @nb: notifier block
  416. * @event: event message
  417. * @data: private data
  418. *
  419. * Handle VTG top field and bottom field event.
  420. *
  421. * RETURNS:
  422. * 0 on success.
  423. */
  424. static int sti_gdp_field_cb(struct notifier_block *nb,
  425. unsigned long event, void *data)
  426. {
  427. struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
  428. if (gdp->plane.status == STI_PLANE_FLUSHING) {
  429. /* disable need to be synchronize on vsync event */
  430. DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
  431. sti_plane_to_str(&gdp->plane));
  432. sti_gdp_disable(gdp);
  433. }
  434. switch (event) {
  435. case VTG_TOP_FIELD_EVENT:
  436. gdp->is_curr_top = true;
  437. break;
  438. case VTG_BOTTOM_FIELD_EVENT:
  439. gdp->is_curr_top = false;
  440. break;
  441. default:
  442. DRM_ERROR("unsupported event: %lu\n", event);
  443. break;
  444. }
  445. return 0;
  446. }
  447. static void sti_gdp_init(struct sti_gdp *gdp)
  448. {
  449. struct device_node *np = gdp->dev->of_node;
  450. dma_addr_t dma_addr;
  451. void *base;
  452. unsigned int i, size;
  453. /* Allocate all the nodes within a single memory page */
  454. size = sizeof(struct sti_gdp_node) *
  455. GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
  456. base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL);
  457. if (!base) {
  458. DRM_ERROR("Failed to allocate memory for GDP node\n");
  459. return;
  460. }
  461. memset(base, 0, size);
  462. for (i = 0; i < GDP_NODE_NB_BANK; i++) {
  463. if (dma_addr & 0xF) {
  464. DRM_ERROR("Mem alignment failed\n");
  465. return;
  466. }
  467. gdp->node_list[i].top_field = base;
  468. gdp->node_list[i].top_field_paddr = dma_addr;
  469. DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
  470. base += sizeof(struct sti_gdp_node);
  471. dma_addr += sizeof(struct sti_gdp_node);
  472. if (dma_addr & 0xF) {
  473. DRM_ERROR("Mem alignment failed\n");
  474. return;
  475. }
  476. gdp->node_list[i].btm_field = base;
  477. gdp->node_list[i].btm_field_paddr = dma_addr;
  478. DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
  479. base += sizeof(struct sti_gdp_node);
  480. dma_addr += sizeof(struct sti_gdp_node);
  481. }
  482. if (of_device_is_compatible(np, "st,stih407-compositor")) {
  483. /* GDP of STiH407 chip have its own pixel clock */
  484. char *clk_name;
  485. switch (gdp->plane.desc) {
  486. case STI_GDP_0:
  487. clk_name = "pix_gdp1";
  488. break;
  489. case STI_GDP_1:
  490. clk_name = "pix_gdp2";
  491. break;
  492. case STI_GDP_2:
  493. clk_name = "pix_gdp3";
  494. break;
  495. case STI_GDP_3:
  496. clk_name = "pix_gdp4";
  497. break;
  498. default:
  499. DRM_ERROR("GDP id not recognized\n");
  500. return;
  501. }
  502. gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
  503. if (IS_ERR(gdp->clk_pix))
  504. DRM_ERROR("Cannot get %s clock\n", clk_name);
  505. gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
  506. if (IS_ERR(gdp->clk_main_parent))
  507. DRM_ERROR("Cannot get main_parent clock\n");
  508. gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
  509. if (IS_ERR(gdp->clk_aux_parent))
  510. DRM_ERROR("Cannot get aux_parent clock\n");
  511. }
  512. }
  513. /**
  514. * sti_gdp_get_dst
  515. * @dev: device
  516. * @dst: requested destination size
  517. * @src: source size
  518. *
  519. * Return the cropped / clamped destination size
  520. *
  521. * RETURNS:
  522. * cropped / clamped destination size
  523. */
  524. static int sti_gdp_get_dst(struct device *dev, int dst, int src)
  525. {
  526. if (dst == src)
  527. return dst;
  528. if (dst < src) {
  529. dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
  530. return dst;
  531. }
  532. dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
  533. return src;
  534. }
  535. static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
  536. struct drm_atomic_state *state)
  537. {
  538. struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
  539. drm_plane);
  540. struct sti_plane *plane = to_sti_plane(drm_plane);
  541. struct sti_gdp *gdp = to_sti_gdp(plane);
  542. struct drm_crtc *crtc = new_plane_state->crtc;
  543. struct drm_framebuffer *fb = new_plane_state->fb;
  544. struct drm_crtc_state *crtc_state;
  545. struct sti_mixer *mixer;
  546. struct drm_display_mode *mode;
  547. int dst_x, dst_y, dst_w, dst_h;
  548. int src_x, src_y, src_w, src_h;
  549. int format;
  550. /* no need for further checks if the plane is being disabled */
  551. if (!crtc || !fb)
  552. return 0;
  553. mixer = to_sti_mixer(crtc);
  554. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  555. mode = &crtc_state->mode;
  556. dst_x = new_plane_state->crtc_x;
  557. dst_y = new_plane_state->crtc_y;
  558. dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x);
  559. dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y);
  560. /* src_x are in 16.16 format */
  561. src_x = new_plane_state->src_x >> 16;
  562. src_y = new_plane_state->src_y >> 16;
  563. src_w = clamp_val(new_plane_state->src_w >> 16, 0,
  564. GAM_GDP_SIZE_MAX_WIDTH);
  565. src_h = clamp_val(new_plane_state->src_h >> 16, 0,
  566. GAM_GDP_SIZE_MAX_HEIGHT);
  567. format = sti_gdp_fourcc2format(fb->format->format);
  568. if (format == -1) {
  569. DRM_ERROR("Format not supported by GDP %.4s\n",
  570. (char *)&fb->format->format);
  571. return -EINVAL;
  572. }
  573. if (!drm_fb_dma_get_gem_obj(fb, 0)) {
  574. DRM_ERROR("Can't get DMA GEM object for fb\n");
  575. return -EINVAL;
  576. }
  577. /* Set gdp clock */
  578. if (mode->clock && gdp->clk_pix) {
  579. struct clk *clkp;
  580. int rate = mode->clock * 1000;
  581. int res;
  582. /*
  583. * According to the mixer used, the gdp pixel clock
  584. * should have a different parent clock.
  585. */
  586. if (mixer->id == STI_MIXER_MAIN)
  587. clkp = gdp->clk_main_parent;
  588. else
  589. clkp = gdp->clk_aux_parent;
  590. if (clkp)
  591. clk_set_parent(gdp->clk_pix, clkp);
  592. res = clk_set_rate(gdp->clk_pix, rate);
  593. if (res < 0) {
  594. DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
  595. rate);
  596. return -EINVAL;
  597. }
  598. }
  599. DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
  600. crtc->base.id, sti_mixer_to_str(mixer),
  601. drm_plane->base.id, sti_plane_to_str(plane));
  602. DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
  603. sti_plane_to_str(plane),
  604. dst_w, dst_h, dst_x, dst_y,
  605. src_w, src_h, src_x, src_y);
  606. return 0;
  607. }
  608. static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
  609. struct drm_atomic_state *state)
  610. {
  611. struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
  612. drm_plane);
  613. struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
  614. drm_plane);
  615. struct sti_plane *plane = to_sti_plane(drm_plane);
  616. struct sti_gdp *gdp = to_sti_gdp(plane);
  617. struct drm_crtc *crtc = newstate->crtc;
  618. struct drm_framebuffer *fb = newstate->fb;
  619. struct drm_display_mode *mode;
  620. int dst_x, dst_y, dst_w, dst_h;
  621. int src_x, src_y, src_w, src_h;
  622. struct drm_gem_dma_object *dma_obj;
  623. struct sti_gdp_node_list *list;
  624. struct sti_gdp_node_list *curr_list;
  625. struct sti_gdp_node *top_field, *btm_field;
  626. u32 dma_updated_top;
  627. u32 dma_updated_btm;
  628. int format;
  629. unsigned int bpp;
  630. u32 ydo, xdo, yds, xds;
  631. if (!crtc || !fb)
  632. return;
  633. if ((oldstate->fb == newstate->fb) &&
  634. (oldstate->crtc_x == newstate->crtc_x) &&
  635. (oldstate->crtc_y == newstate->crtc_y) &&
  636. (oldstate->crtc_w == newstate->crtc_w) &&
  637. (oldstate->crtc_h == newstate->crtc_h) &&
  638. (oldstate->src_x == newstate->src_x) &&
  639. (oldstate->src_y == newstate->src_y) &&
  640. (oldstate->src_w == newstate->src_w) &&
  641. (oldstate->src_h == newstate->src_h)) {
  642. /* No change since last update, do not post cmd */
  643. DRM_DEBUG_DRIVER("No change, not posting cmd\n");
  644. plane->status = STI_PLANE_UPDATED;
  645. return;
  646. }
  647. if (!gdp->vtg) {
  648. struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
  649. struct sti_mixer *mixer = to_sti_mixer(crtc);
  650. /* Register gdp callback */
  651. gdp->vtg = compo->vtg[mixer->id];
  652. sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc);
  653. clk_prepare_enable(gdp->clk_pix);
  654. }
  655. mode = &crtc->mode;
  656. dst_x = newstate->crtc_x;
  657. dst_y = newstate->crtc_y;
  658. dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x);
  659. dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y);
  660. /* src_x are in 16.16 format */
  661. src_x = newstate->src_x >> 16;
  662. src_y = newstate->src_y >> 16;
  663. src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
  664. src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
  665. list = sti_gdp_get_free_nodes(gdp);
  666. top_field = list->top_field;
  667. btm_field = list->btm_field;
  668. dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
  669. sti_plane_to_str(plane), top_field, btm_field);
  670. /* build the top field */
  671. top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
  672. top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
  673. format = sti_gdp_fourcc2format(fb->format->format);
  674. top_field->gam_gdp_ctl |= format;
  675. top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
  676. top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
  677. dma_obj = drm_fb_dma_get_gem_obj(fb, 0);
  678. DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
  679. (char *)&fb->format->format,
  680. (unsigned long) dma_obj->dma_addr);
  681. /* pixel memory location */
  682. bpp = fb->format->cpp[0];
  683. top_field->gam_gdp_pml = (u32) dma_obj->dma_addr + fb->offsets[0];
  684. top_field->gam_gdp_pml += src_x * bpp;
  685. top_field->gam_gdp_pml += src_y * fb->pitches[0];
  686. /* output parameters (clamped / cropped) */
  687. dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
  688. dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
  689. ydo = sti_vtg_get_line_number(*mode, dst_y);
  690. yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
  691. xdo = sti_vtg_get_pixel_number(*mode, dst_x);
  692. xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
  693. top_field->gam_gdp_vpo = (ydo << 16) | xdo;
  694. top_field->gam_gdp_vps = (yds << 16) | xds;
  695. /* input parameters */
  696. src_w = dst_w;
  697. top_field->gam_gdp_pmp = fb->pitches[0];
  698. top_field->gam_gdp_size = src_h << 16 | src_w;
  699. /* Same content and chained together */
  700. memcpy(btm_field, top_field, sizeof(*btm_field));
  701. top_field->gam_gdp_nvn = list->btm_field_paddr;
  702. btm_field->gam_gdp_nvn = list->top_field_paddr;
  703. /* Interlaced mode */
  704. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  705. btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
  706. fb->pitches[0];
  707. /* Update the NVN field of the 'right' field of the current GDP node
  708. * (being used by the HW) with the address of the updated ('free') top
  709. * field GDP node.
  710. * - In interlaced mode the 'right' field is the bottom field as we
  711. * update frames starting from their top field
  712. * - In progressive mode, we update both bottom and top fields which
  713. * are equal nodes.
  714. * At the next VSYNC, the updated node list will be used by the HW.
  715. */
  716. curr_list = sti_gdp_get_current_nodes(gdp);
  717. dma_updated_top = list->top_field_paddr;
  718. dma_updated_btm = list->btm_field_paddr;
  719. dev_dbg(gdp->dev, "Current NVN:0x%X\n",
  720. readl(gdp->regs + GAM_GDP_NVN_OFFSET));
  721. dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
  722. (unsigned long) dma_obj->dma_addr,
  723. readl(gdp->regs + GAM_GDP_PML_OFFSET));
  724. if (!curr_list) {
  725. /* First update or invalid node should directly write in the
  726. * hw register */
  727. DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
  728. sti_plane_to_str(plane));
  729. writel(gdp->is_curr_top ?
  730. dma_updated_btm : dma_updated_top,
  731. gdp->regs + GAM_GDP_NVN_OFFSET);
  732. goto end;
  733. }
  734. if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  735. if (gdp->is_curr_top) {
  736. /* Do not update in the middle of the frame, but
  737. * postpone the update after the bottom field has
  738. * been displayed */
  739. curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
  740. } else {
  741. /* Direct update to avoid one frame delay */
  742. writel(dma_updated_top,
  743. gdp->regs + GAM_GDP_NVN_OFFSET);
  744. }
  745. } else {
  746. /* Direct update for progressive to avoid one frame delay */
  747. writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
  748. }
  749. end:
  750. sti_plane_update_fps(plane, true, false);
  751. plane->status = STI_PLANE_UPDATED;
  752. }
  753. static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
  754. struct drm_atomic_state *state)
  755. {
  756. struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
  757. drm_plane);
  758. struct sti_plane *plane = to_sti_plane(drm_plane);
  759. if (!oldstate->crtc) {
  760. DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
  761. drm_plane->base.id);
  762. return;
  763. }
  764. DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
  765. oldstate->crtc->base.id,
  766. sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
  767. drm_plane->base.id, sti_plane_to_str(plane));
  768. plane->status = STI_PLANE_DISABLING;
  769. }
  770. static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
  771. .atomic_check = sti_gdp_atomic_check,
  772. .atomic_update = sti_gdp_atomic_update,
  773. .atomic_disable = sti_gdp_atomic_disable,
  774. };
  775. static int sti_gdp_late_register(struct drm_plane *drm_plane)
  776. {
  777. struct sti_plane *plane = to_sti_plane(drm_plane);
  778. struct sti_gdp *gdp = to_sti_gdp(plane);
  779. return gdp_debugfs_init(gdp, drm_plane->dev->primary);
  780. }
  781. static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
  782. .update_plane = drm_atomic_helper_update_plane,
  783. .disable_plane = drm_atomic_helper_disable_plane,
  784. .destroy = drm_plane_cleanup,
  785. .reset = drm_atomic_helper_plane_reset,
  786. .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
  787. .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
  788. .late_register = sti_gdp_late_register,
  789. };
  790. struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
  791. struct device *dev, int desc,
  792. void __iomem *baseaddr,
  793. unsigned int possible_crtcs,
  794. enum drm_plane_type type)
  795. {
  796. struct sti_gdp *gdp;
  797. int res;
  798. gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
  799. if (!gdp) {
  800. DRM_ERROR("Failed to allocate memory for GDP\n");
  801. return NULL;
  802. }
  803. gdp->dev = dev;
  804. gdp->regs = baseaddr;
  805. gdp->plane.desc = desc;
  806. gdp->plane.status = STI_PLANE_DISABLED;
  807. gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
  808. sti_gdp_init(gdp);
  809. res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
  810. possible_crtcs,
  811. &sti_gdp_plane_helpers_funcs,
  812. gdp_supported_formats,
  813. ARRAY_SIZE(gdp_supported_formats),
  814. NULL, type, NULL);
  815. if (res) {
  816. DRM_ERROR("Failed to initialize universal plane\n");
  817. goto err;
  818. }
  819. drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
  820. sti_plane_init_property(&gdp->plane, type);
  821. return &gdp->plane.drm_plane;
  822. err:
  823. devm_kfree(dev, gdp);
  824. return NULL;
  825. }