r300.c 42 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/pci.h>
  29. #include <linux/seq_file.h>
  30. #include <linux/slab.h>
  31. #include <drm/drm.h>
  32. #include <drm/drm_crtc_helper.h>
  33. #include <drm/drm_device.h>
  34. #include <drm/drm_file.h>
  35. #include <drm/radeon_drm.h>
  36. #include "r100_track.h"
  37. #include "r300_reg_safe.h"
  38. #include "r300d.h"
  39. #include "radeon.h"
  40. #include "radeon_asic.h"
  41. #include "radeon_reg.h"
  42. #include "rv350d.h"
  43. /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
  44. *
  45. * GPU Errata:
  46. * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
  47. * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
  48. * However, scheduling such write to the ring seems harmless, i suspect
  49. * the CP read collide with the flush somehow, or maybe the MC, hard to
  50. * tell. (Jerome Glisse)
  51. */
  52. /*
  53. * Indirect registers accessor
  54. */
  55. uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
  56. {
  57. unsigned long flags;
  58. uint32_t r;
  59. spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
  60. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  61. r = RREG32(RADEON_PCIE_DATA);
  62. spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
  63. return r;
  64. }
  65. void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  66. {
  67. unsigned long flags;
  68. spin_lock_irqsave(&rdev->pcie_idx_lock, flags);
  69. WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
  70. WREG32(RADEON_PCIE_DATA, (v));
  71. spin_unlock_irqrestore(&rdev->pcie_idx_lock, flags);
  72. }
  73. /*
  74. * rv370,rv380 PCIE GART
  75. */
  76. static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
  77. void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
  78. {
  79. uint32_t tmp;
  80. int i;
  81. /* Workaround HW bug do flush 2 times */
  82. for (i = 0; i < 2; i++) {
  83. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  84. WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
  85. (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  86. WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  87. }
  88. mb();
  89. }
  90. #define R300_PTE_UNSNOOPED (1 << 0)
  91. #define R300_PTE_WRITEABLE (1 << 2)
  92. #define R300_PTE_READABLE (1 << 3)
  93. uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags)
  94. {
  95. addr = (lower_32_bits(addr) >> 8) |
  96. ((upper_32_bits(addr) & 0xff) << 24);
  97. if (flags & RADEON_GART_PAGE_READ)
  98. addr |= R300_PTE_READABLE;
  99. if (flags & RADEON_GART_PAGE_WRITE)
  100. addr |= R300_PTE_WRITEABLE;
  101. if (!(flags & RADEON_GART_PAGE_SNOOP))
  102. addr |= R300_PTE_UNSNOOPED;
  103. return addr;
  104. }
  105. void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
  106. uint64_t entry)
  107. {
  108. void __iomem *ptr = rdev->gart.ptr;
  109. /* on x86 we want this to be CPU endian, on powerpc
  110. * on powerpc without HW swappers, it'll get swapped on way
  111. * into VRAM - so no need for cpu_to_le32 on VRAM tables */
  112. writel(entry, ((void __iomem *)ptr) + (i * 4));
  113. }
  114. int rv370_pcie_gart_init(struct radeon_device *rdev)
  115. {
  116. int r;
  117. if (rdev->gart.robj) {
  118. WARN(1, "RV370 PCIE GART already initialized\n");
  119. return 0;
  120. }
  121. /* Initialize common gart structure */
  122. r = radeon_gart_init(rdev);
  123. if (r)
  124. return r;
  125. rv370_debugfs_pcie_gart_info_init(rdev);
  126. rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  127. rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
  128. rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
  129. rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
  130. return radeon_gart_table_vram_alloc(rdev);
  131. }
  132. int rv370_pcie_gart_enable(struct radeon_device *rdev)
  133. {
  134. uint32_t table_addr;
  135. uint32_t tmp;
  136. int r;
  137. if (rdev->gart.robj == NULL) {
  138. dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  139. return -EINVAL;
  140. }
  141. r = radeon_gart_table_vram_pin(rdev);
  142. if (r)
  143. return r;
  144. /* discard memory request outside of configured range */
  145. tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
  146. WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  147. WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
  148. tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
  149. WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
  150. WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
  151. WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
  152. table_addr = rdev->gart.table_addr;
  153. WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
  154. /* FIXME: setup default page */
  155. WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
  156. WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
  157. /* Clear error */
  158. WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
  159. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  160. tmp |= RADEON_PCIE_TX_GART_EN;
  161. tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
  162. WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
  163. rv370_pcie_gart_tlb_flush(rdev);
  164. DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
  165. (unsigned)(rdev->mc.gtt_size >> 20),
  166. (unsigned long long)table_addr);
  167. rdev->gart.ready = true;
  168. return 0;
  169. }
  170. void rv370_pcie_gart_disable(struct radeon_device *rdev)
  171. {
  172. u32 tmp;
  173. WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0);
  174. WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0);
  175. WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
  176. WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
  177. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  178. tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
  179. WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
  180. radeon_gart_table_vram_unpin(rdev);
  181. }
  182. void rv370_pcie_gart_fini(struct radeon_device *rdev)
  183. {
  184. radeon_gart_fini(rdev);
  185. rv370_pcie_gart_disable(rdev);
  186. radeon_gart_table_vram_free(rdev);
  187. }
  188. void r300_fence_ring_emit(struct radeon_device *rdev,
  189. struct radeon_fence *fence)
  190. {
  191. struct radeon_ring *ring = &rdev->ring[fence->ring];
  192. /* Who ever call radeon_fence_emit should call ring_lock and ask
  193. * for enough space (today caller are ib schedule and buffer move) */
  194. /* Write SC register so SC & US assert idle */
  195. radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
  196. radeon_ring_write(ring, 0);
  197. radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
  198. radeon_ring_write(ring, 0);
  199. /* Flush 3D cache */
  200. radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  201. radeon_ring_write(ring, R300_RB3D_DC_FLUSH);
  202. radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  203. radeon_ring_write(ring, R300_ZC_FLUSH);
  204. /* Wait until IDLE & CLEAN */
  205. radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
  206. radeon_ring_write(ring, (RADEON_WAIT_3D_IDLECLEAN |
  207. RADEON_WAIT_2D_IDLECLEAN |
  208. RADEON_WAIT_DMA_GUI_IDLE));
  209. radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
  210. radeon_ring_write(ring, rdev->config.r300.hdp_cntl |
  211. RADEON_HDP_READ_BUFFER_INVALIDATE);
  212. radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
  213. radeon_ring_write(ring, rdev->config.r300.hdp_cntl);
  214. /* Emit fence sequence & fire IRQ */
  215. radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
  216. radeon_ring_write(ring, fence->seq);
  217. radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
  218. radeon_ring_write(ring, RADEON_SW_INT_FIRE);
  219. }
  220. void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
  221. {
  222. unsigned gb_tile_config;
  223. int r;
  224. /* Sub pixel 1/12 so we can have 4K rendering according to doc */
  225. gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
  226. switch(rdev->num_gb_pipes) {
  227. case 2:
  228. gb_tile_config |= R300_PIPE_COUNT_R300;
  229. break;
  230. case 3:
  231. gb_tile_config |= R300_PIPE_COUNT_R420_3P;
  232. break;
  233. case 4:
  234. gb_tile_config |= R300_PIPE_COUNT_R420;
  235. break;
  236. case 1:
  237. default:
  238. gb_tile_config |= R300_PIPE_COUNT_RV350;
  239. break;
  240. }
  241. r = radeon_ring_lock(rdev, ring, 64);
  242. if (r) {
  243. return;
  244. }
  245. radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
  246. radeon_ring_write(ring,
  247. RADEON_ISYNC_ANY2D_IDLE3D |
  248. RADEON_ISYNC_ANY3D_IDLE2D |
  249. RADEON_ISYNC_WAIT_IDLEGUI |
  250. RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  251. radeon_ring_write(ring, PACKET0(R300_GB_TILE_CONFIG, 0));
  252. radeon_ring_write(ring, gb_tile_config);
  253. radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
  254. radeon_ring_write(ring,
  255. RADEON_WAIT_2D_IDLECLEAN |
  256. RADEON_WAIT_3D_IDLECLEAN);
  257. radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
  258. radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
  259. radeon_ring_write(ring, PACKET0(R300_GB_SELECT, 0));
  260. radeon_ring_write(ring, 0);
  261. radeon_ring_write(ring, PACKET0(R300_GB_ENABLE, 0));
  262. radeon_ring_write(ring, 0);
  263. radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  264. radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
  265. radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  266. radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
  267. radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
  268. radeon_ring_write(ring,
  269. RADEON_WAIT_2D_IDLECLEAN |
  270. RADEON_WAIT_3D_IDLECLEAN);
  271. radeon_ring_write(ring, PACKET0(R300_GB_AA_CONFIG, 0));
  272. radeon_ring_write(ring, 0);
  273. radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
  274. radeon_ring_write(ring, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
  275. radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
  276. radeon_ring_write(ring, R300_ZC_FLUSH | R300_ZC_FREE);
  277. radeon_ring_write(ring, PACKET0(R300_GB_MSPOS0, 0));
  278. radeon_ring_write(ring,
  279. ((6 << R300_MS_X0_SHIFT) |
  280. (6 << R300_MS_Y0_SHIFT) |
  281. (6 << R300_MS_X1_SHIFT) |
  282. (6 << R300_MS_Y1_SHIFT) |
  283. (6 << R300_MS_X2_SHIFT) |
  284. (6 << R300_MS_Y2_SHIFT) |
  285. (6 << R300_MSBD0_Y_SHIFT) |
  286. (6 << R300_MSBD0_X_SHIFT)));
  287. radeon_ring_write(ring, PACKET0(R300_GB_MSPOS1, 0));
  288. radeon_ring_write(ring,
  289. ((6 << R300_MS_X3_SHIFT) |
  290. (6 << R300_MS_Y3_SHIFT) |
  291. (6 << R300_MS_X4_SHIFT) |
  292. (6 << R300_MS_Y4_SHIFT) |
  293. (6 << R300_MS_X5_SHIFT) |
  294. (6 << R300_MS_Y5_SHIFT) |
  295. (6 << R300_MSBD1_SHIFT)));
  296. radeon_ring_write(ring, PACKET0(R300_GA_ENHANCE, 0));
  297. radeon_ring_write(ring, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
  298. radeon_ring_write(ring, PACKET0(R300_GA_POLY_MODE, 0));
  299. radeon_ring_write(ring,
  300. R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
  301. radeon_ring_write(ring, PACKET0(R300_GA_ROUND_MODE, 0));
  302. radeon_ring_write(ring,
  303. R300_GEOMETRY_ROUND_NEAREST |
  304. R300_COLOR_ROUND_NEAREST);
  305. radeon_ring_unlock_commit(rdev, ring, false);
  306. }
  307. static void r300_errata(struct radeon_device *rdev)
  308. {
  309. rdev->pll_errata = 0;
  310. if (rdev->family == CHIP_R300 &&
  311. (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
  312. rdev->pll_errata |= CHIP_ERRATA_R300_CG;
  313. }
  314. }
  315. int r300_mc_wait_for_idle(struct radeon_device *rdev)
  316. {
  317. unsigned i;
  318. uint32_t tmp;
  319. for (i = 0; i < rdev->usec_timeout; i++) {
  320. /* read MC_STATUS */
  321. tmp = RREG32(RADEON_MC_STATUS);
  322. if (tmp & R300_MC_IDLE) {
  323. return 0;
  324. }
  325. udelay(1);
  326. }
  327. return -1;
  328. }
  329. static void r300_gpu_init(struct radeon_device *rdev)
  330. {
  331. uint32_t gb_tile_config, tmp;
  332. if ((rdev->family == CHIP_R300 && rdev->pdev->device != 0x4144) ||
  333. (rdev->family == CHIP_R350 && rdev->pdev->device != 0x4148)) {
  334. /* r300,r350 */
  335. rdev->num_gb_pipes = 2;
  336. } else {
  337. /* rv350,rv370,rv380,r300 AD, r350 AH */
  338. rdev->num_gb_pipes = 1;
  339. }
  340. rdev->num_z_pipes = 1;
  341. gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
  342. switch (rdev->num_gb_pipes) {
  343. case 2:
  344. gb_tile_config |= R300_PIPE_COUNT_R300;
  345. break;
  346. case 3:
  347. gb_tile_config |= R300_PIPE_COUNT_R420_3P;
  348. break;
  349. case 4:
  350. gb_tile_config |= R300_PIPE_COUNT_R420;
  351. break;
  352. default:
  353. case 1:
  354. gb_tile_config |= R300_PIPE_COUNT_RV350;
  355. break;
  356. }
  357. WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
  358. if (r100_gui_wait_for_idle(rdev)) {
  359. pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
  360. }
  361. tmp = RREG32(R300_DST_PIPE_CONFIG);
  362. WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
  363. WREG32(R300_RB2D_DSTCACHE_MODE,
  364. R300_DC_AUTOFLUSH_ENABLE |
  365. R300_DC_DC_DISABLE_IGNORE_PE);
  366. if (r100_gui_wait_for_idle(rdev)) {
  367. pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
  368. }
  369. if (r300_mc_wait_for_idle(rdev)) {
  370. pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
  371. }
  372. DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized\n",
  373. rdev->num_gb_pipes, rdev->num_z_pipes);
  374. }
  375. int r300_asic_reset(struct radeon_device *rdev, bool hard)
  376. {
  377. struct r100_mc_save save;
  378. u32 status, tmp;
  379. int ret = 0;
  380. status = RREG32(R_000E40_RBBM_STATUS);
  381. if (!G_000E40_GUI_ACTIVE(status)) {
  382. return 0;
  383. }
  384. r100_mc_stop(rdev, &save);
  385. status = RREG32(R_000E40_RBBM_STATUS);
  386. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  387. /* stop CP */
  388. WREG32(RADEON_CP_CSQ_CNTL, 0);
  389. tmp = RREG32(RADEON_CP_RB_CNTL);
  390. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
  391. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  392. WREG32(RADEON_CP_RB_WPTR, 0);
  393. WREG32(RADEON_CP_RB_CNTL, tmp);
  394. /* save PCI state */
  395. pci_save_state(rdev->pdev);
  396. /* disable bus mastering */
  397. r100_bm_disable(rdev);
  398. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
  399. S_0000F0_SOFT_RESET_GA(1));
  400. RREG32(R_0000F0_RBBM_SOFT_RESET);
  401. mdelay(500);
  402. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  403. mdelay(1);
  404. status = RREG32(R_000E40_RBBM_STATUS);
  405. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  406. /* resetting the CP seems to be problematic sometimes it end up
  407. * hard locking the computer, but it's necessary for successful
  408. * reset more test & playing is needed on R3XX/R4XX to find a
  409. * reliable (if any solution)
  410. */
  411. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
  412. RREG32(R_0000F0_RBBM_SOFT_RESET);
  413. mdelay(500);
  414. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  415. mdelay(1);
  416. status = RREG32(R_000E40_RBBM_STATUS);
  417. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  418. /* restore PCI & busmastering */
  419. pci_restore_state(rdev->pdev);
  420. r100_enable_bm(rdev);
  421. /* Check if GPU is idle */
  422. if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
  423. dev_err(rdev->dev, "failed to reset GPU\n");
  424. ret = -1;
  425. } else
  426. dev_info(rdev->dev, "GPU reset succeed\n");
  427. r100_mc_resume(rdev, &save);
  428. return ret;
  429. }
  430. /*
  431. * r300,r350,rv350,rv380 VRAM info
  432. */
  433. void r300_mc_init(struct radeon_device *rdev)
  434. {
  435. u64 base;
  436. u32 tmp;
  437. /* DDR for all card after R300 & IGP */
  438. rdev->mc.vram_is_ddr = true;
  439. tmp = RREG32(RADEON_MEM_CNTL);
  440. tmp &= R300_MEM_NUM_CHANNELS_MASK;
  441. switch (tmp) {
  442. case 0: rdev->mc.vram_width = 64; break;
  443. case 1: rdev->mc.vram_width = 128; break;
  444. case 2: rdev->mc.vram_width = 256; break;
  445. default: rdev->mc.vram_width = 128; break;
  446. }
  447. r100_vram_init_sizes(rdev);
  448. base = rdev->mc.aper_base;
  449. if (rdev->flags & RADEON_IS_IGP)
  450. base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
  451. radeon_vram_location(rdev, &rdev->mc, base);
  452. rdev->mc.gtt_base_align = 0;
  453. if (!(rdev->flags & RADEON_IS_AGP))
  454. radeon_gtt_location(rdev, &rdev->mc);
  455. radeon_update_bandwidth_info(rdev);
  456. }
  457. void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
  458. {
  459. uint32_t link_width_cntl, mask;
  460. if (rdev->flags & RADEON_IS_IGP)
  461. return;
  462. if (!(rdev->flags & RADEON_IS_PCIE))
  463. return;
  464. /* FIXME wait for idle */
  465. switch (lanes) {
  466. case 0:
  467. mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
  468. break;
  469. case 1:
  470. mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
  471. break;
  472. case 2:
  473. mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
  474. break;
  475. case 4:
  476. mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
  477. break;
  478. case 8:
  479. mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
  480. break;
  481. case 12:
  482. mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
  483. break;
  484. case 16:
  485. default:
  486. mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
  487. break;
  488. }
  489. link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
  490. if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
  491. (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
  492. return;
  493. link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
  494. RADEON_PCIE_LC_RECONFIG_NOW |
  495. RADEON_PCIE_LC_RECONFIG_LATER |
  496. RADEON_PCIE_LC_SHORT_RECONFIG_EN);
  497. link_width_cntl |= mask;
  498. WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
  499. WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
  500. RADEON_PCIE_LC_RECONFIG_NOW));
  501. /* wait for lane set to complete */
  502. link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
  503. while (link_width_cntl == 0xffffffff)
  504. link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
  505. }
  506. int rv370_get_pcie_lanes(struct radeon_device *rdev)
  507. {
  508. u32 link_width_cntl;
  509. if (rdev->flags & RADEON_IS_IGP)
  510. return 0;
  511. if (!(rdev->flags & RADEON_IS_PCIE))
  512. return 0;
  513. /* FIXME wait for idle */
  514. link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
  515. switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
  516. case RADEON_PCIE_LC_LINK_WIDTH_X0:
  517. return 0;
  518. case RADEON_PCIE_LC_LINK_WIDTH_X1:
  519. return 1;
  520. case RADEON_PCIE_LC_LINK_WIDTH_X2:
  521. return 2;
  522. case RADEON_PCIE_LC_LINK_WIDTH_X4:
  523. return 4;
  524. case RADEON_PCIE_LC_LINK_WIDTH_X8:
  525. return 8;
  526. case RADEON_PCIE_LC_LINK_WIDTH_X16:
  527. default:
  528. return 16;
  529. }
  530. }
  531. #if defined(CONFIG_DEBUG_FS)
  532. static int rv370_debugfs_pcie_gart_info_show(struct seq_file *m, void *unused)
  533. {
  534. struct radeon_device *rdev = (struct radeon_device *)m->private;
  535. uint32_t tmp;
  536. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
  537. seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
  538. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
  539. seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
  540. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
  541. seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
  542. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
  543. seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
  544. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
  545. seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
  546. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
  547. seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
  548. tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
  549. seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
  550. return 0;
  551. }
  552. DEFINE_SHOW_ATTRIBUTE(rv370_debugfs_pcie_gart_info);
  553. #endif
  554. static void rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
  555. {
  556. #if defined(CONFIG_DEBUG_FS)
  557. struct dentry *root = rdev->ddev->primary->debugfs_root;
  558. debugfs_create_file("rv370_pcie_gart_info", 0444, root, rdev,
  559. &rv370_debugfs_pcie_gart_info_fops);
  560. #endif
  561. }
  562. static int r300_packet0_check(struct radeon_cs_parser *p,
  563. struct radeon_cs_packet *pkt,
  564. unsigned idx, unsigned reg)
  565. {
  566. struct radeon_bo_list *reloc;
  567. struct r100_cs_track *track;
  568. volatile uint32_t *ib;
  569. uint32_t tmp, tile_flags = 0;
  570. unsigned i;
  571. int r;
  572. u32 idx_value;
  573. ib = p->ib.ptr;
  574. track = (struct r100_cs_track *)p->track;
  575. idx_value = radeon_get_ib_value(p, idx);
  576. switch(reg) {
  577. case AVIVO_D1MODE_VLINE_START_END:
  578. case RADEON_CRTC_GUI_TRIG_VLINE:
  579. r = r100_cs_packet_parse_vline(p);
  580. if (r) {
  581. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  582. idx, reg);
  583. radeon_cs_dump_packet(p, pkt);
  584. return r;
  585. }
  586. break;
  587. case RADEON_DST_PITCH_OFFSET:
  588. case RADEON_SRC_PITCH_OFFSET:
  589. r = r100_reloc_pitch_offset(p, pkt, idx, reg);
  590. if (r)
  591. return r;
  592. break;
  593. case R300_RB3D_COLOROFFSET0:
  594. case R300_RB3D_COLOROFFSET1:
  595. case R300_RB3D_COLOROFFSET2:
  596. case R300_RB3D_COLOROFFSET3:
  597. i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
  598. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  599. if (r) {
  600. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  601. idx, reg);
  602. radeon_cs_dump_packet(p, pkt);
  603. return r;
  604. }
  605. track->cb[i].robj = reloc->robj;
  606. track->cb[i].offset = idx_value;
  607. track->cb_dirty = true;
  608. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  609. break;
  610. case R300_ZB_DEPTHOFFSET:
  611. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  612. if (r) {
  613. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  614. idx, reg);
  615. radeon_cs_dump_packet(p, pkt);
  616. return r;
  617. }
  618. track->zb.robj = reloc->robj;
  619. track->zb.offset = idx_value;
  620. track->zb_dirty = true;
  621. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  622. break;
  623. case R300_TX_OFFSET_0:
  624. case R300_TX_OFFSET_0+4:
  625. case R300_TX_OFFSET_0+8:
  626. case R300_TX_OFFSET_0+12:
  627. case R300_TX_OFFSET_0+16:
  628. case R300_TX_OFFSET_0+20:
  629. case R300_TX_OFFSET_0+24:
  630. case R300_TX_OFFSET_0+28:
  631. case R300_TX_OFFSET_0+32:
  632. case R300_TX_OFFSET_0+36:
  633. case R300_TX_OFFSET_0+40:
  634. case R300_TX_OFFSET_0+44:
  635. case R300_TX_OFFSET_0+48:
  636. case R300_TX_OFFSET_0+52:
  637. case R300_TX_OFFSET_0+56:
  638. case R300_TX_OFFSET_0+60:
  639. i = (reg - R300_TX_OFFSET_0) >> 2;
  640. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  641. if (r) {
  642. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  643. idx, reg);
  644. radeon_cs_dump_packet(p, pkt);
  645. return r;
  646. }
  647. if (p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) {
  648. ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
  649. ((idx_value & ~31) + (u32)reloc->gpu_offset);
  650. } else {
  651. if (reloc->tiling_flags & RADEON_TILING_MACRO)
  652. tile_flags |= R300_TXO_MACRO_TILE;
  653. if (reloc->tiling_flags & RADEON_TILING_MICRO)
  654. tile_flags |= R300_TXO_MICRO_TILE;
  655. else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
  656. tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
  657. tmp = idx_value + ((u32)reloc->gpu_offset);
  658. tmp |= tile_flags;
  659. ib[idx] = tmp;
  660. }
  661. track->textures[i].robj = reloc->robj;
  662. track->tex_dirty = true;
  663. break;
  664. /* Tracked registers */
  665. case 0x2084:
  666. /* VAP_VF_CNTL */
  667. track->vap_vf_cntl = idx_value;
  668. break;
  669. case 0x20B4:
  670. /* VAP_VTX_SIZE */
  671. track->vtx_size = idx_value & 0x7F;
  672. break;
  673. case 0x2134:
  674. /* VAP_VF_MAX_VTX_INDX */
  675. track->max_indx = idx_value & 0x00FFFFFFUL;
  676. break;
  677. case 0x2088:
  678. /* VAP_ALT_NUM_VERTICES - only valid on r500 */
  679. if (p->rdev->family < CHIP_RV515)
  680. goto fail;
  681. track->vap_alt_nverts = idx_value & 0xFFFFFF;
  682. break;
  683. case 0x43E4:
  684. /* SC_SCISSOR1 */
  685. track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
  686. if (p->rdev->family < CHIP_RV515) {
  687. track->maxy -= 1440;
  688. }
  689. track->cb_dirty = true;
  690. track->zb_dirty = true;
  691. break;
  692. case 0x4E00:
  693. /* RB3D_CCTL */
  694. if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
  695. p->rdev->cmask_filp != p->filp) {
  696. DRM_ERROR("Invalid RB3D_CCTL: Cannot enable CMASK.\n");
  697. return -EINVAL;
  698. }
  699. track->num_cb = ((idx_value >> 5) & 0x3) + 1;
  700. track->cb_dirty = true;
  701. break;
  702. case 0x4E38:
  703. case 0x4E3C:
  704. case 0x4E40:
  705. case 0x4E44:
  706. /* RB3D_COLORPITCH0 */
  707. /* RB3D_COLORPITCH1 */
  708. /* RB3D_COLORPITCH2 */
  709. /* RB3D_COLORPITCH3 */
  710. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  711. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  712. if (r) {
  713. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  714. idx, reg);
  715. radeon_cs_dump_packet(p, pkt);
  716. return r;
  717. }
  718. if (reloc->tiling_flags & RADEON_TILING_MACRO)
  719. tile_flags |= R300_COLOR_TILE_ENABLE;
  720. if (reloc->tiling_flags & RADEON_TILING_MICRO)
  721. tile_flags |= R300_COLOR_MICROTILE_ENABLE;
  722. else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
  723. tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
  724. tmp = idx_value & ~(0x7 << 16);
  725. tmp |= tile_flags;
  726. ib[idx] = tmp;
  727. }
  728. i = (reg - 0x4E38) >> 2;
  729. track->cb[i].pitch = idx_value & 0x3FFE;
  730. switch (((idx_value >> 21) & 0xF)) {
  731. case 9:
  732. case 11:
  733. case 12:
  734. track->cb[i].cpp = 1;
  735. break;
  736. case 3:
  737. case 4:
  738. case 13:
  739. case 15:
  740. track->cb[i].cpp = 2;
  741. break;
  742. case 5:
  743. if (p->rdev->family < CHIP_RV515) {
  744. DRM_ERROR("Invalid color buffer format (%d)!\n",
  745. ((idx_value >> 21) & 0xF));
  746. return -EINVAL;
  747. }
  748. fallthrough;
  749. case 6:
  750. track->cb[i].cpp = 4;
  751. break;
  752. case 10:
  753. track->cb[i].cpp = 8;
  754. break;
  755. case 7:
  756. track->cb[i].cpp = 16;
  757. break;
  758. default:
  759. DRM_ERROR("Invalid color buffer format (%d) !\n",
  760. ((idx_value >> 21) & 0xF));
  761. return -EINVAL;
  762. }
  763. track->cb_dirty = true;
  764. break;
  765. case 0x4F00:
  766. /* ZB_CNTL */
  767. if (idx_value & 2) {
  768. track->z_enabled = true;
  769. } else {
  770. track->z_enabled = false;
  771. }
  772. track->zb_dirty = true;
  773. break;
  774. case 0x4F10:
  775. /* ZB_FORMAT */
  776. switch ((idx_value & 0xF)) {
  777. case 0:
  778. case 1:
  779. track->zb.cpp = 2;
  780. break;
  781. case 2:
  782. track->zb.cpp = 4;
  783. break;
  784. default:
  785. DRM_ERROR("Invalid z buffer format (%d) !\n",
  786. (idx_value & 0xF));
  787. return -EINVAL;
  788. }
  789. track->zb_dirty = true;
  790. break;
  791. case 0x4F24:
  792. /* ZB_DEPTHPITCH */
  793. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  794. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  795. if (r) {
  796. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  797. idx, reg);
  798. radeon_cs_dump_packet(p, pkt);
  799. return r;
  800. }
  801. if (reloc->tiling_flags & RADEON_TILING_MACRO)
  802. tile_flags |= R300_DEPTHMACROTILE_ENABLE;
  803. if (reloc->tiling_flags & RADEON_TILING_MICRO)
  804. tile_flags |= R300_DEPTHMICROTILE_TILED;
  805. else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)
  806. tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
  807. tmp = idx_value & ~(0x7 << 16);
  808. tmp |= tile_flags;
  809. ib[idx] = tmp;
  810. }
  811. track->zb.pitch = idx_value & 0x3FFC;
  812. track->zb_dirty = true;
  813. break;
  814. case 0x4104:
  815. /* TX_ENABLE */
  816. for (i = 0; i < 16; i++) {
  817. bool enabled;
  818. enabled = !!(idx_value & (1 << i));
  819. track->textures[i].enabled = enabled;
  820. }
  821. track->tex_dirty = true;
  822. break;
  823. case 0x44C0:
  824. case 0x44C4:
  825. case 0x44C8:
  826. case 0x44CC:
  827. case 0x44D0:
  828. case 0x44D4:
  829. case 0x44D8:
  830. case 0x44DC:
  831. case 0x44E0:
  832. case 0x44E4:
  833. case 0x44E8:
  834. case 0x44EC:
  835. case 0x44F0:
  836. case 0x44F4:
  837. case 0x44F8:
  838. case 0x44FC:
  839. /* TX_FORMAT1_[0-15] */
  840. i = (reg - 0x44C0) >> 2;
  841. tmp = (idx_value >> 25) & 0x3;
  842. track->textures[i].tex_coord_type = tmp;
  843. switch ((idx_value & 0x1F)) {
  844. case R300_TX_FORMAT_X8:
  845. case R300_TX_FORMAT_Y4X4:
  846. case R300_TX_FORMAT_Z3Y3X2:
  847. track->textures[i].cpp = 1;
  848. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  849. break;
  850. case R300_TX_FORMAT_X16:
  851. case R300_TX_FORMAT_FL_I16:
  852. case R300_TX_FORMAT_Y8X8:
  853. case R300_TX_FORMAT_Z5Y6X5:
  854. case R300_TX_FORMAT_Z6Y5X5:
  855. case R300_TX_FORMAT_W4Z4Y4X4:
  856. case R300_TX_FORMAT_W1Z5Y5X5:
  857. case R300_TX_FORMAT_D3DMFT_CxV8U8:
  858. case R300_TX_FORMAT_B8G8_B8G8:
  859. case R300_TX_FORMAT_G8R8_G8B8:
  860. track->textures[i].cpp = 2;
  861. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  862. break;
  863. case R300_TX_FORMAT_Y16X16:
  864. case R300_TX_FORMAT_FL_I16A16:
  865. case R300_TX_FORMAT_Z11Y11X10:
  866. case R300_TX_FORMAT_Z10Y11X11:
  867. case R300_TX_FORMAT_W8Z8Y8X8:
  868. case R300_TX_FORMAT_W2Z10Y10X10:
  869. case 0x17:
  870. case R300_TX_FORMAT_FL_I32:
  871. case 0x1e:
  872. track->textures[i].cpp = 4;
  873. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  874. break;
  875. case R300_TX_FORMAT_W16Z16Y16X16:
  876. case R300_TX_FORMAT_FL_R16G16B16A16:
  877. case R300_TX_FORMAT_FL_I32A32:
  878. track->textures[i].cpp = 8;
  879. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  880. break;
  881. case R300_TX_FORMAT_FL_R32G32B32A32:
  882. track->textures[i].cpp = 16;
  883. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  884. break;
  885. case R300_TX_FORMAT_DXT1:
  886. track->textures[i].cpp = 1;
  887. track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
  888. break;
  889. case R300_TX_FORMAT_ATI2N:
  890. if (p->rdev->family < CHIP_R420) {
  891. DRM_ERROR("Invalid texture format %u\n",
  892. (idx_value & 0x1F));
  893. return -EINVAL;
  894. }
  895. /* The same rules apply as for DXT3/5. */
  896. fallthrough;
  897. case R300_TX_FORMAT_DXT3:
  898. case R300_TX_FORMAT_DXT5:
  899. track->textures[i].cpp = 1;
  900. track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
  901. break;
  902. default:
  903. DRM_ERROR("Invalid texture format %u\n",
  904. (idx_value & 0x1F));
  905. return -EINVAL;
  906. }
  907. track->tex_dirty = true;
  908. break;
  909. case 0x4400:
  910. case 0x4404:
  911. case 0x4408:
  912. case 0x440C:
  913. case 0x4410:
  914. case 0x4414:
  915. case 0x4418:
  916. case 0x441C:
  917. case 0x4420:
  918. case 0x4424:
  919. case 0x4428:
  920. case 0x442C:
  921. case 0x4430:
  922. case 0x4434:
  923. case 0x4438:
  924. case 0x443C:
  925. /* TX_FILTER0_[0-15] */
  926. i = (reg - 0x4400) >> 2;
  927. tmp = idx_value & 0x7;
  928. if (tmp == 2 || tmp == 4 || tmp == 6) {
  929. track->textures[i].roundup_w = false;
  930. }
  931. tmp = (idx_value >> 3) & 0x7;
  932. if (tmp == 2 || tmp == 4 || tmp == 6) {
  933. track->textures[i].roundup_h = false;
  934. }
  935. track->tex_dirty = true;
  936. break;
  937. case 0x4500:
  938. case 0x4504:
  939. case 0x4508:
  940. case 0x450C:
  941. case 0x4510:
  942. case 0x4514:
  943. case 0x4518:
  944. case 0x451C:
  945. case 0x4520:
  946. case 0x4524:
  947. case 0x4528:
  948. case 0x452C:
  949. case 0x4530:
  950. case 0x4534:
  951. case 0x4538:
  952. case 0x453C:
  953. /* TX_FORMAT2_[0-15] */
  954. i = (reg - 0x4500) >> 2;
  955. tmp = idx_value & 0x3FFF;
  956. track->textures[i].pitch = tmp + 1;
  957. if (p->rdev->family >= CHIP_RV515) {
  958. tmp = ((idx_value >> 15) & 1) << 11;
  959. track->textures[i].width_11 = tmp;
  960. tmp = ((idx_value >> 16) & 1) << 11;
  961. track->textures[i].height_11 = tmp;
  962. /* ATI1N */
  963. if (idx_value & (1 << 14)) {
  964. /* The same rules apply as for DXT1. */
  965. track->textures[i].compress_format =
  966. R100_TRACK_COMP_DXT1;
  967. }
  968. } else if (idx_value & (1 << 14)) {
  969. DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
  970. return -EINVAL;
  971. }
  972. track->tex_dirty = true;
  973. break;
  974. case 0x4480:
  975. case 0x4484:
  976. case 0x4488:
  977. case 0x448C:
  978. case 0x4490:
  979. case 0x4494:
  980. case 0x4498:
  981. case 0x449C:
  982. case 0x44A0:
  983. case 0x44A4:
  984. case 0x44A8:
  985. case 0x44AC:
  986. case 0x44B0:
  987. case 0x44B4:
  988. case 0x44B8:
  989. case 0x44BC:
  990. /* TX_FORMAT0_[0-15] */
  991. i = (reg - 0x4480) >> 2;
  992. tmp = idx_value & 0x7FF;
  993. track->textures[i].width = tmp + 1;
  994. tmp = (idx_value >> 11) & 0x7FF;
  995. track->textures[i].height = tmp + 1;
  996. tmp = (idx_value >> 26) & 0xF;
  997. track->textures[i].num_levels = tmp;
  998. tmp = idx_value & (1 << 31);
  999. track->textures[i].use_pitch = !!tmp;
  1000. tmp = (idx_value >> 22) & 0xF;
  1001. track->textures[i].txdepth = tmp;
  1002. track->tex_dirty = true;
  1003. break;
  1004. case R300_ZB_ZPASS_ADDR:
  1005. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1006. if (r) {
  1007. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1008. idx, reg);
  1009. radeon_cs_dump_packet(p, pkt);
  1010. return r;
  1011. }
  1012. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1013. break;
  1014. case 0x4e0c:
  1015. /* RB3D_COLOR_CHANNEL_MASK */
  1016. track->color_channel_mask = idx_value;
  1017. track->cb_dirty = true;
  1018. break;
  1019. case 0x43a4:
  1020. /* SC_HYPERZ_EN */
  1021. /* r300c emits this register - we need to disable hyperz for it
  1022. * without complaining */
  1023. if (p->rdev->hyperz_filp != p->filp) {
  1024. if (idx_value & 0x1)
  1025. ib[idx] = idx_value & ~1;
  1026. }
  1027. break;
  1028. case 0x4f1c:
  1029. /* ZB_BW_CNTL */
  1030. track->zb_cb_clear = !!(idx_value & (1 << 5));
  1031. track->cb_dirty = true;
  1032. track->zb_dirty = true;
  1033. if (p->rdev->hyperz_filp != p->filp) {
  1034. if (idx_value & (R300_HIZ_ENABLE |
  1035. R300_RD_COMP_ENABLE |
  1036. R300_WR_COMP_ENABLE |
  1037. R300_FAST_FILL_ENABLE))
  1038. goto fail;
  1039. }
  1040. break;
  1041. case 0x4e04:
  1042. /* RB3D_BLENDCNTL */
  1043. track->blend_read_enable = !!(idx_value & (1 << 2));
  1044. track->cb_dirty = true;
  1045. break;
  1046. case R300_RB3D_AARESOLVE_OFFSET:
  1047. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1048. if (r) {
  1049. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1050. idx, reg);
  1051. radeon_cs_dump_packet(p, pkt);
  1052. return r;
  1053. }
  1054. track->aa.robj = reloc->robj;
  1055. track->aa.offset = idx_value;
  1056. track->aa_dirty = true;
  1057. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1058. break;
  1059. case R300_RB3D_AARESOLVE_PITCH:
  1060. track->aa.pitch = idx_value & 0x3FFE;
  1061. track->aa_dirty = true;
  1062. break;
  1063. case R300_RB3D_AARESOLVE_CTL:
  1064. track->aaresolve = idx_value & 0x1;
  1065. track->aa_dirty = true;
  1066. break;
  1067. case 0x4f30: /* ZB_MASK_OFFSET */
  1068. case 0x4f34: /* ZB_ZMASK_PITCH */
  1069. case 0x4f44: /* ZB_HIZ_OFFSET */
  1070. case 0x4f54: /* ZB_HIZ_PITCH */
  1071. if (idx_value && (p->rdev->hyperz_filp != p->filp))
  1072. goto fail;
  1073. break;
  1074. case 0x4028:
  1075. if (idx_value && (p->rdev->hyperz_filp != p->filp))
  1076. goto fail;
  1077. /* GB_Z_PEQ_CONFIG */
  1078. if (p->rdev->family >= CHIP_RV350)
  1079. break;
  1080. goto fail;
  1081. break;
  1082. case 0x4be8:
  1083. /* valid register only on RV530 */
  1084. if (p->rdev->family == CHIP_RV530)
  1085. break;
  1086. fallthrough;
  1087. /* fallthrough do not move */
  1088. default:
  1089. goto fail;
  1090. }
  1091. return 0;
  1092. fail:
  1093. pr_err("Forbidden register 0x%04X in cs at %d (val=%08x)\n",
  1094. reg, idx, idx_value);
  1095. return -EINVAL;
  1096. }
  1097. static int r300_packet3_check(struct radeon_cs_parser *p,
  1098. struct radeon_cs_packet *pkt)
  1099. {
  1100. struct radeon_bo_list *reloc;
  1101. struct r100_cs_track *track;
  1102. volatile uint32_t *ib;
  1103. unsigned idx;
  1104. int r;
  1105. ib = p->ib.ptr;
  1106. idx = pkt->idx + 1;
  1107. track = (struct r100_cs_track *)p->track;
  1108. switch(pkt->opcode) {
  1109. case PACKET3_3D_LOAD_VBPNTR:
  1110. r = r100_packet3_load_vbpntr(p, pkt, idx);
  1111. if (r)
  1112. return r;
  1113. break;
  1114. case PACKET3_INDX_BUFFER:
  1115. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1116. if (r) {
  1117. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1118. radeon_cs_dump_packet(p, pkt);
  1119. return r;
  1120. }
  1121. ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
  1122. r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
  1123. if (r) {
  1124. return r;
  1125. }
  1126. break;
  1127. /* Draw packet */
  1128. case PACKET3_3D_DRAW_IMMD:
  1129. /* Number of dwords is vtx_size * (num_vertices - 1)
  1130. * PRIM_WALK must be equal to 3 vertex data in embedded
  1131. * in cmd stream */
  1132. if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
  1133. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1134. return -EINVAL;
  1135. }
  1136. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1137. track->immd_dwords = pkt->count - 1;
  1138. r = r100_cs_track_check(p->rdev, track);
  1139. if (r) {
  1140. return r;
  1141. }
  1142. break;
  1143. case PACKET3_3D_DRAW_IMMD_2:
  1144. /* Number of dwords is vtx_size * (num_vertices - 1)
  1145. * PRIM_WALK must be equal to 3 vertex data in embedded
  1146. * in cmd stream */
  1147. if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
  1148. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1149. return -EINVAL;
  1150. }
  1151. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1152. track->immd_dwords = pkt->count;
  1153. r = r100_cs_track_check(p->rdev, track);
  1154. if (r) {
  1155. return r;
  1156. }
  1157. break;
  1158. case PACKET3_3D_DRAW_VBUF:
  1159. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1160. r = r100_cs_track_check(p->rdev, track);
  1161. if (r) {
  1162. return r;
  1163. }
  1164. break;
  1165. case PACKET3_3D_DRAW_VBUF_2:
  1166. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1167. r = r100_cs_track_check(p->rdev, track);
  1168. if (r) {
  1169. return r;
  1170. }
  1171. break;
  1172. case PACKET3_3D_DRAW_INDX:
  1173. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1174. r = r100_cs_track_check(p->rdev, track);
  1175. if (r) {
  1176. return r;
  1177. }
  1178. break;
  1179. case PACKET3_3D_DRAW_INDX_2:
  1180. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1181. r = r100_cs_track_check(p->rdev, track);
  1182. if (r) {
  1183. return r;
  1184. }
  1185. break;
  1186. case PACKET3_3D_CLEAR_HIZ:
  1187. case PACKET3_3D_CLEAR_ZMASK:
  1188. if (p->rdev->hyperz_filp != p->filp)
  1189. return -EINVAL;
  1190. break;
  1191. case PACKET3_3D_CLEAR_CMASK:
  1192. if (p->rdev->cmask_filp != p->filp)
  1193. return -EINVAL;
  1194. break;
  1195. case PACKET3_NOP:
  1196. break;
  1197. default:
  1198. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  1199. return -EINVAL;
  1200. }
  1201. return 0;
  1202. }
  1203. int r300_cs_parse(struct radeon_cs_parser *p)
  1204. {
  1205. struct radeon_cs_packet pkt;
  1206. struct r100_cs_track *track;
  1207. int r;
  1208. track = kzalloc(sizeof(*track), GFP_KERNEL);
  1209. if (track == NULL)
  1210. return -ENOMEM;
  1211. r100_cs_track_clear(p->rdev, track);
  1212. p->track = track;
  1213. do {
  1214. r = radeon_cs_packet_parse(p, &pkt, p->idx);
  1215. if (r) {
  1216. return r;
  1217. }
  1218. p->idx += pkt.count + 2;
  1219. switch (pkt.type) {
  1220. case RADEON_PACKET_TYPE0:
  1221. r = r100_cs_parse_packet0(p, &pkt,
  1222. p->rdev->config.r300.reg_safe_bm,
  1223. p->rdev->config.r300.reg_safe_bm_size,
  1224. &r300_packet0_check);
  1225. break;
  1226. case RADEON_PACKET_TYPE2:
  1227. break;
  1228. case RADEON_PACKET_TYPE3:
  1229. r = r300_packet3_check(p, &pkt);
  1230. break;
  1231. default:
  1232. DRM_ERROR("Unknown packet type %d !\n", pkt.type);
  1233. return -EINVAL;
  1234. }
  1235. if (r) {
  1236. return r;
  1237. }
  1238. } while (p->idx < p->chunk_ib->length_dw);
  1239. return 0;
  1240. }
  1241. void r300_set_reg_safe(struct radeon_device *rdev)
  1242. {
  1243. rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
  1244. rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
  1245. }
  1246. void r300_mc_program(struct radeon_device *rdev)
  1247. {
  1248. struct r100_mc_save save;
  1249. r100_debugfs_mc_info_init(rdev);
  1250. /* Stops all mc clients */
  1251. r100_mc_stop(rdev, &save);
  1252. if (rdev->flags & RADEON_IS_AGP) {
  1253. WREG32(R_00014C_MC_AGP_LOCATION,
  1254. S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
  1255. S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
  1256. WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
  1257. WREG32(R_00015C_AGP_BASE_2,
  1258. upper_32_bits(rdev->mc.agp_base) & 0xff);
  1259. } else {
  1260. WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
  1261. WREG32(R_000170_AGP_BASE, 0);
  1262. WREG32(R_00015C_AGP_BASE_2, 0);
  1263. }
  1264. /* Wait for mc idle */
  1265. if (r300_mc_wait_for_idle(rdev))
  1266. DRM_INFO("Failed to wait MC idle before programming MC.\n");
  1267. /* Program MC, should be a 32bits limited address space */
  1268. WREG32(R_000148_MC_FB_LOCATION,
  1269. S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
  1270. S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
  1271. r100_mc_resume(rdev, &save);
  1272. }
  1273. void r300_clock_startup(struct radeon_device *rdev)
  1274. {
  1275. u32 tmp;
  1276. if (radeon_dynclks != -1 && radeon_dynclks)
  1277. radeon_legacy_set_clock_gating(rdev, 1);
  1278. /* We need to force on some of the block */
  1279. tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
  1280. tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
  1281. if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
  1282. tmp |= S_00000D_FORCE_VAP(1);
  1283. WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
  1284. }
  1285. static int r300_startup(struct radeon_device *rdev)
  1286. {
  1287. int r;
  1288. /* set common regs */
  1289. r100_set_common_regs(rdev);
  1290. /* program mc */
  1291. r300_mc_program(rdev);
  1292. /* Resume clock */
  1293. r300_clock_startup(rdev);
  1294. /* Initialize GPU configuration (# pipes, ...) */
  1295. r300_gpu_init(rdev);
  1296. /* Initialize GART (initialize after TTM so we can allocate
  1297. * memory through TTM but finalize after TTM) */
  1298. if (rdev->flags & RADEON_IS_PCIE) {
  1299. r = rv370_pcie_gart_enable(rdev);
  1300. if (r)
  1301. return r;
  1302. }
  1303. if (rdev->family == CHIP_R300 ||
  1304. rdev->family == CHIP_R350 ||
  1305. rdev->family == CHIP_RV350)
  1306. r100_enable_bm(rdev);
  1307. if (rdev->flags & RADEON_IS_PCI) {
  1308. r = r100_pci_gart_enable(rdev);
  1309. if (r)
  1310. return r;
  1311. }
  1312. /* allocate wb buffer */
  1313. r = radeon_wb_init(rdev);
  1314. if (r)
  1315. return r;
  1316. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  1317. if (r) {
  1318. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  1319. return r;
  1320. }
  1321. /* Enable IRQ */
  1322. if (!rdev->irq.installed) {
  1323. r = radeon_irq_kms_init(rdev);
  1324. if (r)
  1325. return r;
  1326. }
  1327. r100_irq_set(rdev);
  1328. rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  1329. /* 1M ring buffer */
  1330. r = r100_cp_init(rdev, 1024 * 1024);
  1331. if (r) {
  1332. dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  1333. return r;
  1334. }
  1335. r = radeon_ib_pool_init(rdev);
  1336. if (r) {
  1337. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  1338. return r;
  1339. }
  1340. return 0;
  1341. }
  1342. int r300_resume(struct radeon_device *rdev)
  1343. {
  1344. int r;
  1345. /* Make sur GART are not working */
  1346. if (rdev->flags & RADEON_IS_PCIE)
  1347. rv370_pcie_gart_disable(rdev);
  1348. if (rdev->flags & RADEON_IS_PCI)
  1349. r100_pci_gart_disable(rdev);
  1350. /* Resume clock before doing reset */
  1351. r300_clock_startup(rdev);
  1352. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  1353. if (radeon_asic_reset(rdev)) {
  1354. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  1355. RREG32(R_000E40_RBBM_STATUS),
  1356. RREG32(R_0007C0_CP_STAT));
  1357. }
  1358. /* post */
  1359. radeon_combios_asic_init(rdev->ddev);
  1360. /* Resume clock after posting */
  1361. r300_clock_startup(rdev);
  1362. /* Initialize surface registers */
  1363. radeon_surface_init(rdev);
  1364. rdev->accel_working = true;
  1365. r = r300_startup(rdev);
  1366. if (r) {
  1367. rdev->accel_working = false;
  1368. }
  1369. return r;
  1370. }
  1371. int r300_suspend(struct radeon_device *rdev)
  1372. {
  1373. radeon_pm_suspend(rdev);
  1374. r100_cp_disable(rdev);
  1375. radeon_wb_disable(rdev);
  1376. r100_irq_disable(rdev);
  1377. if (rdev->flags & RADEON_IS_PCIE)
  1378. rv370_pcie_gart_disable(rdev);
  1379. if (rdev->flags & RADEON_IS_PCI)
  1380. r100_pci_gart_disable(rdev);
  1381. return 0;
  1382. }
  1383. void r300_fini(struct radeon_device *rdev)
  1384. {
  1385. radeon_pm_fini(rdev);
  1386. r100_cp_fini(rdev);
  1387. radeon_wb_fini(rdev);
  1388. radeon_ib_pool_fini(rdev);
  1389. radeon_gem_fini(rdev);
  1390. if (rdev->flags & RADEON_IS_PCIE)
  1391. rv370_pcie_gart_fini(rdev);
  1392. if (rdev->flags & RADEON_IS_PCI)
  1393. r100_pci_gart_fini(rdev);
  1394. radeon_agp_fini(rdev);
  1395. radeon_irq_kms_fini(rdev);
  1396. radeon_fence_driver_fini(rdev);
  1397. radeon_bo_fini(rdev);
  1398. radeon_atombios_fini(rdev);
  1399. kfree(rdev->bios);
  1400. rdev->bios = NULL;
  1401. }
  1402. int r300_init(struct radeon_device *rdev)
  1403. {
  1404. int r;
  1405. /* Disable VGA */
  1406. r100_vga_render_disable(rdev);
  1407. /* Initialize scratch registers */
  1408. radeon_scratch_init(rdev);
  1409. /* Initialize surface registers */
  1410. radeon_surface_init(rdev);
  1411. /* TODO: disable VGA need to use VGA request */
  1412. /* restore some register to sane defaults */
  1413. r100_restore_sanity(rdev);
  1414. /* BIOS*/
  1415. if (!radeon_get_bios(rdev)) {
  1416. if (ASIC_IS_AVIVO(rdev))
  1417. return -EINVAL;
  1418. }
  1419. if (rdev->is_atom_bios) {
  1420. dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
  1421. return -EINVAL;
  1422. } else {
  1423. r = radeon_combios_init(rdev);
  1424. if (r)
  1425. return r;
  1426. }
  1427. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  1428. if (radeon_asic_reset(rdev)) {
  1429. dev_warn(rdev->dev,
  1430. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  1431. RREG32(R_000E40_RBBM_STATUS),
  1432. RREG32(R_0007C0_CP_STAT));
  1433. }
  1434. /* check if cards are posted or not */
  1435. if (radeon_boot_test_post_card(rdev) == false)
  1436. return -EINVAL;
  1437. /* Set asic errata */
  1438. r300_errata(rdev);
  1439. /* Initialize clocks */
  1440. radeon_get_clock_info(rdev->ddev);
  1441. /* initialize AGP */
  1442. if (rdev->flags & RADEON_IS_AGP) {
  1443. r = radeon_agp_init(rdev);
  1444. if (r) {
  1445. radeon_agp_disable(rdev);
  1446. }
  1447. }
  1448. /* initialize memory controller */
  1449. r300_mc_init(rdev);
  1450. /* Fence driver */
  1451. radeon_fence_driver_init(rdev);
  1452. /* Memory manager */
  1453. r = radeon_bo_init(rdev);
  1454. if (r)
  1455. return r;
  1456. if (rdev->flags & RADEON_IS_PCIE) {
  1457. r = rv370_pcie_gart_init(rdev);
  1458. if (r)
  1459. return r;
  1460. }
  1461. if (rdev->flags & RADEON_IS_PCI) {
  1462. r = r100_pci_gart_init(rdev);
  1463. if (r)
  1464. return r;
  1465. }
  1466. r300_set_reg_safe(rdev);
  1467. /* Initialize power management */
  1468. radeon_pm_init(rdev);
  1469. rdev->accel_working = true;
  1470. r = r300_startup(rdev);
  1471. if (r) {
  1472. /* Something went wrong with the accel init, so stop accel */
  1473. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  1474. r100_cp_fini(rdev);
  1475. radeon_wb_fini(rdev);
  1476. radeon_ib_pool_fini(rdev);
  1477. radeon_irq_kms_fini(rdev);
  1478. if (rdev->flags & RADEON_IS_PCIE)
  1479. rv370_pcie_gart_fini(rdev);
  1480. if (rdev->flags & RADEON_IS_PCI)
  1481. r100_pci_gart_fini(rdev);
  1482. radeon_agp_fini(rdev);
  1483. rdev->accel_working = false;
  1484. }
  1485. return 0;
  1486. }