r100.c 117 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/firmware.h>
  29. #include <linux/module.h>
  30. #include <linux/pci.h>
  31. #include <linux/seq_file.h>
  32. #include <linux/slab.h>
  33. #include <drm/drm_device.h>
  34. #include <drm/drm_file.h>
  35. #include <drm/drm_fourcc.h>
  36. #include <drm/drm_framebuffer.h>
  37. #include <drm/drm_vblank.h>
  38. #include <drm/radeon_drm.h>
  39. #include "atom.h"
  40. #include "r100_reg_safe.h"
  41. #include "r100d.h"
  42. #include "radeon.h"
  43. #include "radeon_asic.h"
  44. #include "radeon_reg.h"
  45. #include "rn50_reg_safe.h"
  46. #include "rs100d.h"
  47. #include "rv200d.h"
  48. #include "rv250d.h"
  49. /* Firmware Names */
  50. #define FIRMWARE_R100 "radeon/R100_cp.bin"
  51. #define FIRMWARE_R200 "radeon/R200_cp.bin"
  52. #define FIRMWARE_R300 "radeon/R300_cp.bin"
  53. #define FIRMWARE_R420 "radeon/R420_cp.bin"
  54. #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
  55. #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
  56. #define FIRMWARE_R520 "radeon/R520_cp.bin"
  57. MODULE_FIRMWARE(FIRMWARE_R100);
  58. MODULE_FIRMWARE(FIRMWARE_R200);
  59. MODULE_FIRMWARE(FIRMWARE_R300);
  60. MODULE_FIRMWARE(FIRMWARE_R420);
  61. MODULE_FIRMWARE(FIRMWARE_RS690);
  62. MODULE_FIRMWARE(FIRMWARE_RS600);
  63. MODULE_FIRMWARE(FIRMWARE_R520);
  64. #include "r100_track.h"
  65. /* This files gather functions specifics to:
  66. * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  67. * and others in some cases.
  68. */
  69. static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  70. {
  71. if (crtc == 0) {
  72. if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  73. return true;
  74. else
  75. return false;
  76. } else {
  77. if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  78. return true;
  79. else
  80. return false;
  81. }
  82. }
  83. static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  84. {
  85. u32 vline1, vline2;
  86. if (crtc == 0) {
  87. vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  88. vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  89. } else {
  90. vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  91. vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  92. }
  93. if (vline1 != vline2)
  94. return true;
  95. else
  96. return false;
  97. }
  98. /**
  99. * r100_wait_for_vblank - vblank wait asic callback.
  100. *
  101. * @rdev: radeon_device pointer
  102. * @crtc: crtc to wait for vblank on
  103. *
  104. * Wait for vblank on the requested crtc (r1xx-r4xx).
  105. */
  106. void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
  107. {
  108. unsigned i = 0;
  109. if (crtc >= rdev->num_crtc)
  110. return;
  111. if (crtc == 0) {
  112. if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
  113. return;
  114. } else {
  115. if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
  116. return;
  117. }
  118. /* depending on when we hit vblank, we may be close to active; if so,
  119. * wait for another frame.
  120. */
  121. while (r100_is_in_vblank(rdev, crtc)) {
  122. if (i++ % 100 == 0) {
  123. if (!r100_is_counter_moving(rdev, crtc))
  124. break;
  125. }
  126. }
  127. while (!r100_is_in_vblank(rdev, crtc)) {
  128. if (i++ % 100 == 0) {
  129. if (!r100_is_counter_moving(rdev, crtc))
  130. break;
  131. }
  132. }
  133. }
  134. /**
  135. * r100_page_flip - pageflip callback.
  136. *
  137. * @rdev: radeon_device pointer
  138. * @crtc_id: crtc to cleanup pageflip on
  139. * @crtc_base: new address of the crtc (GPU MC address)
  140. * @async: asynchronous flip
  141. *
  142. * Does the actual pageflip (r1xx-r4xx).
  143. * During vblank we take the crtc lock and wait for the update_pending
  144. * bit to go high, when it does, we release the lock, and allow the
  145. * double buffered update to take place.
  146. */
  147. void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
  148. {
  149. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  150. uint32_t crtc_pitch, pitch_pixels;
  151. struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
  152. u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
  153. int i;
  154. /* Lock the graphics update lock */
  155. /* update the scanout addresses */
  156. WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
  157. /* update pitch */
  158. pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
  159. crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,
  160. fb->format->cpp[0] * 8 * 8);
  161. crtc_pitch |= crtc_pitch << 16;
  162. WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
  163. /* Wait for update_pending to go high. */
  164. for (i = 0; i < rdev->usec_timeout; i++) {
  165. if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
  166. break;
  167. udelay(1);
  168. }
  169. DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
  170. /* Unlock the lock, so double-buffering can take place inside vblank */
  171. tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
  172. WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
  173. }
  174. /**
  175. * r100_page_flip_pending - check if page flip is still pending
  176. *
  177. * @rdev: radeon_device pointer
  178. * @crtc_id: crtc to check
  179. *
  180. * Check if the last pagefilp is still pending (r1xx-r4xx).
  181. * Returns the current update pending status.
  182. */
  183. bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
  184. {
  185. struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
  186. /* Return current update_pending status: */
  187. return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) &
  188. RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET);
  189. }
  190. /**
  191. * r100_pm_get_dynpm_state - look up dynpm power state callback.
  192. *
  193. * @rdev: radeon_device pointer
  194. *
  195. * Look up the optimal power state based on the
  196. * current state of the GPU (r1xx-r5xx).
  197. * Used for dynpm only.
  198. */
  199. void r100_pm_get_dynpm_state(struct radeon_device *rdev)
  200. {
  201. int i;
  202. rdev->pm.dynpm_can_upclock = true;
  203. rdev->pm.dynpm_can_downclock = true;
  204. switch (rdev->pm.dynpm_planned_action) {
  205. case DYNPM_ACTION_MINIMUM:
  206. rdev->pm.requested_power_state_index = 0;
  207. rdev->pm.dynpm_can_downclock = false;
  208. break;
  209. case DYNPM_ACTION_DOWNCLOCK:
  210. if (rdev->pm.current_power_state_index == 0) {
  211. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  212. rdev->pm.dynpm_can_downclock = false;
  213. } else {
  214. if (rdev->pm.active_crtc_count > 1) {
  215. for (i = 0; i < rdev->pm.num_power_states; i++) {
  216. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  217. continue;
  218. else if (i >= rdev->pm.current_power_state_index) {
  219. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  220. break;
  221. } else {
  222. rdev->pm.requested_power_state_index = i;
  223. break;
  224. }
  225. }
  226. } else
  227. rdev->pm.requested_power_state_index =
  228. rdev->pm.current_power_state_index - 1;
  229. }
  230. /* don't use the power state if crtcs are active and no display flag is set */
  231. if ((rdev->pm.active_crtc_count > 0) &&
  232. (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
  233. RADEON_PM_MODE_NO_DISPLAY)) {
  234. rdev->pm.requested_power_state_index++;
  235. }
  236. break;
  237. case DYNPM_ACTION_UPCLOCK:
  238. if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
  239. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  240. rdev->pm.dynpm_can_upclock = false;
  241. } else {
  242. if (rdev->pm.active_crtc_count > 1) {
  243. for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
  244. if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
  245. continue;
  246. else if (i <= rdev->pm.current_power_state_index) {
  247. rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
  248. break;
  249. } else {
  250. rdev->pm.requested_power_state_index = i;
  251. break;
  252. }
  253. }
  254. } else
  255. rdev->pm.requested_power_state_index =
  256. rdev->pm.current_power_state_index + 1;
  257. }
  258. break;
  259. case DYNPM_ACTION_DEFAULT:
  260. rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
  261. rdev->pm.dynpm_can_upclock = false;
  262. break;
  263. case DYNPM_ACTION_NONE:
  264. default:
  265. DRM_ERROR("Requested mode for not defined action\n");
  266. return;
  267. }
  268. /* only one clock mode per power state */
  269. rdev->pm.requested_clock_mode_index = 0;
  270. DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
  271. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  272. clock_info[rdev->pm.requested_clock_mode_index].sclk,
  273. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  274. clock_info[rdev->pm.requested_clock_mode_index].mclk,
  275. rdev->pm.power_state[rdev->pm.requested_power_state_index].
  276. pcie_lanes);
  277. }
  278. /**
  279. * r100_pm_init_profile - Initialize power profiles callback.
  280. *
  281. * @rdev: radeon_device pointer
  282. *
  283. * Initialize the power states used in profile mode
  284. * (r1xx-r3xx).
  285. * Used for profile mode only.
  286. */
  287. void r100_pm_init_profile(struct radeon_device *rdev)
  288. {
  289. /* default */
  290. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
  291. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  292. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
  293. rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
  294. /* low sh */
  295. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
  296. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
  297. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
  298. rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
  299. /* mid sh */
  300. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
  301. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
  302. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
  303. rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
  304. /* high sh */
  305. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
  306. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  307. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
  308. rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
  309. /* low mh */
  310. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
  311. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  312. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
  313. rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
  314. /* mid mh */
  315. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
  316. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  317. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
  318. rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
  319. /* high mh */
  320. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
  321. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
  322. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
  323. rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
  324. }
  325. /**
  326. * r100_pm_misc - set additional pm hw parameters callback.
  327. *
  328. * @rdev: radeon_device pointer
  329. *
  330. * Set non-clock parameters associated with a power state
  331. * (voltage, pcie lanes, etc.) (r1xx-r4xx).
  332. */
  333. void r100_pm_misc(struct radeon_device *rdev)
  334. {
  335. int requested_index = rdev->pm.requested_power_state_index;
  336. struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
  337. struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
  338. u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
  339. if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
  340. if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
  341. tmp = RREG32(voltage->gpio.reg);
  342. if (voltage->active_high)
  343. tmp |= voltage->gpio.mask;
  344. else
  345. tmp &= ~(voltage->gpio.mask);
  346. WREG32(voltage->gpio.reg, tmp);
  347. if (voltage->delay)
  348. udelay(voltage->delay);
  349. } else {
  350. tmp = RREG32(voltage->gpio.reg);
  351. if (voltage->active_high)
  352. tmp &= ~voltage->gpio.mask;
  353. else
  354. tmp |= voltage->gpio.mask;
  355. WREG32(voltage->gpio.reg, tmp);
  356. if (voltage->delay)
  357. udelay(voltage->delay);
  358. }
  359. }
  360. sclk_cntl = RREG32_PLL(SCLK_CNTL);
  361. sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
  362. sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
  363. sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
  364. sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
  365. if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
  366. sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
  367. if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
  368. sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
  369. else
  370. sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
  371. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
  372. sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
  373. else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
  374. sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
  375. } else
  376. sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
  377. if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
  378. sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
  379. if (voltage->delay) {
  380. sclk_more_cntl |= VOLTAGE_DROP_SYNC;
  381. switch (voltage->delay) {
  382. case 33:
  383. sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
  384. break;
  385. case 66:
  386. sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
  387. break;
  388. case 99:
  389. sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
  390. break;
  391. case 132:
  392. sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
  393. break;
  394. }
  395. } else
  396. sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
  397. } else
  398. sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
  399. if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
  400. sclk_cntl &= ~FORCE_HDP;
  401. else
  402. sclk_cntl |= FORCE_HDP;
  403. WREG32_PLL(SCLK_CNTL, sclk_cntl);
  404. WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
  405. WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
  406. /* set pcie lanes */
  407. if ((rdev->flags & RADEON_IS_PCIE) &&
  408. !(rdev->flags & RADEON_IS_IGP) &&
  409. rdev->asic->pm.set_pcie_lanes &&
  410. (ps->pcie_lanes !=
  411. rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
  412. radeon_set_pcie_lanes(rdev,
  413. ps->pcie_lanes);
  414. DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
  415. }
  416. }
  417. /**
  418. * r100_pm_prepare - pre-power state change callback.
  419. *
  420. * @rdev: radeon_device pointer
  421. *
  422. * Prepare for a power state change (r1xx-r4xx).
  423. */
  424. void r100_pm_prepare(struct radeon_device *rdev)
  425. {
  426. struct drm_device *ddev = rdev->ddev;
  427. struct drm_crtc *crtc;
  428. struct radeon_crtc *radeon_crtc;
  429. u32 tmp;
  430. /* disable any active CRTCs */
  431. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  432. radeon_crtc = to_radeon_crtc(crtc);
  433. if (radeon_crtc->enabled) {
  434. if (radeon_crtc->crtc_id) {
  435. tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
  436. tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
  437. WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  438. } else {
  439. tmp = RREG32(RADEON_CRTC_GEN_CNTL);
  440. tmp |= RADEON_CRTC_DISP_REQ_EN_B;
  441. WREG32(RADEON_CRTC_GEN_CNTL, tmp);
  442. }
  443. }
  444. }
  445. }
  446. /**
  447. * r100_pm_finish - post-power state change callback.
  448. *
  449. * @rdev: radeon_device pointer
  450. *
  451. * Clean up after a power state change (r1xx-r4xx).
  452. */
  453. void r100_pm_finish(struct radeon_device *rdev)
  454. {
  455. struct drm_device *ddev = rdev->ddev;
  456. struct drm_crtc *crtc;
  457. struct radeon_crtc *radeon_crtc;
  458. u32 tmp;
  459. /* enable any active CRTCs */
  460. list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  461. radeon_crtc = to_radeon_crtc(crtc);
  462. if (radeon_crtc->enabled) {
  463. if (radeon_crtc->crtc_id) {
  464. tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
  465. tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
  466. WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
  467. } else {
  468. tmp = RREG32(RADEON_CRTC_GEN_CNTL);
  469. tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
  470. WREG32(RADEON_CRTC_GEN_CNTL, tmp);
  471. }
  472. }
  473. }
  474. }
  475. /**
  476. * r100_gui_idle - gui idle callback.
  477. *
  478. * @rdev: radeon_device pointer
  479. *
  480. * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
  481. * Returns true if idle, false if not.
  482. */
  483. bool r100_gui_idle(struct radeon_device *rdev)
  484. {
  485. if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
  486. return false;
  487. else
  488. return true;
  489. }
  490. /* hpd for digital panel detect/disconnect */
  491. /**
  492. * r100_hpd_sense - hpd sense callback.
  493. *
  494. * @rdev: radeon_device pointer
  495. * @hpd: hpd (hotplug detect) pin
  496. *
  497. * Checks if a digital monitor is connected (r1xx-r4xx).
  498. * Returns true if connected, false if not connected.
  499. */
  500. bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  501. {
  502. bool connected = false;
  503. switch (hpd) {
  504. case RADEON_HPD_1:
  505. if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
  506. connected = true;
  507. break;
  508. case RADEON_HPD_2:
  509. if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
  510. connected = true;
  511. break;
  512. default:
  513. break;
  514. }
  515. return connected;
  516. }
  517. /**
  518. * r100_hpd_set_polarity - hpd set polarity callback.
  519. *
  520. * @rdev: radeon_device pointer
  521. * @hpd: hpd (hotplug detect) pin
  522. *
  523. * Set the polarity of the hpd pin (r1xx-r4xx).
  524. */
  525. void r100_hpd_set_polarity(struct radeon_device *rdev,
  526. enum radeon_hpd_id hpd)
  527. {
  528. u32 tmp;
  529. bool connected = r100_hpd_sense(rdev, hpd);
  530. switch (hpd) {
  531. case RADEON_HPD_1:
  532. tmp = RREG32(RADEON_FP_GEN_CNTL);
  533. if (connected)
  534. tmp &= ~RADEON_FP_DETECT_INT_POL;
  535. else
  536. tmp |= RADEON_FP_DETECT_INT_POL;
  537. WREG32(RADEON_FP_GEN_CNTL, tmp);
  538. break;
  539. case RADEON_HPD_2:
  540. tmp = RREG32(RADEON_FP2_GEN_CNTL);
  541. if (connected)
  542. tmp &= ~RADEON_FP2_DETECT_INT_POL;
  543. else
  544. tmp |= RADEON_FP2_DETECT_INT_POL;
  545. WREG32(RADEON_FP2_GEN_CNTL, tmp);
  546. break;
  547. default:
  548. break;
  549. }
  550. }
  551. /**
  552. * r100_hpd_init - hpd setup callback.
  553. *
  554. * @rdev: radeon_device pointer
  555. *
  556. * Setup the hpd pins used by the card (r1xx-r4xx).
  557. * Set the polarity, and enable the hpd interrupts.
  558. */
  559. void r100_hpd_init(struct radeon_device *rdev)
  560. {
  561. struct drm_device *dev = rdev->ddev;
  562. struct drm_connector *connector;
  563. unsigned enable = 0;
  564. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  565. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  566. if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
  567. enable |= 1 << radeon_connector->hpd.hpd;
  568. radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
  569. }
  570. radeon_irq_kms_enable_hpd(rdev, enable);
  571. }
  572. /**
  573. * r100_hpd_fini - hpd tear down callback.
  574. *
  575. * @rdev: radeon_device pointer
  576. *
  577. * Tear down the hpd pins used by the card (r1xx-r4xx).
  578. * Disable the hpd interrupts.
  579. */
  580. void r100_hpd_fini(struct radeon_device *rdev)
  581. {
  582. struct drm_device *dev = rdev->ddev;
  583. struct drm_connector *connector;
  584. unsigned disable = 0;
  585. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  586. struct radeon_connector *radeon_connector = to_radeon_connector(connector);
  587. if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
  588. disable |= 1 << radeon_connector->hpd.hpd;
  589. }
  590. radeon_irq_kms_disable_hpd(rdev, disable);
  591. }
  592. /*
  593. * PCI GART
  594. */
  595. void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  596. {
  597. /* TODO: can we do somethings here ? */
  598. /* It seems hw only cache one entry so we should discard this
  599. * entry otherwise if first GPU GART read hit this entry it
  600. * could end up in wrong address. */
  601. }
  602. int r100_pci_gart_init(struct radeon_device *rdev)
  603. {
  604. int r;
  605. if (rdev->gart.ptr) {
  606. WARN(1, "R100 PCI GART already initialized\n");
  607. return 0;
  608. }
  609. /* Initialize common gart structure */
  610. r = radeon_gart_init(rdev);
  611. if (r)
  612. return r;
  613. rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  614. rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
  615. rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
  616. rdev->asic->gart.set_page = &r100_pci_gart_set_page;
  617. return radeon_gart_table_ram_alloc(rdev);
  618. }
  619. int r100_pci_gart_enable(struct radeon_device *rdev)
  620. {
  621. uint32_t tmp;
  622. /* discard memory request outside of configured range */
  623. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  624. WREG32(RADEON_AIC_CNTL, tmp);
  625. /* set address range for PCI address translate */
  626. WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
  627. WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
  628. /* set PCI GART page-table base address */
  629. WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
  630. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
  631. WREG32(RADEON_AIC_CNTL, tmp);
  632. r100_pci_gart_tlb_flush(rdev);
  633. DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
  634. (unsigned)(rdev->mc.gtt_size >> 20),
  635. (unsigned long long)rdev->gart.table_addr);
  636. rdev->gart.ready = true;
  637. return 0;
  638. }
  639. void r100_pci_gart_disable(struct radeon_device *rdev)
  640. {
  641. uint32_t tmp;
  642. /* discard memory request outside of configured range */
  643. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  644. WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
  645. WREG32(RADEON_AIC_LO_ADDR, 0);
  646. WREG32(RADEON_AIC_HI_ADDR, 0);
  647. }
  648. uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
  649. {
  650. return addr;
  651. }
  652. void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
  653. uint64_t entry)
  654. {
  655. u32 *gtt = rdev->gart.ptr;
  656. gtt[i] = cpu_to_le32(lower_32_bits(entry));
  657. }
  658. void r100_pci_gart_fini(struct radeon_device *rdev)
  659. {
  660. radeon_gart_fini(rdev);
  661. r100_pci_gart_disable(rdev);
  662. radeon_gart_table_ram_free(rdev);
  663. }
  664. int r100_irq_set(struct radeon_device *rdev)
  665. {
  666. uint32_t tmp = 0;
  667. if (!rdev->irq.installed) {
  668. WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
  669. WREG32(R_000040_GEN_INT_CNTL, 0);
  670. return -EINVAL;
  671. }
  672. if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
  673. tmp |= RADEON_SW_INT_ENABLE;
  674. }
  675. if (rdev->irq.crtc_vblank_int[0] ||
  676. atomic_read(&rdev->irq.pflip[0])) {
  677. tmp |= RADEON_CRTC_VBLANK_MASK;
  678. }
  679. if (rdev->irq.crtc_vblank_int[1] ||
  680. atomic_read(&rdev->irq.pflip[1])) {
  681. tmp |= RADEON_CRTC2_VBLANK_MASK;
  682. }
  683. if (rdev->irq.hpd[0]) {
  684. tmp |= RADEON_FP_DETECT_MASK;
  685. }
  686. if (rdev->irq.hpd[1]) {
  687. tmp |= RADEON_FP2_DETECT_MASK;
  688. }
  689. WREG32(RADEON_GEN_INT_CNTL, tmp);
  690. /* read back to post the write */
  691. RREG32(RADEON_GEN_INT_CNTL);
  692. return 0;
  693. }
  694. void r100_irq_disable(struct radeon_device *rdev)
  695. {
  696. u32 tmp;
  697. WREG32(R_000040_GEN_INT_CNTL, 0);
  698. /* Wait and acknowledge irq */
  699. mdelay(1);
  700. tmp = RREG32(R_000044_GEN_INT_STATUS);
  701. WREG32(R_000044_GEN_INT_STATUS, tmp);
  702. }
  703. static uint32_t r100_irq_ack(struct radeon_device *rdev)
  704. {
  705. uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
  706. uint32_t irq_mask = RADEON_SW_INT_TEST |
  707. RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
  708. RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
  709. if (irqs) {
  710. WREG32(RADEON_GEN_INT_STATUS, irqs);
  711. }
  712. return irqs & irq_mask;
  713. }
  714. int r100_irq_process(struct radeon_device *rdev)
  715. {
  716. uint32_t status, msi_rearm;
  717. bool queue_hotplug = false;
  718. status = r100_irq_ack(rdev);
  719. if (!status) {
  720. return IRQ_NONE;
  721. }
  722. if (rdev->shutdown) {
  723. return IRQ_NONE;
  724. }
  725. while (status) {
  726. /* SW interrupt */
  727. if (status & RADEON_SW_INT_TEST) {
  728. radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
  729. }
  730. /* Vertical blank interrupts */
  731. if (status & RADEON_CRTC_VBLANK_STAT) {
  732. if (rdev->irq.crtc_vblank_int[0]) {
  733. drm_handle_vblank(rdev->ddev, 0);
  734. rdev->pm.vblank_sync = true;
  735. wake_up(&rdev->irq.vblank_queue);
  736. }
  737. if (atomic_read(&rdev->irq.pflip[0]))
  738. radeon_crtc_handle_vblank(rdev, 0);
  739. }
  740. if (status & RADEON_CRTC2_VBLANK_STAT) {
  741. if (rdev->irq.crtc_vblank_int[1]) {
  742. drm_handle_vblank(rdev->ddev, 1);
  743. rdev->pm.vblank_sync = true;
  744. wake_up(&rdev->irq.vblank_queue);
  745. }
  746. if (atomic_read(&rdev->irq.pflip[1]))
  747. radeon_crtc_handle_vblank(rdev, 1);
  748. }
  749. if (status & RADEON_FP_DETECT_STAT) {
  750. queue_hotplug = true;
  751. DRM_DEBUG("HPD1\n");
  752. }
  753. if (status & RADEON_FP2_DETECT_STAT) {
  754. queue_hotplug = true;
  755. DRM_DEBUG("HPD2\n");
  756. }
  757. status = r100_irq_ack(rdev);
  758. }
  759. if (queue_hotplug)
  760. schedule_delayed_work(&rdev->hotplug_work, 0);
  761. if (rdev->msi_enabled) {
  762. switch (rdev->family) {
  763. case CHIP_RS400:
  764. case CHIP_RS480:
  765. msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
  766. WREG32(RADEON_AIC_CNTL, msi_rearm);
  767. WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
  768. break;
  769. default:
  770. WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
  771. break;
  772. }
  773. }
  774. return IRQ_HANDLED;
  775. }
  776. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
  777. {
  778. if (crtc == 0)
  779. return RREG32(RADEON_CRTC_CRNT_FRAME);
  780. else
  781. return RREG32(RADEON_CRTC2_CRNT_FRAME);
  782. }
  783. /**
  784. * r100_ring_hdp_flush - flush Host Data Path via the ring buffer
  785. * @rdev: radeon device structure
  786. * @ring: ring buffer struct for emitting packets
  787. */
  788. static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
  789. {
  790. radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
  791. radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
  792. RADEON_HDP_READ_BUFFER_INVALIDATE);
  793. radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
  794. radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
  795. }
  796. /* Who ever call radeon_fence_emit should call ring_lock and ask
  797. * for enough space (today caller are ib schedule and buffer move) */
  798. void r100_fence_ring_emit(struct radeon_device *rdev,
  799. struct radeon_fence *fence)
  800. {
  801. struct radeon_ring *ring = &rdev->ring[fence->ring];
  802. /* We have to make sure that caches are flushed before
  803. * CPU might read something from VRAM. */
  804. radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
  805. radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
  806. radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
  807. radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
  808. /* Wait until IDLE & CLEAN */
  809. radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
  810. radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
  811. r100_ring_hdp_flush(rdev, ring);
  812. /* Emit fence sequence & fire IRQ */
  813. radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
  814. radeon_ring_write(ring, fence->seq);
  815. radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
  816. radeon_ring_write(ring, RADEON_SW_INT_FIRE);
  817. }
  818. bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  819. struct radeon_ring *ring,
  820. struct radeon_semaphore *semaphore,
  821. bool emit_wait)
  822. {
  823. /* Unused on older asics, since we don't have semaphores or multiple rings */
  824. BUG();
  825. return false;
  826. }
  827. struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
  828. uint64_t src_offset,
  829. uint64_t dst_offset,
  830. unsigned num_gpu_pages,
  831. struct dma_resv *resv)
  832. {
  833. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  834. struct radeon_fence *fence;
  835. uint32_t cur_pages;
  836. uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
  837. uint32_t pitch;
  838. uint32_t stride_pixels;
  839. unsigned ndw;
  840. int num_loops;
  841. int r = 0;
  842. /* radeon limited to 16k stride */
  843. stride_bytes &= 0x3fff;
  844. /* radeon pitch is /64 */
  845. pitch = stride_bytes / 64;
  846. stride_pixels = stride_bytes / 4;
  847. num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
  848. /* Ask for enough room for blit + flush + fence */
  849. ndw = 64 + (10 * num_loops);
  850. r = radeon_ring_lock(rdev, ring, ndw);
  851. if (r) {
  852. DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
  853. return ERR_PTR(-EINVAL);
  854. }
  855. while (num_gpu_pages > 0) {
  856. cur_pages = num_gpu_pages;
  857. if (cur_pages > 8191) {
  858. cur_pages = 8191;
  859. }
  860. num_gpu_pages -= cur_pages;
  861. /* pages are in Y direction - height
  862. page width in X direction - width */
  863. radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
  864. radeon_ring_write(ring,
  865. RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
  866. RADEON_GMC_DST_PITCH_OFFSET_CNTL |
  867. RADEON_GMC_SRC_CLIPPING |
  868. RADEON_GMC_DST_CLIPPING |
  869. RADEON_GMC_BRUSH_NONE |
  870. (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
  871. RADEON_GMC_SRC_DATATYPE_COLOR |
  872. RADEON_ROP3_S |
  873. RADEON_DP_SRC_SOURCE_MEMORY |
  874. RADEON_GMC_CLR_CMP_CNTL_DIS |
  875. RADEON_GMC_WR_MSK_DIS);
  876. radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
  877. radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
  878. radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
  879. radeon_ring_write(ring, 0);
  880. radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
  881. radeon_ring_write(ring, num_gpu_pages);
  882. radeon_ring_write(ring, num_gpu_pages);
  883. radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
  884. }
  885. radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
  886. radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
  887. radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
  888. radeon_ring_write(ring,
  889. RADEON_WAIT_2D_IDLECLEAN |
  890. RADEON_WAIT_HOST_IDLECLEAN |
  891. RADEON_WAIT_DMA_GUI_IDLE);
  892. r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
  893. if (r) {
  894. radeon_ring_unlock_undo(rdev, ring);
  895. return ERR_PTR(r);
  896. }
  897. radeon_ring_unlock_commit(rdev, ring, false);
  898. return fence;
  899. }
  900. static int r100_cp_wait_for_idle(struct radeon_device *rdev)
  901. {
  902. unsigned i;
  903. u32 tmp;
  904. for (i = 0; i < rdev->usec_timeout; i++) {
  905. tmp = RREG32(R_000E40_RBBM_STATUS);
  906. if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
  907. return 0;
  908. }
  909. udelay(1);
  910. }
  911. return -1;
  912. }
  913. void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
  914. {
  915. int r;
  916. r = radeon_ring_lock(rdev, ring, 2);
  917. if (r) {
  918. return;
  919. }
  920. radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
  921. radeon_ring_write(ring,
  922. RADEON_ISYNC_ANY2D_IDLE3D |
  923. RADEON_ISYNC_ANY3D_IDLE2D |
  924. RADEON_ISYNC_WAIT_IDLEGUI |
  925. RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  926. radeon_ring_unlock_commit(rdev, ring, false);
  927. }
  928. /* Load the microcode for the CP */
  929. static int r100_cp_init_microcode(struct radeon_device *rdev)
  930. {
  931. const char *fw_name = NULL;
  932. int err;
  933. DRM_DEBUG_KMS("\n");
  934. if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
  935. (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
  936. (rdev->family == CHIP_RS200)) {
  937. DRM_INFO("Loading R100 Microcode\n");
  938. fw_name = FIRMWARE_R100;
  939. } else if ((rdev->family == CHIP_R200) ||
  940. (rdev->family == CHIP_RV250) ||
  941. (rdev->family == CHIP_RV280) ||
  942. (rdev->family == CHIP_RS300)) {
  943. DRM_INFO("Loading R200 Microcode\n");
  944. fw_name = FIRMWARE_R200;
  945. } else if ((rdev->family == CHIP_R300) ||
  946. (rdev->family == CHIP_R350) ||
  947. (rdev->family == CHIP_RV350) ||
  948. (rdev->family == CHIP_RV380) ||
  949. (rdev->family == CHIP_RS400) ||
  950. (rdev->family == CHIP_RS480)) {
  951. DRM_INFO("Loading R300 Microcode\n");
  952. fw_name = FIRMWARE_R300;
  953. } else if ((rdev->family == CHIP_R420) ||
  954. (rdev->family == CHIP_R423) ||
  955. (rdev->family == CHIP_RV410)) {
  956. DRM_INFO("Loading R400 Microcode\n");
  957. fw_name = FIRMWARE_R420;
  958. } else if ((rdev->family == CHIP_RS690) ||
  959. (rdev->family == CHIP_RS740)) {
  960. DRM_INFO("Loading RS690/RS740 Microcode\n");
  961. fw_name = FIRMWARE_RS690;
  962. } else if (rdev->family == CHIP_RS600) {
  963. DRM_INFO("Loading RS600 Microcode\n");
  964. fw_name = FIRMWARE_RS600;
  965. } else if ((rdev->family == CHIP_RV515) ||
  966. (rdev->family == CHIP_R520) ||
  967. (rdev->family == CHIP_RV530) ||
  968. (rdev->family == CHIP_R580) ||
  969. (rdev->family == CHIP_RV560) ||
  970. (rdev->family == CHIP_RV570)) {
  971. DRM_INFO("Loading R500 Microcode\n");
  972. fw_name = FIRMWARE_R520;
  973. }
  974. err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
  975. if (err) {
  976. pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name);
  977. } else if (rdev->me_fw->size % 8) {
  978. pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",
  979. rdev->me_fw->size, fw_name);
  980. err = -EINVAL;
  981. release_firmware(rdev->me_fw);
  982. rdev->me_fw = NULL;
  983. }
  984. return err;
  985. }
  986. u32 r100_gfx_get_rptr(struct radeon_device *rdev,
  987. struct radeon_ring *ring)
  988. {
  989. u32 rptr;
  990. if (rdev->wb.enabled)
  991. rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
  992. else
  993. rptr = RREG32(RADEON_CP_RB_RPTR);
  994. return rptr;
  995. }
  996. u32 r100_gfx_get_wptr(struct radeon_device *rdev,
  997. struct radeon_ring *ring)
  998. {
  999. return RREG32(RADEON_CP_RB_WPTR);
  1000. }
  1001. void r100_gfx_set_wptr(struct radeon_device *rdev,
  1002. struct radeon_ring *ring)
  1003. {
  1004. WREG32(RADEON_CP_RB_WPTR, ring->wptr);
  1005. (void)RREG32(RADEON_CP_RB_WPTR);
  1006. }
  1007. static void r100_cp_load_microcode(struct radeon_device *rdev)
  1008. {
  1009. const __be32 *fw_data;
  1010. int i, size;
  1011. if (r100_gui_wait_for_idle(rdev)) {
  1012. pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
  1013. }
  1014. if (rdev->me_fw) {
  1015. size = rdev->me_fw->size / 4;
  1016. fw_data = (const __be32 *)&rdev->me_fw->data[0];
  1017. WREG32(RADEON_CP_ME_RAM_ADDR, 0);
  1018. for (i = 0; i < size; i += 2) {
  1019. WREG32(RADEON_CP_ME_RAM_DATAH,
  1020. be32_to_cpup(&fw_data[i]));
  1021. WREG32(RADEON_CP_ME_RAM_DATAL,
  1022. be32_to_cpup(&fw_data[i + 1]));
  1023. }
  1024. }
  1025. }
  1026. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
  1027. {
  1028. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  1029. unsigned rb_bufsz;
  1030. unsigned rb_blksz;
  1031. unsigned max_fetch;
  1032. unsigned pre_write_timer;
  1033. unsigned pre_write_limit;
  1034. unsigned indirect2_start;
  1035. unsigned indirect1_start;
  1036. uint32_t tmp;
  1037. int r;
  1038. r100_debugfs_cp_init(rdev);
  1039. if (!rdev->me_fw) {
  1040. r = r100_cp_init_microcode(rdev);
  1041. if (r) {
  1042. DRM_ERROR("Failed to load firmware!\n");
  1043. return r;
  1044. }
  1045. }
  1046. /* Align ring size */
  1047. rb_bufsz = order_base_2(ring_size / 8);
  1048. ring_size = (1 << (rb_bufsz + 1)) * 4;
  1049. r100_cp_load_microcode(rdev);
  1050. r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
  1051. RADEON_CP_PACKET2);
  1052. if (r) {
  1053. return r;
  1054. }
  1055. /* Each time the cp read 1024 bytes (16 dword/quadword) update
  1056. * the rptr copy in system ram */
  1057. rb_blksz = 9;
  1058. /* cp will read 128bytes at a time (4 dwords) */
  1059. max_fetch = 1;
  1060. ring->align_mask = 16 - 1;
  1061. /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
  1062. pre_write_timer = 64;
  1063. /* Force CP_RB_WPTR write if written more than one time before the
  1064. * delay expire
  1065. */
  1066. pre_write_limit = 0;
  1067. /* Setup the cp cache like this (cache size is 96 dwords) :
  1068. * RING 0 to 15
  1069. * INDIRECT1 16 to 79
  1070. * INDIRECT2 80 to 95
  1071. * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
  1072. * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
  1073. * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
  1074. * Idea being that most of the gpu cmd will be through indirect1 buffer
  1075. * so it gets the bigger cache.
  1076. */
  1077. indirect2_start = 80;
  1078. indirect1_start = 16;
  1079. /* cp setup */
  1080. WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
  1081. tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
  1082. REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
  1083. REG_SET(RADEON_MAX_FETCH, max_fetch));
  1084. #ifdef __BIG_ENDIAN
  1085. tmp |= RADEON_BUF_SWAP_32BIT;
  1086. #endif
  1087. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
  1088. /* Set ring address */
  1089. DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
  1090. WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
  1091. /* Force read & write ptr to 0 */
  1092. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
  1093. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  1094. ring->wptr = 0;
  1095. WREG32(RADEON_CP_RB_WPTR, ring->wptr);
  1096. /* set the wb address whether it's enabled or not */
  1097. WREG32(R_00070C_CP_RB_RPTR_ADDR,
  1098. S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
  1099. WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
  1100. if (rdev->wb.enabled)
  1101. WREG32(R_000770_SCRATCH_UMSK, 0xff);
  1102. else {
  1103. tmp |= RADEON_RB_NO_UPDATE;
  1104. WREG32(R_000770_SCRATCH_UMSK, 0);
  1105. }
  1106. WREG32(RADEON_CP_RB_CNTL, tmp);
  1107. udelay(10);
  1108. /* Set cp mode to bus mastering & enable cp*/
  1109. WREG32(RADEON_CP_CSQ_MODE,
  1110. REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
  1111. REG_SET(RADEON_INDIRECT1_START, indirect1_start));
  1112. WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
  1113. WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
  1114. WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
  1115. /* at this point everything should be setup correctly to enable master */
  1116. pci_set_master(rdev->pdev);
  1117. radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
  1118. r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
  1119. if (r) {
  1120. DRM_ERROR("radeon: cp isn't working (%d).\n", r);
  1121. return r;
  1122. }
  1123. ring->ready = true;
  1124. radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
  1125. if (!ring->rptr_save_reg /* not resuming from suspend */
  1126. && radeon_ring_supports_scratch_reg(rdev, ring)) {
  1127. r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
  1128. if (r) {
  1129. DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
  1130. ring->rptr_save_reg = 0;
  1131. }
  1132. }
  1133. return 0;
  1134. }
  1135. void r100_cp_fini(struct radeon_device *rdev)
  1136. {
  1137. if (r100_cp_wait_for_idle(rdev)) {
  1138. DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
  1139. }
  1140. /* Disable ring */
  1141. r100_cp_disable(rdev);
  1142. radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
  1143. radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
  1144. DRM_INFO("radeon: cp finalized\n");
  1145. }
  1146. void r100_cp_disable(struct radeon_device *rdev)
  1147. {
  1148. /* Disable ring */
  1149. radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
  1150. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  1151. WREG32(RADEON_CP_CSQ_MODE, 0);
  1152. WREG32(RADEON_CP_CSQ_CNTL, 0);
  1153. WREG32(R_000770_SCRATCH_UMSK, 0);
  1154. if (r100_gui_wait_for_idle(rdev)) {
  1155. pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n");
  1156. }
  1157. }
  1158. /*
  1159. * CS functions
  1160. */
  1161. int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
  1162. struct radeon_cs_packet *pkt,
  1163. unsigned idx,
  1164. unsigned reg)
  1165. {
  1166. int r;
  1167. u32 tile_flags = 0;
  1168. u32 tmp;
  1169. struct radeon_bo_list *reloc;
  1170. u32 value;
  1171. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1172. if (r) {
  1173. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1174. idx, reg);
  1175. radeon_cs_dump_packet(p, pkt);
  1176. return r;
  1177. }
  1178. value = radeon_get_ib_value(p, idx);
  1179. tmp = value & 0x003fffff;
  1180. tmp += (((u32)reloc->gpu_offset) >> 10);
  1181. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1182. if (reloc->tiling_flags & RADEON_TILING_MACRO)
  1183. tile_flags |= RADEON_DST_TILE_MACRO;
  1184. if (reloc->tiling_flags & RADEON_TILING_MICRO) {
  1185. if (reg == RADEON_SRC_PITCH_OFFSET) {
  1186. DRM_ERROR("Cannot src blit from microtiled surface\n");
  1187. radeon_cs_dump_packet(p, pkt);
  1188. return -EINVAL;
  1189. }
  1190. tile_flags |= RADEON_DST_TILE_MICRO;
  1191. }
  1192. tmp |= tile_flags;
  1193. p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
  1194. } else
  1195. p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
  1196. return 0;
  1197. }
  1198. int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
  1199. struct radeon_cs_packet *pkt,
  1200. int idx)
  1201. {
  1202. unsigned c, i;
  1203. struct radeon_bo_list *reloc;
  1204. struct r100_cs_track *track;
  1205. int r = 0;
  1206. volatile uint32_t *ib;
  1207. u32 idx_value;
  1208. ib = p->ib.ptr;
  1209. track = (struct r100_cs_track *)p->track;
  1210. c = radeon_get_ib_value(p, idx++) & 0x1F;
  1211. if (c > 16) {
  1212. DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
  1213. pkt->opcode);
  1214. radeon_cs_dump_packet(p, pkt);
  1215. return -EINVAL;
  1216. }
  1217. track->num_arrays = c;
  1218. for (i = 0; i < (c - 1); i+=2, idx+=3) {
  1219. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1220. if (r) {
  1221. DRM_ERROR("No reloc for packet3 %d\n",
  1222. pkt->opcode);
  1223. radeon_cs_dump_packet(p, pkt);
  1224. return r;
  1225. }
  1226. idx_value = radeon_get_ib_value(p, idx);
  1227. ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
  1228. track->arrays[i + 0].esize = idx_value >> 8;
  1229. track->arrays[i + 0].robj = reloc->robj;
  1230. track->arrays[i + 0].esize &= 0x7F;
  1231. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1232. if (r) {
  1233. DRM_ERROR("No reloc for packet3 %d\n",
  1234. pkt->opcode);
  1235. radeon_cs_dump_packet(p, pkt);
  1236. return r;
  1237. }
  1238. ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
  1239. track->arrays[i + 1].robj = reloc->robj;
  1240. track->arrays[i + 1].esize = idx_value >> 24;
  1241. track->arrays[i + 1].esize &= 0x7F;
  1242. }
  1243. if (c & 1) {
  1244. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1245. if (r) {
  1246. DRM_ERROR("No reloc for packet3 %d\n",
  1247. pkt->opcode);
  1248. radeon_cs_dump_packet(p, pkt);
  1249. return r;
  1250. }
  1251. idx_value = radeon_get_ib_value(p, idx);
  1252. ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
  1253. track->arrays[i + 0].robj = reloc->robj;
  1254. track->arrays[i + 0].esize = idx_value >> 8;
  1255. track->arrays[i + 0].esize &= 0x7F;
  1256. }
  1257. return r;
  1258. }
  1259. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  1260. struct radeon_cs_packet *pkt,
  1261. const unsigned *auth, unsigned n,
  1262. radeon_packet0_check_t check)
  1263. {
  1264. unsigned reg;
  1265. unsigned i, j, m;
  1266. unsigned idx;
  1267. int r;
  1268. idx = pkt->idx + 1;
  1269. reg = pkt->reg;
  1270. /* Check that register fall into register range
  1271. * determined by the number of entry (n) in the
  1272. * safe register bitmap.
  1273. */
  1274. if (pkt->one_reg_wr) {
  1275. if ((reg >> 7) > n) {
  1276. return -EINVAL;
  1277. }
  1278. } else {
  1279. if (((reg + (pkt->count << 2)) >> 7) > n) {
  1280. return -EINVAL;
  1281. }
  1282. }
  1283. for (i = 0; i <= pkt->count; i++, idx++) {
  1284. j = (reg >> 7);
  1285. m = 1 << ((reg >> 2) & 31);
  1286. if (auth[j] & m) {
  1287. r = check(p, pkt, idx, reg);
  1288. if (r) {
  1289. return r;
  1290. }
  1291. }
  1292. if (pkt->one_reg_wr) {
  1293. if (!(auth[j] & m)) {
  1294. break;
  1295. }
  1296. } else {
  1297. reg += 4;
  1298. }
  1299. }
  1300. return 0;
  1301. }
  1302. /**
  1303. * r100_cs_packet_parse_vline() - parse userspace VLINE packet
  1304. * @p: parser structure holding parsing context.
  1305. *
  1306. * Userspace sends a special sequence for VLINE waits.
  1307. * PACKET0 - VLINE_START_END + value
  1308. * PACKET0 - WAIT_UNTIL +_value
  1309. * RELOC (P3) - crtc_id in reloc.
  1310. *
  1311. * This function parses this and relocates the VLINE START END
  1312. * and WAIT UNTIL packets to the correct crtc.
  1313. * It also detects a switched off crtc and nulls out the
  1314. * wait in that case.
  1315. */
  1316. int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
  1317. {
  1318. struct drm_crtc *crtc;
  1319. struct radeon_crtc *radeon_crtc;
  1320. struct radeon_cs_packet p3reloc, waitreloc;
  1321. int crtc_id;
  1322. int r;
  1323. uint32_t header, h_idx, reg;
  1324. volatile uint32_t *ib;
  1325. ib = p->ib.ptr;
  1326. /* parse the wait until */
  1327. r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
  1328. if (r)
  1329. return r;
  1330. /* check its a wait until and only 1 count */
  1331. if (waitreloc.reg != RADEON_WAIT_UNTIL ||
  1332. waitreloc.count != 0) {
  1333. DRM_ERROR("vline wait had illegal wait until segment\n");
  1334. return -EINVAL;
  1335. }
  1336. if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
  1337. DRM_ERROR("vline wait had illegal wait until\n");
  1338. return -EINVAL;
  1339. }
  1340. /* jump over the NOP */
  1341. r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
  1342. if (r)
  1343. return r;
  1344. h_idx = p->idx - 2;
  1345. p->idx += waitreloc.count + 2;
  1346. p->idx += p3reloc.count + 2;
  1347. header = radeon_get_ib_value(p, h_idx);
  1348. crtc_id = radeon_get_ib_value(p, h_idx + 5);
  1349. reg = R100_CP_PACKET0_GET_REG(header);
  1350. crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
  1351. if (!crtc) {
  1352. DRM_ERROR("cannot find crtc %d\n", crtc_id);
  1353. return -ENOENT;
  1354. }
  1355. radeon_crtc = to_radeon_crtc(crtc);
  1356. crtc_id = radeon_crtc->crtc_id;
  1357. if (!crtc->enabled) {
  1358. /* if the CRTC isn't enabled - we need to nop out the wait until */
  1359. ib[h_idx + 2] = PACKET2(0);
  1360. ib[h_idx + 3] = PACKET2(0);
  1361. } else if (crtc_id == 1) {
  1362. switch (reg) {
  1363. case AVIVO_D1MODE_VLINE_START_END:
  1364. header &= ~R300_CP_PACKET0_REG_MASK;
  1365. header |= AVIVO_D2MODE_VLINE_START_END >> 2;
  1366. break;
  1367. case RADEON_CRTC_GUI_TRIG_VLINE:
  1368. header &= ~R300_CP_PACKET0_REG_MASK;
  1369. header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
  1370. break;
  1371. default:
  1372. DRM_ERROR("unknown crtc reloc\n");
  1373. return -EINVAL;
  1374. }
  1375. ib[h_idx] = header;
  1376. ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
  1377. }
  1378. return 0;
  1379. }
  1380. static int r100_get_vtx_size(uint32_t vtx_fmt)
  1381. {
  1382. int vtx_size;
  1383. vtx_size = 2;
  1384. /* ordered according to bits in spec */
  1385. if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
  1386. vtx_size++;
  1387. if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
  1388. vtx_size += 3;
  1389. if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
  1390. vtx_size++;
  1391. if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
  1392. vtx_size++;
  1393. if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
  1394. vtx_size += 3;
  1395. if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
  1396. vtx_size++;
  1397. if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
  1398. vtx_size++;
  1399. if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
  1400. vtx_size += 2;
  1401. if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
  1402. vtx_size += 2;
  1403. if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
  1404. vtx_size++;
  1405. if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
  1406. vtx_size += 2;
  1407. if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
  1408. vtx_size++;
  1409. if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
  1410. vtx_size += 2;
  1411. if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
  1412. vtx_size++;
  1413. if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
  1414. vtx_size++;
  1415. /* blend weight */
  1416. if (vtx_fmt & (0x7 << 15))
  1417. vtx_size += (vtx_fmt >> 15) & 0x7;
  1418. if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
  1419. vtx_size += 3;
  1420. if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
  1421. vtx_size += 2;
  1422. if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
  1423. vtx_size++;
  1424. if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
  1425. vtx_size++;
  1426. if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
  1427. vtx_size++;
  1428. if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
  1429. vtx_size++;
  1430. return vtx_size;
  1431. }
  1432. static int r100_packet0_check(struct radeon_cs_parser *p,
  1433. struct radeon_cs_packet *pkt,
  1434. unsigned idx, unsigned reg)
  1435. {
  1436. struct radeon_bo_list *reloc;
  1437. struct r100_cs_track *track;
  1438. volatile uint32_t *ib;
  1439. uint32_t tmp;
  1440. int r;
  1441. int i, face;
  1442. u32 tile_flags = 0;
  1443. u32 idx_value;
  1444. ib = p->ib.ptr;
  1445. track = (struct r100_cs_track *)p->track;
  1446. idx_value = radeon_get_ib_value(p, idx);
  1447. switch (reg) {
  1448. case RADEON_CRTC_GUI_TRIG_VLINE:
  1449. r = r100_cs_packet_parse_vline(p);
  1450. if (r) {
  1451. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1452. idx, reg);
  1453. radeon_cs_dump_packet(p, pkt);
  1454. return r;
  1455. }
  1456. break;
  1457. /* FIXME: only allow PACKET3 blit? easier to check for out of
  1458. * range access */
  1459. case RADEON_DST_PITCH_OFFSET:
  1460. case RADEON_SRC_PITCH_OFFSET:
  1461. r = r100_reloc_pitch_offset(p, pkt, idx, reg);
  1462. if (r)
  1463. return r;
  1464. break;
  1465. case RADEON_RB3D_DEPTHOFFSET:
  1466. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1467. if (r) {
  1468. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1469. idx, reg);
  1470. radeon_cs_dump_packet(p, pkt);
  1471. return r;
  1472. }
  1473. track->zb.robj = reloc->robj;
  1474. track->zb.offset = idx_value;
  1475. track->zb_dirty = true;
  1476. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1477. break;
  1478. case RADEON_RB3D_COLOROFFSET:
  1479. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1480. if (r) {
  1481. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1482. idx, reg);
  1483. radeon_cs_dump_packet(p, pkt);
  1484. return r;
  1485. }
  1486. track->cb[0].robj = reloc->robj;
  1487. track->cb[0].offset = idx_value;
  1488. track->cb_dirty = true;
  1489. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1490. break;
  1491. case RADEON_PP_TXOFFSET_0:
  1492. case RADEON_PP_TXOFFSET_1:
  1493. case RADEON_PP_TXOFFSET_2:
  1494. i = (reg - RADEON_PP_TXOFFSET_0) / 24;
  1495. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1496. if (r) {
  1497. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1498. idx, reg);
  1499. radeon_cs_dump_packet(p, pkt);
  1500. return r;
  1501. }
  1502. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1503. if (reloc->tiling_flags & RADEON_TILING_MACRO)
  1504. tile_flags |= RADEON_TXO_MACRO_TILE;
  1505. if (reloc->tiling_flags & RADEON_TILING_MICRO)
  1506. tile_flags |= RADEON_TXO_MICRO_TILE_X2;
  1507. tmp = idx_value & ~(0x7 << 2);
  1508. tmp |= tile_flags;
  1509. ib[idx] = tmp + ((u32)reloc->gpu_offset);
  1510. } else
  1511. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1512. track->textures[i].robj = reloc->robj;
  1513. track->tex_dirty = true;
  1514. break;
  1515. case RADEON_PP_CUBIC_OFFSET_T0_0:
  1516. case RADEON_PP_CUBIC_OFFSET_T0_1:
  1517. case RADEON_PP_CUBIC_OFFSET_T0_2:
  1518. case RADEON_PP_CUBIC_OFFSET_T0_3:
  1519. case RADEON_PP_CUBIC_OFFSET_T0_4:
  1520. i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
  1521. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1522. if (r) {
  1523. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1524. idx, reg);
  1525. radeon_cs_dump_packet(p, pkt);
  1526. return r;
  1527. }
  1528. track->textures[0].cube_info[i].offset = idx_value;
  1529. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1530. track->textures[0].cube_info[i].robj = reloc->robj;
  1531. track->tex_dirty = true;
  1532. break;
  1533. case RADEON_PP_CUBIC_OFFSET_T1_0:
  1534. case RADEON_PP_CUBIC_OFFSET_T1_1:
  1535. case RADEON_PP_CUBIC_OFFSET_T1_2:
  1536. case RADEON_PP_CUBIC_OFFSET_T1_3:
  1537. case RADEON_PP_CUBIC_OFFSET_T1_4:
  1538. i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
  1539. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1540. if (r) {
  1541. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1542. idx, reg);
  1543. radeon_cs_dump_packet(p, pkt);
  1544. return r;
  1545. }
  1546. track->textures[1].cube_info[i].offset = idx_value;
  1547. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1548. track->textures[1].cube_info[i].robj = reloc->robj;
  1549. track->tex_dirty = true;
  1550. break;
  1551. case RADEON_PP_CUBIC_OFFSET_T2_0:
  1552. case RADEON_PP_CUBIC_OFFSET_T2_1:
  1553. case RADEON_PP_CUBIC_OFFSET_T2_2:
  1554. case RADEON_PP_CUBIC_OFFSET_T2_3:
  1555. case RADEON_PP_CUBIC_OFFSET_T2_4:
  1556. i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
  1557. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1558. if (r) {
  1559. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1560. idx, reg);
  1561. radeon_cs_dump_packet(p, pkt);
  1562. return r;
  1563. }
  1564. track->textures[2].cube_info[i].offset = idx_value;
  1565. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1566. track->textures[2].cube_info[i].robj = reloc->robj;
  1567. track->tex_dirty = true;
  1568. break;
  1569. case RADEON_RE_WIDTH_HEIGHT:
  1570. track->maxy = ((idx_value >> 16) & 0x7FF);
  1571. track->cb_dirty = true;
  1572. track->zb_dirty = true;
  1573. break;
  1574. case RADEON_RB3D_COLORPITCH:
  1575. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1576. if (r) {
  1577. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1578. idx, reg);
  1579. radeon_cs_dump_packet(p, pkt);
  1580. return r;
  1581. }
  1582. if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
  1583. if (reloc->tiling_flags & RADEON_TILING_MACRO)
  1584. tile_flags |= RADEON_COLOR_TILE_ENABLE;
  1585. if (reloc->tiling_flags & RADEON_TILING_MICRO)
  1586. tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
  1587. tmp = idx_value & ~(0x7 << 16);
  1588. tmp |= tile_flags;
  1589. ib[idx] = tmp;
  1590. } else
  1591. ib[idx] = idx_value;
  1592. track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
  1593. track->cb_dirty = true;
  1594. break;
  1595. case RADEON_RB3D_DEPTHPITCH:
  1596. track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
  1597. track->zb_dirty = true;
  1598. break;
  1599. case RADEON_RB3D_CNTL:
  1600. switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
  1601. case 7:
  1602. case 8:
  1603. case 9:
  1604. case 11:
  1605. case 12:
  1606. track->cb[0].cpp = 1;
  1607. break;
  1608. case 3:
  1609. case 4:
  1610. case 15:
  1611. track->cb[0].cpp = 2;
  1612. break;
  1613. case 6:
  1614. track->cb[0].cpp = 4;
  1615. break;
  1616. default:
  1617. DRM_ERROR("Invalid color buffer format (%d) !\n",
  1618. ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
  1619. return -EINVAL;
  1620. }
  1621. track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
  1622. track->cb_dirty = true;
  1623. track->zb_dirty = true;
  1624. break;
  1625. case RADEON_RB3D_ZSTENCILCNTL:
  1626. switch (idx_value & 0xf) {
  1627. case 0:
  1628. track->zb.cpp = 2;
  1629. break;
  1630. case 2:
  1631. case 3:
  1632. case 4:
  1633. case 5:
  1634. case 9:
  1635. case 11:
  1636. track->zb.cpp = 4;
  1637. break;
  1638. default:
  1639. break;
  1640. }
  1641. track->zb_dirty = true;
  1642. break;
  1643. case RADEON_RB3D_ZPASS_ADDR:
  1644. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1645. if (r) {
  1646. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1647. idx, reg);
  1648. radeon_cs_dump_packet(p, pkt);
  1649. return r;
  1650. }
  1651. ib[idx] = idx_value + ((u32)reloc->gpu_offset);
  1652. break;
  1653. case RADEON_PP_CNTL:
  1654. {
  1655. uint32_t temp = idx_value >> 4;
  1656. for (i = 0; i < track->num_texture; i++)
  1657. track->textures[i].enabled = !!(temp & (1 << i));
  1658. track->tex_dirty = true;
  1659. }
  1660. break;
  1661. case RADEON_SE_VF_CNTL:
  1662. track->vap_vf_cntl = idx_value;
  1663. break;
  1664. case RADEON_SE_VTX_FMT:
  1665. track->vtx_size = r100_get_vtx_size(idx_value);
  1666. break;
  1667. case RADEON_PP_TEX_SIZE_0:
  1668. case RADEON_PP_TEX_SIZE_1:
  1669. case RADEON_PP_TEX_SIZE_2:
  1670. i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
  1671. track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
  1672. track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
  1673. track->tex_dirty = true;
  1674. break;
  1675. case RADEON_PP_TEX_PITCH_0:
  1676. case RADEON_PP_TEX_PITCH_1:
  1677. case RADEON_PP_TEX_PITCH_2:
  1678. i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
  1679. track->textures[i].pitch = idx_value + 32;
  1680. track->tex_dirty = true;
  1681. break;
  1682. case RADEON_PP_TXFILTER_0:
  1683. case RADEON_PP_TXFILTER_1:
  1684. case RADEON_PP_TXFILTER_2:
  1685. i = (reg - RADEON_PP_TXFILTER_0) / 24;
  1686. track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
  1687. >> RADEON_MAX_MIP_LEVEL_SHIFT);
  1688. tmp = (idx_value >> 23) & 0x7;
  1689. if (tmp == 2 || tmp == 6)
  1690. track->textures[i].roundup_w = false;
  1691. tmp = (idx_value >> 27) & 0x7;
  1692. if (tmp == 2 || tmp == 6)
  1693. track->textures[i].roundup_h = false;
  1694. track->tex_dirty = true;
  1695. break;
  1696. case RADEON_PP_TXFORMAT_0:
  1697. case RADEON_PP_TXFORMAT_1:
  1698. case RADEON_PP_TXFORMAT_2:
  1699. i = (reg - RADEON_PP_TXFORMAT_0) / 24;
  1700. if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
  1701. track->textures[i].use_pitch = true;
  1702. } else {
  1703. track->textures[i].use_pitch = false;
  1704. track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
  1705. track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
  1706. }
  1707. if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
  1708. track->textures[i].tex_coord_type = 2;
  1709. switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
  1710. case RADEON_TXFORMAT_I8:
  1711. case RADEON_TXFORMAT_RGB332:
  1712. case RADEON_TXFORMAT_Y8:
  1713. track->textures[i].cpp = 1;
  1714. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  1715. break;
  1716. case RADEON_TXFORMAT_AI88:
  1717. case RADEON_TXFORMAT_ARGB1555:
  1718. case RADEON_TXFORMAT_RGB565:
  1719. case RADEON_TXFORMAT_ARGB4444:
  1720. case RADEON_TXFORMAT_VYUY422:
  1721. case RADEON_TXFORMAT_YVYU422:
  1722. case RADEON_TXFORMAT_SHADOW16:
  1723. case RADEON_TXFORMAT_LDUDV655:
  1724. case RADEON_TXFORMAT_DUDV88:
  1725. track->textures[i].cpp = 2;
  1726. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  1727. break;
  1728. case RADEON_TXFORMAT_ARGB8888:
  1729. case RADEON_TXFORMAT_RGBA8888:
  1730. case RADEON_TXFORMAT_SHADOW32:
  1731. case RADEON_TXFORMAT_LDUDUV8888:
  1732. track->textures[i].cpp = 4;
  1733. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  1734. break;
  1735. case RADEON_TXFORMAT_DXT1:
  1736. track->textures[i].cpp = 1;
  1737. track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
  1738. break;
  1739. case RADEON_TXFORMAT_DXT23:
  1740. case RADEON_TXFORMAT_DXT45:
  1741. track->textures[i].cpp = 1;
  1742. track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
  1743. break;
  1744. }
  1745. track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
  1746. track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
  1747. track->tex_dirty = true;
  1748. break;
  1749. case RADEON_PP_CUBIC_FACES_0:
  1750. case RADEON_PP_CUBIC_FACES_1:
  1751. case RADEON_PP_CUBIC_FACES_2:
  1752. tmp = idx_value;
  1753. i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
  1754. for (face = 0; face < 4; face++) {
  1755. track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
  1756. track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
  1757. }
  1758. track->tex_dirty = true;
  1759. break;
  1760. default:
  1761. pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);
  1762. return -EINVAL;
  1763. }
  1764. return 0;
  1765. }
  1766. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1767. struct radeon_cs_packet *pkt,
  1768. struct radeon_bo *robj)
  1769. {
  1770. unsigned idx;
  1771. u32 value;
  1772. idx = pkt->idx + 1;
  1773. value = radeon_get_ib_value(p, idx + 2);
  1774. if ((value + 1) > radeon_bo_size(robj)) {
  1775. DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
  1776. "(need %u have %lu) !\n",
  1777. value + 1,
  1778. radeon_bo_size(robj));
  1779. return -EINVAL;
  1780. }
  1781. return 0;
  1782. }
  1783. static int r100_packet3_check(struct radeon_cs_parser *p,
  1784. struct radeon_cs_packet *pkt)
  1785. {
  1786. struct radeon_bo_list *reloc;
  1787. struct r100_cs_track *track;
  1788. unsigned idx;
  1789. volatile uint32_t *ib;
  1790. int r;
  1791. ib = p->ib.ptr;
  1792. idx = pkt->idx + 1;
  1793. track = (struct r100_cs_track *)p->track;
  1794. switch (pkt->opcode) {
  1795. case PACKET3_3D_LOAD_VBPNTR:
  1796. r = r100_packet3_load_vbpntr(p, pkt, idx);
  1797. if (r)
  1798. return r;
  1799. break;
  1800. case PACKET3_INDX_BUFFER:
  1801. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1802. if (r) {
  1803. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1804. radeon_cs_dump_packet(p, pkt);
  1805. return r;
  1806. }
  1807. ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
  1808. r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
  1809. if (r) {
  1810. return r;
  1811. }
  1812. break;
  1813. case 0x23:
  1814. /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
  1815. r = radeon_cs_packet_next_reloc(p, &reloc, 0);
  1816. if (r) {
  1817. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1818. radeon_cs_dump_packet(p, pkt);
  1819. return r;
  1820. }
  1821. ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
  1822. track->num_arrays = 1;
  1823. track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
  1824. track->arrays[0].robj = reloc->robj;
  1825. track->arrays[0].esize = track->vtx_size;
  1826. track->max_indx = radeon_get_ib_value(p, idx+1);
  1827. track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
  1828. track->immd_dwords = pkt->count - 1;
  1829. r = r100_cs_track_check(p->rdev, track);
  1830. if (r)
  1831. return r;
  1832. break;
  1833. case PACKET3_3D_DRAW_IMMD:
  1834. if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
  1835. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1836. return -EINVAL;
  1837. }
  1838. track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
  1839. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1840. track->immd_dwords = pkt->count - 1;
  1841. r = r100_cs_track_check(p->rdev, track);
  1842. if (r)
  1843. return r;
  1844. break;
  1845. /* triggers drawing using in-packet vertex data */
  1846. case PACKET3_3D_DRAW_IMMD_2:
  1847. if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
  1848. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1849. return -EINVAL;
  1850. }
  1851. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1852. track->immd_dwords = pkt->count;
  1853. r = r100_cs_track_check(p->rdev, track);
  1854. if (r)
  1855. return r;
  1856. break;
  1857. /* triggers drawing using in-packet vertex data */
  1858. case PACKET3_3D_DRAW_VBUF_2:
  1859. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1860. r = r100_cs_track_check(p->rdev, track);
  1861. if (r)
  1862. return r;
  1863. break;
  1864. /* triggers drawing of vertex buffers setup elsewhere */
  1865. case PACKET3_3D_DRAW_INDX_2:
  1866. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1867. r = r100_cs_track_check(p->rdev, track);
  1868. if (r)
  1869. return r;
  1870. break;
  1871. /* triggers drawing using indices to vertex buffer */
  1872. case PACKET3_3D_DRAW_VBUF:
  1873. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1874. r = r100_cs_track_check(p->rdev, track);
  1875. if (r)
  1876. return r;
  1877. break;
  1878. /* triggers drawing of vertex buffers setup elsewhere */
  1879. case PACKET3_3D_DRAW_INDX:
  1880. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1881. r = r100_cs_track_check(p->rdev, track);
  1882. if (r)
  1883. return r;
  1884. break;
  1885. /* triggers drawing using indices to vertex buffer */
  1886. case PACKET3_3D_CLEAR_HIZ:
  1887. case PACKET3_3D_CLEAR_ZMASK:
  1888. if (p->rdev->hyperz_filp != p->filp)
  1889. return -EINVAL;
  1890. break;
  1891. case PACKET3_NOP:
  1892. break;
  1893. default:
  1894. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  1895. return -EINVAL;
  1896. }
  1897. return 0;
  1898. }
  1899. int r100_cs_parse(struct radeon_cs_parser *p)
  1900. {
  1901. struct radeon_cs_packet pkt;
  1902. struct r100_cs_track *track;
  1903. int r;
  1904. track = kzalloc(sizeof(*track), GFP_KERNEL);
  1905. if (!track)
  1906. return -ENOMEM;
  1907. r100_cs_track_clear(p->rdev, track);
  1908. p->track = track;
  1909. do {
  1910. r = radeon_cs_packet_parse(p, &pkt, p->idx);
  1911. if (r) {
  1912. return r;
  1913. }
  1914. p->idx += pkt.count + 2;
  1915. switch (pkt.type) {
  1916. case RADEON_PACKET_TYPE0:
  1917. if (p->rdev->family >= CHIP_R200)
  1918. r = r100_cs_parse_packet0(p, &pkt,
  1919. p->rdev->config.r100.reg_safe_bm,
  1920. p->rdev->config.r100.reg_safe_bm_size,
  1921. &r200_packet0_check);
  1922. else
  1923. r = r100_cs_parse_packet0(p, &pkt,
  1924. p->rdev->config.r100.reg_safe_bm,
  1925. p->rdev->config.r100.reg_safe_bm_size,
  1926. &r100_packet0_check);
  1927. break;
  1928. case RADEON_PACKET_TYPE2:
  1929. break;
  1930. case RADEON_PACKET_TYPE3:
  1931. r = r100_packet3_check(p, &pkt);
  1932. break;
  1933. default:
  1934. DRM_ERROR("Unknown packet type %d !\n",
  1935. pkt.type);
  1936. return -EINVAL;
  1937. }
  1938. if (r)
  1939. return r;
  1940. } while (p->idx < p->chunk_ib->length_dw);
  1941. return 0;
  1942. }
  1943. static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
  1944. {
  1945. DRM_ERROR("pitch %d\n", t->pitch);
  1946. DRM_ERROR("use_pitch %d\n", t->use_pitch);
  1947. DRM_ERROR("width %d\n", t->width);
  1948. DRM_ERROR("width_11 %d\n", t->width_11);
  1949. DRM_ERROR("height %d\n", t->height);
  1950. DRM_ERROR("height_11 %d\n", t->height_11);
  1951. DRM_ERROR("num levels %d\n", t->num_levels);
  1952. DRM_ERROR("depth %d\n", t->txdepth);
  1953. DRM_ERROR("bpp %d\n", t->cpp);
  1954. DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
  1955. DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
  1956. DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
  1957. DRM_ERROR("compress format %d\n", t->compress_format);
  1958. }
  1959. static int r100_track_compress_size(int compress_format, int w, int h)
  1960. {
  1961. int block_width, block_height, block_bytes;
  1962. int wblocks, hblocks;
  1963. int min_wblocks;
  1964. int sz;
  1965. block_width = 4;
  1966. block_height = 4;
  1967. switch (compress_format) {
  1968. case R100_TRACK_COMP_DXT1:
  1969. block_bytes = 8;
  1970. min_wblocks = 4;
  1971. break;
  1972. default:
  1973. case R100_TRACK_COMP_DXT35:
  1974. block_bytes = 16;
  1975. min_wblocks = 2;
  1976. break;
  1977. }
  1978. hblocks = (h + block_height - 1) / block_height;
  1979. wblocks = (w + block_width - 1) / block_width;
  1980. if (wblocks < min_wblocks)
  1981. wblocks = min_wblocks;
  1982. sz = wblocks * hblocks * block_bytes;
  1983. return sz;
  1984. }
  1985. static int r100_cs_track_cube(struct radeon_device *rdev,
  1986. struct r100_cs_track *track, unsigned idx)
  1987. {
  1988. unsigned face, w, h;
  1989. struct radeon_bo *cube_robj;
  1990. unsigned long size;
  1991. unsigned compress_format = track->textures[idx].compress_format;
  1992. for (face = 0; face < 5; face++) {
  1993. cube_robj = track->textures[idx].cube_info[face].robj;
  1994. w = track->textures[idx].cube_info[face].width;
  1995. h = track->textures[idx].cube_info[face].height;
  1996. if (compress_format) {
  1997. size = r100_track_compress_size(compress_format, w, h);
  1998. } else
  1999. size = w * h;
  2000. size *= track->textures[idx].cpp;
  2001. size += track->textures[idx].cube_info[face].offset;
  2002. if (size > radeon_bo_size(cube_robj)) {
  2003. DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
  2004. size, radeon_bo_size(cube_robj));
  2005. r100_cs_track_texture_print(&track->textures[idx]);
  2006. return -1;
  2007. }
  2008. }
  2009. return 0;
  2010. }
  2011. static int r100_cs_track_texture_check(struct radeon_device *rdev,
  2012. struct r100_cs_track *track)
  2013. {
  2014. struct radeon_bo *robj;
  2015. unsigned long size;
  2016. unsigned u, i, w, h, d;
  2017. int ret;
  2018. for (u = 0; u < track->num_texture; u++) {
  2019. if (!track->textures[u].enabled)
  2020. continue;
  2021. if (track->textures[u].lookup_disable)
  2022. continue;
  2023. robj = track->textures[u].robj;
  2024. if (robj == NULL) {
  2025. DRM_ERROR("No texture bound to unit %u\n", u);
  2026. return -EINVAL;
  2027. }
  2028. size = 0;
  2029. for (i = 0; i <= track->textures[u].num_levels; i++) {
  2030. if (track->textures[u].use_pitch) {
  2031. if (rdev->family < CHIP_R300)
  2032. w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
  2033. else
  2034. w = track->textures[u].pitch / (1 << i);
  2035. } else {
  2036. w = track->textures[u].width;
  2037. if (rdev->family >= CHIP_RV515)
  2038. w |= track->textures[u].width_11;
  2039. w = w / (1 << i);
  2040. if (track->textures[u].roundup_w)
  2041. w = roundup_pow_of_two(w);
  2042. }
  2043. h = track->textures[u].height;
  2044. if (rdev->family >= CHIP_RV515)
  2045. h |= track->textures[u].height_11;
  2046. h = h / (1 << i);
  2047. if (track->textures[u].roundup_h)
  2048. h = roundup_pow_of_two(h);
  2049. if (track->textures[u].tex_coord_type == 1) {
  2050. d = (1 << track->textures[u].txdepth) / (1 << i);
  2051. if (!d)
  2052. d = 1;
  2053. } else {
  2054. d = 1;
  2055. }
  2056. if (track->textures[u].compress_format) {
  2057. size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
  2058. /* compressed textures are block based */
  2059. } else
  2060. size += w * h * d;
  2061. }
  2062. size *= track->textures[u].cpp;
  2063. switch (track->textures[u].tex_coord_type) {
  2064. case 0:
  2065. case 1:
  2066. break;
  2067. case 2:
  2068. if (track->separate_cube) {
  2069. ret = r100_cs_track_cube(rdev, track, u);
  2070. if (ret)
  2071. return ret;
  2072. } else
  2073. size *= 6;
  2074. break;
  2075. default:
  2076. DRM_ERROR("Invalid texture coordinate type %u for unit "
  2077. "%u\n", track->textures[u].tex_coord_type, u);
  2078. return -EINVAL;
  2079. }
  2080. if (size > radeon_bo_size(robj)) {
  2081. DRM_ERROR("Texture of unit %u needs %lu bytes but is "
  2082. "%lu\n", u, size, radeon_bo_size(robj));
  2083. r100_cs_track_texture_print(&track->textures[u]);
  2084. return -EINVAL;
  2085. }
  2086. }
  2087. return 0;
  2088. }
  2089. int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
  2090. {
  2091. unsigned i;
  2092. unsigned long size;
  2093. unsigned prim_walk;
  2094. unsigned nverts;
  2095. unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
  2096. if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
  2097. !track->blend_read_enable)
  2098. num_cb = 0;
  2099. for (i = 0; i < num_cb; i++) {
  2100. if (track->cb[i].robj == NULL) {
  2101. DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
  2102. return -EINVAL;
  2103. }
  2104. size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
  2105. size += track->cb[i].offset;
  2106. if (size > radeon_bo_size(track->cb[i].robj)) {
  2107. DRM_ERROR("[drm] Buffer too small for color buffer %d "
  2108. "(need %lu have %lu) !\n", i, size,
  2109. radeon_bo_size(track->cb[i].robj));
  2110. DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
  2111. i, track->cb[i].pitch, track->cb[i].cpp,
  2112. track->cb[i].offset, track->maxy);
  2113. return -EINVAL;
  2114. }
  2115. }
  2116. track->cb_dirty = false;
  2117. if (track->zb_dirty && track->z_enabled) {
  2118. if (track->zb.robj == NULL) {
  2119. DRM_ERROR("[drm] No buffer for z buffer !\n");
  2120. return -EINVAL;
  2121. }
  2122. size = track->zb.pitch * track->zb.cpp * track->maxy;
  2123. size += track->zb.offset;
  2124. if (size > radeon_bo_size(track->zb.robj)) {
  2125. DRM_ERROR("[drm] Buffer too small for z buffer "
  2126. "(need %lu have %lu) !\n", size,
  2127. radeon_bo_size(track->zb.robj));
  2128. DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
  2129. track->zb.pitch, track->zb.cpp,
  2130. track->zb.offset, track->maxy);
  2131. return -EINVAL;
  2132. }
  2133. }
  2134. track->zb_dirty = false;
  2135. if (track->aa_dirty && track->aaresolve) {
  2136. if (track->aa.robj == NULL) {
  2137. DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
  2138. return -EINVAL;
  2139. }
  2140. /* I believe the format comes from colorbuffer0. */
  2141. size = track->aa.pitch * track->cb[0].cpp * track->maxy;
  2142. size += track->aa.offset;
  2143. if (size > radeon_bo_size(track->aa.robj)) {
  2144. DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
  2145. "(need %lu have %lu) !\n", i, size,
  2146. radeon_bo_size(track->aa.robj));
  2147. DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
  2148. i, track->aa.pitch, track->cb[0].cpp,
  2149. track->aa.offset, track->maxy);
  2150. return -EINVAL;
  2151. }
  2152. }
  2153. track->aa_dirty = false;
  2154. prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
  2155. if (track->vap_vf_cntl & (1 << 14)) {
  2156. nverts = track->vap_alt_nverts;
  2157. } else {
  2158. nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
  2159. }
  2160. switch (prim_walk) {
  2161. case 1:
  2162. for (i = 0; i < track->num_arrays; i++) {
  2163. size = track->arrays[i].esize * track->max_indx * 4;
  2164. if (track->arrays[i].robj == NULL) {
  2165. DRM_ERROR("(PW %u) Vertex array %u no buffer "
  2166. "bound\n", prim_walk, i);
  2167. return -EINVAL;
  2168. }
  2169. if (size > radeon_bo_size(track->arrays[i].robj)) {
  2170. dev_err(rdev->dev, "(PW %u) Vertex array %u "
  2171. "need %lu dwords have %lu dwords\n",
  2172. prim_walk, i, size >> 2,
  2173. radeon_bo_size(track->arrays[i].robj)
  2174. >> 2);
  2175. DRM_ERROR("Max indices %u\n", track->max_indx);
  2176. return -EINVAL;
  2177. }
  2178. }
  2179. break;
  2180. case 2:
  2181. for (i = 0; i < track->num_arrays; i++) {
  2182. size = track->arrays[i].esize * (nverts - 1) * 4;
  2183. if (track->arrays[i].robj == NULL) {
  2184. DRM_ERROR("(PW %u) Vertex array %u no buffer "
  2185. "bound\n", prim_walk, i);
  2186. return -EINVAL;
  2187. }
  2188. if (size > radeon_bo_size(track->arrays[i].robj)) {
  2189. dev_err(rdev->dev, "(PW %u) Vertex array %u "
  2190. "need %lu dwords have %lu dwords\n",
  2191. prim_walk, i, size >> 2,
  2192. radeon_bo_size(track->arrays[i].robj)
  2193. >> 2);
  2194. return -EINVAL;
  2195. }
  2196. }
  2197. break;
  2198. case 3:
  2199. size = track->vtx_size * nverts;
  2200. if (size != track->immd_dwords) {
  2201. DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
  2202. track->immd_dwords, size);
  2203. DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
  2204. nverts, track->vtx_size);
  2205. return -EINVAL;
  2206. }
  2207. break;
  2208. default:
  2209. DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
  2210. prim_walk);
  2211. return -EINVAL;
  2212. }
  2213. if (track->tex_dirty) {
  2214. track->tex_dirty = false;
  2215. return r100_cs_track_texture_check(rdev, track);
  2216. }
  2217. return 0;
  2218. }
  2219. void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
  2220. {
  2221. unsigned i, face;
  2222. track->cb_dirty = true;
  2223. track->zb_dirty = true;
  2224. track->tex_dirty = true;
  2225. track->aa_dirty = true;
  2226. if (rdev->family < CHIP_R300) {
  2227. track->num_cb = 1;
  2228. if (rdev->family <= CHIP_RS200)
  2229. track->num_texture = 3;
  2230. else
  2231. track->num_texture = 6;
  2232. track->maxy = 2048;
  2233. track->separate_cube = true;
  2234. } else {
  2235. track->num_cb = 4;
  2236. track->num_texture = 16;
  2237. track->maxy = 4096;
  2238. track->separate_cube = false;
  2239. track->aaresolve = false;
  2240. track->aa.robj = NULL;
  2241. }
  2242. for (i = 0; i < track->num_cb; i++) {
  2243. track->cb[i].robj = NULL;
  2244. track->cb[i].pitch = 8192;
  2245. track->cb[i].cpp = 16;
  2246. track->cb[i].offset = 0;
  2247. }
  2248. track->z_enabled = true;
  2249. track->zb.robj = NULL;
  2250. track->zb.pitch = 8192;
  2251. track->zb.cpp = 4;
  2252. track->zb.offset = 0;
  2253. track->vtx_size = 0x7F;
  2254. track->immd_dwords = 0xFFFFFFFFUL;
  2255. track->num_arrays = 11;
  2256. track->max_indx = 0x00FFFFFFUL;
  2257. for (i = 0; i < track->num_arrays; i++) {
  2258. track->arrays[i].robj = NULL;
  2259. track->arrays[i].esize = 0x7F;
  2260. }
  2261. for (i = 0; i < track->num_texture; i++) {
  2262. track->textures[i].compress_format = R100_TRACK_COMP_NONE;
  2263. track->textures[i].pitch = 16536;
  2264. track->textures[i].width = 16536;
  2265. track->textures[i].height = 16536;
  2266. track->textures[i].width_11 = 1 << 11;
  2267. track->textures[i].height_11 = 1 << 11;
  2268. track->textures[i].num_levels = 12;
  2269. if (rdev->family <= CHIP_RS200) {
  2270. track->textures[i].tex_coord_type = 0;
  2271. track->textures[i].txdepth = 0;
  2272. } else {
  2273. track->textures[i].txdepth = 16;
  2274. track->textures[i].tex_coord_type = 1;
  2275. }
  2276. track->textures[i].cpp = 64;
  2277. track->textures[i].robj = NULL;
  2278. /* CS IB emission code makes sure texture unit are disabled */
  2279. track->textures[i].enabled = false;
  2280. track->textures[i].lookup_disable = false;
  2281. track->textures[i].roundup_w = true;
  2282. track->textures[i].roundup_h = true;
  2283. if (track->separate_cube)
  2284. for (face = 0; face < 5; face++) {
  2285. track->textures[i].cube_info[face].robj = NULL;
  2286. track->textures[i].cube_info[face].width = 16536;
  2287. track->textures[i].cube_info[face].height = 16536;
  2288. track->textures[i].cube_info[face].offset = 0;
  2289. }
  2290. }
  2291. }
  2292. /*
  2293. * Global GPU functions
  2294. */
  2295. static void r100_errata(struct radeon_device *rdev)
  2296. {
  2297. rdev->pll_errata = 0;
  2298. if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
  2299. rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
  2300. }
  2301. if (rdev->family == CHIP_RV100 ||
  2302. rdev->family == CHIP_RS100 ||
  2303. rdev->family == CHIP_RS200) {
  2304. rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
  2305. }
  2306. }
  2307. static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
  2308. {
  2309. unsigned i;
  2310. uint32_t tmp;
  2311. for (i = 0; i < rdev->usec_timeout; i++) {
  2312. tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
  2313. if (tmp >= n) {
  2314. return 0;
  2315. }
  2316. udelay(1);
  2317. }
  2318. return -1;
  2319. }
  2320. int r100_gui_wait_for_idle(struct radeon_device *rdev)
  2321. {
  2322. unsigned i;
  2323. uint32_t tmp;
  2324. if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
  2325. pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n");
  2326. }
  2327. for (i = 0; i < rdev->usec_timeout; i++) {
  2328. tmp = RREG32(RADEON_RBBM_STATUS);
  2329. if (!(tmp & RADEON_RBBM_ACTIVE)) {
  2330. return 0;
  2331. }
  2332. udelay(1);
  2333. }
  2334. return -1;
  2335. }
  2336. int r100_mc_wait_for_idle(struct radeon_device *rdev)
  2337. {
  2338. unsigned i;
  2339. uint32_t tmp;
  2340. for (i = 0; i < rdev->usec_timeout; i++) {
  2341. /* read MC_STATUS */
  2342. tmp = RREG32(RADEON_MC_STATUS);
  2343. if (tmp & RADEON_MC_IDLE) {
  2344. return 0;
  2345. }
  2346. udelay(1);
  2347. }
  2348. return -1;
  2349. }
  2350. bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
  2351. {
  2352. u32 rbbm_status;
  2353. rbbm_status = RREG32(R_000E40_RBBM_STATUS);
  2354. if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
  2355. radeon_ring_lockup_update(rdev, ring);
  2356. return false;
  2357. }
  2358. return radeon_ring_test_lockup(rdev, ring);
  2359. }
  2360. /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
  2361. void r100_enable_bm(struct radeon_device *rdev)
  2362. {
  2363. uint32_t tmp;
  2364. /* Enable bus mastering */
  2365. tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  2366. WREG32(RADEON_BUS_CNTL, tmp);
  2367. }
  2368. void r100_bm_disable(struct radeon_device *rdev)
  2369. {
  2370. u32 tmp;
  2371. /* disable bus mastering */
  2372. tmp = RREG32(R_000030_BUS_CNTL);
  2373. WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
  2374. mdelay(1);
  2375. WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
  2376. mdelay(1);
  2377. WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
  2378. tmp = RREG32(RADEON_BUS_CNTL);
  2379. mdelay(1);
  2380. pci_clear_master(rdev->pdev);
  2381. mdelay(1);
  2382. }
  2383. int r100_asic_reset(struct radeon_device *rdev, bool hard)
  2384. {
  2385. struct r100_mc_save save;
  2386. u32 status, tmp;
  2387. int ret = 0;
  2388. status = RREG32(R_000E40_RBBM_STATUS);
  2389. if (!G_000E40_GUI_ACTIVE(status)) {
  2390. return 0;
  2391. }
  2392. r100_mc_stop(rdev, &save);
  2393. status = RREG32(R_000E40_RBBM_STATUS);
  2394. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  2395. /* stop CP */
  2396. WREG32(RADEON_CP_CSQ_CNTL, 0);
  2397. tmp = RREG32(RADEON_CP_RB_CNTL);
  2398. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
  2399. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  2400. WREG32(RADEON_CP_RB_WPTR, 0);
  2401. WREG32(RADEON_CP_RB_CNTL, tmp);
  2402. /* save PCI state */
  2403. pci_save_state(rdev->pdev);
  2404. /* disable bus mastering */
  2405. r100_bm_disable(rdev);
  2406. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
  2407. S_0000F0_SOFT_RESET_RE(1) |
  2408. S_0000F0_SOFT_RESET_PP(1) |
  2409. S_0000F0_SOFT_RESET_RB(1));
  2410. RREG32(R_0000F0_RBBM_SOFT_RESET);
  2411. mdelay(500);
  2412. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  2413. mdelay(1);
  2414. status = RREG32(R_000E40_RBBM_STATUS);
  2415. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  2416. /* reset CP */
  2417. WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
  2418. RREG32(R_0000F0_RBBM_SOFT_RESET);
  2419. mdelay(500);
  2420. WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
  2421. mdelay(1);
  2422. status = RREG32(R_000E40_RBBM_STATUS);
  2423. dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
  2424. /* restore PCI & busmastering */
  2425. pci_restore_state(rdev->pdev);
  2426. r100_enable_bm(rdev);
  2427. /* Check if GPU is idle */
  2428. if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
  2429. G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
  2430. dev_err(rdev->dev, "failed to reset GPU\n");
  2431. ret = -1;
  2432. } else
  2433. dev_info(rdev->dev, "GPU reset succeed\n");
  2434. r100_mc_resume(rdev, &save);
  2435. return ret;
  2436. }
  2437. void r100_set_common_regs(struct radeon_device *rdev)
  2438. {
  2439. bool force_dac2 = false;
  2440. u32 tmp;
  2441. /* set these so they don't interfere with anything */
  2442. WREG32(RADEON_OV0_SCALE_CNTL, 0);
  2443. WREG32(RADEON_SUBPIC_CNTL, 0);
  2444. WREG32(RADEON_VIPH_CONTROL, 0);
  2445. WREG32(RADEON_I2C_CNTL_1, 0);
  2446. WREG32(RADEON_DVI_I2C_CNTL_1, 0);
  2447. WREG32(RADEON_CAP0_TRIG_CNTL, 0);
  2448. WREG32(RADEON_CAP1_TRIG_CNTL, 0);
  2449. /* always set up dac2 on rn50 and some rv100 as lots
  2450. * of servers seem to wire it up to a VGA port but
  2451. * don't report it in the bios connector
  2452. * table.
  2453. */
  2454. switch (rdev->pdev->device) {
  2455. /* RN50 */
  2456. case 0x515e:
  2457. case 0x5969:
  2458. force_dac2 = true;
  2459. break;
  2460. /* RV100*/
  2461. case 0x5159:
  2462. case 0x515a:
  2463. /* DELL triple head servers */
  2464. if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
  2465. ((rdev->pdev->subsystem_device == 0x016c) ||
  2466. (rdev->pdev->subsystem_device == 0x016d) ||
  2467. (rdev->pdev->subsystem_device == 0x016e) ||
  2468. (rdev->pdev->subsystem_device == 0x016f) ||
  2469. (rdev->pdev->subsystem_device == 0x0170) ||
  2470. (rdev->pdev->subsystem_device == 0x017d) ||
  2471. (rdev->pdev->subsystem_device == 0x017e) ||
  2472. (rdev->pdev->subsystem_device == 0x0183) ||
  2473. (rdev->pdev->subsystem_device == 0x018a) ||
  2474. (rdev->pdev->subsystem_device == 0x019a)))
  2475. force_dac2 = true;
  2476. break;
  2477. }
  2478. if (force_dac2) {
  2479. u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
  2480. u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
  2481. u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
  2482. /* For CRT on DAC2, don't turn it on if BIOS didn't
  2483. enable it, even it's detected.
  2484. */
  2485. /* force it to crtc0 */
  2486. dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
  2487. dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
  2488. disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
  2489. /* set up the TV DAC */
  2490. tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
  2491. RADEON_TV_DAC_STD_MASK |
  2492. RADEON_TV_DAC_RDACPD |
  2493. RADEON_TV_DAC_GDACPD |
  2494. RADEON_TV_DAC_BDACPD |
  2495. RADEON_TV_DAC_BGADJ_MASK |
  2496. RADEON_TV_DAC_DACADJ_MASK);
  2497. tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
  2498. RADEON_TV_DAC_NHOLD |
  2499. RADEON_TV_DAC_STD_PS2 |
  2500. (0x58 << 16));
  2501. WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
  2502. WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
  2503. WREG32(RADEON_DAC_CNTL2, dac2_cntl);
  2504. }
  2505. /* switch PM block to ACPI mode */
  2506. tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
  2507. tmp &= ~RADEON_PM_MODE_SEL;
  2508. WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
  2509. }
  2510. /*
  2511. * VRAM info
  2512. */
  2513. static void r100_vram_get_type(struct radeon_device *rdev)
  2514. {
  2515. uint32_t tmp;
  2516. rdev->mc.vram_is_ddr = false;
  2517. if (rdev->flags & RADEON_IS_IGP)
  2518. rdev->mc.vram_is_ddr = true;
  2519. else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  2520. rdev->mc.vram_is_ddr = true;
  2521. if ((rdev->family == CHIP_RV100) ||
  2522. (rdev->family == CHIP_RS100) ||
  2523. (rdev->family == CHIP_RS200)) {
  2524. tmp = RREG32(RADEON_MEM_CNTL);
  2525. if (tmp & RV100_HALF_MODE) {
  2526. rdev->mc.vram_width = 32;
  2527. } else {
  2528. rdev->mc.vram_width = 64;
  2529. }
  2530. if (rdev->flags & RADEON_SINGLE_CRTC) {
  2531. rdev->mc.vram_width /= 4;
  2532. rdev->mc.vram_is_ddr = true;
  2533. }
  2534. } else if (rdev->family <= CHIP_RV280) {
  2535. tmp = RREG32(RADEON_MEM_CNTL);
  2536. if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
  2537. rdev->mc.vram_width = 128;
  2538. } else {
  2539. rdev->mc.vram_width = 64;
  2540. }
  2541. } else {
  2542. /* newer IGPs */
  2543. rdev->mc.vram_width = 128;
  2544. }
  2545. }
  2546. static u32 r100_get_accessible_vram(struct radeon_device *rdev)
  2547. {
  2548. u32 aper_size;
  2549. u8 byte;
  2550. aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
  2551. /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  2552. * that is has the 2nd generation multifunction PCI interface
  2553. */
  2554. if (rdev->family == CHIP_RV280 ||
  2555. rdev->family >= CHIP_RV350) {
  2556. WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  2557. ~RADEON_HDP_APER_CNTL);
  2558. DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
  2559. return aper_size * 2;
  2560. }
  2561. /* Older cards have all sorts of funny issues to deal with. First
  2562. * check if it's a multifunction card by reading the PCI config
  2563. * header type... Limit those to one aperture size
  2564. */
  2565. pci_read_config_byte(rdev->pdev, 0xe, &byte);
  2566. if (byte & 0x80) {
  2567. DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
  2568. DRM_INFO("Limiting VRAM to one aperture\n");
  2569. return aper_size;
  2570. }
  2571. /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  2572. * have set it up. We don't write this as it's broken on some ASICs but
  2573. * we expect the BIOS to have done the right thing (might be too optimistic...)
  2574. */
  2575. if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  2576. return aper_size * 2;
  2577. return aper_size;
  2578. }
  2579. void r100_vram_init_sizes(struct radeon_device *rdev)
  2580. {
  2581. u64 config_aper_size;
  2582. /* work out accessible VRAM */
  2583. rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
  2584. rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
  2585. rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
  2586. /* FIXME we don't use the second aperture yet when we could use it */
  2587. if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
  2588. rdev->mc.visible_vram_size = rdev->mc.aper_size;
  2589. config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
  2590. if (rdev->flags & RADEON_IS_IGP) {
  2591. uint32_t tom;
  2592. /* read NB_TOM to get the amount of ram stolen for the GPU */
  2593. tom = RREG32(RADEON_NB_TOM);
  2594. rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
  2595. WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  2596. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  2597. } else {
  2598. rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  2599. /* Some production boards of m6 will report 0
  2600. * if it's 8 MB
  2601. */
  2602. if (rdev->mc.real_vram_size == 0) {
  2603. rdev->mc.real_vram_size = 8192 * 1024;
  2604. WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  2605. }
  2606. /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  2607. * Novell bug 204882 + along with lots of ubuntu ones
  2608. */
  2609. if (rdev->mc.aper_size > config_aper_size)
  2610. config_aper_size = rdev->mc.aper_size;
  2611. if (config_aper_size > rdev->mc.real_vram_size)
  2612. rdev->mc.mc_vram_size = config_aper_size;
  2613. else
  2614. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  2615. }
  2616. }
  2617. void r100_vga_set_state(struct radeon_device *rdev, bool state)
  2618. {
  2619. uint32_t temp;
  2620. temp = RREG32(RADEON_CONFIG_CNTL);
  2621. if (!state) {
  2622. temp &= ~RADEON_CFG_VGA_RAM_EN;
  2623. temp |= RADEON_CFG_VGA_IO_DIS;
  2624. } else {
  2625. temp &= ~RADEON_CFG_VGA_IO_DIS;
  2626. }
  2627. WREG32(RADEON_CONFIG_CNTL, temp);
  2628. }
  2629. static void r100_mc_init(struct radeon_device *rdev)
  2630. {
  2631. u64 base;
  2632. r100_vram_get_type(rdev);
  2633. r100_vram_init_sizes(rdev);
  2634. base = rdev->mc.aper_base;
  2635. if (rdev->flags & RADEON_IS_IGP)
  2636. base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
  2637. radeon_vram_location(rdev, &rdev->mc, base);
  2638. rdev->mc.gtt_base_align = 0;
  2639. if (!(rdev->flags & RADEON_IS_AGP))
  2640. radeon_gtt_location(rdev, &rdev->mc);
  2641. radeon_update_bandwidth_info(rdev);
  2642. }
  2643. /*
  2644. * Indirect registers accessor
  2645. */
  2646. void r100_pll_errata_after_index(struct radeon_device *rdev)
  2647. {
  2648. if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
  2649. (void)RREG32(RADEON_CLOCK_CNTL_DATA);
  2650. (void)RREG32(RADEON_CRTC_GEN_CNTL);
  2651. }
  2652. }
  2653. static void r100_pll_errata_after_data(struct radeon_device *rdev)
  2654. {
  2655. /* This workarounds is necessary on RV100, RS100 and RS200 chips
  2656. * or the chip could hang on a subsequent access
  2657. */
  2658. if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
  2659. mdelay(5);
  2660. }
  2661. /* This function is required to workaround a hardware bug in some (all?)
  2662. * revisions of the R300. This workaround should be called after every
  2663. * CLOCK_CNTL_INDEX register access. If not, register reads afterward
  2664. * may not be correct.
  2665. */
  2666. if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
  2667. uint32_t save, tmp;
  2668. save = RREG32(RADEON_CLOCK_CNTL_INDEX);
  2669. tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
  2670. WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
  2671. tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
  2672. WREG32(RADEON_CLOCK_CNTL_INDEX, save);
  2673. }
  2674. }
  2675. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
  2676. {
  2677. unsigned long flags;
  2678. uint32_t data;
  2679. spin_lock_irqsave(&rdev->pll_idx_lock, flags);
  2680. WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
  2681. r100_pll_errata_after_index(rdev);
  2682. data = RREG32(RADEON_CLOCK_CNTL_DATA);
  2683. r100_pll_errata_after_data(rdev);
  2684. spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
  2685. return data;
  2686. }
  2687. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  2688. {
  2689. unsigned long flags;
  2690. spin_lock_irqsave(&rdev->pll_idx_lock, flags);
  2691. WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
  2692. r100_pll_errata_after_index(rdev);
  2693. WREG32(RADEON_CLOCK_CNTL_DATA, v);
  2694. r100_pll_errata_after_data(rdev);
  2695. spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
  2696. }
  2697. static void r100_set_safe_registers(struct radeon_device *rdev)
  2698. {
  2699. if (ASIC_IS_RN50(rdev)) {
  2700. rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
  2701. rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
  2702. } else if (rdev->family < CHIP_R200) {
  2703. rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
  2704. rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
  2705. } else {
  2706. r200_set_safe_registers(rdev);
  2707. }
  2708. }
  2709. /*
  2710. * Debugfs info
  2711. */
  2712. #if defined(CONFIG_DEBUG_FS)
  2713. static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
  2714. {
  2715. struct radeon_device *rdev = (struct radeon_device *)m->private;
  2716. uint32_t reg, value;
  2717. unsigned i;
  2718. seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
  2719. seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
  2720. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  2721. for (i = 0; i < 64; i++) {
  2722. WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
  2723. reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
  2724. WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
  2725. value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
  2726. seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
  2727. }
  2728. return 0;
  2729. }
  2730. static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
  2731. {
  2732. struct radeon_device *rdev = (struct radeon_device *)m->private;
  2733. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  2734. uint32_t rdp, wdp;
  2735. unsigned count, i, j;
  2736. radeon_ring_free_size(rdev, ring);
  2737. rdp = RREG32(RADEON_CP_RB_RPTR);
  2738. wdp = RREG32(RADEON_CP_RB_WPTR);
  2739. count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
  2740. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  2741. seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
  2742. seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
  2743. seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
  2744. seq_printf(m, "%u dwords in ring\n", count);
  2745. if (ring->ready) {
  2746. for (j = 0; j <= count; j++) {
  2747. i = (rdp + j) & ring->ptr_mask;
  2748. seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
  2749. }
  2750. }
  2751. return 0;
  2752. }
  2753. static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
  2754. {
  2755. struct radeon_device *rdev = (struct radeon_device *)m->private;
  2756. uint32_t csq_stat, csq2_stat, tmp;
  2757. unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
  2758. unsigned i;
  2759. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  2760. seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
  2761. csq_stat = RREG32(RADEON_CP_CSQ_STAT);
  2762. csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
  2763. r_rptr = (csq_stat >> 0) & 0x3ff;
  2764. r_wptr = (csq_stat >> 10) & 0x3ff;
  2765. ib1_rptr = (csq_stat >> 20) & 0x3ff;
  2766. ib1_wptr = (csq2_stat >> 0) & 0x3ff;
  2767. ib2_rptr = (csq2_stat >> 10) & 0x3ff;
  2768. ib2_wptr = (csq2_stat >> 20) & 0x3ff;
  2769. seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
  2770. seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
  2771. seq_printf(m, "Ring rptr %u\n", r_rptr);
  2772. seq_printf(m, "Ring wptr %u\n", r_wptr);
  2773. seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
  2774. seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
  2775. seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
  2776. seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
  2777. /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
  2778. * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
  2779. seq_printf(m, "Ring fifo:\n");
  2780. for (i = 0; i < 256; i++) {
  2781. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  2782. tmp = RREG32(RADEON_CP_CSQ_DATA);
  2783. seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
  2784. }
  2785. seq_printf(m, "Indirect1 fifo:\n");
  2786. for (i = 256; i <= 512; i++) {
  2787. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  2788. tmp = RREG32(RADEON_CP_CSQ_DATA);
  2789. seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
  2790. }
  2791. seq_printf(m, "Indirect2 fifo:\n");
  2792. for (i = 640; i < ib1_wptr; i++) {
  2793. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  2794. tmp = RREG32(RADEON_CP_CSQ_DATA);
  2795. seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
  2796. }
  2797. return 0;
  2798. }
  2799. static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
  2800. {
  2801. struct radeon_device *rdev = (struct radeon_device *)m->private;
  2802. uint32_t tmp;
  2803. tmp = RREG32(RADEON_CONFIG_MEMSIZE);
  2804. seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
  2805. tmp = RREG32(RADEON_MC_FB_LOCATION);
  2806. seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
  2807. tmp = RREG32(RADEON_BUS_CNTL);
  2808. seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
  2809. tmp = RREG32(RADEON_MC_AGP_LOCATION);
  2810. seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
  2811. tmp = RREG32(RADEON_AGP_BASE);
  2812. seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
  2813. tmp = RREG32(RADEON_HOST_PATH_CNTL);
  2814. seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
  2815. tmp = RREG32(0x01D0);
  2816. seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
  2817. tmp = RREG32(RADEON_AIC_LO_ADDR);
  2818. seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
  2819. tmp = RREG32(RADEON_AIC_HI_ADDR);
  2820. seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
  2821. tmp = RREG32(0x01E4);
  2822. seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
  2823. return 0;
  2824. }
  2825. DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
  2826. DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
  2827. DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
  2828. DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);
  2829. #endif
  2830. void r100_debugfs_rbbm_init(struct radeon_device *rdev)
  2831. {
  2832. #if defined(CONFIG_DEBUG_FS)
  2833. struct dentry *root = rdev->ddev->primary->debugfs_root;
  2834. debugfs_create_file("r100_rbbm_info", 0444, root, rdev,
  2835. &r100_debugfs_rbbm_info_fops);
  2836. #endif
  2837. }
  2838. void r100_debugfs_cp_init(struct radeon_device *rdev)
  2839. {
  2840. #if defined(CONFIG_DEBUG_FS)
  2841. struct dentry *root = rdev->ddev->primary->debugfs_root;
  2842. debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,
  2843. &r100_debugfs_cp_ring_info_fops);
  2844. debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,
  2845. &r100_debugfs_cp_csq_fifo_fops);
  2846. #endif
  2847. }
  2848. void r100_debugfs_mc_info_init(struct radeon_device *rdev)
  2849. {
  2850. #if defined(CONFIG_DEBUG_FS)
  2851. struct dentry *root = rdev->ddev->primary->debugfs_root;
  2852. debugfs_create_file("r100_mc_info", 0444, root, rdev,
  2853. &r100_debugfs_mc_info_fops);
  2854. #endif
  2855. }
  2856. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  2857. uint32_t tiling_flags, uint32_t pitch,
  2858. uint32_t offset, uint32_t obj_size)
  2859. {
  2860. int surf_index = reg * 16;
  2861. int flags = 0;
  2862. if (rdev->family <= CHIP_RS200) {
  2863. if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  2864. == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  2865. flags |= RADEON_SURF_TILE_COLOR_BOTH;
  2866. if (tiling_flags & RADEON_TILING_MACRO)
  2867. flags |= RADEON_SURF_TILE_COLOR_MACRO;
  2868. /* setting pitch to 0 disables tiling */
  2869. if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  2870. == 0)
  2871. pitch = 0;
  2872. } else if (rdev->family <= CHIP_RV280) {
  2873. if (tiling_flags & (RADEON_TILING_MACRO))
  2874. flags |= R200_SURF_TILE_COLOR_MACRO;
  2875. if (tiling_flags & RADEON_TILING_MICRO)
  2876. flags |= R200_SURF_TILE_COLOR_MICRO;
  2877. } else {
  2878. if (tiling_flags & RADEON_TILING_MACRO)
  2879. flags |= R300_SURF_TILE_MACRO;
  2880. if (tiling_flags & RADEON_TILING_MICRO)
  2881. flags |= R300_SURF_TILE_MICRO;
  2882. }
  2883. if (tiling_flags & RADEON_TILING_SWAP_16BIT)
  2884. flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
  2885. if (tiling_flags & RADEON_TILING_SWAP_32BIT)
  2886. flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
  2887. /* r100/r200 divide by 16 */
  2888. if (rdev->family < CHIP_R300)
  2889. flags |= pitch / 16;
  2890. else
  2891. flags |= pitch / 8;
  2892. DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
  2893. WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
  2894. WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
  2895. WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
  2896. return 0;
  2897. }
  2898. void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
  2899. {
  2900. int surf_index = reg * 16;
  2901. WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
  2902. }
  2903. void r100_bandwidth_update(struct radeon_device *rdev)
  2904. {
  2905. fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
  2906. fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
  2907. fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
  2908. fixed20_12 crit_point_ff = {0};
  2909. uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
  2910. fixed20_12 memtcas_ff[8] = {
  2911. dfixed_init(1),
  2912. dfixed_init(2),
  2913. dfixed_init(3),
  2914. dfixed_init(0),
  2915. dfixed_init_half(1),
  2916. dfixed_init_half(2),
  2917. dfixed_init(0),
  2918. };
  2919. fixed20_12 memtcas_rs480_ff[8] = {
  2920. dfixed_init(0),
  2921. dfixed_init(1),
  2922. dfixed_init(2),
  2923. dfixed_init(3),
  2924. dfixed_init(0),
  2925. dfixed_init_half(1),
  2926. dfixed_init_half(2),
  2927. dfixed_init_half(3),
  2928. };
  2929. fixed20_12 memtcas2_ff[8] = {
  2930. dfixed_init(0),
  2931. dfixed_init(1),
  2932. dfixed_init(2),
  2933. dfixed_init(3),
  2934. dfixed_init(4),
  2935. dfixed_init(5),
  2936. dfixed_init(6),
  2937. dfixed_init(7),
  2938. };
  2939. fixed20_12 memtrbs[8] = {
  2940. dfixed_init(1),
  2941. dfixed_init_half(1),
  2942. dfixed_init(2),
  2943. dfixed_init_half(2),
  2944. dfixed_init(3),
  2945. dfixed_init_half(3),
  2946. dfixed_init(4),
  2947. dfixed_init_half(4)
  2948. };
  2949. fixed20_12 memtrbs_r4xx[8] = {
  2950. dfixed_init(4),
  2951. dfixed_init(5),
  2952. dfixed_init(6),
  2953. dfixed_init(7),
  2954. dfixed_init(8),
  2955. dfixed_init(9),
  2956. dfixed_init(10),
  2957. dfixed_init(11)
  2958. };
  2959. fixed20_12 min_mem_eff;
  2960. fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
  2961. fixed20_12 cur_latency_mclk, cur_latency_sclk;
  2962. fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
  2963. disp_drain_rate2, read_return_rate;
  2964. fixed20_12 time_disp1_drop_priority;
  2965. int c;
  2966. int cur_size = 16; /* in octawords */
  2967. int critical_point = 0, critical_point2;
  2968. /* uint32_t read_return_rate, time_disp1_drop_priority; */
  2969. int stop_req, max_stop_req;
  2970. struct drm_display_mode *mode1 = NULL;
  2971. struct drm_display_mode *mode2 = NULL;
  2972. uint32_t pixel_bytes1 = 0;
  2973. uint32_t pixel_bytes2 = 0;
  2974. /* Guess line buffer size to be 8192 pixels */
  2975. u32 lb_size = 8192;
  2976. if (!rdev->mode_info.mode_config_initialized)
  2977. return;
  2978. radeon_update_display_priority(rdev);
  2979. if (rdev->mode_info.crtcs[0]->base.enabled) {
  2980. const struct drm_framebuffer *fb =
  2981. rdev->mode_info.crtcs[0]->base.primary->fb;
  2982. mode1 = &rdev->mode_info.crtcs[0]->base.mode;
  2983. pixel_bytes1 = fb->format->cpp[0];
  2984. }
  2985. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  2986. if (rdev->mode_info.crtcs[1]->base.enabled) {
  2987. const struct drm_framebuffer *fb =
  2988. rdev->mode_info.crtcs[1]->base.primary->fb;
  2989. mode2 = &rdev->mode_info.crtcs[1]->base.mode;
  2990. pixel_bytes2 = fb->format->cpp[0];
  2991. }
  2992. }
  2993. min_mem_eff.full = dfixed_const_8(0);
  2994. /* get modes */
  2995. if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
  2996. uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
  2997. mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
  2998. mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
  2999. /* check crtc enables */
  3000. if (mode2)
  3001. mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
  3002. if (mode1)
  3003. mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
  3004. WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
  3005. }
  3006. /*
  3007. * determine is there is enough bw for current mode
  3008. */
  3009. sclk_ff = rdev->pm.sclk;
  3010. mclk_ff = rdev->pm.mclk;
  3011. temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
  3012. temp_ff.full = dfixed_const(temp);
  3013. mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
  3014. pix_clk.full = 0;
  3015. pix_clk2.full = 0;
  3016. peak_disp_bw.full = 0;
  3017. if (mode1) {
  3018. temp_ff.full = dfixed_const(1000);
  3019. pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
  3020. pix_clk.full = dfixed_div(pix_clk, temp_ff);
  3021. temp_ff.full = dfixed_const(pixel_bytes1);
  3022. peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
  3023. }
  3024. if (mode2) {
  3025. temp_ff.full = dfixed_const(1000);
  3026. pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
  3027. pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
  3028. temp_ff.full = dfixed_const(pixel_bytes2);
  3029. peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
  3030. }
  3031. mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
  3032. if (peak_disp_bw.full >= mem_bw.full) {
  3033. DRM_ERROR("You may not have enough display bandwidth for current mode\n"
  3034. "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
  3035. }
  3036. /* Get values from the EXT_MEM_CNTL register...converting its contents. */
  3037. temp = RREG32(RADEON_MEM_TIMING_CNTL);
  3038. if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
  3039. mem_trcd = ((temp >> 2) & 0x3) + 1;
  3040. mem_trp = ((temp & 0x3)) + 1;
  3041. mem_tras = ((temp & 0x70) >> 4) + 1;
  3042. } else if (rdev->family == CHIP_R300 ||
  3043. rdev->family == CHIP_R350) { /* r300, r350 */
  3044. mem_trcd = (temp & 0x7) + 1;
  3045. mem_trp = ((temp >> 8) & 0x7) + 1;
  3046. mem_tras = ((temp >> 11) & 0xf) + 4;
  3047. } else if (rdev->family == CHIP_RV350 ||
  3048. rdev->family == CHIP_RV380) {
  3049. /* rv3x0 */
  3050. mem_trcd = (temp & 0x7) + 3;
  3051. mem_trp = ((temp >> 8) & 0x7) + 3;
  3052. mem_tras = ((temp >> 11) & 0xf) + 6;
  3053. } else if (rdev->family == CHIP_R420 ||
  3054. rdev->family == CHIP_R423 ||
  3055. rdev->family == CHIP_RV410) {
  3056. /* r4xx */
  3057. mem_trcd = (temp & 0xf) + 3;
  3058. if (mem_trcd > 15)
  3059. mem_trcd = 15;
  3060. mem_trp = ((temp >> 8) & 0xf) + 3;
  3061. if (mem_trp > 15)
  3062. mem_trp = 15;
  3063. mem_tras = ((temp >> 12) & 0x1f) + 6;
  3064. if (mem_tras > 31)
  3065. mem_tras = 31;
  3066. } else { /* RV200, R200 */
  3067. mem_trcd = (temp & 0x7) + 1;
  3068. mem_trp = ((temp >> 8) & 0x7) + 1;
  3069. mem_tras = ((temp >> 12) & 0xf) + 4;
  3070. }
  3071. /* convert to FF */
  3072. trcd_ff.full = dfixed_const(mem_trcd);
  3073. trp_ff.full = dfixed_const(mem_trp);
  3074. tras_ff.full = dfixed_const(mem_tras);
  3075. /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
  3076. temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
  3077. data = (temp & (7 << 20)) >> 20;
  3078. if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
  3079. if (rdev->family == CHIP_RS480) /* don't think rs400 */
  3080. tcas_ff = memtcas_rs480_ff[data];
  3081. else
  3082. tcas_ff = memtcas_ff[data];
  3083. } else
  3084. tcas_ff = memtcas2_ff[data];
  3085. if (rdev->family == CHIP_RS400 ||
  3086. rdev->family == CHIP_RS480) {
  3087. /* extra cas latency stored in bits 23-25 0-4 clocks */
  3088. data = (temp >> 23) & 0x7;
  3089. if (data < 5)
  3090. tcas_ff.full += dfixed_const(data);
  3091. }
  3092. if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
  3093. /* on the R300, Tcas is included in Trbs.
  3094. */
  3095. temp = RREG32(RADEON_MEM_CNTL);
  3096. data = (R300_MEM_NUM_CHANNELS_MASK & temp);
  3097. if (data == 1) {
  3098. if (R300_MEM_USE_CD_CH_ONLY & temp) {
  3099. temp = RREG32(R300_MC_IND_INDEX);
  3100. temp &= ~R300_MC_IND_ADDR_MASK;
  3101. temp |= R300_MC_READ_CNTL_CD_mcind;
  3102. WREG32(R300_MC_IND_INDEX, temp);
  3103. temp = RREG32(R300_MC_IND_DATA);
  3104. data = (R300_MEM_RBS_POSITION_C_MASK & temp);
  3105. } else {
  3106. temp = RREG32(R300_MC_READ_CNTL_AB);
  3107. data = (R300_MEM_RBS_POSITION_A_MASK & temp);
  3108. }
  3109. } else {
  3110. temp = RREG32(R300_MC_READ_CNTL_AB);
  3111. data = (R300_MEM_RBS_POSITION_A_MASK & temp);
  3112. }
  3113. if (rdev->family == CHIP_RV410 ||
  3114. rdev->family == CHIP_R420 ||
  3115. rdev->family == CHIP_R423)
  3116. trbs_ff = memtrbs_r4xx[data];
  3117. else
  3118. trbs_ff = memtrbs[data];
  3119. tcas_ff.full += trbs_ff.full;
  3120. }
  3121. sclk_eff_ff.full = sclk_ff.full;
  3122. if (rdev->flags & RADEON_IS_AGP) {
  3123. fixed20_12 agpmode_ff;
  3124. agpmode_ff.full = dfixed_const(radeon_agpmode);
  3125. temp_ff.full = dfixed_const_666(16);
  3126. sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
  3127. }
  3128. /* TODO PCIE lanes may affect this - agpmode == 16?? */
  3129. if (ASIC_IS_R300(rdev)) {
  3130. sclk_delay_ff.full = dfixed_const(250);
  3131. } else {
  3132. if ((rdev->family == CHIP_RV100) ||
  3133. rdev->flags & RADEON_IS_IGP) {
  3134. if (rdev->mc.vram_is_ddr)
  3135. sclk_delay_ff.full = dfixed_const(41);
  3136. else
  3137. sclk_delay_ff.full = dfixed_const(33);
  3138. } else {
  3139. if (rdev->mc.vram_width == 128)
  3140. sclk_delay_ff.full = dfixed_const(57);
  3141. else
  3142. sclk_delay_ff.full = dfixed_const(41);
  3143. }
  3144. }
  3145. mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
  3146. if (rdev->mc.vram_is_ddr) {
  3147. if (rdev->mc.vram_width == 32) {
  3148. k1.full = dfixed_const(40);
  3149. c = 3;
  3150. } else {
  3151. k1.full = dfixed_const(20);
  3152. c = 1;
  3153. }
  3154. } else {
  3155. k1.full = dfixed_const(40);
  3156. c = 3;
  3157. }
  3158. temp_ff.full = dfixed_const(2);
  3159. mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
  3160. temp_ff.full = dfixed_const(c);
  3161. mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
  3162. temp_ff.full = dfixed_const(4);
  3163. mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
  3164. mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
  3165. mc_latency_mclk.full += k1.full;
  3166. mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
  3167. mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
  3168. /*
  3169. HW cursor time assuming worst case of full size colour cursor.
  3170. */
  3171. temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
  3172. temp_ff.full += trcd_ff.full;
  3173. if (temp_ff.full < tras_ff.full)
  3174. temp_ff.full = tras_ff.full;
  3175. cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
  3176. temp_ff.full = dfixed_const(cur_size);
  3177. cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
  3178. /*
  3179. Find the total latency for the display data.
  3180. */
  3181. disp_latency_overhead.full = dfixed_const(8);
  3182. disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
  3183. mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
  3184. mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
  3185. if (mc_latency_mclk.full > mc_latency_sclk.full)
  3186. disp_latency.full = mc_latency_mclk.full;
  3187. else
  3188. disp_latency.full = mc_latency_sclk.full;
  3189. /* setup Max GRPH_STOP_REQ default value */
  3190. if (ASIC_IS_RV100(rdev))
  3191. max_stop_req = 0x5c;
  3192. else
  3193. max_stop_req = 0x7c;
  3194. if (mode1) {
  3195. /* CRTC1
  3196. Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
  3197. GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
  3198. */
  3199. stop_req = mode1->hdisplay * pixel_bytes1 / 16;
  3200. if (stop_req > max_stop_req)
  3201. stop_req = max_stop_req;
  3202. /*
  3203. Find the drain rate of the display buffer.
  3204. */
  3205. temp_ff.full = dfixed_const((16/pixel_bytes1));
  3206. disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
  3207. /*
  3208. Find the critical point of the display buffer.
  3209. */
  3210. crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
  3211. crit_point_ff.full += dfixed_const_half(0);
  3212. critical_point = dfixed_trunc(crit_point_ff);
  3213. if (rdev->disp_priority == 2) {
  3214. critical_point = 0;
  3215. }
  3216. /*
  3217. The critical point should never be above max_stop_req-4. Setting
  3218. GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
  3219. */
  3220. if (max_stop_req - critical_point < 4)
  3221. critical_point = 0;
  3222. if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
  3223. /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
  3224. critical_point = 0x10;
  3225. }
  3226. temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
  3227. temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
  3228. temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
  3229. temp &= ~(RADEON_GRPH_START_REQ_MASK);
  3230. if ((rdev->family == CHIP_R350) &&
  3231. (stop_req > 0x15)) {
  3232. stop_req -= 0x10;
  3233. }
  3234. temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
  3235. temp |= RADEON_GRPH_BUFFER_SIZE;
  3236. temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
  3237. RADEON_GRPH_CRITICAL_AT_SOF |
  3238. RADEON_GRPH_STOP_CNTL);
  3239. /*
  3240. Write the result into the register.
  3241. */
  3242. WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
  3243. (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
  3244. #if 0
  3245. if ((rdev->family == CHIP_RS400) ||
  3246. (rdev->family == CHIP_RS480)) {
  3247. /* attempt to program RS400 disp regs correctly ??? */
  3248. temp = RREG32(RS400_DISP1_REG_CNTL);
  3249. temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
  3250. RS400_DISP1_STOP_REQ_LEVEL_MASK);
  3251. WREG32(RS400_DISP1_REQ_CNTL1, (temp |
  3252. (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
  3253. (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
  3254. temp = RREG32(RS400_DMIF_MEM_CNTL1);
  3255. temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
  3256. RS400_DISP1_CRITICAL_POINT_STOP_MASK);
  3257. WREG32(RS400_DMIF_MEM_CNTL1, (temp |
  3258. (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
  3259. (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
  3260. }
  3261. #endif
  3262. DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
  3263. /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
  3264. (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
  3265. }
  3266. if (mode2) {
  3267. u32 grph2_cntl;
  3268. stop_req = mode2->hdisplay * pixel_bytes2 / 16;
  3269. if (stop_req > max_stop_req)
  3270. stop_req = max_stop_req;
  3271. /*
  3272. Find the drain rate of the display buffer.
  3273. */
  3274. temp_ff.full = dfixed_const((16/pixel_bytes2));
  3275. disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
  3276. grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
  3277. grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
  3278. grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
  3279. grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
  3280. if ((rdev->family == CHIP_R350) &&
  3281. (stop_req > 0x15)) {
  3282. stop_req -= 0x10;
  3283. }
  3284. grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
  3285. grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
  3286. grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
  3287. RADEON_GRPH_CRITICAL_AT_SOF |
  3288. RADEON_GRPH_STOP_CNTL);
  3289. if ((rdev->family == CHIP_RS100) ||
  3290. (rdev->family == CHIP_RS200))
  3291. critical_point2 = 0;
  3292. else {
  3293. temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
  3294. temp_ff.full = dfixed_const(temp);
  3295. temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
  3296. if (sclk_ff.full < temp_ff.full)
  3297. temp_ff.full = sclk_ff.full;
  3298. read_return_rate.full = temp_ff.full;
  3299. if (mode1) {
  3300. temp_ff.full = read_return_rate.full - disp_drain_rate.full;
  3301. time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
  3302. } else {
  3303. time_disp1_drop_priority.full = 0;
  3304. }
  3305. crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
  3306. crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
  3307. crit_point_ff.full += dfixed_const_half(0);
  3308. critical_point2 = dfixed_trunc(crit_point_ff);
  3309. if (rdev->disp_priority == 2) {
  3310. critical_point2 = 0;
  3311. }
  3312. if (max_stop_req - critical_point2 < 4)
  3313. critical_point2 = 0;
  3314. }
  3315. if (critical_point2 == 0 && rdev->family == CHIP_R300) {
  3316. /* some R300 cards have problem with this set to 0 */
  3317. critical_point2 = 0x10;
  3318. }
  3319. WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
  3320. (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
  3321. if ((rdev->family == CHIP_RS400) ||
  3322. (rdev->family == CHIP_RS480)) {
  3323. #if 0
  3324. /* attempt to program RS400 disp2 regs correctly ??? */
  3325. temp = RREG32(RS400_DISP2_REQ_CNTL1);
  3326. temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
  3327. RS400_DISP2_STOP_REQ_LEVEL_MASK);
  3328. WREG32(RS400_DISP2_REQ_CNTL1, (temp |
  3329. (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
  3330. (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
  3331. temp = RREG32(RS400_DISP2_REQ_CNTL2);
  3332. temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
  3333. RS400_DISP2_CRITICAL_POINT_STOP_MASK);
  3334. WREG32(RS400_DISP2_REQ_CNTL2, (temp |
  3335. (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
  3336. (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
  3337. #endif
  3338. WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
  3339. WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
  3340. WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
  3341. WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
  3342. }
  3343. DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
  3344. (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
  3345. }
  3346. /* Save number of lines the linebuffer leads before the scanout */
  3347. if (mode1)
  3348. rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay);
  3349. if (mode2)
  3350. rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay);
  3351. }
  3352. int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
  3353. {
  3354. uint32_t scratch;
  3355. uint32_t tmp = 0;
  3356. unsigned i;
  3357. int r;
  3358. r = radeon_scratch_get(rdev, &scratch);
  3359. if (r) {
  3360. DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
  3361. return r;
  3362. }
  3363. WREG32(scratch, 0xCAFEDEAD);
  3364. r = radeon_ring_lock(rdev, ring, 2);
  3365. if (r) {
  3366. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  3367. radeon_scratch_free(rdev, scratch);
  3368. return r;
  3369. }
  3370. radeon_ring_write(ring, PACKET0(scratch, 0));
  3371. radeon_ring_write(ring, 0xDEADBEEF);
  3372. radeon_ring_unlock_commit(rdev, ring, false);
  3373. for (i = 0; i < rdev->usec_timeout; i++) {
  3374. tmp = RREG32(scratch);
  3375. if (tmp == 0xDEADBEEF) {
  3376. break;
  3377. }
  3378. udelay(1);
  3379. }
  3380. if (i < rdev->usec_timeout) {
  3381. DRM_INFO("ring test succeeded in %d usecs\n", i);
  3382. } else {
  3383. DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
  3384. scratch, tmp);
  3385. r = -EINVAL;
  3386. }
  3387. radeon_scratch_free(rdev, scratch);
  3388. return r;
  3389. }
  3390. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  3391. {
  3392. struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
  3393. if (ring->rptr_save_reg) {
  3394. u32 next_rptr = ring->wptr + 2 + 3;
  3395. radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
  3396. radeon_ring_write(ring, next_rptr);
  3397. }
  3398. radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
  3399. radeon_ring_write(ring, ib->gpu_addr);
  3400. radeon_ring_write(ring, ib->length_dw);
  3401. }
  3402. int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
  3403. {
  3404. struct radeon_ib ib;
  3405. uint32_t scratch;
  3406. uint32_t tmp = 0;
  3407. unsigned i;
  3408. int r;
  3409. r = radeon_scratch_get(rdev, &scratch);
  3410. if (r) {
  3411. DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
  3412. return r;
  3413. }
  3414. WREG32(scratch, 0xCAFEDEAD);
  3415. r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
  3416. if (r) {
  3417. DRM_ERROR("radeon: failed to get ib (%d).\n", r);
  3418. goto free_scratch;
  3419. }
  3420. ib.ptr[0] = PACKET0(scratch, 0);
  3421. ib.ptr[1] = 0xDEADBEEF;
  3422. ib.ptr[2] = PACKET2(0);
  3423. ib.ptr[3] = PACKET2(0);
  3424. ib.ptr[4] = PACKET2(0);
  3425. ib.ptr[5] = PACKET2(0);
  3426. ib.ptr[6] = PACKET2(0);
  3427. ib.ptr[7] = PACKET2(0);
  3428. ib.length_dw = 8;
  3429. r = radeon_ib_schedule(rdev, &ib, NULL, false);
  3430. if (r) {
  3431. DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
  3432. goto free_ib;
  3433. }
  3434. r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(
  3435. RADEON_USEC_IB_TEST_TIMEOUT));
  3436. if (r < 0) {
  3437. DRM_ERROR("radeon: fence wait failed (%d).\n", r);
  3438. goto free_ib;
  3439. } else if (r == 0) {
  3440. DRM_ERROR("radeon: fence wait timed out.\n");
  3441. r = -ETIMEDOUT;
  3442. goto free_ib;
  3443. }
  3444. r = 0;
  3445. for (i = 0; i < rdev->usec_timeout; i++) {
  3446. tmp = RREG32(scratch);
  3447. if (tmp == 0xDEADBEEF) {
  3448. break;
  3449. }
  3450. udelay(1);
  3451. }
  3452. if (i < rdev->usec_timeout) {
  3453. DRM_INFO("ib test succeeded in %u usecs\n", i);
  3454. } else {
  3455. DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
  3456. scratch, tmp);
  3457. r = -EINVAL;
  3458. }
  3459. free_ib:
  3460. radeon_ib_free(rdev, &ib);
  3461. free_scratch:
  3462. radeon_scratch_free(rdev, scratch);
  3463. return r;
  3464. }
  3465. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
  3466. {
  3467. /* Shutdown CP we shouldn't need to do that but better be safe than
  3468. * sorry
  3469. */
  3470. rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
  3471. WREG32(R_000740_CP_CSQ_CNTL, 0);
  3472. /* Save few CRTC registers */
  3473. save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
  3474. save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
  3475. save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
  3476. save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
  3477. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3478. save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
  3479. save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
  3480. }
  3481. /* Disable VGA aperture access */
  3482. WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
  3483. /* Disable cursor, overlay, crtc */
  3484. WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
  3485. WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
  3486. S_000054_CRTC_DISPLAY_DIS(1));
  3487. WREG32(R_000050_CRTC_GEN_CNTL,
  3488. (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
  3489. S_000050_CRTC_DISP_REQ_EN_B(1));
  3490. WREG32(R_000420_OV0_SCALE_CNTL,
  3491. C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
  3492. WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
  3493. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3494. WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
  3495. S_000360_CUR2_LOCK(1));
  3496. WREG32(R_0003F8_CRTC2_GEN_CNTL,
  3497. (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
  3498. S_0003F8_CRTC2_DISPLAY_DIS(1) |
  3499. S_0003F8_CRTC2_DISP_REQ_EN_B(1));
  3500. WREG32(R_000360_CUR2_OFFSET,
  3501. C_000360_CUR2_LOCK & save->CUR2_OFFSET);
  3502. }
  3503. }
  3504. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
  3505. {
  3506. /* Update base address for crtc */
  3507. WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
  3508. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3509. WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
  3510. }
  3511. /* Restore CRTC registers */
  3512. WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
  3513. WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
  3514. WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
  3515. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  3516. WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
  3517. }
  3518. }
  3519. void r100_vga_render_disable(struct radeon_device *rdev)
  3520. {
  3521. u32 tmp;
  3522. tmp = RREG8(R_0003C2_GENMO_WT);
  3523. WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
  3524. }
  3525. static void r100_mc_program(struct radeon_device *rdev)
  3526. {
  3527. struct r100_mc_save save;
  3528. /* Stops all mc clients */
  3529. r100_mc_stop(rdev, &save);
  3530. if (rdev->flags & RADEON_IS_AGP) {
  3531. WREG32(R_00014C_MC_AGP_LOCATION,
  3532. S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
  3533. S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
  3534. WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
  3535. if (rdev->family > CHIP_RV200)
  3536. WREG32(R_00015C_AGP_BASE_2,
  3537. upper_32_bits(rdev->mc.agp_base) & 0xff);
  3538. } else {
  3539. WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
  3540. WREG32(R_000170_AGP_BASE, 0);
  3541. if (rdev->family > CHIP_RV200)
  3542. WREG32(R_00015C_AGP_BASE_2, 0);
  3543. }
  3544. /* Wait for mc idle */
  3545. if (r100_mc_wait_for_idle(rdev))
  3546. dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
  3547. /* Program MC, should be a 32bits limited address space */
  3548. WREG32(R_000148_MC_FB_LOCATION,
  3549. S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
  3550. S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
  3551. r100_mc_resume(rdev, &save);
  3552. }
  3553. static void r100_clock_startup(struct radeon_device *rdev)
  3554. {
  3555. u32 tmp;
  3556. if (radeon_dynclks != -1 && radeon_dynclks)
  3557. radeon_legacy_set_clock_gating(rdev, 1);
  3558. /* We need to force on some of the block */
  3559. tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
  3560. tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
  3561. if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
  3562. tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
  3563. WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
  3564. }
  3565. static int r100_startup(struct radeon_device *rdev)
  3566. {
  3567. int r;
  3568. /* set common regs */
  3569. r100_set_common_regs(rdev);
  3570. /* program mc */
  3571. r100_mc_program(rdev);
  3572. /* Resume clock */
  3573. r100_clock_startup(rdev);
  3574. /* Initialize GART (initialize after TTM so we can allocate
  3575. * memory through TTM but finalize after TTM) */
  3576. r100_enable_bm(rdev);
  3577. if (rdev->flags & RADEON_IS_PCI) {
  3578. r = r100_pci_gart_enable(rdev);
  3579. if (r)
  3580. return r;
  3581. }
  3582. /* allocate wb buffer */
  3583. r = radeon_wb_init(rdev);
  3584. if (r)
  3585. return r;
  3586. r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
  3587. if (r) {
  3588. dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
  3589. return r;
  3590. }
  3591. /* Enable IRQ */
  3592. if (!rdev->irq.installed) {
  3593. r = radeon_irq_kms_init(rdev);
  3594. if (r)
  3595. return r;
  3596. }
  3597. r100_irq_set(rdev);
  3598. rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
  3599. /* 1M ring buffer */
  3600. r = r100_cp_init(rdev, 1024 * 1024);
  3601. if (r) {
  3602. dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
  3603. return r;
  3604. }
  3605. r = radeon_ib_pool_init(rdev);
  3606. if (r) {
  3607. dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
  3608. return r;
  3609. }
  3610. return 0;
  3611. }
  3612. int r100_resume(struct radeon_device *rdev)
  3613. {
  3614. int r;
  3615. /* Make sur GART are not working */
  3616. if (rdev->flags & RADEON_IS_PCI)
  3617. r100_pci_gart_disable(rdev);
  3618. /* Resume clock before doing reset */
  3619. r100_clock_startup(rdev);
  3620. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  3621. if (radeon_asic_reset(rdev)) {
  3622. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  3623. RREG32(R_000E40_RBBM_STATUS),
  3624. RREG32(R_0007C0_CP_STAT));
  3625. }
  3626. /* post */
  3627. radeon_combios_asic_init(rdev->ddev);
  3628. /* Resume clock after posting */
  3629. r100_clock_startup(rdev);
  3630. /* Initialize surface registers */
  3631. radeon_surface_init(rdev);
  3632. rdev->accel_working = true;
  3633. r = r100_startup(rdev);
  3634. if (r) {
  3635. rdev->accel_working = false;
  3636. }
  3637. return r;
  3638. }
  3639. int r100_suspend(struct radeon_device *rdev)
  3640. {
  3641. radeon_pm_suspend(rdev);
  3642. r100_cp_disable(rdev);
  3643. radeon_wb_disable(rdev);
  3644. r100_irq_disable(rdev);
  3645. if (rdev->flags & RADEON_IS_PCI)
  3646. r100_pci_gart_disable(rdev);
  3647. return 0;
  3648. }
  3649. void r100_fini(struct radeon_device *rdev)
  3650. {
  3651. radeon_pm_fini(rdev);
  3652. r100_cp_fini(rdev);
  3653. radeon_wb_fini(rdev);
  3654. radeon_ib_pool_fini(rdev);
  3655. radeon_gem_fini(rdev);
  3656. if (rdev->flags & RADEON_IS_PCI)
  3657. r100_pci_gart_fini(rdev);
  3658. radeon_agp_fini(rdev);
  3659. radeon_irq_kms_fini(rdev);
  3660. radeon_fence_driver_fini(rdev);
  3661. radeon_bo_fini(rdev);
  3662. radeon_atombios_fini(rdev);
  3663. kfree(rdev->bios);
  3664. rdev->bios = NULL;
  3665. }
  3666. /*
  3667. * Due to how kexec works, it can leave the hw fully initialised when it
  3668. * boots the new kernel. However doing our init sequence with the CP and
  3669. * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
  3670. * do some quick sanity checks and restore sane values to avoid this
  3671. * problem.
  3672. */
  3673. void r100_restore_sanity(struct radeon_device *rdev)
  3674. {
  3675. u32 tmp;
  3676. tmp = RREG32(RADEON_CP_CSQ_CNTL);
  3677. if (tmp) {
  3678. WREG32(RADEON_CP_CSQ_CNTL, 0);
  3679. }
  3680. tmp = RREG32(RADEON_CP_RB_CNTL);
  3681. if (tmp) {
  3682. WREG32(RADEON_CP_RB_CNTL, 0);
  3683. }
  3684. tmp = RREG32(RADEON_SCRATCH_UMSK);
  3685. if (tmp) {
  3686. WREG32(RADEON_SCRATCH_UMSK, 0);
  3687. }
  3688. }
  3689. int r100_init(struct radeon_device *rdev)
  3690. {
  3691. int r;
  3692. /* Register debugfs file specific to this group of asics */
  3693. r100_debugfs_mc_info_init(rdev);
  3694. /* Disable VGA */
  3695. r100_vga_render_disable(rdev);
  3696. /* Initialize scratch registers */
  3697. radeon_scratch_init(rdev);
  3698. /* Initialize surface registers */
  3699. radeon_surface_init(rdev);
  3700. /* sanity check some register to avoid hangs like after kexec */
  3701. r100_restore_sanity(rdev);
  3702. /* TODO: disable VGA need to use VGA request */
  3703. /* BIOS*/
  3704. if (!radeon_get_bios(rdev)) {
  3705. if (ASIC_IS_AVIVO(rdev))
  3706. return -EINVAL;
  3707. }
  3708. if (rdev->is_atom_bios) {
  3709. dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
  3710. return -EINVAL;
  3711. } else {
  3712. r = radeon_combios_init(rdev);
  3713. if (r)
  3714. return r;
  3715. }
  3716. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  3717. if (radeon_asic_reset(rdev)) {
  3718. dev_warn(rdev->dev,
  3719. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  3720. RREG32(R_000E40_RBBM_STATUS),
  3721. RREG32(R_0007C0_CP_STAT));
  3722. }
  3723. /* check if cards are posted or not */
  3724. if (radeon_boot_test_post_card(rdev) == false)
  3725. return -EINVAL;
  3726. /* Set asic errata */
  3727. r100_errata(rdev);
  3728. /* Initialize clocks */
  3729. radeon_get_clock_info(rdev->ddev);
  3730. /* initialize AGP */
  3731. if (rdev->flags & RADEON_IS_AGP) {
  3732. r = radeon_agp_init(rdev);
  3733. if (r) {
  3734. radeon_agp_disable(rdev);
  3735. }
  3736. }
  3737. /* initialize VRAM */
  3738. r100_mc_init(rdev);
  3739. /* Fence driver */
  3740. radeon_fence_driver_init(rdev);
  3741. /* Memory manager */
  3742. r = radeon_bo_init(rdev);
  3743. if (r)
  3744. return r;
  3745. if (rdev->flags & RADEON_IS_PCI) {
  3746. r = r100_pci_gart_init(rdev);
  3747. if (r)
  3748. return r;
  3749. }
  3750. r100_set_safe_registers(rdev);
  3751. /* Initialize power management */
  3752. radeon_pm_init(rdev);
  3753. rdev->accel_working = true;
  3754. r = r100_startup(rdev);
  3755. if (r) {
  3756. /* Somethings want wront with the accel init stop accel */
  3757. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  3758. r100_cp_fini(rdev);
  3759. radeon_wb_fini(rdev);
  3760. radeon_ib_pool_fini(rdev);
  3761. radeon_irq_kms_fini(rdev);
  3762. if (rdev->flags & RADEON_IS_PCI)
  3763. r100_pci_gart_fini(rdev);
  3764. rdev->accel_working = false;
  3765. }
  3766. return 0;
  3767. }
  3768. uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
  3769. {
  3770. unsigned long flags;
  3771. uint32_t ret;
  3772. spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
  3773. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  3774. ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  3775. spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
  3776. return ret;
  3777. }
  3778. void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  3779. {
  3780. unsigned long flags;
  3781. spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
  3782. writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
  3783. writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
  3784. spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
  3785. }
  3786. u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
  3787. {
  3788. if (reg < rdev->rio_mem_size)
  3789. return ioread32(rdev->rio_mem + reg);
  3790. else {
  3791. iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
  3792. return ioread32(rdev->rio_mem + RADEON_MM_DATA);
  3793. }
  3794. }
  3795. void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
  3796. {
  3797. if (reg < rdev->rio_mem_size)
  3798. iowrite32(v, rdev->rio_mem + reg);
  3799. else {
  3800. iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
  3801. iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
  3802. }
  3803. }