ati_pcigart.c 6.1 KB

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  1. /*
  2. * \file ati_pcigart.c
  3. * ATI PCI GART support
  4. *
  5. * \author Gareth Hughes <[email protected]>
  6. */
  7. /*
  8. * Created: Wed Dec 13 21:52:19 2000 by [email protected]
  9. *
  10. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  11. * All Rights Reserved.
  12. *
  13. * Permission is hereby granted, free of charge, to any person obtaining a
  14. * copy of this software and associated documentation files (the "Software"),
  15. * to deal in the Software without restriction, including without limitation
  16. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  17. * and/or sell copies of the Software, and to permit persons to whom the
  18. * Software is furnished to do so, subject to the following conditions:
  19. *
  20. * The above copyright notice and this permission notice (including the next
  21. * paragraph) shall be included in all copies or substantial portions of the
  22. * Software.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  25. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  26. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  27. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  28. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  29. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  30. * DEALINGS IN THE SOFTWARE.
  31. */
  32. #include <linux/export.h>
  33. #include <linux/pci.h>
  34. #include <drm/drm_device.h>
  35. #include <drm/drm_legacy.h>
  36. #include <drm/drm_print.h>
  37. #include "ati_pcigart.h"
  38. # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
  39. static int drm_ati_alloc_pcigart_table(struct drm_device *dev,
  40. struct drm_ati_pcigart_info *gart_info)
  41. {
  42. drm_dma_handle_t *dmah = kmalloc(sizeof(drm_dma_handle_t), GFP_KERNEL);
  43. if (!dmah)
  44. return -ENOMEM;
  45. dmah->size = gart_info->table_size;
  46. dmah->vaddr = dma_alloc_coherent(dev->dev,
  47. dmah->size,
  48. &dmah->busaddr,
  49. GFP_KERNEL);
  50. if (!dmah->vaddr) {
  51. kfree(dmah);
  52. return -ENOMEM;
  53. }
  54. gart_info->table_handle = dmah;
  55. return 0;
  56. }
  57. static void drm_ati_free_pcigart_table(struct drm_device *dev,
  58. struct drm_ati_pcigart_info *gart_info)
  59. {
  60. drm_dma_handle_t *dmah = gart_info->table_handle;
  61. dma_free_coherent(dev->dev, dmah->size, dmah->vaddr, dmah->busaddr);
  62. kfree(dmah);
  63. gart_info->table_handle = NULL;
  64. }
  65. int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
  66. {
  67. struct drm_sg_mem *entry = dev->sg;
  68. struct pci_dev *pdev = to_pci_dev(dev->dev);
  69. unsigned long pages;
  70. int i;
  71. int max_pages;
  72. /* we need to support large memory configurations */
  73. if (!entry) {
  74. DRM_ERROR("no scatter/gather memory!\n");
  75. return 0;
  76. }
  77. if (gart_info->bus_addr) {
  78. max_pages = (gart_info->table_size / sizeof(u32));
  79. pages = (entry->pages <= max_pages)
  80. ? entry->pages : max_pages;
  81. for (i = 0; i < pages; i++) {
  82. if (!entry->busaddr[i])
  83. break;
  84. dma_unmap_page(&pdev->dev, entry->busaddr[i],
  85. PAGE_SIZE, DMA_BIDIRECTIONAL);
  86. }
  87. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
  88. gart_info->bus_addr = 0;
  89. }
  90. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN &&
  91. gart_info->table_handle) {
  92. drm_ati_free_pcigart_table(dev, gart_info);
  93. }
  94. return 1;
  95. }
  96. int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
  97. {
  98. struct drm_local_map *map = &gart_info->mapping;
  99. struct drm_sg_mem *entry = dev->sg;
  100. struct pci_dev *pdev = to_pci_dev(dev->dev);
  101. void *address = NULL;
  102. unsigned long pages;
  103. u32 *pci_gart = NULL, page_base, gart_idx;
  104. dma_addr_t bus_address = 0;
  105. int i, j, ret = -ENOMEM;
  106. int max_ati_pages, max_real_pages;
  107. if (!entry) {
  108. DRM_ERROR("no scatter/gather memory!\n");
  109. goto done;
  110. }
  111. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
  112. DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
  113. if (dma_set_mask(&pdev->dev, gart_info->table_mask)) {
  114. DRM_ERROR("fail to set dma mask to 0x%Lx\n",
  115. (unsigned long long)gart_info->table_mask);
  116. ret = -EFAULT;
  117. goto done;
  118. }
  119. ret = drm_ati_alloc_pcigart_table(dev, gart_info);
  120. if (ret) {
  121. DRM_ERROR("cannot allocate PCI GART page!\n");
  122. goto done;
  123. }
  124. pci_gart = gart_info->table_handle->vaddr;
  125. address = gart_info->table_handle->vaddr;
  126. bus_address = gart_info->table_handle->busaddr;
  127. } else {
  128. address = gart_info->addr;
  129. bus_address = gart_info->bus_addr;
  130. DRM_DEBUG("PCI: Gart Table: VRAM %08LX mapped at %08lX\n",
  131. (unsigned long long)bus_address,
  132. (unsigned long)address);
  133. }
  134. max_ati_pages = (gart_info->table_size / sizeof(u32));
  135. max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
  136. pages = (entry->pages <= max_real_pages)
  137. ? entry->pages : max_real_pages;
  138. if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
  139. memset(pci_gart, 0, max_ati_pages * sizeof(u32));
  140. } else {
  141. memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u32));
  142. }
  143. gart_idx = 0;
  144. for (i = 0; i < pages; i++) {
  145. /* we need to support large memory configurations */
  146. entry->busaddr[i] = dma_map_page(&pdev->dev, entry->pagelist[i],
  147. 0, PAGE_SIZE, DMA_BIDIRECTIONAL);
  148. if (dma_mapping_error(&pdev->dev, entry->busaddr[i])) {
  149. DRM_ERROR("unable to map PCIGART pages!\n");
  150. drm_ati_pcigart_cleanup(dev, gart_info);
  151. address = NULL;
  152. bus_address = 0;
  153. ret = -ENOMEM;
  154. goto done;
  155. }
  156. page_base = (u32) entry->busaddr[i];
  157. for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
  158. u32 offset;
  159. u32 val;
  160. switch(gart_info->gart_reg_if) {
  161. case DRM_ATI_GART_IGP:
  162. val = page_base | 0xc;
  163. break;
  164. case DRM_ATI_GART_PCIE:
  165. val = (page_base >> 8) | 0xc;
  166. break;
  167. default:
  168. case DRM_ATI_GART_PCI:
  169. val = page_base;
  170. break;
  171. }
  172. if (gart_info->gart_table_location ==
  173. DRM_ATI_GART_MAIN) {
  174. pci_gart[gart_idx] = cpu_to_le32(val);
  175. } else {
  176. offset = gart_idx * sizeof(u32);
  177. writel(val, (void __iomem *)map->handle + offset);
  178. }
  179. gart_idx++;
  180. page_base += ATI_PCIGART_PAGE_SIZE;
  181. }
  182. }
  183. ret = 0;
  184. #ifdef CONFIG_X86
  185. wbinvd();
  186. #else
  187. mb();
  188. #endif
  189. done:
  190. gart_info->addr = address;
  191. gart_info->bus_addr = bus_address;
  192. return ret;
  193. }