panel-ilitek-ili9341.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ilitek ILI9341 TFT LCD drm_panel driver.
  4. *
  5. * This panel can be configured to support:
  6. * - 16-bit parallel RGB interface
  7. * - 18-bit parallel RGB interface
  8. * - 4-line serial spi interface
  9. *
  10. * Copyright (C) 2021 Dillon Min <[email protected]>
  11. *
  12. * For dbi+dpi part:
  13. * Derived from drivers/drm/gpu/panel/panel-ilitek-ili9322.c
  14. * the reuse of DBI abstraction part referred from Linus's patch
  15. * "drm/panel: s6e63m0: Switch to DBI abstraction for SPI"
  16. *
  17. * For only-dbi part, copy from David's code (drm/tiny/ili9341.c)
  18. * Copyright 2018 David Lechner <[email protected]>
  19. */
  20. #include <linux/bitops.h>
  21. #include <linux/delay.h>
  22. #include <linux/gpio/consumer.h>
  23. #include <linux/module.h>
  24. #include <linux/of_device.h>
  25. #include <linux/regulator/consumer.h>
  26. #include <linux/spi/spi.h>
  27. #include <video/mipi_display.h>
  28. #include <drm/drm_atomic_helper.h>
  29. #include <drm/drm_drv.h>
  30. #include <drm/drm_fb_helper.h>
  31. #include <drm/drm_gem_atomic_helper.h>
  32. #include <drm/drm_gem_dma_helper.h>
  33. #include <drm/drm_gem_framebuffer_helper.h>
  34. #include <drm/drm_mipi_dbi.h>
  35. #include <drm/drm_modes.h>
  36. #include <drm/drm_panel.h>
  37. #include <drm/drm_print.h>
  38. #define ILI9341_RGB_INTERFACE 0xb0 /* RGB Interface Signal Control */
  39. #define ILI9341_FRC 0xb1 /* Frame Rate Control register */
  40. #define ILI9341_DFC 0xb6 /* Display Function Control register */
  41. #define ILI9341_POWER1 0xc0 /* Power Control 1 register */
  42. #define ILI9341_POWER2 0xc1 /* Power Control 2 register */
  43. #define ILI9341_VCOM1 0xc5 /* VCOM Control 1 register */
  44. #define ILI9341_VCOM2 0xc7 /* VCOM Control 2 register */
  45. #define ILI9341_POWERA 0xcb /* Power control A register */
  46. #define ILI9341_POWERB 0xcf /* Power control B register */
  47. #define ILI9341_PGAMMA 0xe0 /* Positive Gamma Correction register */
  48. #define ILI9341_NGAMMA 0xe1 /* Negative Gamma Correction register */
  49. #define ILI9341_DTCA 0xe8 /* Driver timing control A */
  50. #define ILI9341_DTCB 0xea /* Driver timing control B */
  51. #define ILI9341_POWER_SEQ 0xed /* Power on sequence register */
  52. #define ILI9341_3GAMMA_EN 0xf2 /* 3 Gamma enable register */
  53. #define ILI9341_INTERFACE 0xf6 /* Interface control register */
  54. #define ILI9341_PRC 0xf7 /* Pump ratio control register */
  55. #define ILI9341_ETMOD 0xb7 /* Entry mode set */
  56. #define ILI9341_MADCTL_BGR BIT(3)
  57. #define ILI9341_MADCTL_MV BIT(5)
  58. #define ILI9341_MADCTL_MX BIT(6)
  59. #define ILI9341_MADCTL_MY BIT(7)
  60. #define ILI9341_POWER_B_LEN 3
  61. #define ILI9341_POWER_SEQ_LEN 4
  62. #define ILI9341_DTCA_LEN 3
  63. #define ILI9341_DTCB_LEN 2
  64. #define ILI9341_POWER_A_LEN 5
  65. #define ILI9341_DFC_1_LEN 2
  66. #define ILI9341_FRC_LEN 2
  67. #define ILI9341_VCOM_1_LEN 2
  68. #define ILI9341_DFC_2_LEN 4
  69. #define ILI9341_COLUMN_ADDR_LEN 4
  70. #define ILI9341_PAGE_ADDR_LEN 4
  71. #define ILI9341_INTERFACE_LEN 3
  72. #define ILI9341_PGAMMA_LEN 15
  73. #define ILI9341_NGAMMA_LEN 15
  74. #define ILI9341_CA_LEN 3
  75. #define ILI9341_PIXEL_DPI_16_BITS (BIT(6) | BIT(4))
  76. #define ILI9341_PIXEL_DPI_18_BITS (BIT(6) | BIT(5))
  77. #define ILI9341_GAMMA_CURVE_1 BIT(0)
  78. #define ILI9341_IF_WE_MODE BIT(0)
  79. #define ILI9341_IF_BIG_ENDIAN 0x00
  80. #define ILI9341_IF_DM_RGB BIT(2)
  81. #define ILI9341_IF_DM_INTERNAL 0x00
  82. #define ILI9341_IF_DM_VSYNC BIT(3)
  83. #define ILI9341_IF_RM_RGB BIT(1)
  84. #define ILI9341_IF_RIM_RGB 0x00
  85. #define ILI9341_COLUMN_ADDR 0x00ef
  86. #define ILI9341_PAGE_ADDR 0x013f
  87. #define ILI9341_RGB_EPL BIT(0)
  88. #define ILI9341_RGB_DPL BIT(1)
  89. #define ILI9341_RGB_HSPL BIT(2)
  90. #define ILI9341_RGB_VSPL BIT(3)
  91. #define ILI9341_RGB_DE_MODE BIT(6)
  92. #define ILI9341_RGB_DISP_PATH_MEM BIT(7)
  93. #define ILI9341_DBI_VCOMH_4P6V 0x23
  94. #define ILI9341_DBI_PWR_2_DEFAULT 0x10
  95. #define ILI9341_DBI_PRC_NORMAL 0x20
  96. #define ILI9341_DBI_VCOM_1_VMH_4P25V 0x3e
  97. #define ILI9341_DBI_VCOM_1_VML_1P5V 0x28
  98. #define ILI9341_DBI_VCOM_2_DEC_58 0x86
  99. #define ILI9341_DBI_FRC_DIVA 0x00
  100. #define ILI9341_DBI_FRC_RTNA 0x1b
  101. #define ILI9341_DBI_EMS_GAS BIT(0)
  102. #define ILI9341_DBI_EMS_DTS BIT(1)
  103. #define ILI9341_DBI_EMS_GON BIT(2)
  104. /* struct ili9341_config - the system specific ILI9341 configuration */
  105. struct ili9341_config {
  106. u32 max_spi_speed;
  107. /* mode: the drm display mode */
  108. const struct drm_display_mode mode;
  109. /* ca: TODO: need comments for this register */
  110. u8 ca[ILI9341_CA_LEN];
  111. /* power_b: TODO: need comments for this register */
  112. u8 power_b[ILI9341_POWER_B_LEN];
  113. /* power_seq: TODO: need comments for this register */
  114. u8 power_seq[ILI9341_POWER_SEQ_LEN];
  115. /* dtca: TODO: need comments for this register */
  116. u8 dtca[ILI9341_DTCA_LEN];
  117. /* dtcb: TODO: need comments for this register */
  118. u8 dtcb[ILI9341_DTCB_LEN];
  119. /* power_a: TODO: need comments for this register */
  120. u8 power_a[ILI9341_POWER_A_LEN];
  121. /* frc: Frame Rate Control (In Normal Mode/Full Colors) (B1h) */
  122. u8 frc[ILI9341_FRC_LEN];
  123. /* prc: TODO: need comments for this register */
  124. u8 prc;
  125. /* dfc_1: B6h DISCTRL (Display Function Control) */
  126. u8 dfc_1[ILI9341_DFC_1_LEN];
  127. /* power_1: Power Control 1 (C0h) */
  128. u8 power_1;
  129. /* power_2: Power Control 2 (C1h) */
  130. u8 power_2;
  131. /* vcom_1: VCOM Control 1(C5h) */
  132. u8 vcom_1[ILI9341_VCOM_1_LEN];
  133. /* vcom_2: VCOM Control 2(C7h) */
  134. u8 vcom_2;
  135. /* address_mode: Memory Access Control (36h) */
  136. u8 address_mode;
  137. /* g3amma_en: TODO: need comments for this register */
  138. u8 g3amma_en;
  139. /* rgb_interface: RGB Interface Signal Control (B0h) */
  140. u8 rgb_interface;
  141. /* dfc_2: refer to dfc_1 */
  142. u8 dfc_2[ILI9341_DFC_2_LEN];
  143. /* column_addr: Column Address Set (2Ah) */
  144. u8 column_addr[ILI9341_COLUMN_ADDR_LEN];
  145. /* page_addr: Page Address Set (2Bh) */
  146. u8 page_addr[ILI9341_PAGE_ADDR_LEN];
  147. /* interface: Interface Control (F6h) */
  148. u8 interface[ILI9341_INTERFACE_LEN];
  149. /*
  150. * pixel_format: This command sets the pixel format for the RGB
  151. * image data used by
  152. */
  153. u8 pixel_format;
  154. /*
  155. * gamma_curve: This command is used to select the desired Gamma
  156. * curve for the
  157. */
  158. u8 gamma_curve;
  159. /* pgamma: Positive Gamma Correction (E0h) */
  160. u8 pgamma[ILI9341_PGAMMA_LEN];
  161. /* ngamma: Negative Gamma Correction (E1h) */
  162. u8 ngamma[ILI9341_NGAMMA_LEN];
  163. };
  164. struct ili9341 {
  165. struct device *dev;
  166. const struct ili9341_config *conf;
  167. struct drm_panel panel;
  168. struct gpio_desc *reset_gpio;
  169. struct gpio_desc *dc_gpio;
  170. struct mipi_dbi *dbi;
  171. u32 max_spi_speed;
  172. struct regulator_bulk_data supplies[3];
  173. };
  174. /*
  175. * The Stm32f429-disco board has a panel ili9341 connected to ltdc controller
  176. */
  177. static const struct ili9341_config ili9341_stm32f429_disco_data = {
  178. .max_spi_speed = 10000000,
  179. .mode = {
  180. .clock = 6100,
  181. .hdisplay = 240,
  182. .hsync_start = 240 + 10,/* hfp 10 */
  183. .hsync_end = 240 + 10 + 10,/* hsync 10 */
  184. .htotal = 240 + 10 + 10 + 20,/* hbp 20 */
  185. .vdisplay = 320,
  186. .vsync_start = 320 + 4,/* vfp 4 */
  187. .vsync_end = 320 + 4 + 2,/* vsync 2 */
  188. .vtotal = 320 + 4 + 2 + 2,/* vbp 2 */
  189. .flags = 0,
  190. .width_mm = 65,
  191. .height_mm = 50,
  192. .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  193. },
  194. .ca = {0xc3, 0x08, 0x50},
  195. .power_b = {0x00, 0xc1, 0x30},
  196. .power_seq = {0x64, 0x03, 0x12, 0x81},
  197. .dtca = {0x85, 0x00, 0x78},
  198. .power_a = {0x39, 0x2c, 0x00, 0x34, 0x02},
  199. .prc = 0x20,
  200. .dtcb = {0x00, 0x00},
  201. /* 0x00 fosc, 0x1b 70hz */
  202. .frc = {0x00, 0x1b},
  203. /*
  204. * 0x0a Interval scan, AGND AGND AGND AGND
  205. * 0xa2 Normally white, G1 -> G320, S720 -> S1,
  206. * Scan Cycle 5 frames,85ms
  207. */
  208. .dfc_1 = {0x0a, 0xa2},
  209. /* 0x10 3.65v */
  210. .power_1 = 0x10,
  211. /* 0x10 AVDD=vci*2, VGH=vci*7, VGL=-vci*4 */
  212. .power_2 = 0x10,
  213. /* 0x45 VCOMH 4.425v, 0x15 VCOML -1.975*/
  214. .vcom_1 = {0x45, 0x15},
  215. /* 0x90 offset voltage, VMH-48, VML-48 */
  216. .vcom_2 = 0x90,
  217. /*
  218. * 0xc8 Row Address Order, Column Address Order
  219. * BGR 1
  220. */
  221. .address_mode = 0xc8,
  222. .g3amma_en = 0x00,
  223. /*
  224. * 0xc2
  225. * Display Data Path: Memory
  226. * RGB: DE mode
  227. * DOTCLK polarity set (data fetched at the falling time)
  228. */
  229. .rgb_interface = ILI9341_RGB_DISP_PATH_MEM |
  230. ILI9341_RGB_DE_MODE |
  231. ILI9341_RGB_DPL,
  232. /*
  233. * 0x0a
  234. * Gate outputs in non-display area: Interval scan
  235. * Determine source/VCOM output in a non-display area in the partial
  236. * display mode: AGND AGND AGND AGND
  237. *
  238. * 0xa7
  239. * Scan Cycle: 15 frames
  240. * fFLM = 60Hz: 255ms
  241. * Liquid crystal type: Normally white
  242. * Gate Output Scan Direction: G1 -> G320
  243. * Source Output Scan Direction: S720 -> S1
  244. *
  245. * 0x27
  246. * LCD Driver Line: 320 lines
  247. *
  248. * 0x04
  249. * PCDIV: 4
  250. */
  251. .dfc_2 = {0x0a, 0xa7, 0x27, 0x04},
  252. /* column address: 240 */
  253. .column_addr = {0x00, 0x00, (ILI9341_COLUMN_ADDR >> 4) & 0xff,
  254. ILI9341_COLUMN_ADDR & 0xff},
  255. /* page address: 320 */
  256. .page_addr = {0x00, 0x00, (ILI9341_PAGE_ADDR >> 4) & 0xff,
  257. ILI9341_PAGE_ADDR & 0xff},
  258. /*
  259. * Memory write control: When the transfer number of data exceeds
  260. * (EC-SC+1)*(EP-SP+1), the column and page number will be
  261. * reset, and the exceeding data will be written into the following
  262. * column and page.
  263. * Display Operation Mode: RGB Interface Mode
  264. * Interface for RAM Access: RGB interface
  265. * 16- bit RGB interface (1 transfer/pixel)
  266. */
  267. .interface = {ILI9341_IF_WE_MODE, 0x00,
  268. ILI9341_IF_DM_RGB | ILI9341_IF_RM_RGB},
  269. /* DPI: 16 bits / pixel */
  270. .pixel_format = ILI9341_PIXEL_DPI_16_BITS,
  271. /* Curve Selected: Gamma curve 1 (G2.2) */
  272. .gamma_curve = ILI9341_GAMMA_CURVE_1,
  273. .pgamma = {0x0f, 0x29, 0x24, 0x0c, 0x0e,
  274. 0x09, 0x4e, 0x78, 0x3c, 0x09,
  275. 0x13, 0x05, 0x17, 0x11, 0x00},
  276. .ngamma = {0x00, 0x16, 0x1b, 0x04, 0x11,
  277. 0x07, 0x31, 0x33, 0x42, 0x05,
  278. 0x0c, 0x0a, 0x28, 0x2f, 0x0f},
  279. };
  280. static inline struct ili9341 *panel_to_ili9341(struct drm_panel *panel)
  281. {
  282. return container_of(panel, struct ili9341, panel);
  283. }
  284. static void ili9341_dpi_init(struct ili9341 *ili)
  285. {
  286. struct device *dev = (&ili->panel)->dev;
  287. struct mipi_dbi *dbi = ili->dbi;
  288. struct ili9341_config *cfg = (struct ili9341_config *)ili->conf;
  289. /* Power Control */
  290. mipi_dbi_command_stackbuf(dbi, 0xca, cfg->ca, ILI9341_CA_LEN);
  291. mipi_dbi_command_stackbuf(dbi, ILI9341_POWERB, cfg->power_b,
  292. ILI9341_POWER_B_LEN);
  293. mipi_dbi_command_stackbuf(dbi, ILI9341_POWER_SEQ, cfg->power_seq,
  294. ILI9341_POWER_SEQ_LEN);
  295. mipi_dbi_command_stackbuf(dbi, ILI9341_DTCA, cfg->dtca,
  296. ILI9341_DTCA_LEN);
  297. mipi_dbi_command_stackbuf(dbi, ILI9341_POWERA, cfg->power_a,
  298. ILI9341_POWER_A_LEN);
  299. mipi_dbi_command(ili->dbi, ILI9341_PRC, cfg->prc);
  300. mipi_dbi_command_stackbuf(dbi, ILI9341_DTCB, cfg->dtcb,
  301. ILI9341_DTCB_LEN);
  302. mipi_dbi_command_stackbuf(dbi, ILI9341_FRC, cfg->frc, ILI9341_FRC_LEN);
  303. mipi_dbi_command_stackbuf(dbi, ILI9341_DFC, cfg->dfc_1,
  304. ILI9341_DFC_1_LEN);
  305. mipi_dbi_command(dbi, ILI9341_POWER1, cfg->power_1);
  306. mipi_dbi_command(dbi, ILI9341_POWER2, cfg->power_2);
  307. /* VCOM */
  308. mipi_dbi_command_stackbuf(dbi, ILI9341_VCOM1, cfg->vcom_1,
  309. ILI9341_VCOM_1_LEN);
  310. mipi_dbi_command(dbi, ILI9341_VCOM2, cfg->vcom_2);
  311. mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, cfg->address_mode);
  312. /* Gamma */
  313. mipi_dbi_command(dbi, ILI9341_3GAMMA_EN, cfg->g3amma_en);
  314. mipi_dbi_command(dbi, ILI9341_RGB_INTERFACE, cfg->rgb_interface);
  315. mipi_dbi_command_stackbuf(dbi, ILI9341_DFC, cfg->dfc_2,
  316. ILI9341_DFC_2_LEN);
  317. /* Colomn address set */
  318. mipi_dbi_command_stackbuf(dbi, MIPI_DCS_SET_COLUMN_ADDRESS,
  319. cfg->column_addr, ILI9341_COLUMN_ADDR_LEN);
  320. /* Page address set */
  321. mipi_dbi_command_stackbuf(dbi, MIPI_DCS_SET_PAGE_ADDRESS,
  322. cfg->page_addr, ILI9341_PAGE_ADDR_LEN);
  323. mipi_dbi_command_stackbuf(dbi, ILI9341_INTERFACE, cfg->interface,
  324. ILI9341_INTERFACE_LEN);
  325. /* Format */
  326. mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT, cfg->pixel_format);
  327. mipi_dbi_command(dbi, MIPI_DCS_WRITE_MEMORY_START);
  328. msleep(200);
  329. mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, cfg->gamma_curve);
  330. mipi_dbi_command_stackbuf(dbi, ILI9341_PGAMMA, cfg->pgamma,
  331. ILI9341_PGAMMA_LEN);
  332. mipi_dbi_command_stackbuf(dbi, ILI9341_NGAMMA, cfg->ngamma,
  333. ILI9341_NGAMMA_LEN);
  334. mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
  335. msleep(200);
  336. mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
  337. mipi_dbi_command(dbi, MIPI_DCS_WRITE_MEMORY_START);
  338. dev_info(dev, "Initialized display rgb interface\n");
  339. }
  340. static int ili9341_dpi_power_on(struct ili9341 *ili)
  341. {
  342. struct device *dev = (&ili->panel)->dev;
  343. int ret = 0;
  344. /* Assert RESET */
  345. gpiod_set_value(ili->reset_gpio, 1);
  346. /* Enable power */
  347. ret = regulator_bulk_enable(ARRAY_SIZE(ili->supplies),
  348. ili->supplies);
  349. if (ret < 0) {
  350. dev_err(dev, "unable to enable vcc\n");
  351. return ret;
  352. }
  353. msleep(20);
  354. /* De-assert RESET */
  355. gpiod_set_value(ili->reset_gpio, 0);
  356. msleep(20);
  357. return 0;
  358. }
  359. static int ili9341_dpi_power_off(struct ili9341 *ili)
  360. {
  361. /* Assert RESET */
  362. gpiod_set_value(ili->reset_gpio, 1);
  363. /* Disable power */
  364. return regulator_bulk_disable(ARRAY_SIZE(ili->supplies),
  365. ili->supplies);
  366. }
  367. static int ili9341_dpi_disable(struct drm_panel *panel)
  368. {
  369. struct ili9341 *ili = panel_to_ili9341(panel);
  370. mipi_dbi_command(ili->dbi, MIPI_DCS_SET_DISPLAY_OFF);
  371. return 0;
  372. }
  373. static int ili9341_dpi_unprepare(struct drm_panel *panel)
  374. {
  375. struct ili9341 *ili = panel_to_ili9341(panel);
  376. return ili9341_dpi_power_off(ili);
  377. }
  378. static int ili9341_dpi_prepare(struct drm_panel *panel)
  379. {
  380. struct ili9341 *ili = panel_to_ili9341(panel);
  381. int ret;
  382. ret = ili9341_dpi_power_on(ili);
  383. if (ret < 0)
  384. return ret;
  385. ili9341_dpi_init(ili);
  386. return ret;
  387. }
  388. static int ili9341_dpi_enable(struct drm_panel *panel)
  389. {
  390. struct ili9341 *ili = panel_to_ili9341(panel);
  391. mipi_dbi_command(ili->dbi, MIPI_DCS_SET_DISPLAY_ON);
  392. return 0;
  393. }
  394. static int ili9341_dpi_get_modes(struct drm_panel *panel,
  395. struct drm_connector *connector)
  396. {
  397. struct ili9341 *ili = panel_to_ili9341(panel);
  398. struct drm_device *drm = connector->dev;
  399. struct drm_display_mode *mode;
  400. struct drm_display_info *info;
  401. info = &connector->display_info;
  402. info->width_mm = ili->conf->mode.width_mm;
  403. info->height_mm = ili->conf->mode.height_mm;
  404. if (ili->conf->rgb_interface & ILI9341_RGB_DPL)
  405. info->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
  406. else
  407. info->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
  408. if (ili->conf->rgb_interface & ILI9341_RGB_EPL)
  409. info->bus_flags |= DRM_BUS_FLAG_DE_LOW;
  410. else
  411. info->bus_flags |= DRM_BUS_FLAG_DE_HIGH;
  412. mode = drm_mode_duplicate(drm, &ili->conf->mode);
  413. if (!mode) {
  414. drm_err(drm, "bad mode or failed to add mode\n");
  415. return -EINVAL;
  416. }
  417. drm_mode_set_name(mode);
  418. /* Set up the polarity */
  419. if (ili->conf->rgb_interface & ILI9341_RGB_HSPL)
  420. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  421. else
  422. mode->flags |= DRM_MODE_FLAG_NHSYNC;
  423. if (ili->conf->rgb_interface & ILI9341_RGB_VSPL)
  424. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  425. else
  426. mode->flags |= DRM_MODE_FLAG_NVSYNC;
  427. drm_mode_probed_add(connector, mode);
  428. return 1; /* Number of modes */
  429. }
  430. static const struct drm_panel_funcs ili9341_dpi_funcs = {
  431. .disable = ili9341_dpi_disable,
  432. .unprepare = ili9341_dpi_unprepare,
  433. .prepare = ili9341_dpi_prepare,
  434. .enable = ili9341_dpi_enable,
  435. .get_modes = ili9341_dpi_get_modes,
  436. };
  437. static void ili9341_dbi_enable(struct drm_simple_display_pipe *pipe,
  438. struct drm_crtc_state *crtc_state,
  439. struct drm_plane_state *plane_state)
  440. {
  441. struct mipi_dbi_dev *dbidev = drm_to_mipi_dbi_dev(pipe->crtc.dev);
  442. struct mipi_dbi *dbi = &dbidev->dbi;
  443. u8 addr_mode;
  444. int ret, idx;
  445. if (!drm_dev_enter(pipe->crtc.dev, &idx))
  446. return;
  447. ret = mipi_dbi_poweron_conditional_reset(dbidev);
  448. if (ret < 0)
  449. goto out_exit;
  450. if (ret == 1)
  451. goto out_enable;
  452. mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
  453. mipi_dbi_command(dbi, ILI9341_POWERB, 0x00, 0xc1, 0x30);
  454. mipi_dbi_command(dbi, ILI9341_POWER_SEQ, 0x64, 0x03, 0x12, 0x81);
  455. mipi_dbi_command(dbi, ILI9341_DTCA, 0x85, 0x00, 0x78);
  456. mipi_dbi_command(dbi, ILI9341_POWERA, 0x39, 0x2c, 0x00, 0x34, 0x02);
  457. mipi_dbi_command(dbi, ILI9341_PRC, ILI9341_DBI_PRC_NORMAL);
  458. mipi_dbi_command(dbi, ILI9341_DTCB, 0x00, 0x00);
  459. /* Power Control */
  460. mipi_dbi_command(dbi, ILI9341_POWER1, ILI9341_DBI_VCOMH_4P6V);
  461. mipi_dbi_command(dbi, ILI9341_POWER2, ILI9341_DBI_PWR_2_DEFAULT);
  462. /* VCOM */
  463. mipi_dbi_command(dbi, ILI9341_VCOM1, ILI9341_DBI_VCOM_1_VMH_4P25V,
  464. ILI9341_DBI_VCOM_1_VML_1P5V);
  465. mipi_dbi_command(dbi, ILI9341_VCOM2, ILI9341_DBI_VCOM_2_DEC_58);
  466. /* Memory Access Control */
  467. mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
  468. MIPI_DCS_PIXEL_FMT_16BIT);
  469. /* Frame Rate */
  470. mipi_dbi_command(dbi, ILI9341_FRC, ILI9341_DBI_FRC_DIVA & 0x03,
  471. ILI9341_DBI_FRC_RTNA & 0x1f);
  472. /* Gamma */
  473. mipi_dbi_command(dbi, ILI9341_3GAMMA_EN, 0x00);
  474. mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, ILI9341_GAMMA_CURVE_1);
  475. mipi_dbi_command(dbi, ILI9341_PGAMMA,
  476. 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
  477. 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
  478. mipi_dbi_command(dbi, ILI9341_NGAMMA,
  479. 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
  480. 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
  481. /* DDRAM */
  482. mipi_dbi_command(dbi, ILI9341_ETMOD, ILI9341_DBI_EMS_GAS |
  483. ILI9341_DBI_EMS_DTS |
  484. ILI9341_DBI_EMS_GON);
  485. /* Display */
  486. mipi_dbi_command(dbi, ILI9341_DFC, 0x08, 0x82, 0x27, 0x00);
  487. mipi_dbi_command(dbi, MIPI_DCS_EXIT_SLEEP_MODE);
  488. msleep(100);
  489. mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_ON);
  490. msleep(100);
  491. out_enable:
  492. switch (dbidev->rotation) {
  493. default:
  494. addr_mode = ILI9341_MADCTL_MX;
  495. break;
  496. case 90:
  497. addr_mode = ILI9341_MADCTL_MV;
  498. break;
  499. case 180:
  500. addr_mode = ILI9341_MADCTL_MY;
  501. break;
  502. case 270:
  503. addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
  504. ILI9341_MADCTL_MX;
  505. break;
  506. }
  507. addr_mode |= ILI9341_MADCTL_BGR;
  508. mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
  509. mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
  510. drm_info(&dbidev->drm, "Initialized display serial interface\n");
  511. out_exit:
  512. drm_dev_exit(idx);
  513. }
  514. static const struct drm_simple_display_pipe_funcs ili9341_dbi_funcs = {
  515. .mode_valid = mipi_dbi_pipe_mode_valid,
  516. .enable = ili9341_dbi_enable,
  517. .disable = mipi_dbi_pipe_disable,
  518. .update = mipi_dbi_pipe_update,
  519. .prepare_fb = drm_gem_simple_display_pipe_prepare_fb,
  520. };
  521. static const struct drm_display_mode ili9341_dbi_mode = {
  522. DRM_SIMPLE_MODE(240, 320, 37, 49),
  523. };
  524. DEFINE_DRM_GEM_DMA_FOPS(ili9341_dbi_fops);
  525. static struct drm_driver ili9341_dbi_driver = {
  526. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  527. .fops = &ili9341_dbi_fops,
  528. DRM_GEM_DMA_DRIVER_OPS_VMAP,
  529. .debugfs_init = mipi_dbi_debugfs_init,
  530. .name = "ili9341",
  531. .desc = "Ilitek ILI9341",
  532. .date = "20210716",
  533. .major = 1,
  534. .minor = 0,
  535. };
  536. static int ili9341_dbi_probe(struct spi_device *spi, struct gpio_desc *dc,
  537. struct gpio_desc *reset)
  538. {
  539. struct device *dev = &spi->dev;
  540. struct mipi_dbi_dev *dbidev;
  541. struct mipi_dbi *dbi;
  542. struct drm_device *drm;
  543. struct regulator *vcc;
  544. u32 rotation = 0;
  545. int ret;
  546. vcc = devm_regulator_get_optional(dev, "vcc");
  547. if (IS_ERR(vcc)) {
  548. dev_err(dev, "get optional vcc failed\n");
  549. vcc = NULL;
  550. }
  551. dbidev = devm_drm_dev_alloc(dev, &ili9341_dbi_driver,
  552. struct mipi_dbi_dev, drm);
  553. if (IS_ERR(dbidev))
  554. return PTR_ERR(dbidev);
  555. dbi = &dbidev->dbi;
  556. drm = &dbidev->drm;
  557. dbi->reset = reset;
  558. dbidev->regulator = vcc;
  559. drm_mode_config_init(drm);
  560. dbidev->backlight = devm_of_find_backlight(dev);
  561. if (IS_ERR(dbidev->backlight))
  562. return PTR_ERR(dbidev->backlight);
  563. device_property_read_u32(dev, "rotation", &rotation);
  564. ret = mipi_dbi_spi_init(spi, dbi, dc);
  565. if (ret)
  566. return ret;
  567. ret = mipi_dbi_dev_init(dbidev, &ili9341_dbi_funcs,
  568. &ili9341_dbi_mode, rotation);
  569. if (ret)
  570. return ret;
  571. drm_mode_config_reset(drm);
  572. ret = drm_dev_register(drm, 0);
  573. if (ret)
  574. return ret;
  575. spi_set_drvdata(spi, drm);
  576. drm_fbdev_generic_setup(drm, 0);
  577. return 0;
  578. }
  579. static int ili9341_dpi_probe(struct spi_device *spi, struct gpio_desc *dc,
  580. struct gpio_desc *reset)
  581. {
  582. struct device *dev = &spi->dev;
  583. struct ili9341 *ili;
  584. int ret;
  585. ili = devm_kzalloc(dev, sizeof(struct ili9341), GFP_KERNEL);
  586. if (!ili)
  587. return -ENOMEM;
  588. ili->dbi = devm_kzalloc(dev, sizeof(struct mipi_dbi),
  589. GFP_KERNEL);
  590. if (!ili->dbi)
  591. return -ENOMEM;
  592. ili->supplies[0].supply = "vci";
  593. ili->supplies[1].supply = "vddi";
  594. ili->supplies[2].supply = "vddi-led";
  595. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ili->supplies),
  596. ili->supplies);
  597. if (ret < 0) {
  598. dev_err(dev, "failed to get regulators: %d\n", ret);
  599. return ret;
  600. }
  601. ret = mipi_dbi_spi_init(spi, ili->dbi, dc);
  602. if (ret)
  603. return ret;
  604. spi_set_drvdata(spi, ili);
  605. ili->reset_gpio = reset;
  606. /*
  607. * Every new incarnation of this display must have a unique
  608. * data entry for the system in this driver.
  609. */
  610. ili->conf = of_device_get_match_data(dev);
  611. if (!ili->conf) {
  612. dev_err(dev, "missing device configuration\n");
  613. return -ENODEV;
  614. }
  615. ili->max_spi_speed = ili->conf->max_spi_speed;
  616. drm_panel_init(&ili->panel, dev, &ili9341_dpi_funcs,
  617. DRM_MODE_CONNECTOR_DPI);
  618. drm_panel_add(&ili->panel);
  619. return 0;
  620. }
  621. static int ili9341_probe(struct spi_device *spi)
  622. {
  623. struct device *dev = &spi->dev;
  624. struct gpio_desc *dc;
  625. struct gpio_desc *reset;
  626. const struct spi_device_id *id = spi_get_device_id(spi);
  627. reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
  628. if (IS_ERR(reset))
  629. dev_err(dev, "Failed to get gpio 'reset'\n");
  630. dc = devm_gpiod_get_optional(dev, "dc", GPIOD_OUT_LOW);
  631. if (IS_ERR(dc))
  632. dev_err(dev, "Failed to get gpio 'dc'\n");
  633. if (!strcmp(id->name, "sf-tc240t-9370-t"))
  634. return ili9341_dpi_probe(spi, dc, reset);
  635. else if (!strcmp(id->name, "yx240qv29"))
  636. return ili9341_dbi_probe(spi, dc, reset);
  637. return -1;
  638. }
  639. static void ili9341_remove(struct spi_device *spi)
  640. {
  641. const struct spi_device_id *id = spi_get_device_id(spi);
  642. struct ili9341 *ili = spi_get_drvdata(spi);
  643. struct drm_device *drm = spi_get_drvdata(spi);
  644. if (!strcmp(id->name, "sf-tc240t-9370-t")) {
  645. ili9341_dpi_power_off(ili);
  646. drm_panel_remove(&ili->panel);
  647. } else if (!strcmp(id->name, "yx240qv29")) {
  648. drm_dev_unplug(drm);
  649. drm_atomic_helper_shutdown(drm);
  650. }
  651. }
  652. static void ili9341_shutdown(struct spi_device *spi)
  653. {
  654. const struct spi_device_id *id = spi_get_device_id(spi);
  655. if (!strcmp(id->name, "yx240qv29"))
  656. drm_atomic_helper_shutdown(spi_get_drvdata(spi));
  657. }
  658. static const struct of_device_id ili9341_of_match[] = {
  659. {
  660. .compatible = "st,sf-tc240t-9370-t",
  661. .data = &ili9341_stm32f429_disco_data,
  662. },
  663. {
  664. /* porting from tiny/ili9341.c
  665. * for original mipi dbi compitable
  666. */
  667. .compatible = "adafruit,yx240qv29",
  668. .data = NULL,
  669. },
  670. { }
  671. };
  672. MODULE_DEVICE_TABLE(of, ili9341_of_match);
  673. static const struct spi_device_id ili9341_id[] = {
  674. { "yx240qv29", 0 },
  675. { "sf-tc240t-9370-t", 0 },
  676. { }
  677. };
  678. MODULE_DEVICE_TABLE(spi, ili9341_id);
  679. static struct spi_driver ili9341_driver = {
  680. .probe = ili9341_probe,
  681. .remove = ili9341_remove,
  682. .shutdown = ili9341_shutdown,
  683. .id_table = ili9341_id,
  684. .driver = {
  685. .name = "panel-ilitek-ili9341",
  686. .of_match_table = ili9341_of_match,
  687. },
  688. };
  689. module_spi_driver(ili9341_driver);
  690. MODULE_AUTHOR("Dillon Min <[email protected]>");
  691. MODULE_DESCRIPTION("ILI9341 LCD panel driver");
  692. MODULE_LICENSE("GPL v2");