msm_rd.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. */
  6. /* For debugging crashes, userspace can:
  7. *
  8. * tail -f /sys/kernel/debug/dri/<minor>/rd > logfile.rd
  9. *
  10. * to log the cmdstream in a format that is understood by freedreno/cffdump
  11. * utility. By comparing the last successfully completed fence #, to the
  12. * cmdstream for the next fence, you can narrow down which process and submit
  13. * caused the gpu crash/lockup.
  14. *
  15. * Additionally:
  16. *
  17. * tail -f /sys/kernel/debug/dri/<minor>/hangrd > logfile.rd
  18. *
  19. * will capture just the cmdstream from submits which triggered a GPU hang.
  20. *
  21. * This bypasses drm_debugfs_create_files() mainly because we need to use
  22. * our own fops for a bit more control. In particular, we don't want to
  23. * do anything if userspace doesn't have the debugfs file open.
  24. *
  25. * The module-param "rd_full", which defaults to false, enables snapshotting
  26. * all (non-written) buffers in the submit, rather than just cmdstream bo's.
  27. * This is useful to capture the contents of (for example) vbo's or textures,
  28. * or shader programs (if not emitted inline in cmdstream).
  29. */
  30. #include <linux/circ_buf.h>
  31. #include <linux/debugfs.h>
  32. #include <linux/kfifo.h>
  33. #include <linux/uaccess.h>
  34. #include <linux/wait.h>
  35. #include <drm/drm_file.h>
  36. #include "msm_drv.h"
  37. #include "msm_gpu.h"
  38. #include "msm_gem.h"
  39. bool rd_full = false;
  40. MODULE_PARM_DESC(rd_full, "If true, $debugfs/.../rd will snapshot all buffer contents");
  41. module_param_named(rd_full, rd_full, bool, 0600);
  42. #ifdef CONFIG_DEBUG_FS
  43. enum rd_sect_type {
  44. RD_NONE,
  45. RD_TEST, /* ascii text */
  46. RD_CMD, /* ascii text */
  47. RD_GPUADDR, /* u32 gpuaddr, u32 size */
  48. RD_CONTEXT, /* raw dump */
  49. RD_CMDSTREAM, /* raw dump */
  50. RD_CMDSTREAM_ADDR, /* gpu addr of cmdstream */
  51. RD_PARAM, /* u32 param_type, u32 param_val, u32 bitlen */
  52. RD_FLUSH, /* empty, clear previous params */
  53. RD_PROGRAM, /* shader program, raw dump */
  54. RD_VERT_SHADER,
  55. RD_FRAG_SHADER,
  56. RD_BUFFER_CONTENTS,
  57. RD_GPU_ID,
  58. RD_CHIP_ID,
  59. };
  60. #define BUF_SZ 512 /* should be power of 2 */
  61. /* space used: */
  62. #define circ_count(circ) \
  63. (CIRC_CNT((circ)->head, (circ)->tail, BUF_SZ))
  64. #define circ_count_to_end(circ) \
  65. (CIRC_CNT_TO_END((circ)->head, (circ)->tail, BUF_SZ))
  66. /* space available: */
  67. #define circ_space(circ) \
  68. (CIRC_SPACE((circ)->head, (circ)->tail, BUF_SZ))
  69. #define circ_space_to_end(circ) \
  70. (CIRC_SPACE_TO_END((circ)->head, (circ)->tail, BUF_SZ))
  71. struct msm_rd_state {
  72. struct drm_device *dev;
  73. bool open;
  74. /* current submit to read out: */
  75. struct msm_gem_submit *submit;
  76. /* fifo access is synchronized on the producer side by
  77. * gpu->lock held by submit code (otherwise we could
  78. * end up w/ cmds logged in different order than they
  79. * were executed). And read_lock synchronizes the reads
  80. */
  81. struct mutex read_lock;
  82. wait_queue_head_t fifo_event;
  83. struct circ_buf fifo;
  84. char buf[BUF_SZ];
  85. };
  86. static void rd_write(struct msm_rd_state *rd, const void *buf, int sz)
  87. {
  88. struct circ_buf *fifo = &rd->fifo;
  89. const char *ptr = buf;
  90. while (sz > 0) {
  91. char *fptr = &fifo->buf[fifo->head];
  92. int n;
  93. wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open);
  94. if (!rd->open)
  95. return;
  96. /* Note that smp_load_acquire() is not strictly required
  97. * as CIRC_SPACE_TO_END() does not access the tail more
  98. * than once.
  99. */
  100. n = min(sz, circ_space_to_end(&rd->fifo));
  101. memcpy(fptr, ptr, n);
  102. smp_store_release(&fifo->head, (fifo->head + n) & (BUF_SZ - 1));
  103. sz -= n;
  104. ptr += n;
  105. wake_up_all(&rd->fifo_event);
  106. }
  107. }
  108. static void rd_write_section(struct msm_rd_state *rd,
  109. enum rd_sect_type type, const void *buf, int sz)
  110. {
  111. rd_write(rd, &type, 4);
  112. rd_write(rd, &sz, 4);
  113. rd_write(rd, buf, sz);
  114. }
  115. static ssize_t rd_read(struct file *file, char __user *buf,
  116. size_t sz, loff_t *ppos)
  117. {
  118. struct msm_rd_state *rd = file->private_data;
  119. struct circ_buf *fifo = &rd->fifo;
  120. const char *fptr = &fifo->buf[fifo->tail];
  121. int n = 0, ret = 0;
  122. mutex_lock(&rd->read_lock);
  123. ret = wait_event_interruptible(rd->fifo_event,
  124. circ_count(&rd->fifo) > 0);
  125. if (ret)
  126. goto out;
  127. /* Note that smp_load_acquire() is not strictly required
  128. * as CIRC_CNT_TO_END() does not access the head more than
  129. * once.
  130. */
  131. n = min_t(int, sz, circ_count_to_end(&rd->fifo));
  132. if (copy_to_user(buf, fptr, n)) {
  133. ret = -EFAULT;
  134. goto out;
  135. }
  136. smp_store_release(&fifo->tail, (fifo->tail + n) & (BUF_SZ - 1));
  137. *ppos += n;
  138. wake_up_all(&rd->fifo_event);
  139. out:
  140. mutex_unlock(&rd->read_lock);
  141. if (ret)
  142. return ret;
  143. return n;
  144. }
  145. static int rd_open(struct inode *inode, struct file *file)
  146. {
  147. struct msm_rd_state *rd = inode->i_private;
  148. struct drm_device *dev = rd->dev;
  149. struct msm_drm_private *priv = dev->dev_private;
  150. struct msm_gpu *gpu = priv->gpu;
  151. uint64_t val;
  152. uint32_t gpu_id;
  153. uint32_t zero = 0;
  154. int ret = 0;
  155. if (!gpu)
  156. return -ENODEV;
  157. mutex_lock(&gpu->lock);
  158. if (rd->open) {
  159. ret = -EBUSY;
  160. goto out;
  161. }
  162. file->private_data = rd;
  163. rd->open = true;
  164. /* Reset fifo to clear any previously unread data: */
  165. rd->fifo.head = rd->fifo.tail = 0;
  166. /* the parsing tools need to know gpu-id to know which
  167. * register database to load.
  168. *
  169. * Note: These particular params do not require a context
  170. */
  171. gpu->funcs->get_param(gpu, NULL, MSM_PARAM_GPU_ID, &val, &zero);
  172. gpu_id = val;
  173. rd_write_section(rd, RD_GPU_ID, &gpu_id, sizeof(gpu_id));
  174. gpu->funcs->get_param(gpu, NULL, MSM_PARAM_CHIP_ID, &val, &zero);
  175. rd_write_section(rd, RD_CHIP_ID, &val, sizeof(val));
  176. out:
  177. mutex_unlock(&gpu->lock);
  178. return ret;
  179. }
  180. static int rd_release(struct inode *inode, struct file *file)
  181. {
  182. struct msm_rd_state *rd = inode->i_private;
  183. rd->open = false;
  184. wake_up_all(&rd->fifo_event);
  185. return 0;
  186. }
  187. static const struct file_operations rd_debugfs_fops = {
  188. .owner = THIS_MODULE,
  189. .open = rd_open,
  190. .read = rd_read,
  191. .llseek = no_llseek,
  192. .release = rd_release,
  193. };
  194. static void rd_cleanup(struct msm_rd_state *rd)
  195. {
  196. if (!rd)
  197. return;
  198. mutex_destroy(&rd->read_lock);
  199. kfree(rd);
  200. }
  201. static struct msm_rd_state *rd_init(struct drm_minor *minor, const char *name)
  202. {
  203. struct msm_rd_state *rd;
  204. rd = kzalloc(sizeof(*rd), GFP_KERNEL);
  205. if (!rd)
  206. return ERR_PTR(-ENOMEM);
  207. rd->dev = minor->dev;
  208. rd->fifo.buf = rd->buf;
  209. mutex_init(&rd->read_lock);
  210. init_waitqueue_head(&rd->fifo_event);
  211. debugfs_create_file(name, S_IFREG | S_IRUGO, minor->debugfs_root, rd,
  212. &rd_debugfs_fops);
  213. return rd;
  214. }
  215. int msm_rd_debugfs_init(struct drm_minor *minor)
  216. {
  217. struct msm_drm_private *priv = minor->dev->dev_private;
  218. struct msm_rd_state *rd;
  219. int ret;
  220. /* only create on first minor: */
  221. if (priv->rd)
  222. return 0;
  223. rd = rd_init(minor, "rd");
  224. if (IS_ERR(rd)) {
  225. ret = PTR_ERR(rd);
  226. goto fail;
  227. }
  228. priv->rd = rd;
  229. rd = rd_init(minor, "hangrd");
  230. if (IS_ERR(rd)) {
  231. ret = PTR_ERR(rd);
  232. goto fail;
  233. }
  234. priv->hangrd = rd;
  235. return 0;
  236. fail:
  237. msm_rd_debugfs_cleanup(priv);
  238. return ret;
  239. }
  240. void msm_rd_debugfs_cleanup(struct msm_drm_private *priv)
  241. {
  242. rd_cleanup(priv->rd);
  243. priv->rd = NULL;
  244. rd_cleanup(priv->hangrd);
  245. priv->hangrd = NULL;
  246. }
  247. static void snapshot_buf(struct msm_rd_state *rd,
  248. struct msm_gem_submit *submit, int idx,
  249. uint64_t iova, uint32_t size, bool full)
  250. {
  251. struct msm_gem_object *obj = submit->bos[idx].obj;
  252. unsigned offset = 0;
  253. const char *buf;
  254. if (iova) {
  255. offset = iova - submit->bos[idx].iova;
  256. } else {
  257. iova = submit->bos[idx].iova;
  258. size = obj->base.size;
  259. }
  260. /*
  261. * Always write the GPUADDR header so can get a complete list of all the
  262. * buffers in the cmd
  263. */
  264. rd_write_section(rd, RD_GPUADDR,
  265. (uint32_t[3]){ iova, size, iova >> 32 }, 12);
  266. if (!full)
  267. return;
  268. /* But only dump the contents of buffers marked READ */
  269. if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ))
  270. return;
  271. msm_gem_lock(&obj->base);
  272. buf = msm_gem_get_vaddr_active(&obj->base);
  273. if (IS_ERR(buf))
  274. goto out_unlock;
  275. buf += offset;
  276. rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
  277. msm_gem_put_vaddr_locked(&obj->base);
  278. out_unlock:
  279. msm_gem_unlock(&obj->base);
  280. }
  281. /* called under gpu->lock */
  282. void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
  283. const char *fmt, ...)
  284. {
  285. struct task_struct *task;
  286. char msg[256];
  287. int i, n;
  288. if (!rd->open)
  289. return;
  290. /* writing into fifo is serialized by caller, and
  291. * rd->read_lock is used to serialize the reads
  292. */
  293. WARN_ON(!mutex_is_locked(&submit->gpu->lock));
  294. if (fmt) {
  295. va_list args;
  296. va_start(args, fmt);
  297. n = vscnprintf(msg, sizeof(msg), fmt, args);
  298. va_end(args);
  299. rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4));
  300. }
  301. rcu_read_lock();
  302. task = pid_task(submit->pid, PIDTYPE_PID);
  303. if (task) {
  304. n = scnprintf(msg, sizeof(msg), "%.*s/%d: fence=%u",
  305. TASK_COMM_LEN, task->comm,
  306. pid_nr(submit->pid), submit->seqno);
  307. } else {
  308. n = scnprintf(msg, sizeof(msg), "???/%d: fence=%u",
  309. pid_nr(submit->pid), submit->seqno);
  310. }
  311. rcu_read_unlock();
  312. rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4));
  313. for (i = 0; i < submit->nr_bos; i++)
  314. snapshot_buf(rd, submit, i, 0, 0, should_dump(submit, i));
  315. for (i = 0; i < submit->nr_cmds; i++) {
  316. uint32_t szd = submit->cmd[i].size; /* in dwords */
  317. /* snapshot cmdstream bo's (if we haven't already): */
  318. if (!should_dump(submit, i)) {
  319. snapshot_buf(rd, submit, submit->cmd[i].idx,
  320. submit->cmd[i].iova, szd * 4, true);
  321. }
  322. }
  323. for (i = 0; i < submit->nr_cmds; i++) {
  324. uint64_t iova = submit->cmd[i].iova;
  325. uint32_t szd = submit->cmd[i].size; /* in dwords */
  326. switch (submit->cmd[i].type) {
  327. case MSM_SUBMIT_CMD_IB_TARGET_BUF:
  328. /* ignore IB-targets, we've logged the buffer, the
  329. * parser tool will follow the IB based on the logged
  330. * buffer/gpuaddr, so nothing more to do.
  331. */
  332. break;
  333. case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
  334. case MSM_SUBMIT_CMD_BUF:
  335. rd_write_section(rd, RD_CMDSTREAM_ADDR,
  336. (uint32_t[3]){ iova, szd, iova >> 32 }, 12);
  337. break;
  338. }
  339. }
  340. }
  341. #endif