meson_drv.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2016 BayLibre, SAS
  4. * Author: Neil Armstrong <[email protected]>
  5. * Copyright (C) 2014 Endless Mobile
  6. *
  7. * Written by:
  8. * Jasper St. Pierre <[email protected]>
  9. */
  10. #include <linux/component.h>
  11. #include <linux/module.h>
  12. #include <linux/of_graph.h>
  13. #include <linux/sys_soc.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/soc/amlogic/meson-canvas.h>
  16. #include <drm/drm_aperture.h>
  17. #include <drm/drm_atomic_helper.h>
  18. #include <drm/drm_drv.h>
  19. #include <drm/drm_fb_helper.h>
  20. #include <drm/drm_gem_dma_helper.h>
  21. #include <drm/drm_gem_framebuffer_helper.h>
  22. #include <drm/drm_modeset_helper_vtables.h>
  23. #include <drm/drm_module.h>
  24. #include <drm/drm_probe_helper.h>
  25. #include <drm/drm_vblank.h>
  26. #include "meson_crtc.h"
  27. #include "meson_drv.h"
  28. #include "meson_overlay.h"
  29. #include "meson_plane.h"
  30. #include "meson_osd_afbcd.h"
  31. #include "meson_registers.h"
  32. #include "meson_encoder_cvbs.h"
  33. #include "meson_encoder_hdmi.h"
  34. #include "meson_viu.h"
  35. #include "meson_vpp.h"
  36. #include "meson_rdma.h"
  37. #define DRIVER_NAME "meson"
  38. #define DRIVER_DESC "Amlogic Meson DRM driver"
  39. /**
  40. * DOC: Video Processing Unit
  41. *
  42. * VPU Handles the Global Video Processing, it includes management of the
  43. * clocks gates, blocks reset lines and power domains.
  44. *
  45. * What is missing :
  46. *
  47. * - Full reset of entire video processing HW blocks
  48. * - Scaling and setup of the VPU clock
  49. * - Bus clock gates
  50. * - Powering up video processing HW blocks
  51. * - Powering Up HDMI controller and PHY
  52. */
  53. static const struct drm_mode_config_funcs meson_mode_config_funcs = {
  54. .atomic_check = drm_atomic_helper_check,
  55. .atomic_commit = drm_atomic_helper_commit,
  56. .fb_create = drm_gem_fb_create,
  57. };
  58. static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = {
  59. .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
  60. };
  61. static irqreturn_t meson_irq(int irq, void *arg)
  62. {
  63. struct drm_device *dev = arg;
  64. struct meson_drm *priv = dev->dev_private;
  65. (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
  66. meson_crtc_irq(priv);
  67. return IRQ_HANDLED;
  68. }
  69. static int meson_dumb_create(struct drm_file *file, struct drm_device *dev,
  70. struct drm_mode_create_dumb *args)
  71. {
  72. /*
  73. * We need 64bytes aligned stride, and PAGE aligned size
  74. */
  75. args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64);
  76. args->size = PAGE_ALIGN(args->pitch * args->height);
  77. return drm_gem_dma_dumb_create_internal(file, dev, args);
  78. }
  79. DEFINE_DRM_GEM_DMA_FOPS(fops);
  80. static const struct drm_driver meson_driver = {
  81. .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
  82. /* DMA Ops */
  83. DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create),
  84. /* Misc */
  85. .fops = &fops,
  86. .name = DRIVER_NAME,
  87. .desc = DRIVER_DESC,
  88. .date = "20161109",
  89. .major = 1,
  90. .minor = 0,
  91. };
  92. static bool meson_vpu_has_available_connectors(struct device *dev)
  93. {
  94. struct device_node *ep, *remote;
  95. /* Parses each endpoint and check if remote exists */
  96. for_each_endpoint_of_node(dev->of_node, ep) {
  97. /* If the endpoint node exists, consider it enabled */
  98. remote = of_graph_get_remote_port(ep);
  99. if (remote) {
  100. of_node_put(remote);
  101. of_node_put(ep);
  102. return true;
  103. }
  104. }
  105. return false;
  106. }
  107. static struct regmap_config meson_regmap_config = {
  108. .reg_bits = 32,
  109. .val_bits = 32,
  110. .reg_stride = 4,
  111. .max_register = 0x1000,
  112. };
  113. static void meson_vpu_init(struct meson_drm *priv)
  114. {
  115. u32 value;
  116. /*
  117. * Slave dc0 and dc5 connected to master port 1.
  118. * By default other slaves are connected to master port 0.
  119. */
  120. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) |
  121. VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1);
  122. writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
  123. /* Slave dc0 connected to master port 1 */
  124. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1);
  125. writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
  126. /* Slave dc4 and dc7 connected to master port 1 */
  127. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) |
  128. VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1);
  129. writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
  130. /* Slave dc1 connected to master port 1 */
  131. value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1);
  132. writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
  133. }
  134. struct meson_drm_soc_attr {
  135. struct meson_drm_soc_limits limits;
  136. const struct soc_device_attribute *attrs;
  137. };
  138. static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = {
  139. /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */
  140. {
  141. .limits = {
  142. .max_hdmi_phy_freq = 1650000,
  143. },
  144. .attrs = (const struct soc_device_attribute []) {
  145. { .soc_id = "GXL (S805*)", },
  146. { /* sentinel */ }
  147. }
  148. },
  149. };
  150. static int meson_drv_bind_master(struct device *dev, bool has_components)
  151. {
  152. struct platform_device *pdev = to_platform_device(dev);
  153. const struct meson_drm_match_data *match;
  154. struct meson_drm *priv;
  155. struct drm_device *drm;
  156. struct resource *res;
  157. void __iomem *regs;
  158. int ret, i;
  159. /* Checks if an output connector is available */
  160. if (!meson_vpu_has_available_connectors(dev)) {
  161. dev_err(dev, "No output connector available\n");
  162. return -ENODEV;
  163. }
  164. match = of_device_get_match_data(dev);
  165. if (!match)
  166. return -ENODEV;
  167. drm = drm_dev_alloc(&meson_driver, dev);
  168. if (IS_ERR(drm))
  169. return PTR_ERR(drm);
  170. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  171. if (!priv) {
  172. ret = -ENOMEM;
  173. goto free_drm;
  174. }
  175. drm->dev_private = priv;
  176. priv->drm = drm;
  177. priv->dev = dev;
  178. priv->compat = match->compat;
  179. priv->afbcd.ops = match->afbcd_ops;
  180. regs = devm_platform_ioremap_resource_byname(pdev, "vpu");
  181. if (IS_ERR(regs)) {
  182. ret = PTR_ERR(regs);
  183. goto free_drm;
  184. }
  185. priv->io_base = regs;
  186. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi");
  187. if (!res) {
  188. ret = -EINVAL;
  189. goto free_drm;
  190. }
  191. /* Simply ioremap since it may be a shared register zone */
  192. regs = devm_ioremap(dev, res->start, resource_size(res));
  193. if (!regs) {
  194. ret = -EADDRNOTAVAIL;
  195. goto free_drm;
  196. }
  197. priv->hhi = devm_regmap_init_mmio(dev, regs,
  198. &meson_regmap_config);
  199. if (IS_ERR(priv->hhi)) {
  200. dev_err(&pdev->dev, "Couldn't create the HHI regmap\n");
  201. ret = PTR_ERR(priv->hhi);
  202. goto free_drm;
  203. }
  204. priv->canvas = meson_canvas_get(dev);
  205. if (IS_ERR(priv->canvas)) {
  206. ret = PTR_ERR(priv->canvas);
  207. goto free_drm;
  208. }
  209. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
  210. if (ret)
  211. goto free_drm;
  212. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
  213. if (ret) {
  214. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  215. goto free_drm;
  216. }
  217. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
  218. if (ret) {
  219. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  220. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
  221. goto free_drm;
  222. }
  223. ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
  224. if (ret) {
  225. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  226. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
  227. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
  228. goto free_drm;
  229. }
  230. priv->vsync_irq = platform_get_irq(pdev, 0);
  231. ret = drm_vblank_init(drm, 1);
  232. if (ret)
  233. goto free_drm;
  234. /* Assign limits per soc revision/package */
  235. for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) {
  236. if (soc_device_match(meson_drm_soc_attrs[i].attrs)) {
  237. priv->limits = &meson_drm_soc_attrs[i].limits;
  238. break;
  239. }
  240. }
  241. /*
  242. * Remove early framebuffers (ie. simplefb). The framebuffer can be
  243. * located anywhere in RAM
  244. */
  245. ret = drm_aperture_remove_framebuffers(false, &meson_driver);
  246. if (ret)
  247. goto free_drm;
  248. ret = drmm_mode_config_init(drm);
  249. if (ret)
  250. goto free_drm;
  251. drm->mode_config.max_width = 3840;
  252. drm->mode_config.max_height = 2160;
  253. drm->mode_config.funcs = &meson_mode_config_funcs;
  254. drm->mode_config.helper_private = &meson_mode_config_helpers;
  255. /* Hardware Initialization */
  256. meson_vpu_init(priv);
  257. meson_venc_init(priv);
  258. meson_vpp_init(priv);
  259. meson_viu_init(priv);
  260. if (priv->afbcd.ops) {
  261. ret = priv->afbcd.ops->init(priv);
  262. if (ret)
  263. goto free_drm;
  264. }
  265. /* Encoder Initialization */
  266. ret = meson_encoder_cvbs_init(priv);
  267. if (ret)
  268. goto exit_afbcd;
  269. if (has_components) {
  270. ret = component_bind_all(drm->dev, drm);
  271. if (ret) {
  272. dev_err(drm->dev, "Couldn't bind all components\n");
  273. goto exit_afbcd;
  274. }
  275. }
  276. ret = meson_encoder_hdmi_init(priv);
  277. if (ret)
  278. goto unbind_all;
  279. ret = meson_plane_create(priv);
  280. if (ret)
  281. goto unbind_all;
  282. ret = meson_overlay_create(priv);
  283. if (ret)
  284. goto unbind_all;
  285. ret = meson_crtc_create(priv);
  286. if (ret)
  287. goto unbind_all;
  288. ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm);
  289. if (ret)
  290. goto unbind_all;
  291. drm_mode_config_reset(drm);
  292. drm_kms_helper_poll_init(drm);
  293. platform_set_drvdata(pdev, priv);
  294. ret = drm_dev_register(drm, 0);
  295. if (ret)
  296. goto uninstall_irq;
  297. drm_fbdev_generic_setup(drm, 32);
  298. return 0;
  299. uninstall_irq:
  300. free_irq(priv->vsync_irq, drm);
  301. unbind_all:
  302. if (has_components)
  303. component_unbind_all(drm->dev, drm);
  304. exit_afbcd:
  305. if (priv->afbcd.ops)
  306. priv->afbcd.ops->exit(priv);
  307. free_drm:
  308. drm_dev_put(drm);
  309. return ret;
  310. }
  311. static int meson_drv_bind(struct device *dev)
  312. {
  313. return meson_drv_bind_master(dev, true);
  314. }
  315. static void meson_drv_unbind(struct device *dev)
  316. {
  317. struct meson_drm *priv = dev_get_drvdata(dev);
  318. struct drm_device *drm = priv->drm;
  319. if (priv->canvas) {
  320. meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
  321. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
  322. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
  323. meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2);
  324. }
  325. drm_dev_unregister(drm);
  326. drm_kms_helper_poll_fini(drm);
  327. drm_atomic_helper_shutdown(drm);
  328. free_irq(priv->vsync_irq, drm);
  329. drm_dev_put(drm);
  330. meson_encoder_hdmi_remove(priv);
  331. meson_encoder_cvbs_remove(priv);
  332. component_unbind_all(dev, drm);
  333. if (priv->afbcd.ops)
  334. priv->afbcd.ops->exit(priv);
  335. }
  336. static const struct component_master_ops meson_drv_master_ops = {
  337. .bind = meson_drv_bind,
  338. .unbind = meson_drv_unbind,
  339. };
  340. static int __maybe_unused meson_drv_pm_suspend(struct device *dev)
  341. {
  342. struct meson_drm *priv = dev_get_drvdata(dev);
  343. if (!priv)
  344. return 0;
  345. return drm_mode_config_helper_suspend(priv->drm);
  346. }
  347. static int __maybe_unused meson_drv_pm_resume(struct device *dev)
  348. {
  349. struct meson_drm *priv = dev_get_drvdata(dev);
  350. if (!priv)
  351. return 0;
  352. meson_vpu_init(priv);
  353. meson_venc_init(priv);
  354. meson_vpp_init(priv);
  355. meson_viu_init(priv);
  356. if (priv->afbcd.ops)
  357. priv->afbcd.ops->init(priv);
  358. return drm_mode_config_helper_resume(priv->drm);
  359. }
  360. static void meson_drv_shutdown(struct platform_device *pdev)
  361. {
  362. struct meson_drm *priv = dev_get_drvdata(&pdev->dev);
  363. if (!priv)
  364. return;
  365. drm_kms_helper_poll_fini(priv->drm);
  366. drm_atomic_helper_shutdown(priv->drm);
  367. }
  368. /* Possible connectors nodes to ignore */
  369. static const struct of_device_id connectors_match[] = {
  370. { .compatible = "composite-video-connector" },
  371. { .compatible = "svideo-connector" },
  372. {}
  373. };
  374. static int meson_drv_probe(struct platform_device *pdev)
  375. {
  376. struct component_match *match = NULL;
  377. struct device_node *np = pdev->dev.of_node;
  378. struct device_node *ep, *remote;
  379. int count = 0;
  380. for_each_endpoint_of_node(np, ep) {
  381. remote = of_graph_get_remote_port_parent(ep);
  382. if (!remote || !of_device_is_available(remote)) {
  383. of_node_put(remote);
  384. continue;
  385. }
  386. /* If an analog connector is detected, count it as an output */
  387. if (of_match_node(connectors_match, remote)) {
  388. ++count;
  389. of_node_put(remote);
  390. continue;
  391. }
  392. dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n",
  393. np, remote, dev_name(&pdev->dev));
  394. component_match_add(&pdev->dev, &match, component_compare_of, remote);
  395. of_node_put(remote);
  396. ++count;
  397. }
  398. if (count && !match)
  399. return meson_drv_bind_master(&pdev->dev, false);
  400. /* If some endpoints were found, initialize the nodes */
  401. if (count) {
  402. dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count);
  403. return component_master_add_with_match(&pdev->dev,
  404. &meson_drv_master_ops,
  405. match);
  406. }
  407. /* If no output endpoints were available, simply bail out */
  408. return 0;
  409. };
  410. static int meson_drv_remove(struct platform_device *pdev)
  411. {
  412. component_master_del(&pdev->dev, &meson_drv_master_ops);
  413. return 0;
  414. }
  415. static struct meson_drm_match_data meson_drm_gxbb_data = {
  416. .compat = VPU_COMPATIBLE_GXBB,
  417. };
  418. static struct meson_drm_match_data meson_drm_gxl_data = {
  419. .compat = VPU_COMPATIBLE_GXL,
  420. };
  421. static struct meson_drm_match_data meson_drm_gxm_data = {
  422. .compat = VPU_COMPATIBLE_GXM,
  423. .afbcd_ops = &meson_afbcd_gxm_ops,
  424. };
  425. static struct meson_drm_match_data meson_drm_g12a_data = {
  426. .compat = VPU_COMPATIBLE_G12A,
  427. .afbcd_ops = &meson_afbcd_g12a_ops,
  428. };
  429. static const struct of_device_id dt_match[] = {
  430. { .compatible = "amlogic,meson-gxbb-vpu",
  431. .data = (void *)&meson_drm_gxbb_data },
  432. { .compatible = "amlogic,meson-gxl-vpu",
  433. .data = (void *)&meson_drm_gxl_data },
  434. { .compatible = "amlogic,meson-gxm-vpu",
  435. .data = (void *)&meson_drm_gxm_data },
  436. { .compatible = "amlogic,meson-g12a-vpu",
  437. .data = (void *)&meson_drm_g12a_data },
  438. {}
  439. };
  440. MODULE_DEVICE_TABLE(of, dt_match);
  441. static const struct dev_pm_ops meson_drv_pm_ops = {
  442. SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume)
  443. };
  444. static struct platform_driver meson_drm_platform_driver = {
  445. .probe = meson_drv_probe,
  446. .remove = meson_drv_remove,
  447. .shutdown = meson_drv_shutdown,
  448. .driver = {
  449. .name = "meson-drm",
  450. .of_match_table = dt_match,
  451. .pm = &meson_drv_pm_ops,
  452. },
  453. };
  454. drm_module_platform_driver(meson_drm_platform_driver);
  455. MODULE_AUTHOR("Jasper St. Pierre <[email protected]>");
  456. MODULE_AUTHOR("Neil Armstrong <[email protected]>");
  457. MODULE_DESCRIPTION(DRIVER_DESC);
  458. MODULE_LICENSE("GPL");