mtk_cec.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Jie Qiu <[email protected]>
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/delay.h>
  8. #include <linux/io.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/module.h>
  11. #include <linux/mod_devicetable.h>
  12. #include <linux/platform_device.h>
  13. #include "mtk_cec.h"
  14. #define TR_CONFIG 0x00
  15. #define CLEAR_CEC_IRQ BIT(15)
  16. #define CEC_CKGEN 0x04
  17. #define CEC_32K_PDN BIT(19)
  18. #define PDN BIT(16)
  19. #define RX_EVENT 0x54
  20. #define HDMI_PORD BIT(25)
  21. #define HDMI_HTPLG BIT(24)
  22. #define HDMI_PORD_INT_EN BIT(9)
  23. #define HDMI_HTPLG_INT_EN BIT(8)
  24. #define RX_GEN_WD 0x58
  25. #define HDMI_PORD_INT_32K_STATUS BIT(26)
  26. #define RX_RISC_INT_32K_STATUS BIT(25)
  27. #define HDMI_HTPLG_INT_32K_STATUS BIT(24)
  28. #define HDMI_PORD_INT_32K_CLR BIT(18)
  29. #define RX_INT_32K_CLR BIT(17)
  30. #define HDMI_HTPLG_INT_32K_CLR BIT(16)
  31. #define HDMI_PORD_INT_32K_STA_MASK BIT(10)
  32. #define RX_RISC_INT_32K_STA_MASK BIT(9)
  33. #define HDMI_HTPLG_INT_32K_STA_MASK BIT(8)
  34. #define HDMI_PORD_INT_32K_EN BIT(2)
  35. #define RX_INT_32K_EN BIT(1)
  36. #define HDMI_HTPLG_INT_32K_EN BIT(0)
  37. #define NORMAL_INT_CTRL 0x5C
  38. #define HDMI_HTPLG_INT_STA BIT(0)
  39. #define HDMI_PORD_INT_STA BIT(1)
  40. #define HDMI_HTPLG_INT_CLR BIT(16)
  41. #define HDMI_PORD_INT_CLR BIT(17)
  42. #define HDMI_FULL_INT_CLR BIT(20)
  43. struct mtk_cec {
  44. void __iomem *regs;
  45. struct clk *clk;
  46. int irq;
  47. bool hpd;
  48. void (*hpd_event)(bool hpd, struct device *dev);
  49. struct device *hdmi_dev;
  50. spinlock_t lock;
  51. };
  52. static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
  53. unsigned int bits)
  54. {
  55. void __iomem *reg = cec->regs + offset;
  56. u32 tmp;
  57. tmp = readl(reg);
  58. tmp &= ~bits;
  59. writel(tmp, reg);
  60. }
  61. static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
  62. unsigned int bits)
  63. {
  64. void __iomem *reg = cec->regs + offset;
  65. u32 tmp;
  66. tmp = readl(reg);
  67. tmp |= bits;
  68. writel(tmp, reg);
  69. }
  70. static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
  71. unsigned int val, unsigned int mask)
  72. {
  73. u32 tmp = readl(cec->regs + offset) & ~mask;
  74. tmp |= val & mask;
  75. writel(tmp, cec->regs + offset);
  76. }
  77. void mtk_cec_set_hpd_event(struct device *dev,
  78. void (*hpd_event)(bool hpd, struct device *dev),
  79. struct device *hdmi_dev)
  80. {
  81. struct mtk_cec *cec = dev_get_drvdata(dev);
  82. unsigned long flags;
  83. spin_lock_irqsave(&cec->lock, flags);
  84. cec->hdmi_dev = hdmi_dev;
  85. cec->hpd_event = hpd_event;
  86. spin_unlock_irqrestore(&cec->lock, flags);
  87. }
  88. bool mtk_cec_hpd_high(struct device *dev)
  89. {
  90. struct mtk_cec *cec = dev_get_drvdata(dev);
  91. unsigned int status;
  92. status = readl(cec->regs + RX_EVENT);
  93. return (status & (HDMI_PORD | HDMI_HTPLG)) == (HDMI_PORD | HDMI_HTPLG);
  94. }
  95. static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
  96. {
  97. mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
  98. mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
  99. RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
  100. mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
  101. HDMI_HTPLG_INT_32K_CLR | HDMI_PORD_INT_32K_EN |
  102. RX_INT_32K_EN | HDMI_HTPLG_INT_32K_EN);
  103. }
  104. static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
  105. {
  106. mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
  107. }
  108. static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
  109. {
  110. mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
  111. }
  112. static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
  113. {
  114. mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
  115. mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
  116. HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
  117. mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
  118. RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
  119. usleep_range(5, 10);
  120. mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
  121. HDMI_PORD_INT_CLR | HDMI_FULL_INT_CLR);
  122. mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
  123. mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
  124. RX_INT_32K_CLR | HDMI_HTPLG_INT_32K_CLR);
  125. }
  126. static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
  127. {
  128. void (*hpd_event)(bool hpd, struct device *dev);
  129. struct device *hdmi_dev;
  130. unsigned long flags;
  131. spin_lock_irqsave(&cec->lock, flags);
  132. hpd_event = cec->hpd_event;
  133. hdmi_dev = cec->hdmi_dev;
  134. spin_unlock_irqrestore(&cec->lock, flags);
  135. if (hpd_event)
  136. hpd_event(hpd, hdmi_dev);
  137. }
  138. static irqreturn_t mtk_cec_htplg_isr_thread(int irq, void *arg)
  139. {
  140. struct device *dev = arg;
  141. struct mtk_cec *cec = dev_get_drvdata(dev);
  142. bool hpd;
  143. mtk_cec_clear_htplg_irq(cec);
  144. hpd = mtk_cec_hpd_high(dev);
  145. if (cec->hpd != hpd) {
  146. dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
  147. cec->hpd, hpd);
  148. cec->hpd = hpd;
  149. mtk_cec_hpd_event(cec, hpd);
  150. }
  151. return IRQ_HANDLED;
  152. }
  153. static int mtk_cec_probe(struct platform_device *pdev)
  154. {
  155. struct device *dev = &pdev->dev;
  156. struct mtk_cec *cec;
  157. struct resource *res;
  158. int ret;
  159. cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
  160. if (!cec)
  161. return -ENOMEM;
  162. platform_set_drvdata(pdev, cec);
  163. spin_lock_init(&cec->lock);
  164. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  165. cec->regs = devm_ioremap_resource(dev, res);
  166. if (IS_ERR(cec->regs)) {
  167. ret = PTR_ERR(cec->regs);
  168. dev_err(dev, "Failed to ioremap cec: %d\n", ret);
  169. return ret;
  170. }
  171. cec->clk = devm_clk_get(dev, NULL);
  172. if (IS_ERR(cec->clk)) {
  173. ret = PTR_ERR(cec->clk);
  174. dev_err(dev, "Failed to get cec clock: %d\n", ret);
  175. return ret;
  176. }
  177. cec->irq = platform_get_irq(pdev, 0);
  178. if (cec->irq < 0)
  179. return cec->irq;
  180. ret = devm_request_threaded_irq(dev, cec->irq, NULL,
  181. mtk_cec_htplg_isr_thread,
  182. IRQF_SHARED | IRQF_TRIGGER_LOW |
  183. IRQF_ONESHOT, "hdmi hpd", dev);
  184. if (ret) {
  185. dev_err(dev, "Failed to register cec irq: %d\n", ret);
  186. return ret;
  187. }
  188. ret = clk_prepare_enable(cec->clk);
  189. if (ret) {
  190. dev_err(dev, "Failed to enable cec clock: %d\n", ret);
  191. return ret;
  192. }
  193. mtk_cec_htplg_irq_init(cec);
  194. mtk_cec_htplg_irq_enable(cec);
  195. return 0;
  196. }
  197. static int mtk_cec_remove(struct platform_device *pdev)
  198. {
  199. struct mtk_cec *cec = platform_get_drvdata(pdev);
  200. mtk_cec_htplg_irq_disable(cec);
  201. clk_disable_unprepare(cec->clk);
  202. return 0;
  203. }
  204. static const struct of_device_id mtk_cec_of_ids[] = {
  205. { .compatible = "mediatek,mt8173-cec", },
  206. {}
  207. };
  208. MODULE_DEVICE_TABLE(of, mtk_cec_of_ids);
  209. struct platform_driver mtk_cec_driver = {
  210. .probe = mtk_cec_probe,
  211. .remove = mtk_cec_remove,
  212. .driver = {
  213. .name = "mediatek-cec",
  214. .of_match_table = mtk_cec_of_ids,
  215. },
  216. };